Memory device and control method thereof

Abstract

A memory device includes: a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between a word line and a bit line; a word line driver coupled to the plurality of memory cell arrays and configured to drive one or more incremented read voltages into one of the plurality of memory cells; a sense amplifier configured to compare each of the one or more incremented read voltages with a reference voltage and generate a comparison output signal; and a data register configured to store readout data and the comparison output signal.

Description

Technical Field

[0001] The present disclosure relates to a memory device and an operation method thereof. Background Art

[0002] A conventional read operation of a memory cell may be much more frequent and continuous than a write operation or other operations, thus becoming a key factor in the lifespan of the memory cell. In particular, when the read signal is much higher than the signal that may be required to read out the data, for example, using a higher read voltage to read a memory cell having a lower threshold voltage, the higher read voltage may wear out the memory cell faster than in normal operation. On the other hand, if the read voltage is too low, it may not be possible to distinguish between the "set" state and the "reset" state because the threshold voltages of both the "set" state and the "reset" state are higher than the read voltage. Therefore, finding an appropriate read voltage may become challenging. In addition, since the memory cells may have a wide threshold voltage distribution in the memory array, it becomes even more challenging to determine an appropriate read voltage for all memory cells to distinguish between the "set" state and the "reset" state of the memory cells while keeping the read voltage as low as possible to increase the lifespan of the memory cells. Summary of the Invention

[0003] In one aspect, a memory device includes: a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between a word line and a bit line; a word line driver, coupled to the plurality of memory cell arrays and configured to drive one or more increasing read voltages into a memory cell among the plurality of memory cells; a sense amplifier, configured to compare each of the one or more increasing read voltages with a reference voltage and generate a comparison output signal; and a data register, configured to store read-out data and the comparison output signal.

[0004] In another aspect, a system includes a memory device configured to store data, and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes: a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between a word line and a bit line; a word line driver, coupled to the plurality of memory cell arrays and configured to drive one or more increasing read voltages into a memory cell among the plurality of memory cells; a sense amplifier, configured to compare each of the one or more increasing read voltages with a reference voltage and generate a comparison output signal, and a data register, configured to store read-out data and the comparison output signal.

[0005] In yet another aspect, a method for operating a memory device is disclosed. The memory device includes a plurality of memory cell arrays, and each memory cell array includes a plurality of memory cells connected between a word line and a bit line. The method includes: applying an increasing read voltage to one of the plurality of memory cells; determining whether the increasing read voltage is higher than a threshold voltage of one of the plurality of memory cells; in response to the increasing read voltage being higher than the threshold voltage, determining the state of the memory cell as a "set" state; and in response to the increasing read voltage being lower than the threshold voltage, repeating applying the next increasing read voltage to one of the plurality of memory cells until the increasing read voltage reaches a maximum voltage, and then determining the state of the memory cell as "reset".

[0006] In yet another aspect, a method for operating a memory device is disclosed. The memory device includes a plurality of memory cell arrays, and each memory cell array includes a plurality of memory cells connected between a word line and a bit line. The method includes: in response to determining that a command corresponds to a read operation; setting a read voltage V read to an initial read voltage V read_1 ; applying the read voltage V read to one of the plurality of memory cells; determining whether the read voltage V read is higher than a threshold voltage V th of one of the plurality of memory cells; in response to the read voltage V read being higher than the threshold voltage V th , determining the state of one of the plurality of memory cells as a "set" state; in response to the read voltage V read being lower than the threshold voltage V th , setting the read voltage V read to be equal to the initial read voltage V read_1 plus a step voltage V dac ; determining whether the read voltage V read is equal to or higher than a maximum read voltage V read_max ; in response to the read voltage V read being equal to or higher than the maximum read voltage V read_max , determining the state of one of the plurality of memory cells as a "reset" state, and in response to the read voltage V read being lower than the maximum read voltage V read_max , repeating applying the read voltage V read . BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings incorporated herein and forming a part of the specification illustrate aspects of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable one of ordinary skill in the art to practice and use the present disclosure.

[0008] Figure 1 A block diagram of an exemplary system having a memory device in accordance with some aspects of the present disclosure is shown.

[0009] Figure 2 A schematic diagram of an exemplary memory device including peripheral circuitry in accordance with some aspects of the present disclosure is shown.

[0010] Figure 3 A schematic diagram of an exemplary memory device including phase change memory (PCM) cells in accordance with some aspects of the present disclosure is shown.

[0011] Figure 4 A block diagram of an exemplary memory device including a memory cell array and peripheral circuitry in accordance with some aspects of the present disclosure is shown.

[0012] Figure 5 A block diagram of an exemplary memory device including a memory cell array and peripheral circuitry in accordance with some aspects of the present disclosure is shown.

[0013] Figure 6 A voltage graph showing the distribution of threshold voltages for "set" and "reset" states in accordance with some aspects of the present disclosure, and the selection of a series of read voltages based on the distribution is shown.

[0014] Figure 7 A flowchart of an exemplary method for operating a memory device in accordance with some aspects of the present disclosure is shown.

[0015] Figure 8 A flowchart of an exemplary method for operating a memory device in accordance with some aspects of the present disclosure is shown.

[0016] The present disclosure will be described with reference to the accompanying drawings. Detailed Description

[0017] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of the present disclosure. Additionally, the present disclosure may be used in a variety of other applications. The functional and structural features described in the present disclosure may be combined, adjusted, and modified with each other and in ways not specifically shown in the drawings such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0018] Generally, terms can be understood at least in part from their usage in context. For example, as used herein, the term "one or more" depends at least in part on context and can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can also be understood to express a singular usage or a plural usage, at least in part depending on context. Additionally, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but can allow for the presence of other factors that are not necessarily explicitly described, which also depends at least in part on context.

[0019] A phase-change memory (PCM) cell is a non-volatile memory device that stores data using a phase-change material. PCM can utilize the difference in resistivity between the amorphous and crystalline phases in a phase-change material (e.g., a chalcogenide alloy) by heating and quenching the phase-change material in an electro-thermal manner. The phase-change material in a PCM cell can be located between two electrodes and can be applied with a current to repeatedly switch the material between two phases (or at least a part of its current-blocking path) to store data. The "set" state is the low-resistance state of the PCM cell, which can be obtained by generating a crystalline region in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated for a sufficient duration at the crystallization temperature. In contrast, the "reset" state is the high-resistance state of the PCM cell, which can be obtained by generating an amorphous region in the chalcogenide material. The amorphous state can be produced when the chalcogenide material is heated above its melting temperature and then rapidly quenched to form an amorphous state. The "set" state can be referred to as the "on" state, while the "reset" state can be referred to as the "off" state.

[0020] As described above, a conventional read operation of a memory cell may reduce the lifespan of the memory cell. In particular, when a higher read voltage is used to read a memory cell with a lower threshold voltage, the higher read voltage may wear out the memory cell much faster than in normal operation. This may be more significant when the threshold voltage distribution of the memory cell is in the lower voltage region. On the other hand, if a lower read voltage may not be able to distinguish between the "set" state and the "reset" state because the threshold voltages of both the "set" state and the "reset" state are higher than the read voltage. That is, it cannot be determined whether the measurement result is set data or reset data. Therefore, finding an appropriate read voltage may become challenging. In addition, the resistance distribution may vary widely due to inherent cell variations or other factors. It is not easy to find an appropriate read voltage for all memory cells. Finally, if the read voltage is too high, the read current may also be too high, and the possibility of read interference is increased, which may undesirably program unselected memory cells. Therefore, it becomes more challenging to determine an ideal read voltage for all memory cells to distinguish between the "set" state and the "reset" state of the memory cell while keeping the read voltage as low as possible to increase the lifespan of the memory cell.

[0021] To solve one or more of the above problems, the present disclosure introduces a solution in which a stepwise read operation is introduced to identify whether a memory cell is in a "set" state or a "reset" state, and the result is read out after the read operation. Specifically, an initial read voltage is configured to be predetermined according to the threshold voltage distribution in the "set" state of the memory cells in the memory array. Then, a read voltage (e.g., the initial read voltage) is applied to one of the memory cells, and it is determined whether the read voltage is higher than the threshold voltage of one of the memory cells. If the read voltage is higher than the threshold voltage, the memory cell is in the "set" state, and thus, the read data (e.g., the read current) can be read out. On the contrary, if the read voltage is lower than the threshold voltage, the memory cell may be in the "set" state or the "reset" state, and a higher read voltage needs to be introduced to identify which state the memory cell is in. In response thereto, a new and increasing read voltage is determined, which is the initial read voltage plus the step voltage. In addition, if the read voltage is not higher than the maximum threshold read voltage, which can be determined according to the threshold voltage distribution in the "reset" state of the memory cells in the memory array, the read voltage is repeatedly and iteratively applied to the memory cell and its subsequent processing until the state of the memory cell is determined to be the "set" state or the "reset" state. Therefore, if the initial read voltage is higher than the threshold voltage in the "set" state, a much lower initial read voltage can be used to read out the data. In addition, if the initial read voltage is lower than the threshold voltage in the "set" state, several iterations can identify the state of the memory cell and the corresponding read data. As a result, the loss of the memory cells can be minimized, and their lifespan can be extended.

[0022] Figure 1 FIG. shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As Figure 1As shown, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). In some embodiments, the host 108 may be configured to send or receive data to and from the memory device 104. In some embodiments, the host may be user logic or a user interface such that a user can give instructions to the host and transmit the instructions to the memory device or memory array.

[0023] The memory device 104 may be any memory device disclosed in the present disclosure. As will be disclosed in detail below, according to some embodiments, the memory device 104 (e.g., a phase change random access memory (PCRAM), a dynamic random access memory (DRAM), or a NAND flash device) may include a clock input, a command bus, control logic, an address register, a row decoder / word line driver, a memory cell array having memory cells, a voltage generator, a page buffer / sense amplifier, a column decoder / bit line driver, an input / output circuit (I / O circuit) / read data latch, and a data register / data I / O.

[0024] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a solid-state drive (SSD) or an embedded multi-media-card (eMMC) in a high-duty-cycle environment, serving as data storage for mobile devices (e.g., smart phones, tablets, laptop computers, etc.) and enterprise storage arrays. The memory controller 106 can be configured to control the operations of the memory device 104, such as read, erase, and write operations. The memory controller 106 can also be configured to manage various functions regarding the data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) for the data read from or written to the memory device 104. Any other suitable functions can also be performed by the memory controller 106, e.g., formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 may communicate with an external device via at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, high-speed PCI (PCI-express, PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc. In addition, the memory controller 106 may also be configured to control the operation of the memory device 104 to perform the method according to some embodiments of the present disclosure. For example, in some embodiments, the memory controller 106 may determine an initial read voltage V based on the set threshold voltage distribution of the memory cells in the memory array. read_1 . In some embodiments, the memory controller 106 may determine the read voltage V read whether it is higher than the threshold voltage V of one of the multiple memory cells th . In some embodiments, the memory controller 106 may, in response to the read voltage V read being higher than the threshold voltage V th determine that the state of the memory cell is the "set" state. In some embodiments, the memory controller 106 may set the read voltage V read to the initial read voltage V read_1 plus the step voltage V dac . In some embodiments, the memory controller 106 may, in response to the read voltage V read being equal to or higher than the maximum read voltage V read_max determine that the state of the memory cell is the "reset" state. In some embodiments, in response to the read voltage V read being lower than the maximum read voltage V read_max , the memory controller 106 may repeatedly or iteratively apply the read voltage V to one of the multiple memory cells read . Note that according to some embodiments of the present disclosure, one or more of these operations of the memory device 104 may also be performed partially or completely by the control logic.

[0025] Figure 2Schematic circuit diagram of an exemplary memory device 200 including peripheral circuits according to some aspects of the present disclosure is shown. The memory device 200 may be an example of the memory device 104 in Figure 1 . The memory device 200 may include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The memory cell array 201 may include word lines 214, bit lines 216, and memory cells 208 formed between the word lines 214 and the bit lines 216. In some embodiments, each memory cell 208 may include a PCM element (not shown) in series with a selector (not shown). In some embodiments, the memory cell 208 may also be a DRAM cell including a pair of transistors and a capacitor. To operate the memory cell array 201, a word line voltage (V w ) may be applied to each word line 214, and a bit line voltage (V b ) may be applied to each bit line 216.

[0026] Figure 3 Side view of a cross-section of a memory device 300 having a PCM element in series with a selector is shown. The memory device 300 includes a plurality of parallel bit lines 304 (i.e., corresponding to the bit lines 216 in Figure 2 ) above a substrate 302 and a plurality of parallel word lines 316 (i.e., corresponding to the word lines 214 in Figure 2 ) above the bit lines 304. The memory device 300 further includes a plurality of PCM cells 301 (i.e., corresponding to the memory cells 208 in Figure 2 ), each disposed at the intersection of a corresponding pair of bit lines 304 and word lines 316. Adjacent PCM cells 301 are separated by an insulating structure 322. Each PCM cell 301 includes a selector 308 and a PCM element 312 above the selector 308. Each PCM cell 301 further includes three electrodes 306, 310, and 314 vertically located between the corresponding bit line 304, selector 308, PCM element 312, and the corresponding word line 316, respectively. As described above, the read operation of the memory cell may reduce the life of the memory cell. This phenomenon is particularly observed in PCM cells (e.g., 301) having a PCM element (e.g., 312) in series with a selector (e.g., 308) because the PCM cells are more sensitive to the read voltage and may have a greater chance of getting stuck in the "reset" state when the read voltage is too high.

[0027] Note that the PCM element 312 can utilize the difference in resistivity between the amorphous and crystalline phases in the phase change material by heating and quenching the phase change material (e.g., chalcogenide alloy) in an electrothermal manner. The phase change element can be located between two electrodes, and a current can be applied to repeatedly switch the material (or at least a part of its current-blocking path) between the two phases to store data.

[0028] The selector 308 can include a bidirectional threshold switch (ovonic threshold switch, OTS) selector having an OTS material (e.g., zinc telluride (ZnTe)), which exhibits field-dependent volatile resistive switching behavior (referred to as the "OTS phenomenon") when an external bias voltage (Va) higher than the threshold voltage (Vth) is applied. At a lower voltage (|Va| < Vth), the high resistance of the OTS selector in its off state keeps the off-state current (Ioff) low. At a higher voltage (|Va| > Vth), the OTS selector undergoes the OTS phenomenon and switches to an on state with low resistance; thus, the current (Ion) through the on-state OTS selector increases. The volatile on state is maintained as long as the high voltage is provided.

[0029] Figure 4 FIG. shows an exemplary memory device 400 (e.g., corresponding to 104 in Figure 2 and including a memory cell array 401 (e.g., corresponding to 201 in Figure 1 and peripheral circuits according to some aspects of the present disclosure. In some embodiments, the memory cells of the memory cell array 401 include PCM cells 301 as in Figure 3

[0030] As shown in Figure 4 , the page buffer / sense amplifier 404 can be configured to read data from and program (write) data to the memory cell array 401 according to control signals from the control logic 412. In one example, the page buffer / sense amplifier 404 can store data to be programmed into the memory cell array 201 (e.g., Figure 2One - page programming data (write data) in a page in (China). In another example, the page buffer / sense amplifier 404 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cells 208 coupled to the selected word line 214. In yet another example, the page buffer / sense amplifier 404 can also sense a low - power signal representing the data bits stored in the memory cells 208 from the selected bit line 216 and amplify the small voltage swing to an identifiable logic level during a read operation. In some embodiments, the page buffer / sense amplifier 404 can include a comparator (e.g., a voltage comparator) for comparing a voltage signal (e.g., a read voltage) with a reference voltage signal (e.g., a predetermined threshold voltage of a memory cell in the "set" state).

[0031] The column decoder / bit - line driver / data latch 406 can be configured to be controlled by the control logic 412 and select one or more memory cells 208 and bit lines 216. The column decoder / bit - line driver / data latch 406 can be further configured to drive the selected bit lines 216. The column decoder / bit - line driver / data latch 406 can be further configured to drive the bit lines 216 using the bit - line voltages generated from the voltage generator 410. The column decoder / bit - line driver / data latch 406 can be a temporary binary data storage device for storing bits. In some embodiments, the column decoder / bit - line driver / data latch 406 can include a read data latch for temporarily storing read data.

[0032] The data register / data I / O 416 can be coupled to the page buffer / sense amplifier 404 and / or the column decoder / bit - line driver / data latch 406 and is configured to direct (route) the data input from the data bus 423 to the desired memory cells 208 of the memory cell array 201 and direct (route) the data output from the desired memory cells to the data bus 423.

[0033] The row decoder / word - line driver 408 can be configured to be controlled by the control logic 412 and select one or more memory cells 208 and word lines 214 of the memory cell array 201. The row decoder / word - line driver 408 can be further configured to drive the selected word lines 214. The row decoder / word - line driver 408 can be further configured to drive the word lines 214 using the word - line voltages generated from the voltage generator 410.

[0034] The voltage generator 410 can be configured to be controlled by the control logic 412 according to a control signal from the control logic 412, and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 401. In some embodiments, the voltage generator 410 is configured to generate a read voltage V to one of the memory cells in the memory cell array 401 read , and in response to a new, increasing read voltage V read being lower than the maximum read voltage V read_max , repeatedly generate another read voltage V to the memory cells in the memory cell array 401 read .

[0035] The control logic 412 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The control logic 412 is configured to receive from a host (e.g., Figure 1108) in receive a clock signal, a command signal, an address signal, and a data signal. Receive the command signal via the command bus 421. Receive the data signal via the data bus 423. In some embodiments, the control logic 412 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, strobe logic, discrete hardware circuits, and other suitable hardware, firmware, and / or software configured to perform the various functions described. In some embodiments, the control logic 412 is configured to direct one or more incremented read voltages to one of the memory cells in the memory cell array 401. That is, the control logic 412 may instruct the voltage generator 410 to generate one or more incremented read voltages and instruct the word line driver 408 to apply the one or more incremented read voltages to one of the memory cells in the memory cell array 401. In some embodiments, the control logic 412 is further configured to receive a feedback signal from the data register 416 to determine whether to direct another incremented read voltage to one of the memory cells in the memory cell array 401. The feedback signal based on whether the state of one of the memory cells in the memory cell array 401 has been determined may be processed by the control logic 412.

[0036] The address register 414 may be coupled to or included in the control logic 412. The address register 414 may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0037] Figure 5 FIG. shows a block diagram of a memory device 500 (e.g., corresponding to Figure 4 400) in accordance with some aspects of the present disclosure. As Figure 5As shown, once the control logic 412 determines that the command signal is a read command, the control logic 412 triggers a read operation. Then, the read data is transmitted to the word line driver 408 to introduce a read voltage into the memory cell array 401. To select an appropriate read voltage, the set threshold voltage distribution and the reset threshold voltage distribution of a plurality of memory cells in the memory cell array 401 can be determined first.

[0038] Figure 6 The set threshold voltage distribution and the reset threshold voltage distribution are shown in. As Figure 6 shown, in the "set" state and the "reset" state, each memory cell in the memory cell array 401 can have a different threshold voltage. The distribution of the threshold voltage can vary from one memory array to another memory array. In some embodiments, this distribution can be obtained through a preliminary endurance test cycle. According to some embodiments, when selecting the initial read voltage V read_1 , it can be determined that the initial read voltage V read_1 is at the peak of the set threshold voltage distribution. According to some embodiments, the initial read voltage V read_1 is at least higher than the minimum set threshold voltage and lower than the maximum set threshold voltage. The second read voltage V read_2 is the initial read voltage V read_1 plus the step voltage V dac . In some embodiments, the second read voltage V read_2 should be higher than the maximum set threshold voltage, which means that the step voltage V dac should be high enough so that the second read voltage V read_2 is outside the distribution range of the set threshold voltage. However, in some cases where the maximum set threshold voltage and the minimum reset threshold voltage are too close or too far apart, the determination of the initial read voltage V read_1 or the step voltage V dac can be adjusted accordingly. According to some embodiments of the present disclosure, the incremented read voltage V read is configured to increase in an incremental manner to reach the latest incremented read voltage V read_n , where V read_n is equal to the previous read voltage plus a step voltage V dac , and n is an integer representing the number of read voltages applied during the read operation. According to some embodiments, the latest incremented read voltage V read_n may not be equal to or higher than the maximum read voltage V read_max (where the maximum read voltage V read_max can be determined to be at the peak of the reset threshold voltage distribution) or the minimum reset threshold voltage. Because the higher the read voltage, the higher the likelihood of undesirably programming the memory cells. The maximum read voltage Vread_max to prevent programming of the memory cells. In some embodiments, one of the memory cells is a PCM cell 301 as shown in Figure 3 .

[0039] In some embodiments, the number of read voltages applied during a read operation may not exceed three, since each iteration of the read operation may take an additional 40 to 50 nanoseconds (ns) to process, which would reduce the operation speed. For example, in a typical DRAM application where each read cycle takes about 80 to 200 ns, the number of read voltages can be limited to two or three.

[0040] In some embodiments, when the distribution window of the set threshold voltage and the reset threshold voltage (i.e., the range between the maximum reset threshold voltage (e.g., 2.5V) and the minimum set threshold voltage (e.g., 0.5V)) is 1.5V to 2.5V (e.g., 2.0V), the initial read voltage V read_1 can be determined to be 0.8V to 1.2V (e.g., 1.0V), and the step voltage V dac can be determined to be 0.3V to 0.7V (e.g., 0.5V). It should also be noted that the step voltage V dac can be adjusted such that the step voltage V dac can be different for each read operation.

[0041] Returning to Figure 5 , after selecting an appropriate read voltage, the read voltage is applied to the memory cells of the memory cell array 401 via the word line. The sense amplifier 404 is configured to and will receive the read data, such as a read current or a read voltage. The sense amplifier 404 may also include a comparator (e.g., a voltage comparator) to compare the read voltage with a reference voltage. According to some embodiments, the reference voltage can be pre-determined as the set threshold voltage or the reset threshold voltage. The comparison output signal and / or the readout signal are configured to be temporarily stored in a data latch 406 as shown in Figure 4 . In some embodiments, the data latch may be included in a data register 416. For example, the read address and the read data accompanying the read command are temporarily stored in the data register and are held until the next read command. The read data stored in the data register / data I / O 416 can be output to the next stage via the output of the data register 416 for corresponding signal processing.

[0042] Figure 7 FIG. shows a flowchart of an exemplary method 700 for operating a memory device according to some aspects of the present disclosure. The memory device can be any suitable memory device disclosed herein. Method 700 can be partially or fully performed by, for example,Figure 4 is implemented by the control logic 412 in Figure 1 or the memory controller 106 in Figure 7 . It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Additionally, some operations may be performed simultaneously, or in a different order than

[0043] Refer to Figure 7 , method 700 begins with operation 702, where an increasing read voltage is applied to a memory cell among a plurality of memory cells in the memory cell array 401 as in Figure 4 . Specifically, the increasing read voltage is applied to one of the memory cells via one of the word lines of the memory cell array 401. Note that the increasing read voltage hereinafter means that the read voltage is configured to increase in an increasing manner for each iteration (increase when the read voltage is positive or decrease when the read voltage is negative) until the read voltage reaches a certain voltage level, such as the maximum voltage, which can be predetermined by the user or predetermined according to the distribution of the reset voltages of the plurality of memory cells as described above. In some embodiments, the memory cell is a PCM cell 301 as in Figure 3 .

[0044] Method 700 proceeds to operation 704, as in Figure 7 , where it is determined whether the increasing read voltage is higher than the threshold voltage of the memory cell. The comparison between the two voltages can be performed by a comparator, for example, a voltage comparator included in the sense amplifier 404 as in Figure 4 .

[0045] Method 700 proceeds to operation 706, as in Figure 7 , where, in response to the increasing read voltage being higher than the threshold voltage, the state of the memory cell is determined to be in the "set" state. In some embodiments, after operation 706, the read output data in the "set" state is obtained. The read output data in the "set" state can be, for example, the set current or set voltage of the memory cell. Then, the read output data in the "set" state is stored in the data latch of the data register 416 as in Figure 4 or 5. However, if the read voltage V read is lower than the threshold voltage V th of the memory cell, the state of the memory cell cannot be determined because when the read voltage V read is too low, i.e., lower than the threshold voltage V th in the "set" state or the threshold voltage V thWhen, the state of the memory cell can be a "set" state or a "reset" state. Therefore, a relatively high read voltage V read is required to distinguish between the "set" state and the "reset" state.

[0046] Method 700 proceeds to operation 708, as Figure 7 shown, wherein in response to the incremental read voltage being lower than the threshold voltage, the next incremental read voltage is repeatedly applied to the memory cell until the incremental read voltage reaches the maximum voltage, and then the state of the memory cell is determined to be "reset". Note that the next incremental read voltage is higher than the initial incremental read voltage. The step-by-step increase in the read voltage can ensure that the read voltage can be kept as low as possible, such that the read voltage reduces the unwanted programming changes to the memory cell that reset or damage the memory cell during frequent read operations. However, as described above, if the next incremental read voltage is too high (i.e., higher than the voltage at which the memory cell can be programmed to reset), then the next incremental read voltage may undesirably write to the memory cell. Thus, the next incremental read voltage is configured to first determine whether the next incremental read voltage reaches a specific voltage level, i.e., the maximum read voltage, which can be predetermined by the user or predetermined according to the distribution of the reset voltages of the multiple memory cells in the memory cell array 401 as in Figure 4 . The selection or determination of the maximum read voltage to avoid accidentally programming the memory cell has been mentioned above. To check the next incremental read voltage, if the next incremental read voltage reaches (i.e., is equal to or higher than) the maximum read voltage, then the next incremental read voltage may have reached the reset voltage level, and thus the state of the memory cell is determined to be the "reset" state. Conversely, if the next incremental read voltage has not reached (i.e., is less than) the maximum read voltage, then the next iteration can begin. The loop of the iteration is configured to repeat the loop of the iteration until the state of the memory cell is determined to be the "set" state or the "reset" state.

[0047] Figure 8 shows a flowchart of an exemplary method 800 for operating a memory device in accordance with some aspects of the present disclosure. The memory device can be any suitable memory device disclosed herein. Method 800 can be implemented in part or in whole by control logic 412 as in Figure 4 or by a memory controller 106 as in Figure 1 . It should be understood that the operations shown in method 800 are not exhaustive, and other operations can also be performed before, after, or between any of the shown operations. Additionally, some operations can be performed simultaneously, or in a different order than Figure 8 shown.

[0048] Refer toFigure 8 The method 800 begins with operation 802, where, in response to determining that the command signal corresponds to a read operation, the read voltage V read is set to an initial read voltage V read_1 , where the initial read voltage V Figure 4 is determined according to the set threshold voltage distribution of multiple memory cells in the memory cell array 401 as shown in read_1 . In some embodiments, one of the multiple memory cells is a PCM cell 301 as shown in Figure 3 .

[0049] The method 800 proceeds to operation 804, as shown in Figure 8 , where the read voltage V read is applied to one of the multiple memory cells in the memory cell array 401. In particular, the read voltage V read is applied to one of the memory cells via one of the word lines of the memory cell array 401.

[0050] The method 800 proceeds to operation 806, as shown in Figure 8 , where, after applying the read voltage V read to the memory cell, it is determined whether the read voltage V read is higher than the threshold voltage V th of the memory cell under the read operation. The comparison between the two voltages can be performed by a comparator (e.g., a voltage comparator) included in the sense amplifier 404 mentioned above.

[0051] The method 800 proceeds to operation 808, as shown in Figure 8 , where, in response to determining that the read voltage V read is higher than the threshold voltage V th of the memory cell in the read operation, it is determined that the state of the memory cell is in the "set" state. In some embodiments, after operation 808, the read output data in the "set" state is obtained. The read output data in the "set" state can be, for example, the set current or set voltage of the memory cell. Then, the read output data in the "set" state is stored in the data latch of the data register 416 as shown in Figure 4 or 5. However, if the read voltage V read is lower than the threshold voltage V th of the memory cell in the read operation, the state of the memory cell cannot be determined because when the read voltage V read is too low (i.e., lower than the threshold voltage V th in the "set" state or the threshold voltage V th in the "reset" state)) When, the memory cell can be in a "set" state or a "reset" state. Therefore, a relatively high read voltage V is required read to distinguish between the "set" state and the "reset" state.

[0052] Method 800 proceeds to operation 810, as Figure 8 shown, wherein, in response to determining that the read voltage V read is lower than the threshold voltage V of the memory cell during the read operation th , the read voltage V read is set to be equal to the initial read voltage V read_1 plus the step voltage V dac . However, as described above, if the new read voltage V read is too high (i.e., higher than the voltage at which the memory cell can be programmed to reset), then this new read voltage V read may undesirably write to the memory cell. Therefore, the new read voltage V read should be within the maximum read voltage V read_max . Determining the maximum read voltage V read_max is mentioned above to avoid accidentally programming the memory cell. On the contrary, if the new read voltage V read is equal to or higher than the maximum read voltage V read_max , then the incremented read voltage V read has reached the reset voltage level, and thus the state of the memory cell is determined to be in the "reset" state.

[0053] Based on the above description, method 800 then proceeds to operation 812, as Figure 8 shown, wherein, it is determined whether the read voltage V read is equal to or higher than the maximum read voltage V read_max . If the read voltage V read is equal to or higher than the maximum read voltage V read_max , then the memory cell is in the reset state.

[0054] Therefore, method 800 then proceeds to operation 814, as Figure 8 shown, wherein, in response to determining that the read voltage V read is equal to or higher than the maximum read voltage V read_max , the state of the memory cell is determined to be in the "reset" state. In some embodiments, after operation 814, the read output data in the "reset" state is obtained. The read output data in the "reset" state can be, for example, the reset current or reset voltage of the memory cell. Then, the read output data in the "reset" state is stored in the data latch of the data register 416 as Figure 4 or 5 shown.

[0055] Conversely, method 800 proceeds to operation 816, as Figure 8 shown, in which, in response to determining that the read voltage V read is lower than the maximum read voltage V read_max , operation 804 (which applies the read voltage V read to the memory cell) and subsequent operations after operation 804 are repeated until the state of the memory cell is determined to be "set" or "reset". To repeat operation 804, data register 416 is configured to send a feedback signal that notifies and requests control logic 412 to send a new incremented read voltage V read to the memory cell.

[0056] According to one aspect of the present disclosure, a memory device includes: a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between a word line and a bit line; a word line driver coupled to the plurality of memory cell arrays and configured to drive one or more incremented read voltages into one of the plurality of memory cells; a sense amplifier configured to compare each of the one or more incremented read voltages with a reference voltage and generate a comparison output signal; and a data register configured to store read-out data and the comparison output signal.

[0057] In some embodiments, the memory device further includes control logic configured to direct one of the one or more incremented read voltages to one of the plurality of memory cells via the word line driver.

[0058] In some embodiments, the control logic is configured to receive a feedback signal from the data register to determine whether to direct another incremented read voltage to one of the plurality of memory cells.

[0059] In some embodiments, the feedback signal from the data register is whether one of the one or more incremented read voltages is higher than the threshold voltage of one of the plurality of memory cells.

[0060] In some embodiments, the memory device further includes a voltage generator configured to generate one or more incremented read voltages.

[0061] In some embodiments, each memory cell includes a phase change memory (PCM) cell.

[0062] In some embodiments, the phase change memory (PCM) cell includes a PCM element and a selector in series with the PCM element.

[0063] In some embodiments, the one or more incremented read voltages include an initial read voltage Vread_1 , and adds the step voltage V dac to the most recently read voltage V in an increasing manner read_n , where n is an integer representing the number of increasing read voltages applied to one of the plurality of memory cells during a read operation. In some embodiments, the initial read voltage V is determined according to the set threshold voltage distribution of the plurality of memory cells in each memory cell array of the plurality of memory cell arrays read_1 .

[0064] In some embodiments, the reference voltage includes the threshold voltage of one of the plurality of memory cells

[0065] In some embodiments, the reference voltage includes the maximum read voltage V of one of the plurality of memory cells read_max .

[0066] In some embodiments, the maximum read voltage V is determined according to the reset threshold voltage distribution of the plurality of memory cells in each memory cell array of the plurality of memory cell arrays read_max .

[0067] According to another aspect of the present disclosure, a system includes a memory device configured to store data, and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes: a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between a word line and a bit line; a word line driver coupled to the plurality of memory cell arrays and configured to drive one or more increasing read voltages into one of the plurality of memory cells; a sense amplifier configured to compare each of the one or more increasing read voltages with a reference voltage and generate a comparison output signal; and a data register configured to store the read-out data and the comparison output signal

[0068] In some embodiments, the memory device of the system further includes control logic configured to direct one or more increasing read voltages to one of the plurality of memory cells via the word line driver

[0069] In some embodiments, the control logic is configured to receive a feedback signal from the data register to determine whether to direct another increasing read voltage to one of the plurality of memory cells

[0070] In some embodiments, the feedback signal from the data register is whether one or more increasing read voltages are higher than the threshold voltage of one of the plurality of memory cells

[0071] In some embodiments, the memory device of the system further includes a voltage generator configured to generate one or more increasing read voltages.

[0072] In some embodiments, each memory cell includes a phase change memory (PCM) cell.

[0073] In some embodiments, the PCM cell includes a PCM element and a selector connected in series with the PCM element.

[0074] In some embodiments, one or more increasing read voltages include an initial read voltage V read_1 , and a step voltage V dac is added to the latest read voltage V read_n in an increasing manner, where n is an integer representing the number of increasing read voltages applied to one memory cell among a plurality of memory cells during a read operation.

[0075] In some embodiments, the initial read voltage V read_1 is determined according to the threshold voltage distribution in the "set" states of the plurality of memory cells in each memory cell array among a plurality of memory cell arrays.

[0076] In some embodiments, the reference voltage includes the threshold voltage of one memory cell among a plurality of memory cells.

[0077] In some embodiments, the reference voltage includes the maximum read voltage V read_max of one memory cell among a plurality of memory cells.

[0078] In some embodiments, the maximum read voltage V read_max is determined according to the reset threshold voltage distribution of the plurality of memory cells in each memory cell array among a plurality of memory cell arrays.

[0079] According to another aspect of the present disclosure, a method for operating a memory device is disclosed. The memory device includes a plurality of memory cell arrays, and each memory cell array includes a plurality of memory cells connected between a word line and a bit line. The method includes: applying an increasing read voltage to one memory cell among a plurality of memory cells; determining whether the increasing read voltage is higher than the threshold voltage of one memory cell among a plurality of memory cells; in response to the increasing read voltage being higher than the threshold voltage, determining the state of the memory cell as a "set" state; and in response to the increasing read voltage being lower than the threshold voltage, repeating to apply the next increasing read voltage to one memory cell among a plurality of memory cells until the increasing read voltage reaches the maximum voltage, and then determining the state of the memory cell as "reset".

[0080] In some embodiments, each memory cell includes a phase change memory (PCM) cell.

[0081] In some embodiments, the PCM cell includes a PCM element and a selector in series with the PCM element.

[0082] According to another aspect of the present disclosure, a method for operating a memory device is disclosed. The memory device includes a plurality of memory cell arrays, and each memory cell array includes a plurality of memory cells connected between a word line and a bit line. The method includes: in response to determining that the command corresponds to a read operation, setting a read voltage V read to an initial read voltage V read_1 ; applying the read voltage V read to one of the plurality of memory cells; determining whether the read voltage V read is higher than a threshold voltage V th of one of the plurality of memory cells; in response to the read voltage V read being higher than the threshold voltage V th , determining the state of one of the plurality of memory cells as the "set" state; in response to the read voltage V read being lower than the threshold voltage V th , setting the read voltage V read to be equal to the initial read voltage V read_1 plus a step voltage V dac ; determining whether the read voltage V read is equal to or higher than a maximum read voltage V read_max ; in response to the read voltage V read being equal to or higher than the maximum read voltage V read_max , determining the state of one of the plurality of memory cells as the "reset" state; and in response to the read voltage V read being lower than the maximum read voltage V read_max , repeating applying the read voltage V read to one of the plurality of memory cells.

[0083] In some embodiments, the initial read voltage V read_1 is determined according to the set threshold voltage distribution of the plurality of memory cells.

[0084] In some embodiments, the maximum read voltage V read_max is determined according to the reset threshold voltage distribution of the plurality of memory cells.

[0085] In some embodiments, the method further includes storing the read output data in the "set" state or the "reset" state in a data latch of the memory device.

[0086] The above description of specific embodiments can be readily modified and / or adapted for various applications. Thus, such adaptations and modifications are intended to be within the meaning and scope of the equivalent variations of the disclosed embodiments, based on the teachings and guidance presented herein.

[0087] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalent variations.

Claims

1. A memory device, comprising: A plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between a word line and a bit line; A word line driver, coupled to the plurality of memory cell arrays and configured to drive one or more increasing read voltages into one of the plurality of memory cells; A sense amplifier, configured to compare each of the one or more increasing read voltages with a reference voltage to determine whether the one memory cell is in a "set" state or a "reset" state, and generate a comparison output signal; And A data register, configured to store read-out data and the comparison output signal.

2. The memory device according to claim 1, further comprising: Control logic, configured to direct one of the one or more increasing read voltages to the one memory cell among the plurality of memory cells via the word line driver.

3. The memory device according to claim 2, wherein, The control logic is configured to receive a feedback signal from the data register to determine whether to direct another increasing read voltage to the one memory cell among the plurality of memory cells.

4. The memory device according to claim 3, wherein, The feedback signal from the data register is whether one of the one or more increasing read voltages is higher than the threshold voltage of the one memory cell among the plurality of memory cells.

5. The memory device according to claim 1, further comprising: A voltage generator, configured to generate the one or more increasing read voltages.

6. The memory device according to claim 1, wherein, Each memory cell includes a phase change memory (PCM) cell.

7. The memory device according to claim 6, wherein, The phase change memory cell includes a PCM element and a selector connected in series with the PCM element.

8. The memory device according to any one of claims 1-7, wherein, The one or more increasing read voltages include an initial read voltage V read_1 , and a step voltage V dac is added incrementally to the most recent read voltage V read_n , where n is an integer representing the number of increasing read voltages applied to the one memory cell among the plurality of memory cells during a read operation.

9. The memory device according to claim 8, wherein, Determine the initial read voltage V according to the set threshold voltage distributions of the multiple memory cells in each of the multiple memory cell arrays read_1 .

10. The memory device according to any one of claims 1-7 and 9, wherein, The reference voltage includes the threshold voltage of the one memory cell among the plurality of memory cells.

11. The memory device according to any one of claims 1-7 and 9, wherein, The reference voltage includes the maximum read voltage V of the one memory cell among the plurality of memory cells read_max .

12. The memory device according to claim 11, wherein, Determine the maximum read voltage V according to the reset threshold voltage distribution of the multiple memory cells in each of the multiple memory cell arrays read_max .

13. A memory system, comprising: A memory device configured to store data, the memory device including: A plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between a word line and a bit line; A word line driver, coupled to the plurality of memory cell arrays and configured to drive one or more increasing read voltages into one of the plurality of memory cells; A sense amplifier, configured to compare each of the one or more increasing read voltages with a reference voltage to determine whether the one memory cell is in a "set" state or a "reset" state, and generate a comparison output signal; and A data register, configured to store read-out data and the comparison output signal; and a memory controller, coupled to the memory device and configured to control the memory device.

14. The memory system according to claim 13, further comprising: Control logic, configured to direct one of the one or more increasing read voltages to the one memory cell among the plurality of memory cells via the word line driver.

15. The memory system according to claim 14, wherein, The control logic is configured to receive a feedback signal from the data register to determine whether to direct another incremented read voltage to the one memory cell among the plurality of memory cells.

16. The memory system according to claim 15, wherein, The feedback signal from the data register is whether the one or more incremented read voltages are higher than the threshold voltage of the one memory cell among the plurality of memory cells.

17. The memory system according to claim 13, further comprising: A voltage generator configured to generate the one or more incremented read voltages.

18. The memory system according to claim 13, wherein, Each memory cell includes a phase change memory (PCM) cell.

19. The memory system according to claim 18, wherein, The phase change memory cell includes a PCM element and a selector connected in series with the PCM element.

20. The memory system according to any one of claims 13-19, wherein, The one or more increasing read voltages include an initial read voltage V read1 , and a step voltage V dac is added to the most recent read voltage V read_n in an increasing manner, where n is an integer representing the number of increasing read voltages applied to the one memory cell among the plurality of memory cells during a read operation.

21. The memory system according to claim 20, wherein, Determine the initial read voltage V according to the threshold voltage distribution in the "set" state of the multiple memory cells in each of the multiple memory cell arrays read_1 .

22. The memory system according to any one of claims 13-19 and 21, wherein, The reference voltage includes the threshold voltage of the one memory cell among the plurality of memory cells.

23. The memory system according to any one of claims 13-19 and 21, wherein, The reference voltage includes a maximum read voltage V of the one memory cell among the plurality of memory cells read_max .

24. The memory system according to claim 23, wherein, Determine the maximum read voltage V according to the reset threshold voltage distribution of the multiple memory cells in each of the multiple memory cell arrays read_max .

25. A method for operating a memory device, the memory device comprising: A plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between a word line and a bit line, the method comprising: Applying an incremented read voltage to one memory cell among the plurality of memory cells; Determining whether the incremented read voltage is higher than the threshold voltage of the one memory cell among the plurality of memory cells; In response to the incremented read voltage being higher than the threshold voltage, determining the state of the one memory cell as the "set" state; and In response to the incremented read voltage being lower than the threshold voltage, repeatedly applying the next incremented read voltage to the one memory cell among the plurality of memory cells until the incremented read voltage reaches a maximum voltage, and then determining the state of the one memory cell as the "reset" state.

26. The method according to claim 25, wherein, Each memory cell includes a phase change memory (PCM) cell.

27. The method according to claim 26, wherein, The phase change memory cell includes a PCM element and a selector connected in series with the PCM element.

28. A method for operating a memory device, the memory device comprising: A plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between a word line and a bit line, the method comprising: In response to determining that the command corresponds to a read operation, set the read voltage V read to an initial read voltage V read_1 ; Apply the read voltage V to one of the plurality of memory cells read ; Determine whether the read voltage V read is higher than the threshold voltage V of the one memory cell among the plurality of memory cells th ; In response to the read voltage V read being higher than the threshold voltage V th , determine that the state of the one memory cell among the multiple memory cells is in the "set" state; In response to the read voltage V read being lower than the threshold voltage V th , set the read voltage V read to be equal to the initial read voltage V read_1 plus the step voltage V dac ; Determine whether the read voltage V read is equal to or higher than the maximum read voltage V read_max ; In response to the read voltage V read equal to or higher than the maximum read voltage V read_max , determining that the state of the one memory cell among the plurality of memory cells is in a "reset" state; and In response to the read voltage V read being lower than the maximum read voltage V read_max , the read voltage V is repeatedly applied to the one memory cell among the plurality of memory cells read .

29. The method according to claim 28, wherein, Determine the initial read voltage V according to the set threshold voltage distribution of the plurality of memory cells read_1 .

30. The method according to claim 28, wherein, Determine the maximum read voltage V according to the reset threshold voltage distribution of the plurality of memory cells read_max .

31. The method according to any one of claims 28 - 30, further comprising: Storing the read output data in the "set" state or the "reset" state in a data latch of the memory device.

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