Optoelectronic semiconductor chips

Abstract

The optoelectronic semiconductor chip (1) comprises: a semiconductor layer sequence (10) having a first semiconductor layer (101), a second semiconductor layer (102) and an active layer (103) between the first semiconductor layer (101) and the second semiconductor layer (102). The optoelectronic semiconductor chip (1) comprises: a first contact structure having a plurality of first contact pins (21) for electrically contacting the first semiconductor layer (101) and a first contact layer (210); and a second contact structure for electrically contacting the second semiconductor layer (102). The first semiconductor layer (101) is arranged between the first contact layer (210) and the active layer (103). The first contact pins (21) are arranged between the first contact layer (210) and the first semiconductor layer (101) and are separated and spaced apart from each other in a lateral direction. An electrical connection having a resistance is formed between the first contact layer (210) and the first semiconductor layer (101) by each first contact pin (21). In this case, the first contact pins (21) are selected such that an electrical connection formed by two different first contact pins (21) has different resistances.

Description

Technical Field

[0001] An optoelectronic semiconductor chip is provided. Summary of the invention

[0002] The object to be achieved is, inter alia, to specify an optoelectronic semiconductor chip which is characterized by a particularly uniform current density distribution, light density distribution and temperature distribution.

[0003] This object is achieved by the subject matter having the characteristics of the invention. Advantageous embodiments and improvements are the subject matter of the following description.

[0004] According to at least one embodiment of the optoelectronic semiconductor chip, the optoelectronic semiconductor chip comprises a semiconductor layer sequence having a first semiconductor layer, a second semiconductor layer and an active layer arranged between the first semiconductor layer and the second semiconductor layer. The semiconductor layer sequence is based on, for example, a III-V compound semiconductor material. The semiconductor material is, for example, a nitride compound semiconductor material, such as Al n In 1-n-m Ga m N, or phosphide compound semiconductor materials, such as Al n In 1-n-m Ga m P, or arsenide compound semiconductor materials, such as Al n In 1-n-m Ga m As or Al n In 1-n-m Ga m AsP, where 0≤n≤1, 0≤m≤1 and m+n≤1 respectively apply. The semiconductor layer sequence may comprise doping materials and additional components. For simplicity, however, only the main components of the crystal lattice of the semiconductor layer sequence are described, namely Al, As, Ga, In, N or P, even if these main components can be partially replaced and / or supplemented by small amounts of other substances. Preferably, the semiconductor layer sequence is based on InGaAlP.

[0005] The active layer is used to generate or absorb electromagnetic radiation. The active layer comprises in particular at least one pn junction and / or at least one quantum well structure in the form of a single quantum well, SQW for short, or in the form of a multiple quantum well structure, MQW for short. Preferably, the semiconductor chip comprises in particular exactly one connected active layer.

[0006] For example, during normal operation the semiconductor chip generates electromagnetic radiation in the blue or green or red spectral range or in the UV range or in the IR range.

[0007] For example, the first semiconductor layer is formed with a p-type conductive material and the second semiconductor layer is formed with an n-type conductive material. Alternatively, the first semiconductor layer is formed with an n-type conductive material and the second semiconductor layer is formed with a p-type conductive material.

[0008] Here and hereinafter, a semiconductor chip is understood to be an element that can be handled individually and can be electrically contacted. The semiconductor chip is preferably produced from the wafer composite by singulation. In particular, the side surfaces of such a semiconductor chip then have traces of the singulation process from the wafer composite, for example.

[0009] The semiconductor chip preferably comprises exactly one originally connected region of the semiconductor layer sequence grown in the wafer composite. The semiconductor layer sequence of the semiconductor chip is preferably formed in a connected manner. The lateral extent of the semiconductor chip measured parallel to the semiconductor layer sequence or the main extension plane of the semiconductor chip is, for example, at most 5% or at most 10% greater than the lateral extent of the semiconductor layer sequence.

[0010] According to at least one embodiment, the optoelectronic semiconductor chip comprises a first contact structure having a plurality of first contact pins for electrically contacting the first semiconductor layer and a first contact layer. In particular, in normal operation, the first semiconductor layer is supplied with current via the first contact structure. Preferably, the first contact layer comprises a metal, such as gold, silver, aluminum, palladium, platinum, titanium, nickel, a conductive oxide or consists of one of these materials or a mixture of these materials.

[0011] According to at least one embodiment of the optoelectronic semiconductor chip, the optoelectronic semiconductor chip comprises a second contact structure for electrically contacting the second semiconductor layer. In particular, in normal operation, the second semiconductor layer is electrically connected via the second contact structure. Preferably, the second contact structure comprises a metal, such as gold, silver, aluminum, palladium, platinum, titanium, nickel, a conductive oxide, or consists of one of these materials or a mixture of these materials. The second contact structure is formed, for example, from the same material as the first contact layer.

[0012] According to at least one embodiment, the first semiconductor layer is arranged between the first contact layer and the active layer. For example, the main extension planes of the first semiconductor layer, the first contact layer and the active layer extend substantially parallel to each other. In particular, the first semiconductor layer and the active layer have the same lateral extension within the scope of manufacturing tolerances. Here and hereinafter, the term "lateral extension" of a layer means an extension in a plane extending parallel to the main extension plane of the layer. In particular, the first semiconductor layer is adjacent to the active layer and the first contact pin. Preferably, the first semiconductor layer is in direct contact with the active layer and with the first contact pin.

[0013] According to at least one embodiment, the first contact pin is arranged between the first semiconductor layer and the first contact layer. For example, the first contact layer is not in direct contact with the first semiconductor layer. In particular, the first contact layer is in electrical contact with the first semiconductor layer only via the first contact pin.

[0014] According to at least one embodiment, the first contact pins are arranged separated and spaced apart from each other in a lateral direction. Here and hereinafter, "lateral direction" refers to a direction extending parallel to the main extension plane of the active layer. In particular, the first contact pins are electrically insulated from each other in the lateral direction. That is, two arbitrary first contact pins are only conductively connected to each other via the first contact layer and / or the first semiconductor layer. For example, the intermediate space between two arbitrary, adjacent first contact pins is filled with an electrically insulating material. The electrically insulating material, for example, includes or consists of silicon dioxide and / or silicon nitride and / or aluminum oxide. Alternatively, the space between the two first contact pins is filled with air or a gas. For example, the spacing between two adjacent first contact pins in the lateral direction is at least 2 μm or at least 4 μm or at least 6 μm or at least 8 μm.

[0015] According to at least one embodiment, an electrical connection with a resistance is formed between the first contact layer and the first semiconductor layer by each first contact pin. For example, the first semiconductor layer is energized via the first contact pin during normal operation. Preferably, charge carriers can be exchanged between the first semiconductor layer and the first contact layer only via the first contact pin. In this case, the current passes through the resistor on its path from the first contact layer to the first semiconductor layer through the contact pin.

[0016] According to at least one embodiment, the first contact pins are selected such that the electrical connections formed by two different first contact pins have different resistances. "Different resistances" here means that the resistances are differently preset, i.e. not only due to manufacturing tolerances. For example, the resistance of one electrical connection is at least 1.1 times, or at least 1.2 times, or at least 1.5 times, the resistance of the other electrical connection. Preferably, the larger resistance is at most 10 times, or at most 5 times, the smaller resistance.

[0017] For example, the first contact pins are selected such that all electrical connections formed by the first contact pins, except for one electrical connection formed by the first contact pin, have the same resistance within the scope of manufacturing tolerances. The electrical connections formed by the remaining first contact pins have a different resistance value than the other electrical connections.

[0018] Alternatively, the first contact pins are selected such that each individual electrical connection has a resistance that the other electrical connections generally do not have. In this case, the resistances of the electrical connections formed by the first contact pins are different in pairs.

[0019] In at least one embodiment, the optoelectronic semiconductor chip includes a semiconductor layer sequence having a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer. The optoelectronic semiconductor chip includes a first contact structure having a plurality of first contact pins and a first contact layer for electrically contacting the first semiconductor layer, and includes a second contact structure for electrically contacting the second semiconductor layer. The first semiconductor layer is arranged between the first contact layer and the active layer. The first contact pins are arranged between the first contact layer and the first semiconductor layer and are separated and spaced apart from each other in a lateral direction. An electrical connection with resistance is formed between the first contact layer and the first semiconductor layer by each first contact pin. Here, the first contact pins are selected so that the electrical connection formed by two different first contact pins has different resistances.

[0020] Here, the optoelectronic semiconductor chip described here is based in particular on the following considerations. In order to achieve a luminous image that is as uniform as possible and a temperature distribution that is as uniform as possible, it is necessary to evenly energize the optoelectronic semiconductor chip via a surface that is as large as possible. If the external connection location of the semiconductor chip is placed on the outside of the semiconductor chip, then the voltage drop within the current-guiding layer causes an uneven current density distribution, which has an impact on the uneven light density distribution of the semiconductor chip and / or the uneven temperature distribution within the semiconductor chip. Typically, the improved current distribution can be achieved by increasing the layer thickness of the current-guiding layer. However, the increase in layer thickness only has a global impact on the entire semiconductor chip, and thus a local increase in current density cannot be achieved. Local changes in layer thickness can cause the desired effect, but are technically expensive. Alternatively, the current-guiding element is adjusted to affect the local current density, wherein the current-guiding element is in direct contact with the semiconductor layer sequence. For example, this influence is carried out via the adjustment of the contact structure of the semiconductor layer belonging to the n-type conduction.

[0021] The optoelectronic semiconductor chip described here also uses the concept of influencing the current density locally by influencing the p-type contact structure. For this purpose, the p-type contact structure comprises a current-conducting contact layer, which is electrically contacted to the semiconductor layer sequence via a contact pin. In this case, the resistance through which the current flows through the contact pin is specifically influenced in order to compensate for the voltage drop in the contact layer and to achieve a current density distribution that is as uniform as possible in the semiconductor chip.

[0022] Advantageously, a more uniform current density distribution results in a more uniform light image of the semiconductor chip and a more uniform temperature distribution within the semiconductor chip. Both can reduce aging effects. An optoelectronic semiconductor chip with a uniform light density is desirable, for example, for applications with imaging optical devices. In addition, the selection of an optimized process or operating point of the optoelectronic semiconductor chip becomes easier.

[0023] Furthermore, adaptation to a specific application can alternatively be achieved. For example, a local temperature increase is desirable because the application here has a heat sink. By selectively increasing the current density locally in the region of the heat sink, an increased efficiency and durability of the optoelectronic semiconductor chip in the application can be achieved.

[0024] According to at least one embodiment of the optoelectronic semiconductor chip, the first contact pins are in direct contact with the first semiconductor layer via contact surfaces. The areas of the contact surfaces of two different first contact pins are selected to be different. For example, the area of ​​the contact surface of one first contact pin is at least 1.1 times, at least 1.2 times, or at least 1.5 times the area of ​​the contact surface of another first contact pin.

[0025] The contact resistance of the first contact pin to the first semiconductor layer can be influenced by selecting the area of ​​the contact surface. As a result, the resistance of the electrical connection formed between the first contact layer and the first semiconductor layer by the first contact pin can be influenced. For example, the contact surface has a pentagonal shape. The pentagon has, for example, a width between 19 μm and 26 μm and a length between 26 μm and 33 μm. The length and width are two dimensions of the pentagon that are perpendicular to each other in the transverse plane.

[0026] For example, the contact surface area is 500 μm 2 and 850 μm 2 Advantageously, the influencing of the contact surface during production is particularly simple, for example by means of a lift-off process or a photographic technique and subsequent active structuring by means of a wet or dry etching process.

[0027] According to at least one embodiment, the lateral extension of the two different first contact pins is selected differently. For example, the first contact pin has a circular or pentagonal basic contour in a transverse plane. In particular, the diameters of the two different first contact pins are also selected to be different. In particular, the first contact pin has an extension, referred to below as length, in a direction perpendicular to its transverse plane. The lateral extension of the first contact pin is, for example, constant over its entire length within the scope of manufacturing tolerances. Preferably, all first contact pins have the same length within the scope of manufacturing tolerances.

[0028] Preferably, the lateral extension of the first contact pin increases or decreases suddenly at a specific length. For example, the lateral extension of the first contact pin is constant from its side facing the first contact layer up to a specific length and then increases or decreases suddenly, respectively, wherein the lateral extension is constant over the entire remaining length after the sudden change. The length in which the lateral extension changes suddenly is, for example, between 2% and 50% of the total length of the first contact pin, inclusive, preferably between 2% and 15%, inclusive. Alternatively, the length in which the lateral extension changes suddenly is between 50% and 98% of the total length of the first contact pin, inclusive, preferably between 80% and 98%, inclusive. The lateral extension of the first contact pin after the sudden change is, for example, at most 10% or at most 40% or at most 80% of the lateral extension before the sudden change. Alternatively, the lateral extension after the sudden change is, for example, at least 1.5 times, 2 times or 10 times greater than before the sudden change. In particular, the lengths of two different first contact pins, in which the abrupt change in the lateral extent occurs, and / or the abrupt change in the lateral extent, are selected to be different.

[0029] Advantageously, the resistance of the electrical connection between the first contact layer and the first semiconductor layer, which connection is formed by the first contact pin, can be influenced particularly easily by means of a targeted choice of the lateral extent of the first contact pin.

[0030] According to at least one embodiment, the material composition of the two different first contact pins is selected to be different. For example, the first contact pin is partially or completely formed of a metal or a conductive oxide. For example, the first contact pin comprises gold, silver, aluminum, target, platinum, titanium, nickel, a conductive oxide or is composed of one of these materials or a mixture of these materials. In particular, the materials of the different first contact pins are different. For example, the two different first contact pins are formed of at least partially different materials. Alternatively, the two different first contact pins are formed of the same material, but the proportions of the different materials are different. For example, the first contact pin is based on gold or is formed of a gold alloy. In this case, the different first contact pins differ, for example, in the gold content of the corresponding alloy.

[0031] According to at least one embodiment, the first contact pin is selected such that the resistance of the electrical connection decreases monotonically in the lateral direction. For example, the resistance of the first contact pin decreases monotonically from the side of the semiconductor chip as the spacing of the side increases, wherein the side connects the second semiconductor layer and the side of the first semiconductor layer facing away from the active region to each other. Alternatively, the resistance of the first contact pin increases monotonically from such a side. Preferably, all electrical connections formed by the first contact pin have the same resistance, wherein the first contact pin has the same spacing from the side within the range of manufacturing tolerances. Advantageously, voltage drops can be particularly well compensated along the lateral direction by electrical connections having a monotonically decreasing resistance in this direction, thereby achieving a uniform current distribution in the semiconductor layer sequence.

[0032] For example, the first contact pin is selected such that the resistance of the electrical connection additionally decreases monotonically along the second lateral direction. In particular, the lateral direction and the second lateral direction are perpendicular to one another.

[0033] The electrical connection formed by the first contact pin having the smallest possible distance to the side surface has, for example, a resistance that is at least 1.2 times, at least 1.5 times, or at least 2 times greater than the electrical connection formed by the first contact pin having the largest possible distance to the side surface. The resistance of the electrical connection formed by the first contact pin that does not have the smallest possible distance and the largest possible distance to the side surface preferably decreases linearly as a function of the distance to the side surface.

[0034] According to at least one embodiment, the semiconductor layer sequence has at least two non-intersecting regions which are adjacent to each other in a lateral direction. A plurality of first contact pins are respectively associated with the regions. The first contact pins associated with the common regions are selected so that the electrical connections formed by them all have the same resistance (within the range of manufacturing tolerances). The first contact pins associated with different regions are selected so that the electrical connections realized by them have different resistances. The resistances differ from each other by at least 10% or at least 20% or at least 50%, for example.

[0035] For example, the regions are connected, preferably singly connected, respectively. Preferably, all regions have the same size. In particular, the same number of first contact pins are associated with each region. For example, each region has at least 80 first contact pins or at least 100 first contact pins or at least 200 first contact pins. Alternatively or additionally, each region can have a maximum of 300 or a maximum of 400 or a maximum of 600 first contact pins. For example, all these first contact pins have the same large contact surface with the first semiconductor layer and / or all have the same lateral extension and / or all have the same material composition. The first contact pins associated with different regions are different in at least one of the characteristics, for example, and the electrical connections formed therefrom have different resistances.

[0036] According to at least one embodiment, the first contact pins each comprise an oxide layer. The oxide layer is formed by a transparent conductive oxide. The oxide layer is in direct contact with the first semiconductor layer via a contact surface. For example, the transparent conductive oxide comprises indium tin oxide, ITO for short, and / or other tin oxide compounds, such as tin oxide doped with fluorine or tin oxide doped with antimony. In particular, the oxide layer is transparent to the radiation emitted by the semiconductor chip. For example, the absorption coefficient of the material of the oxide layer is sufficiently small for the radiation emitted by the semiconductor chip, so that less than 5%, preferably less than 1% of the emitted power is absorbed.

[0037] For example, the contact surface of the oxide layer and the first semiconductor layer substantially determines the contact resistance of the first contact pin. In particular, the resistance of the first contact pin can be influenced by selecting the area of ​​the contact surface. The use of an at least partially transparent first contact pin has the advantage that the first contact pin does not have a strong influence on the brightness of the optoelectronic semiconductor chip.

[0038] According to at least one embodiment, the first contact pins each have a metal layer. In each first contact pin, the metal layer is in direct contact with the oxide layer via an interface. The contact surface and the interface are opposite sides of the oxide layer. For example, the metal layer comprises gold, silver, aluminum, palladium, platinum, titanium, nickel or is composed of one of these materials or a mixture of these materials. In particular, the metal layer comprises the same material as the first contact layer. Preferably, the metal layer is in direct contact with the first contact layer, respectively. More preferably, the metal layer is formed in one piece with the first contact layer. In particular, the metal layer is not in direct contact with the semiconductor layer sequence. For example, the resistance of the first contact pin can be selected by means of the material composition of the metal layer.

[0039] According to at least one embodiment, the areas of the boundary surfaces of two different first contact pins are different. If, for example, the first contact pin conducts an electric current, the resistance through which the current flows is also determined by the size of the boundary surface between the metal layer and the oxide layer. Advantageously, the resistance of the electrical connection formed by the first contact pin can thus be selected by appropriately selecting the area of ​​the boundary surface of the first contact pin. For example, the area of ​​the boundary surface of one first contact pin is at least 1.1 times, or at least 1.2 times, or at least 1.5 times the area of ​​the boundary surface of the other first contact pin.

[0040] Preferably, the contact surface of the first contact pins is in each case at least 5 times, at least 10 times, or at least 20 times larger than the area of ​​the associated boundary surface.

[0041] According to at least one embodiment, the optoelectronic semiconductor chip has a bottom side. The first semiconductor layer is arranged between the bottom side and the active layer. The optoelectronic semiconductor chip has a first connection surface and a second connection surface for electrically contacting the semiconductor chip from the outside. The first connection surface is conductively connected to the first contact structure and the second connection surface is conductively connected to the second contact structure. In addition, the first connection surface and the second connection surface are exposed in a non-contact state of the semiconductor chip. For example, the optoelectronic semiconductor chip can be operated from the outside via the first connection surface and the second connection surface. For this purpose, for example, the first connection surface and the second connection surface are contacted with contact wires and supplied with current. In particular, the semiconductor layer sequence is electrically contacted via the conductive connection of the first connection surface to the first contact structure and the second connection surface to the second contact structure.

[0042] The bottom side is, for example, the side of the semiconductor chip via which the semiconductor chip is mounted in the application. For example, in the application, the optoelectronic semiconductor chip is mounted in a housing and / or on a lead frame via the bottom side. Preferably, the optoelectronic semiconductor chip has a radiation side, which is opposite the bottom side. For example, the optoelectronic semiconductor chip emits a large part of all its emitted radiation via the radiation side. In particular, the semiconductor chip emits more than 50% or more than 70% or more than 85% of all its emitted radiation via the radiation side. For example, the optoelectronic semiconductor chip is a so-called thin-film chip. For example, the optoelectronic semiconductor chip is used as a light source in a headlight, for example for a motor vehicle. Advantageously, the optoelectronic semiconductor chip described here with a particularly uniform current density distribution and thus a particularly uniform light density distribution forms a light source that is particularly well suited for use in a headlight.

[0043] According to at least one embodiment, the first connection surface is a surface of the optoelectronic semiconductor chip that is opposite to the bottom side. The first connection surface is formed on the edge of the optoelectronic semiconductor chip. For example, by arranging the first connection surface on a surface of the semiconductor chip that is opposite to the bottom side, it is possible to contact the first connection surface from the outside in the direction of the radiation side. Advantageously, the optoelectronic semiconductor chip can thus be mounted particularly simply via its bottom side in the application case, because the first connection surface is contacted from the outside in the direction opposite to the bottom side. For example, the second connection surface is also arranged on the side of the semiconductor chip that faces away from the bottom side. Thus, in this case, the first and second connection surfaces can be contacted from a common direction. For example, the second connection surface forms part of the radiation side.

[0044] In particular, the edge of the optoelectronic semiconductor chip adjoins a side surface of the optoelectronic semiconductor chip. A side surface is an outer surface of the semiconductor chip which extends transversely to a main extension plane of the semiconductor layer sequence and connects the radiation side to the bottom side. Preferably, the first connection surface adjoins the side surface.

[0045] For example, in a lateral direction the first contact layer has a greater extent than the semiconductor layer sequence. In particular, the side of the first contact layer facing away from the bottom then forms the first connection surface. In particular, the part of this side of the first contact layer that forms the first connection surface does not have the semiconductor layer sequence.

[0046] According to at least one embodiment, the first connection surface forms at least a part of the bottom side of the optoelectronic semiconductor chip. For example, the first connection surface is then electrically contacted from the bottom side. For example, the optoelectronic semiconductor chip is mounted on a lead frame in the application, so that an electrical connection is produced between the lead frame and the bottom side of the optoelectronic semiconductor chip. For example, the entire bottom side of the optoelectronic semiconductor chip forms the first connection surface.

[0047] According to at least one embodiment, the second contact structure comprises a plurality of contact strips. The contact strips are arranged on the side of the second semiconductor layer facing away from the active layer and preferably extend substantially parallel to each other. For example, the second contact structure forms part of the radiation side of the optoelectronic semiconductor chip. In particular, the contact strips are in direct contact with the second semiconductor layer. In addition, for example, the second connection surface is formed as part of the radiation side, thereby advantageously simplifying the electrical contacting of the second contact structure via the second connection surface. For example, the contact strips extend substantially parallel to the outer edge of the radiation side. The outer edge of the radiation side is here a line of the radiation side that delimits the radiation side in the lateral direction.

[0048] For example, the contact strip is selected so that a particularly uniform current density distribution is achieved in the second semiconductor layer. For this purpose, for example, the diameter of the contact strip is selected in a suitable manner. In particular, the width of the contact strip increases along its main extension direction from the second connection surface. The diameter is the extension of the contact strip measured perpendicular to the main extension direction of the contact strip.

[0049] According to at least one embodiment, the second contact structure includes a plurality of vias and a second contact layer. The vias are in direct contact with the second semiconductor layer and the second contact layer is arranged on the side of the first contact layer facing away from the semiconductor layer sequence. The vias penetrate the first contact layer, the first semiconductor layer and the active layer respectively and are electrically insulated relative to them. An electrical connection between the second contact layer and the second semiconductor layer is formed by each via. In particular, a resistor is associated with each of the electrical connections. For example, the resistor can be specifically influenced. The features disclosed for the influence of the resistance of the first contact pin are preferably also disclosed for the influence of the resistance of the via and vice versa.

[0050] For example, an optoelectronic semiconductor chip comprising a via is a so-called thin-film chip with a via design. For example, in such an optoelectronic semiconductor chip, the first connection area and the second connection area are formed as part of the bottom side. For example, in the case of application, such an optoelectronic semiconductor chip can be mounted particularly easily on a current-carrying surface and electrically contacted. In particular, the use of contact wires can be dispensed with.

[0051] According to at least one embodiment, the active layer and / or the first semiconductor layer and / or the second semiconductor layer are each designed to be simply connected. In particular, such a semiconductor chip does not comprise any vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Further advantages and advantageous embodiments of the optoelectronic semiconductor chip are apparent from the following exemplary embodiments illustrated in conjunction with the drawings. Identical elements, elements of the same type or elements that function in the same manner are provided with the same reference numerals in the drawings. The drawings and the size relationships of the elements illustrated in the drawings to one another are not to be regarded as true to scale. Rather, individual elements are illustrated with an exaggerated size for the sake of better illustration and / or for the sake of better understanding.

[0053] The accompanying drawings show:

[0054] Figure 1A , 1B 8 show different views of an exemplary embodiment of an optoelectronic semiconductor chip;

[0055] Figure 2 a schematic cross-sectional view showing a detail of an embodiment of a first contact pin;

[0056] Figure 3 A top view showing a variant of a semiconductor chip;

[0057] Figures 4A to 4C , 6A and 6B show detailed views of contact pins in an embodiment of a semiconductor chip;

[0058] Figure 4D A detailed view showing a contact pin in a variant of a semiconductor chip;

[0059] Figure 5 a graph showing the accumulated current density for different types of configurations of the first contact pin; and

[0060] Figure 7 Graph showing the optical density for different types of configurations of the first contact pins. DETAILED DESCRIPTION

[0061] exist Figure 1A 1 shows a perspective view of a first exemplary embodiment of an optoelectronic semiconductor chip 1 described here. The optoelectronic semiconductor chip 1 comprises a semiconductor layer sequence 10 having a first semiconductor layer 101, a second semiconductor layer 102 and an active layer 103 arranged between the first semiconductor layer 101 and the second semiconductor layer 102. Furthermore, the optoelectronic semiconductor chip 1 comprises a first contact layer 210, wherein the first semiconductor layer 101 is arranged between the active layer 103 and the first contact layer 210.

[0062] Preferably, the first contact layer 210 includes at least one metal or is formed by a metal. For example, the first contact layer 210 is based on gold. The semiconductor layer sequence 10 is based on InGaAlP, for example. In particular, the first semiconductor layer 101 is doped with a p-type dopant and the second semiconductor layer 102 is doped with an n-type dopant. The first contact layer 210 forms a first contact structure together with the first contact pin 21. The semiconductor layer sequence 10, in particular the first semiconductor layer 101, can be structured between the first contact pins 21. For example, for this purpose, the semiconductor material between the first contact pins 21 can be removed by etching. Etching can be performed, for example, dry chemically or wet chemically. The structured portion of the first semiconductor layer 101 produced by etching and / or the first contact pin 21 can therefore have an etching angle.

[0063] The optoelectronic semiconductor chip 1 further comprises a bottom side 1a. The bottom side 1a is formed here by the side of the carrier 40 which faces away from the first contact layer 210. Preferably, the carrier 40 is characterized by a coefficient of thermal expansion that is matched to the first contact layer 210 and / or the semiconductor layer sequence 10, so as to avoid stresses that may occur when the optoelectronic semiconductor chip 1 heats up during operation. For example, the carrier 40 may comprise semiconductor materials such as germanium, gallium arsenide, gallium nitride, silicon and / or other materials such as sapphire, silicon nitride, aluminum nitride and metals. In addition, the carrier 40 has a high thermal conductivity in particular, so that the heat generated during normal operation can be at least partially output to the surroundings via the carrier 40.

[0064] Preferably, the carrier 40 comprises a mirror layer. The mirror layer comprises, for example, a Bragg mirror, a dielectric mirror or a metal-containing mirror layer. It is also preferred that the side of the carrier 40 facing the semiconductor layer sequence 10 is formed as a mirror. For example, the side of the carrier 40 is formed by a material, such as a metal or a metal alloy, which at least partially reflects the radiation generated in the active layer 103. For example, the side of the carrier 40 facing the semiconductor layer sequence 10 reflects at least 80% or at least 90% or at least 95% of the radiation generated in the active layer 103. Advantageously, the light loss can be reduced by the mirror-reflecting carrier 40.

[0065] The optoelectronic semiconductor chip 1 further comprises a first connection surface 20. The first connection surface 20 is arranged on the side of the optoelectronic semiconductor chip 1 facing away from the bottom side 1a, here on the side of the first contact layer 210 facing away from the bottom side 1a. The second contact structure of the optoelectronic semiconductor chip 1 comprises a contact web 31. The contact web 31 is electrically conductively connected to the second connection surface 30, which is arranged on the side of the second semiconductor layer 102 facing away from the active layer 103. The contact web 31 is in direct contact with the second semiconductor layer 102 in particular.

[0066] The first contact pin 21 is in direct contact with the first semiconductor layer 101 via the contact surface 21a. In the present exemplary embodiment, the semiconductor chip 1 is not contacted from the outside, so that the first connection surface 20 and the second connection surface 30 are exposed. In normal operation, the optoelectronic semiconductor chip 1 is contacted from the outside, for example, by means of contact wires. During operation, the first contact structure and the second contact structure are therefore energized via the first connection surface 20 and the second connection surface 30. The semiconductor layer sequence 10 is energized by means of the contact tab 31 and the first contact pin 21. Preferably, the contact tab 31, viewed in the vertical direction, is arranged without overlapping the first contact pin 21.

[0067] An electrical connection is formed between the first contact layer 210 and the first semiconductor layer 101 by the first contact pin 21. The electrical connections have a resistance. In the present embodiment, different contact surfaces 21a have different areas and different lateral extensions. Due to the different contact surfaces 21a and lateral extensions of the first contact pin 21, different electrical connections formed by different first contact pins 21 have different resistances. Here, the contact surface 21a with a larger spacing from the first connection surface 20 has a larger area compared to the contact surface 21a with a smaller spacing from the connection surface 20. Thus, the electrical connection with a larger spacing from the connection surface 20 has a smaller resistance. Advantageously, the voltage drop in the first contact layer 210 can be compensated and the first semiconductor layer 101 can be energized by means of a uniform current distribution.

[0068] exist Figure 1B 2 shows a perspective view of a second exemplary embodiment of an optoelectronic semiconductor chip 1 . Figure 1B Basically, it shows Figure 1A The same features, except that the contact layer 210 has the same lateral extension as the semiconductor layer sequence 10. In addition, the side of the first contact layer 210 facing away from the semiconductor layer sequence 10 forms the bottom side 1a of the optoelectronic semiconductor chip 1. The first connection surface 20 is arranged on the bottom side 1a of the optoelectronic semiconductor chip 1. Another difference from the first embodiment of the optoelectronic semiconductor chip is that the contact surfaces 21a all have the same area. For example, the intrinsic resistance of the first contact pins 21 then has different values. As a result, the electrical connections formed by the first contact pins 21 also have different values ​​of resistance. In particular, for example, the material composition of different first contact pins 21 is selected so that different electrical connections have different resistances.

[0069] exist Figure 2, a schematic cross-sectional view of a detail of a first contact pin 21 according to a first embodiment is shown. The first contact pin 21 comprises a metal layer 211 and an oxide layer 212, which are formed of a transparent conductive oxide. The oxide layer 212 is in direct contact with the first semiconductor layer 101 via a contact surface 21a and in direct contact with the metal layer 211 via a boundary surface 21b. The metal layer 211 is in direct contact with the first contact layer 210. The area between the first semiconductor layer 101 and the first contact layer 210 that is not filled by the first contact pin 21 is filled with an electrically insulating material 50, such as silicon oxide or silicon nitride. Alternatively, the electrically insulating material can also be air or a gas. Thus, the first contact pin 21 comprises a first region 201 and a second region 202, wherein the first region 201 of the first contact pin 21 is formed by a section of the metal layer 211, and the second region 202 of the first contact pin 21 is formed by a section of the oxide layer 212 that is adjacent to the section of the metal layer 211. Similar conclusions apply to each first contact pin 21. That is, each first contact pin 21 includes a first region 201 and a second region. The second region 202 of each first contact pin 21 advantageously has a greater lateral extension than its first region 201, so that better current spreading can be achieved. In particular, the oxide layer 212 of the first contact pin 21 or a section of the oxide layer 212 can each be formed only for current spreading.

[0070] The first contact pin 21 forms an electrical connection between the first semiconductor layer 101 and the first contact layer 210. The electrical connection has an electrical resistance. The electrical resistance is determined by the size of the contact surface 21a, the size of the boundary surface 21b, the material composition of the oxide layer 212, the material composition of the metal layer 211, and the lateral and longitudinal extension of the oxide layer 212 and the metal layer 211. The electrical resistance can be preset by adjusting these properties of the first contact pin 21. Advantageously, the configuration of the first contact pin 21 described here provides particularly many possibilities for adjusting the electrical resistance of the electrical connection formed by the first contact pin 21. As a result, a particularly large value range of the electrical resistance can be advantageously selected.

[0071] Figure 3 A top view of a variant of a semiconductor chip with a current density distribution is schematically shown on the side facing away from the bottom 1a of the semiconductor chip 1. For example, the expansion of the semiconductor chip in the X direction is between 500 μm and 3000 μm, inclusive, and the expansion in the Y direction is between 500 μm and 3000 μm, inclusive. In particular, the expansion of the semiconductor chip in the X direction and in the Y direction is respectively between 1000 μm and 2000 μm, inclusive.

[0072] The first contact pins 21 of this variant form each have a contact surface 21a. The first contact pins 21 are all formed identically within the scope of manufacturing tolerances. The first contact pins 21 are arranged in strips. This means that the first contact pins 21 are unevenly distributed on the side shown in the top view. More precisely, the density in the area of ​​the strip-shaped sections on the first contact pins 21 is greater than the density outside these sections. These sections basically all have the same size and extend parallel to each other. The contact surfaces 21a of the first contact pins 21 are each configured as a pentagon here.

[0073] Furthermore, the optoelectronic semiconductor chip 1 has a first connection area 20 and a second connection area 30 which are arranged at the edge of the optoelectronic semiconductor chip 1. The first connection area 20 and the second connection area 30 are arranged on the side of the semiconductor chip 1 facing away from the bottom side 1a and can be contacted from a common direction.

[0074] In this variant, A / m 2 The current density i measured in units of 1.4 mA / m in a region of the semiconductor chip in which the first contact pin 21 has a small distance from the first connection area 20 in the direction X has 1.4 mA / m 2 As the distance from the connection surface 20 along the X direction increases, the current density i decreases to about 0.6MA / m 2 The reduction in current density is caused by the voltage drop along the first contact surface and the identical design of all contact pins.

[0075] exist Figure 4A 1 shows a strip of first contact pins 21 in one embodiment of a semiconductor chip. Such a strip is used, for example, in the embodiment of FIG. 1 . The area of ​​the contact surface 21 a increases in the X direction. As a result, the electrical connection formed by the first contact pins 21 at a large distance from the first connection surface 20 in the X direction has a lower resistance than the electrical connection formed by the first contact pins 21 at a small distance from the first connection surface 20 in the X direction. By selecting the first contact pins 21 in this way, the distribution of the current density i can be influenced in a targeted manner and can be controlled with the Figure 3 Thus, the optical density can also be made uniform.

[0076] Figure 4B A strip of first contact pins 21 is shown in another exemplary embodiment of a semiconductor chip. Figure 4B Basically, it shows Figure 4AThe same features, with the following difference: the area of ​​the contact surface 21a decreases with increasing distance from the first connection surface 20 in the X direction. As a result of this selection of the first contact pins 21, the current density i is increased in the region of the optoelectronic semiconductor chip 1 which has a small distance from the first connection surface 20, because the resistance of the electrical connection formed by the first contact pins 21 in this region is reduced compared to the region with a larger distance. This local increase in the current density i leads in particular to a local increase in the light density and / or the temperature during operation of the semiconductor chip 1. This results in advantages in the application case when, for example, special optical devices for imaging are arranged downstream of the region of increased light density in the emission direction.

[0077] exist Figure 4C 2 shows a strip of first contact pins 21 in a further exemplary embodiment of a semiconductor chip. Figure 4C Basically, it shows Figure 4A The same features, with the following difference: the area of ​​the contact surface 21a is the same throughout within the scope of manufacturing tolerances, but the area of ​​the boundary surface 21b between the oxide layer 212 and the metal layer 211 increases monotonically in the X direction. The increase causes the resistance of the electrical connection formed by the first contact pin 21 to decrease in the X direction. This results in a quantitative difference with the Figure 4A The same effect is achieved by selecting the area of ​​the contact surface 21a as described above.

[0078] exist Figure 4D According to Figure 3 In a variant of the semiconductor chip of FIG. 1 , a strip of first contact pins 21 is formed. Here, the contact pins 21 are Figure 4A The contact pins 21 of the first contact pins 21 are different, but all have the same area. In addition, all first contact pins 21 have the same lateral extension. In particular, the electrical connections formed by the first contact pins 21 all have the same resistance within the scope of manufacturing tolerances.

[0079] Figure 5 The relative cumulative current density I for four cases is shown. The four cases correspond to Figures 4A to 4C Embodiments and according to Figure 4D A variation of Figure 4A Embodiment, dotted line describes according to Figure 4B Embodiment, the dotted line describes the Figure 4C The embodiment and the thin line are used as the basis Figure 4D The current density i is integrated along the X direction and is shown in the present figure as the accumulated current density I. Therefore, the curve describes the value of the current density integrated up to this spacing for each spacing along the X direction. All curves are normalized to the reference, wherein the reference corresponds to the value according to Figure 3A variant of an optoelectronic semiconductor chip of , in which the electrical connections formed by the first contact pins 21 all have the same resistance.

[0080] according to Figure 4A The graph of the embodiment of FIG. 1 shows that the relative cumulative current density I increases in the X direction relative to the reference. As a result, more current flows into the semiconductor layer sequence 10 via the first contact pin 21 which has a large distance from the first connection surface 20 in the X direction compared to the reference. As a result, the pressure drop in the first contact layer 210 in the X direction can be compensated and a more uniform light density distribution can be achieved. The same applies to the embodiment according to Figure 4C The opposite situation is based on Figure 4B This is the case of an embodiment of the invention, in which the accumulated current density I decreases as the distance from the first connection surface 20 along the X direction increases compared to the reference.

[0081] exist Fig. 6A , a detailed view of the first contact pin 21 is shown looking down toward the contact surface 21a. The contact surface 21a has a pentagonal shape. The width D1 of the pentagon measured parallel to the X direction is, for example, between 19 μm and 26 μm, inclusive. The length D2 of the pentagon measured parallel to the Y direction is, for example, between 26 μm and 33 μm, inclusive. The spacing D3 between two pentagons measured along the X direction is, for example, between 2 μm and 8 μm, inclusive.

[0082] exist Figure 6B A detailed view of a strip of first contact pins 21 is shown in FIG. Figure 6B Herein, Figure 4A Basically the same features, with the following differences: The contact surface 21a is increased in sections. The first contact pin 21 is associated with four areas B1 to B4. In each area B1 to B4, the contact surface 21a has basically the same area and the same spacing between each other. In particular, the electrical connections formed by the first contact pins 21 associated with the common areas B1 to B4 have the same resistance within the scope of manufacturing tolerances. The contact surfaces 21a of different areas have different areas and thus the electrical connections formed by the corresponding first contact pins 21 have different resistances. In the X direction, the area of ​​the contact surface 21a increases in sections. For example, the value of the width D1 of the contact surface measured over the entire extension parallel to the X direction increases by 8 nm per μm. At the same time, for example, the value of the length D2 increases by 8.5 nm per μm and the spacing D3 increases by 8 nm per μm. The entire extension parallel to the X direction is, for example, between 700 μm and 1200 μm, inclusive.

[0083] exist Figure 72 shows a diagram of the relative integrated light density L of an optoelectronic semiconductor chip 1 according to two exemplary embodiments and a reference. The reference is essentially a variant of a semiconductor chip in which the electrical connections formed by the first contact pins 21 all have the same resistance. The exemplary embodiment is essentially based on Figure 6B Embodiments of the present invention, in which the contact surface 21a of the first contact pin 21 increases in sections. In particular, the X direction extends from the first connection surface 20 in each case. The curves describe the light density L integrated in the Y direction for each distance from the first connection surface in the X direction. All curves shown are normalized to their maximum values ​​in each case. In other words, the graph shows the normalized light density L as a function of the distance from the first connection surface 20 in the X direction.

[0084] The solid line shows a reference. The light density L decreases continuously with increasing distance from the connection area 20 in the X direction. At the outer edge of the optoelectronic semiconductor chip opposite the connection area, the light density L is less than 85% of the light density L in the direct vicinity of the connection area.

[0085] The dashed line shows the light density of an exemplary embodiment of an optoelectronic semiconductor chip 1, in which the semiconductor layer sequence 10 has three non-intersecting regions B1 to B3. The three regions preferably all have the same lateral extension. In particular, the electrical connections formed by the first contact pins 21 associated with the common region all have the same resistance within the scope of manufacturing tolerances. However, the electrical connections formed by the first contact pins 21 associated with different regions have different resistances. For example, the resistances differ by 5%, 10% or 20%. In Figure 7 It can be clearly seen in FIG. 1 that the local adjustment of the resistors results in a homogenization of the light density L. The light density L is at least 90% of the maximum light density for each distance between the first contact pin 21 and the first connection area 20 .

[0086] The dotted line essentially relates to the optoelectronic semiconductor chip 1 on which it is based, with the following difference: the semiconductor layer sequence 10 is divided into four non-intersecting regions B1 to B4. In the present case, a homogenization of the integrated light density L can also be achieved. In this case, the values ​​do not fall below 80% of the maximum light density L at any point in time. In particular, the effect of a reduction in the light density L with increasing distance from the connection area 20 in the X direction can be counteracted.

[0087] Figure 8An optoelectronic semiconductor chip 1 according to another embodiment is shown. The present optoelectronic semiconductor chip 1 shows essentially the same features as the semiconductor chip according to FIG. 1 , with the following difference: the second contact structure comprises a via 32 and a second contact layer 310. In addition, the second connection surface 30 is arranged on the lower side 1a of the optoelectronic semiconductor chip. The lower side 1a is formed by the side of the second contact layer 310 facing away from the semiconductor layer sequence 10. A layer composed of an electrically insulating material 51 is arranged between the first contact layer 210 and the second contact layer 310. The electrically insulating material 51 comprises, for example, silicon dioxide and / or silicon nitride and / or aluminum oxide. The via 32 completely penetrates the layer composed of the insulating material 51, the first contact layer 210, the first semiconductor layer 101 and the active layer 103. In addition, the via 32 is electrically insulated relative to the first contact layer 210, the first semiconductor layer 101 and the active layer 103 by means of the electrically insulating material 52. The electrically insulating material 52 comprises, for example, the same material as the electrically insulating material 51. In particular, the electrically insulating material 52 is formed from the same material as the electrically insulating material 51 .

[0088] The present invention is not limited to this by the description based on the exemplary embodiments. Rather, the present invention includes any new features and any combination of features, which in particular includes the combination of features in the exemplary embodiments, even if the features or the combination themselves are not exhaustively presented in the exemplary embodiments.

[0089] Reference numerals list

[0090] 1 Optoelectronic semiconductor chips

[0091] 1a Lower side

[0092] 10 Semiconductor layer sequence

[0093] 20 First connection surface

[0094] 21 First contact pin

[0095] 21a Contact surface

[0096] 21b Boundary surface

[0097] 30 Second connection surface

[0098] 31 Contact tab

[0099] 32 Vias

[0100] 40 Carrier

[0101] 50 Electrical insulation materials

[0102] 51 Electrical insulation materials

[0103] 52 Electrical insulation materials

[0104] 101 First semiconductor layer

[0105] 102 Second semiconductor layer

[0106] 103 Active layer

[0107] 201 First Area

[0108] 202 Second Area

[0109] 210 First contact layer

[0110] 211 Metal Layer

[0111] 212 Oxide layer

[0112] D1 Width

[0113] D2 Length

[0114] D3 Spacing

[0115] i Current density

[0116] I Accumulated current density

[0117] L Integrated optical density

Claims

1. An optoelectronic semiconductor chip (1), comprising: A semiconductor layer sequence (10), comprising a first semiconductor layer (101), a second semiconductor layer (102) and an active layer (103) between the first semiconductor layer (101) and the second semiconductor layer (102); A first contact structure, the first contact structure having a first contact layer (210) for electrically contacting the first semiconductor layer (101) and a plurality of first contact pins (21); and a second contact structure, the second contact structure being used for electrically contacting the second semiconductor layer (102), wherein The first semiconductor layer (101) is arranged between the first contact layer (210) and the active layer (103); The first contact pin (21) is arranged between the first semiconductor layer (101) and the first contact layer (210); The first contact pins (21) are arranged to be separated and spaced apart from each other in a transverse direction; forming an electrical connection having resistance between the first contact layer (210) and the first semiconductor layer (101) through each first contact pin (21); The first contact pins (21) are selected such that an electrical connection formed by two different first contact pins (21) has different resistances; Each first contact pin (21) comprises a first region (201) and a second region (202), The first contact pins (21) each include an oxide layer (212), wherein the oxide layer is formed of a transparent conductive oxide. The oxide layer (212) is in direct contact with the first semiconductor layer (101) via the contact surface (21a). The first contact pins (21) each include a metal layer (211), In each first contact pin (21), the metal layer (211) is in direct contact with the oxide layer (212) via a boundary surface (21b), and The contact surface (21a) and the boundary surface (21b) are opposite sides of the oxide layer (212), A first region (201) of the first contact pin (21) is formed by a section of the metal layer (211), and a second region (202) of the first contact pin (21) is formed by a section of the oxide layer (212) adjacent to the section of the metal layer (211), and the second region (202) of each first contact pin (21) has a larger lateral extension than its first region (201).

2. The optoelectronic semiconductor chip ( 1 ) as claimed in claim 1 , wherein The first contact pins (21) are in direct contact with the first semiconductor layer (101) via contact surfaces (21a). The areas of the contact surfaces (21a) of two different first contact pins (21) are selected to be different.

3. The optoelectronic semiconductor chip (1) according to claim 1 or 2, The lateral extents of two different first contact pins (21) are selected to be different.

4. The optoelectronic semiconductor chip (1) according to claim 1 or 2, The material compositions of the two different first contact pins (21) are selected to be different.

5. The optoelectronic semiconductor chip (1) according to claim 1 or 2, The first contact pin (21) is selected such that the resistance of the electrical connection decreases monotonically in a lateral direction.

6. The optoelectronic semiconductor chip (1) as claimed in claim 1 or 2, wherein The semiconductor layer sequence (10) comprises at least two regions which are adjacent to one another in a lateral direction and do not intersect each other. A plurality of first contact pins (21) are respectively associated with the regions, The first contact pins (21) associated with the common region are selected such that the electrical connections realized thereby all have the same resistance, The first contact pins (21) associated with different regions are selected such that the electrical connections realized thereby have different resistances.

7. The optoelectronic semiconductor chip (1) according to claim 1 or 2, The boundary surfaces (21b) of two different first contact pins (21) have different areas.

8. The optoelectronic semiconductor chip (1) as claimed in claim 1 or 2, wherein The optoelectronic semiconductor chip (1) has an underside (1a). The first semiconductor layer (101) is arranged between the lower side (1a) and the active layer (103), The optoelectronic semiconductor chip (1) comprises a first connection surface (20) and a second connection surface (30) for external electrical contacting of the semiconductor chip (1). The first connection surface (20) is electrically conductively connected to the first contact structure (210), The second connection surface (30) is electrically conductively connected to the second contact structure (310), In the non-contact state of the semiconductor chip (1), the first connection surface (20) and the second connection surface (30) are exposed.

9. The optoelectronic semiconductor chip (1) as claimed in claim 8, wherein The first connection area (20) forms the area of ​​the optoelectronic semiconductor chip (1) which is opposite the bottom side (1a), and The first connection area (20) is formed at an edge of the optoelectronic semiconductor chip (1).

10. The optoelectronic semiconductor chip (1) as claimed in claim 8, wherein The first connection area (20) forms at least a part of the bottom side (1a) of the optoelectronic semiconductor chip (1).

11. The optoelectronic semiconductor chip (1) as claimed in claim 1 or 2, wherein The second contact structure comprises a plurality of contact strips (31), The contact strips (31) are arranged on a side of the second semiconductor layer (102) facing away from the active layer (103) and extend substantially parallel to one another.

12. The optoelectronic semiconductor chip (1) as claimed in claim 11, wherein The second contact structure comprises a plurality of vias (32) and a second contact layer (310), The via hole (32) is in direct contact with the second semiconductor layer (102), The second contact layer (310) is arranged on a side of the first contact layer (210) facing away from the semiconductor layer sequence, The via holes (32) penetrate the first contact layer (210), the first semiconductor layer (101) and the active layer (103) respectively and are electrically insulated from them, and An electrical connection between the second contact layer (310) and the second semiconductor layer (102) is formed through each via (32).

13. The optoelectronic semiconductor chip (1) as claimed in claim 1 or 2, wherein The active layer (103) and / or The first semiconductor layer (101) and / or The second semiconductor layers (102) are each configured to be simply connected.

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