Resource management method, device, processor and equipment

Abstract

A method for resource management in a device includes: detecting the state of a thread running on a first processor core; when it is detected that the thread running on the first processor core meets a preset condition, controlling the first processor core to operate in a low power consumption mode, wherein the operating frequency of the first processor core when operating in the low power consumption mode is less than a frequency threshold, thereby reducing processor resource waste.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a method, apparatus, processor and device for resource management. Background Art

[0002] The central processing unit (CPU) of the server includes at least one processor core, each of which can run at least one polling thread, and each polling thread is bound to a shared memory in the server. The data generation module (such as a network card) of the server generates data and saves the data to the shared memory. Each polling thread bound to the shared memory can periodically detect whether the shared memory stores data. If data is detected in the shared memory, the data is obtained and processed. At present, there is not data in the shared memory all the time, but the polling thread bound to the shared memory always keeps detecting whether there is data in the shared memory, which occupies more processor computing resources and power consumption, resulting in a waste of processor resources. Summary of the invention

[0003] The present application provides a resource management method and device to reduce processor resource waste.

[0004] In a first aspect, the present application provides a resource management method, which is applied to a device, and the device includes at least one processor core. In the method, the state of a thread running on a first processor core is detected, and the first processor core is any one of the at least one processor core. When it is detected that the thread running on the first processor core meets a preset condition, the first processor core is controlled to operate in a low power consumption mode, wherein the operating frequency of the first processor core when the first processor core operates in the low power consumption mode is less than a frequency threshold. When the first processor core is controlled to operate in a low power consumption mode, each thread running on the first processor core will not occupy computing resources, and the operating frequency of the first processor core is less than the frequency threshold, so that the power consumption of the first processor core is very low, saving computing resources of the processor where the first processor core is located and reducing the power consumption of the processor.

[0005] In a possible implementation, the preset condition includes that the threads running on the first processor core are all in a suspended state, so as to ensure that the threads running on the first processor core will not be awakened for a long time, thereby ensuring that the threads will not be awakened soon after the first processor core is controlled to work in a low power consumption mode.

[0006] In another possible implementation, the threads running on the first processor core include a first thread, the first thread is bound to a shared memory included in the device, and the first thread is used to detect whether the shared memory stores data, and the shared memory is a memory space in the memory of the device. When the first thread detects that the duration of the shared memory without data exceeds a first time threshold, the state of the first thread is set to a suspended state. When the first thread detects that the duration of the shared memory without data exceeds the first time threshold, it indicates that no data will be stored in the shared memory for a long time. After the first thread is set to a suspended state, the first thread will release the occupied computing resources, thereby avoiding waste of computing resources.

[0007] In another possible implementation manner, the first thread detects the shared memory in a periodic detection manner or in a real-time detection manner.

[0008] In another possible implementation, when it is detected that the duration of each thread on the first processor core being in the suspended state exceeds the second time threshold, the first processor core is controlled to operate in a low power consumption mode. This ensures that the thread running on the first processor core will not be awakened for a long time, so that the first processor core can be controlled to operate in a low power consumption mode for a long time.

[0009] In another possible implementation, when it is detected that the duration of the second thread being in the suspended state exceeds the second time threshold, the second thread is migrated to the second processor core, the second thread is any thread running on the first processor core, the second processor core is a processor core in the device that has been working in a low power consumption mode, and the load of the second processor core is lower than the load threshold. Since the load of the second processor core is lower than the load threshold, it is ensured that when the second thread wakes up, the number of other threads competing with the second thread for computing resources can be reduced, so that the second thread can compete for computing resources as soon as possible.

[0010] In another possible implementation, when the usage rate of the first processor core is lower than the usage rate threshold, the third thread is migrated to the third processor core, the third thread is a thread in a non-suspended state on the first processor core, the usage rate of the first processor core is used to indicate the effective utilization rate of the computing resources of the first processor core, and the third processor core is a processor core in the device that works in a normal working mode. In this way, each thread on the first processor core can be suspended as soon as possible, and the first processor core can be controlled to work in a low power consumption mode as soon as possible.

[0011] In another possible implementation, threads in a non-suspended state on multiple processor cores in a device are merged into some of the multiple processor cores. The part of the processor cores may be located on one or more processors, so that threads in a non-suspended state can be concentrated on one processor or multiple processors, thereby controlling other processors in the device to work in a low power consumption mode.

[0012] In another possible implementation, when there is data in the shared memory of the device, the first processor core is controlled to operate in a normal operating mode, and the state of the first thread is set to a normal operating state, wherein the operating frequency of the first processor core when the first processor core operates in the normal operating mode is greater than or equal to a frequency threshold, thereby ensuring that the first thread can process tasks normally.

[0013] In another possible implementation, a notification command is triggered by a data generation module included in the receiving device, the notification command is triggered when the data generation module stores data in the shared memory, the notification command includes an identifier of the shared memory, and the notification command includes a command for indicating that data exists in the shared memory. Since the notification command is triggered by the data generation module included in the receiving device, it is ensured that when there is data in the shared memory, the first thread can be immediately awakened to process the data.

[0014] In another possible implementation manner, the notification command includes at least one of a software signal and a hardware signal.

[0015] In another possible implementation, the processor core included in the device is a virtual processor core or a physical processor core.

[0016] In a second aspect, the present application provides a resource management device, which is used to execute the method in the first aspect or any possible implementation of the first aspect. Specifically, the device includes a unit for executing the method in the first aspect or any possible implementation of the first aspect.

[0017] In a third aspect, the present application provides a resource management device, the device comprising: a processor, a memory, and a communication interface. The processor, the memory, and the communication interface may be connected via a bus system. The memory is used to store one or more programs, and the processor is used to execute one or more programs in the memory, so that the detection device completes the method in the first aspect or any possible implementation of the first aspect.

[0018] In a fourth aspect, the present application provides a processor, comprising a processor core, and the processor core is used to complete the method in the first aspect or any possible implementation of the first aspect.

[0019] In a fifth aspect, the present application provides a device, comprising a processor, wherein the processor comprises a processor core, and the processor core is used to complete the method in the first aspect or any possible implementation of the first aspect.

[0020] In a sixth aspect, the present application provides a computer-readable storage medium, in which program code is stored. When the computer-readable storage medium is run on a computer, the computer executes the method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0021] In a seventh aspect, the present application provides a computer program product comprising program code, which, when executed on a processor core included in a processor, enables the processor core to execute the above-mentioned first aspect or any possible implementation of the first aspect.

[0022] In an eighth aspect, the present application provides a chip comprising a memory and a processor, the memory being used to store computer instructions, the processor comprising a processor core, and the processor core being used to call and run the computer instructions from a storage device to execute the method in the above-mentioned first aspect and any possible implementation of the above-mentioned first aspect.

[0023] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of a resource scheduling scenario provided in an embodiment of the present application;

[0025] Figure 2 It is a structural schematic diagram of a device provided in an embodiment of the present application;

[0026] Figure 3 is a structural schematic diagram of another device provided in an embodiment of the present application;

[0027] Figure 4 It is a flow chart of a resource management method provided by an embodiment of the present application;

[0028] Figure 5 is a schematic diagram of a migration thread provided in an embodiment of the present application;

[0029] Figure 6 is a schematic diagram of merging threads provided in an embodiment of the present application;

[0030] Figure 7 This is a schematic diagram of a data processing process for an audio and video conference provided in an embodiment of the present application;

[0031] Figure 8 It is a schematic diagram of the structure of a resource management device provided in an embodiment of the present application;

[0032] Fig. 9 This is another schematic diagram of the device structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0034] The embodiment of the present application is applicable to a resource scheduling scenario including producers and consumers. The consumer is bound to a shared memory, which can be shared between the producer and the consumer, and both the producer and the consumer can read and write the shared memory. The consumer has the function of polling the shared memory, which means that the consumer periodically detects whether there is data in the shared memory.

[0035] The producer can use the shared memory to store data, and when the consumer detects that there is data in the shared memory, it obtains the data and processes the data.

[0036] It should be noted that in this scenario, the producer does not store data in the shared memory all the time. The producer stores data in the shared memory according to the needs of the upper-layer application.

[0037] Optional, see Figure 1 , the generator can also be called data generation module 1, and the consumer can be thread 2, for example, the consumer can be a polling thread. Thread 2 is bound to shared memory 3, and thread 2 can periodically detect whether there is data in shared memory 3. Data generation module 1 obtains data and stores data in shared memory 3. When thread 2 detects data from shared memory 3, it obtains and processes the data.

[0038] Optional, Figure 1 The data generation module 1, thread 2 and shared memory 3 shown may be located in a device, and the shared memory 3 is a storage space in the memory of the device, and the shared memory 3 occupies a memory address segment in the memory. The binding of thread 2 to the shared memory 3 means that thread 2 is bound to the memory address segment, for example, thread 2 is bound to the start address and the end address of the shared memory 3, and thread 2 can access the memory address segment.

[0039] Optionally, the device may include one or more threads 2, and the memory of the device may include one or more shared memories 3. Each shared memory 3 may be bound to one or more threads 2 in the device. In other words, the one or more threads 2 may detect whether there is data in the shared memory 3.

[0040] Optionally, one thread 2 may be bound to one shared memory 3 or to multiple shared memories 3 .

[0041] Optionally, the device is a physical device or a virtual device, for example, the device is a physical device such as a server or a network device, or the device is a virtual device such as a virtual machine or a container, and the network device may be a switch, etc.

[0042] Optionally, when the device is a physical device, the data generation module 1 may be a device with computing capabilities, such as a processor, a network card, or a process or thread running on the device, etc. For example, when the data generation module 1 is a network card, the network card receives data and stores the data in a shared memory 3, and the thread 2 bound to the shared memory 3 detects the shared memory 3, and when the data is detected from the shared memory 3, the thread 2 acquires and processes the data.

[0043] Optionally, when the device is a virtual device, that is, the device is a virtual machine or a container, etc., the data generation module may be a process or a thread, etc. running in the virtual machine or the container.

[0044] The device may include at least one data generation module 1 , at least one shared memory 3 , and at least one thread 2 bound to any shared memory 3 .

[0045] See also Figure 2 The device includes at least one processor, each processor includes at least one processor core. The threads in the device run on the processor core, and one processor core can run one or more threads 2. For any shared memory 3 included in the memory of the device, at least one thread 2 bound to the shared memory 3 can run on one processor core, or can run on different processor cores. In the case where the at least one thread 2 runs on different processor cores, the different processor cores can be located on the same processor or on different processors.

[0046] For example, in Figure 2 In the embodiment, the device includes a first processor 4 and a second processor 5. The first processor 4 includes two processor cores, which are processor core 41 and processor core 42. The second processor 5 includes processor core 51. Processor core 41 runs threads 21 and 22, processor core 42 runs threads 23 and 24, and processor core 51 runs threads 25 and 26.

[0047] Optionally, the six threads may be bound to different shared memories 3, or some of the six threads may be bound to one shared memory 3. For example, assuming that the memory of the device includes three shared memories 3, thread 21, thread 22, and thread 23 are all bound to one of the shared memories 3, thread 24 and thread 25 are bound to another shared memory 3, and thread 26 is bound to the remaining shared memory 3.

[0048] See also Figure 2 In the embodiment of the present application, a scheduling module 6 is added to the device. For any processor core in the device, for the sake of convenience, the processor core is called the first processor core. The scheduling module 6 detects the state of the thread running on the first processor core; when it is detected that the thread running on the first processor core meets the preset conditions, the first processor core is controlled to operate in a low power consumption mode, wherein the operating frequency of the first processor core when the first processor core operates in the low power consumption mode is less than the frequency threshold, thereby reducing the power consumption of the first processor. The detailed implementation process of detecting the first processor core and controlling the first processor core will be described later. Figure 4 The embodiments shown are described in detail and will not be described in detail here.

[0049] Optionally, the scheduling module 6 can run on a processor core of the device, in which case the scheduling module 6 is the processor core; or the scheduling module 6 can run on a processor core together with at least one thread in the device, in which case the scheduling module can be a thread or process running on the processor core, etc.

[0050] It should be noted that the processor core may be a physical processor core, for example, see Figure 2 , the first processor 4 and the second processor 5 are both CPUs, and the processor core 41 and the processor core 42 included in the first processor 4 can be CPU cores, or, see Figure 3 , the processor core can be a virtual physical core, but each virtual physical core can also run on one or more physical processor cores. Figure 3 In the embodiment, the device includes virtual processor core 1, virtual processor core 2 and virtual processor core 3. Virtual processor core 1 runs on physical processor core 41, and virtual processor core 2 and virtual processor core 3 run on physical processor core 42.

[0051] See also Figure 4 , the present application embodiment provides a resource management method, the method is applied to Figure 2 In the device shown in or 3, the device includes at least one processor core, including:

[0052] Step 401: Detect the state of a thread running on a first processor core, where the first processor core is any one of the at least one processor core.

[0053] One or more threads may run on the first processor core. For the convenience of description, any thread on the first processor core is called the first thread. The first thread has a polling function. The first thread is bound to a shared memory. The so-called polling function means that the first thread periodically detects whether there is data in the shared memory bound to it. The shared memory is a storage space in the memory of the device.

[0054] The state of the first thread may be set by the first thread. Optionally, the state of the first thread itself may be:

[0055] When the length of time during which the first thread continuously detects that there is no data in the shared memory bound to the first thread reaches a first time threshold, the first thread sets its own state to a suspended state.

[0056] Optionally, the first thread may periodically detect whether there is data in the shared memory bound to it, or the first thread may detect in real time whether there is data in the shared memory bound to it.

[0057] After the first thread sets its state to the suspended state, it will not compete for the computing resources on the first processing core. However, when the first thread is in the non-suspended state, it will compete for the computing resources on the first processing core.

[0058] Optionally, before setting its own state to the suspended state, the first thread performs a yield operation (also called a yield operation) to release computing resources occupied by the first processor core when the length of time for which the first thread continuously detects that there is no data in the shared memory bound to it reaches a third time threshold, so as to enable the first processor core to run other threads preferentially, and the third time threshold is less than the first time threshold.

[0059] Optionally, when the first thread is in a non-suspended state, the first thread will detect the shared memory bound to the first thread in real time or periodically. The first thread needs to occupy the computing resources of the first processor core to detect the shared memory. After the first thread sets its own state to the suspended state, the first thread will not periodically detect the shared memory. The first processor core can release the computing resources occupied by the first thread, thereby saving the computing resources of the first processor core.

[0060] Optionally, when the scheduling module detects that the first thread sets its own state to a suspended state, it obtains the identifier of the first thread and the start time of the suspended state, and saves the identifier of the first thread and the start time of the suspended state in correspondence between the identifier of the thread and the start time of the suspended state.

[0061] For example, see Figure 2 , assuming that the thread 21 on the processor core 41 sets its own state to the suspended state when the length of time for continuously detecting that the shared memory bound to it has no data reaches a first time threshold, and assuming that the current time is t1.

[0062] Correspondingly, the scheduling module detects that the state of thread 21 changes to the suspended state at time t1, obtains the identification ID1 of thread 21 and the start time t1 of the suspended state, and saves the identification ID1 of thread 21 and the start time t1 of the suspended state correspondingly in the corresponding relationship between the identification of the thread and the start time of the suspended state as shown in Table 1 below.

[0063] Again, see Figure 2 , assuming that thread 22 on processor core 1 sets its own state to the suspended state when the length of time for continuously detecting that the shared memory bound to it has no data reaches a first time threshold, and assuming that the current time is t2.

[0064] Correspondingly, the scheduling module detects that the state of thread 22 changes to the suspended state at time t2, obtains the identification ID2 of thread 22 and the start time t2 of the suspended state, and saves the identification ID2 of thread 22 and the start time t2 of the suspended state correspondingly in the corresponding relationship between the thread identification and the start time of the suspended state shown in Table 1 below.

[0065] Table 1

[0066] Thread ID Suspend state start time Thread 21 ID1 t1 Thread 22 ID2 t2 …… ……

[0067] Wherein, the device includes at least one thread with a polling function, each thread is bound to a shared memory, and is used to detect the shared memory bound to it. Before executing step 401, for each thread, the thread registers the identifier of the thread and the identifier of the shared memory bound to the thread in the scheduling module. The scheduling module stores the identifier of the thread and the identifier of the shared memory bound to the thread in the corresponding relationship between the identifier of the thread and the identifier of the shared memory. Therefore, the corresponding relationship between the identifier of the thread and the identifier of the shared memory stores the identifier of each thread in the device and the identifier of the shared memory bound to each thread.

[0068] For example, see Figure 2 , thread 21 registers the identifier ID1 of thread 21 and the identifier IM1 of shared memory 1 bound to thread 21 to the scheduling module, and the scheduling module saves the correspondence between the identifier ID1 of thread 21 and the identifier IM1 of shared memory 1 bound to thread 21 in the correspondence between the thread identifier and the shared memory identifier as shown in Table 2 below.

[0069] Similarly, the scheduling module stores the correspondence between the identifier ID2 of thread 22 and the identifier IM2 of shared memory 2 bound to thread 22, the correspondence between the identifier ID3 of thread 23 and the identifier IM3 of shared memory 3 bound to thread 23, the correspondence between the identifier ID4 of thread 24 and the identifier IM4 of shared memory 4 bound to thread 24, the correspondence between the identifier ID5 of thread 25 and the identifier IM5 of shared memory 5 bound to thread 25, and the correspondence between the identifier ID6 of thread 26 and the identifier IM6 of shared memory 6 bound to thread 26 in the correspondence between thread identifiers and shared memory identifiers as shown in Table 2 below.

[0070] Table 2

[0071] Thread ID Shared memory identifier Thread 21 ID1 Shared memory 1 identifier IM1 Thread 22 ID2 Shared memory 2 identifier IM2 Thread 23 ID3 Shared memory 3 identifier IM3 Thread 24 ID 4 Shared memory 4 identifier IM4 Thread 25 ID 5 Shared memory 5 identifier IM5 Thread 26 ID 6 Shared memory 6 identifier IM6

[0072] Optionally, the shared memory is a storage space in the device memory, and the identifier of the shared memory may include the starting address of the storage space, or the starting address and ending address of the storage space.

[0073] Optionally, before executing step 401, the identification of each processor core in the device and the identification of the thread running on each processor core can also be obtained, and the identification of each processor core and the identification of the thread on each processor core are saved in the corresponding relationship between the identification of the processor core and the identification of the thread.

[0074] For example, participating in Figure 2 In the example shown, the identification IC1 of the processor core 41, the identification ID1 of the thread 21 running on the processor core 41, and the identification ID2 of the thread 22 are obtained, and the identification IC1 of the processor core 41, the identification ID1 of the thread 21 running on the processor core 41, and the identification ID2 of the thread 22 are correspondingly saved in the corresponding relationship between the identification of the processor core and the identification of the thread as shown in Table 3 below. Similarly, the identification IC2 of the processor core 42, the identification ID4 of the thread 24 running on the processor core 42, and the identification ID5 of the thread 25, as well as the identification IC3 of the processor core 51, the identification ID5 of the thread 25 running on the processor core 51, and the identification ID6 of the thread 26 are correspondingly saved in the corresponding relationship between the identification of the processor core and the identification of the thread as shown in Table 3 below.

[0075] Table 3

[0076]

[0077] Step 402: When it is detected that the thread running on the first processor core meets a preset condition, the first processor core is controlled to operate in a low power consumption mode, wherein the operating frequency of the first processor core in the low power consumption mode is less than a frequency threshold.

[0078] Optionally, the preset condition includes that the threads running on the first processor core are all in suspended state. That is, in step 402, when it is detected that the threads running on the first processor core are all in suspended state, the first processor core is controlled to operate in low power consumption mode.

[0079] Since the first processor core works in the low power consumption mode, the operating frequency of the first processor core is less than the frequency threshold, which can reduce the power consumption of the first processor core. The frequency threshold can be pre-set according to actual business needs, or pre-set according to an empirical value, or the frequency threshold can be determined according to statistical historical data. The frequency threshold is used to limit the operating frequency of the processor core in the low power consumption mode, so that the power consumption of the processor core in the low power consumption mode is lower than that in the normal working mode, thereby achieving the purpose of reducing the power consumption of the entire processor and saving energy.

[0080] Optionally, the preset condition includes that the duration of each thread on the first processor core being in a suspended state exceeds a second time threshold. In step 402, when it is detected that the duration of each thread on the first processor core being in a suspended state exceeds the second time threshold, the first processor core is controlled to operate in a low power consumption mode.

[0081] Optionally, during implementation, according to the identifier of the first processor core, the identifier of each thread on the first processor core is obtained from the correspondence between the identifier of the processor core and the identifier of the thread. According to the identifier of each thread, the correspondence between the identifier of the thread and the start time of the suspended state is queried. If the start time of the suspended state corresponding to each thread is queried, it is determined that the state of each thread on the first processor core is the suspended state. According to the current time and the start time of the suspended state of each thread, the duration of each thread in the suspended state is obtained. When the duration of each thread in the suspended state exceeds the second time threshold, the first processor core is controlled to operate in a low power consumption mode.

[0082] For example, see Figure 2, taking the processor core 41 as an example, according to the identifier IC1 of the processor core 41, the identifier ID1 of the thread 21 and the identifier ID2 of the thread 22 running on the processor core 41 are obtained from the correspondence between the identifier of the processor core and the identifier of the thread shown in Table 3 above. According to the identifier ID1 of the thread 21 and the identifier ID2 of the thread 22, the start time of the suspended state of the thread 21 is obtained as t1, and the start time of the suspended state of the thread 2 is obtained as t2 from the correspondence between the identifier of the thread and the start time of the suspended state shown in Table 1 above. According to the current time t3, the start time t1 of the suspended state of the thread 21, and the start time t2 of the suspended state of the thread 22, the first duration of the suspended state of the thread 21 is obtained as t3-t1, and the second duration of the suspended state of the thread 22 is obtained as t3-t2. Assuming that the first duration t3-t1 and the second duration t3-t2 both exceed the second time threshold, the processor core 41 is controlled to work in the low power consumption mode.

[0083] Optionally, the method of controlling the first processor core to operate in the low power consumption mode may be:

[0084] The scheduling module sends an instruction to enter low power consumption to the first processor core, and the first processor receives the instruction and operates in the low power consumption mode.

[0085] Optionally, the first processor core turns off its own operating clock to operate in a low power consumption mode.

[0086] For example, assuming that the first processor core is an advanced RISC machines (ARM), the low power consumption instruction sent by the scheduling module to the first processor core is a wait for event (WFE) instruction. The first processor core receives the WFE instruction and turns off its own working clock.

[0087] Although the first processor core works in the low power consumption mode, the first processor core is still powered to ensure that the first processor core can be awakened in time when it is needed to be awakened to work in the normal working mode.

[0088] Optionally, before controlling the first processor to operate in the low power consumption mode, the thread that has been processed in the suspended state for a long time on the first processor core can be migrated to other processor cores that operate in the low power consumption mode and have a low load.

[0089] During implementation: when it is detected that the duration of the second thread in the suspended state exceeds the second time threshold, the second thread is migrated to the second processor core, the second thread is any thread included in the first processor core, the second processor core is a processor core in the device that has been working in low power consumption mode, and the load of the second processor core is lower than the load threshold.

[0090] The first processor core and the second processor core may be located on the same processor or on different processors.

[0091] The load threshold may be preset according to actual business requirements or based on empirical values, or may be determined based on statistical historical data.

[0092] Since the load of the second processor core is lower than the load threshold, after the second thread is migrated to the second processor core, after the second processor core and the second thread are awakened, the number of threads competing with the second thread for computing resources is small, and the second thread can obtain computing resources from the second processor core as soon as possible.

[0093] Optionally, after migrating the second thread to the second processor core, the identifier of the first processor core corresponding to the second thread is updated to the identifier of the second processor core in the correspondence between the thread identifier and the processor core identifier.

[0094] For example, see Figure 2 , assuming that the processor core 42 is already working in the low power consumption mode, and the threads 23 and 24 are running on the processor core 42, and the load of the processor core 42 is 2, which is less than the load threshold 3. It is also assumed that the state of the thread 21 on the processor core 41 is suspended, and the duration of the thread 21 in the suspended state exceeds the second time threshold. So see Figure 5 , migrate thread 21 to processor core 42, and update the identifier IC1 of processor core 41 corresponding to thread 21 to the identifier IC2 of processor core 42 in the correspondence between the identifiers of the processor cores and the identifiers of the threads as shown in Table 3, and obtain the correspondence between the identifiers of the processor cores and the identifiers of the threads as shown in Table 4 below.

[0095] Table 4

[0096]

[0097] Optionally, before controlling the first processor to work in the low power consumption mode, the threads in the non-suspended state on the first processor core may be migrated to other processor cores working in the normal working mode, and the threads in the suspended state on the first processor core are retained, so that the threads on the first processor core are all suspended threads as soon as possible, so as to control the first processor core to work in the low power consumption mode as soon as possible. Optionally, during implementation:

[0098] When the usage rate of the first processor core is lower than the usage rate threshold, the third thread is migrated to the third processor core, the third thread is a thread in a non-suspended state on the first processor core, the usage rate of the first processor core is used to indicate the effective utilization rate of the computing resources of the first processor core, and the third processor core is a processor core in the device that operates in a normal working mode.

[0099] The first processor core and the third processor core may be located on the same processor or on different processors.

[0100] Optionally, the first processor core and the third processor core are located on different processors, and the third thread can be migrated to the third processor core that is not on the same processor as the first processor. For the processor where the first processor core is located, each processor core on the processor can be made to meet the conditions for entering the low power consumption working mode as much as possible, so that the entire processor works in the low power consumption mode.

[0101] Optionally, when it is detected that the usage rate of the first processor core is lower than the usage rate threshold, the identifier of each thread running on the first processor core is obtained from the correspondence between the identifier of the processor core and the identifier of the thread according to the identifier of the first processor core, and the identifier of the thread that exists in the correspondence between the identifier of the thread and the start time of the suspended state is removed from the identifiers of each thread, and the threads corresponding to the remaining thread identifiers are all threads in a non-suspended state on the first processor core.

[0102] Optionally, after migrating the third thread to the third processor core, the identifier of the first processor core corresponding to the third thread is updated to the identifier of the third processor in the correspondence between the thread identifier and the processor core identifier.

[0103] Optionally, in step 402, for multiple processor cores in a normal working state, threads in a non-suspended state on the multiple processor cores may be merged into some of the multiple processor cores. In this way, threads on more processor cores may be suspended, so as to control more processor cores to work in a low power consumption mode.

[0104] Optionally, during implementation: determine multiple processor cores, all of which are operating in a normal working mode, and select a portion of the processor cores from the multiple processor cores. Migrate threads in a non-suspended state on the multiple processor cores to a portion of the processor cores, which may include one or more processor cores, so that threads on more processor cores are in a suspended state. When all remaining unmigrated threads on a processor core are in a suspended state, control the processor core to operate in a low power consumption mode; or, when the duration of the suspended state of each remaining unmigrated thread on the processor core exceeds a second time threshold, control the processor core to operate in a low power consumption mode.

[0105] Optionally, a processor core located on the same processor can be selected from the multiple processor cores, so that threads in a non-suspended state can be migrated to a processor core included in one processor as much as possible. The processor cores on other processors in the device meet the conditions for entering a low-power working mode, so that other processors work in a low-power mode to reduce the power consumption of more processors.

[0106] For example, for Figure 2 In the example shown, it is assumed that processor cores 41, 42, and 51 are all operating in normal working mode, thread 21 on processor core 41 is in suspended state, and thread 22 is in non-suspended state. Threads 23 and 24 on processor core 42 are both in non-suspended state, and thread 25 on processor core 51 is in suspended state, and thread 26 is in non-suspended state. In this way, the threads in non-suspended state on the three processor cores can be merged. For example, see Figure 6 , thread 22 on processor core 41 and threads 23 and 24 on processor core 42 are migrated to processor core 51, that is, the threads in the non-suspended state on the three processor cores are merged into processor core 51. Then, processor cores 41 and 42 are controlled to work in a low power consumption mode, so that the first processor 4 works in a low power consumption mode.

[0107] Optionally, when controlling the first processor core to operate in the low power consumption mode, the record including the identifier of each thread running on the first processor core is deleted from the correspondence between the thread identifier and the start suspension time.

[0108] Optionally, during implementation: according to the identifier of the first processor, obtain the identifier of each thread running on the first processor core from the correspondence between the processor identifier and the thread identifier; delete the record including the obtained identifier of each thread from the correspondence between the thread identifier and the start suspension time.

[0109] Optionally, it should be noted that: if the first processor core is a virtual processor core, the first processor core runs on a physical processor core, and controlling the first processor core to operate in a low power consumption mode not only reduces the power consumption of the first processor core, but also saves computing resources of the physical processor core.

[0110] Optionally, each virtual processor core running on the physical processor core operates in a low power consumption mode, and the physical processor core can also be controlled to operate in a low power consumption mode to reduce the power consumption of the processor core (also called the physical core) where the virtual processor core is located.

[0111] Step 403: When there is data in the shared memory bound to the first thread, control the first processor core to operate in a normal working mode, and set the state of the first thread to a normal working state, wherein the operating frequency of the first processor core when the first processor core operates in the normal working mode is greater than or equal to a frequency threshold.

[0112] Optionally, when a data generation module in the device stores data into the shared memory bound to the first thread, the data generation module triggers a notification command to the scheduling module, where the notification command includes an identifier of the shared memory.

[0113] Optionally, the notification command includes a command for indicating that data exists in the shared memory.

[0114] Optionally, the notification command includes at least one of a software signal and a hardware signal.

[0115] In step 403, the scheduling module needs to wake up the first processor core and the first thread on the first processor core in the low power consumption mode. In implementation:

[0116] The scheduling module receives the notification command, and determines, based on the shared memory identifier included in the notification command, that data exists in the shared memory corresponding to the shared memory identifier. According to the shared memory identifier, the identifier of the first thread bound to the shared memory is obtained from the thread identifier and the shared memory identifier. According to the first thread identifier, the identifier of the first processor core where the first thread is located is obtained from the correspondence between the processor core identifier and the thread identifier.

[0117] The scheduling module determines whether the first processor core is operating in a low power consumption mode according to the identifier of the first processor core. When the first processor core is operating in the low power consumption mode, the scheduling module controls the first processor core to operate in a normal operating mode to wake up the first processor core. When the first processor core is operating in the normal operating mode, the scheduling module sets the state of the first thread to a non-suspended state to wake up the first thread.

[0118] Optionally, when the first processor core is a virtual processor core, and the physical processor core where the first processor core is located also operates in a low power consumption mode, the physical processor core is first controlled to operate in a normal operating mode, and then the first processor core is controlled to operate in a normal operating mode.

[0119] When the first processor core works in a normal working state and the state of the first thread is set to a non-suspended state, the first processor core runs the first thread. The first thread periodically detects the shared memory bound to it, obtains data from the shared memory, and processes the data.

[0120] Optionally, in step 403, the scheduling module may send an instruction to the first processor to enter the normal working mode. The first processor receives the instruction and works in the normal working mode.

[0121] Optionally, the first processor core starts its own working clock to operate in a normal working mode.

[0122] For example, assuming that the first processor core is an ARM, the instruction sent by the scheduling module to the first processor core to enter the normal working mode is a send event local (SEVL) instruction. The first processor core receives the SEVL instruction and starts its own working clock to work in the normal working mode.

[0123] For example, it is assumed that when the data generation module of the device stores data in the shared memory bound to the thread 21, a notification command is triggered to the scheduling module, and the notification command includes the identifier IM1 of the shared memory. The scheduling module receives the notification command, and determines that there is data in the shared memory corresponding to the identifier IM1 of the shared memory according to the identifier IM1 of the shared memory included in the notification command. According to the identifier IM1 of the shared memory, the identifier ID1 of the thread 21 bound to the shared memory is obtained from the correspondence between the identifier of the thread and the identifier of the shared memory shown in Table 3 above. According to the identifier ID1 of the thread 21, the identifier IC1 of the processor core 41 where the thread 21 is located is obtained from the correspondence between the identifier of the processor core and the identifier of the thread. According to the identifier IC1 of the processor core 41, it is determined that the processor core 41 is working in the low power consumption mode, and then the processor core 41 is controlled to work in the normal working mode to wake up the processor core 41; the state of the thread 21 is set to the non-suspended state. Then, the processor core 41 runs the thread 21, and the thread 21 periodically detects the shared memory bound to it, obtains data from the shared memory, and processes the data.

[0124] Optionally, if the data generation module is software (such as a thread or process, etc.), the data generation module and the scheduling module can receive the notification command triggered by the data generation module through inter-process communication (IPC) or polling detection by the scheduling module. If the data generation module is a hardware device (such as a network card), the scheduling module can receive the notification command triggered by the data generation module by detecting hardware signals (registers or interrupts). Of course, these two mechanisms for receiving notification commands are just examples, as a way of implementation, and are not limited to this. For example, the data generation module can also trigger a notification command to the scheduling module by means of a semaphore.

[0125] Optionally, the embodiments of the present application can be used in scenarios such as a shared cloud, where the device is a server in a public cloud. Figure 7 As shown, taking the audio and video conference application in the public cloud as an example, in the audio and video conference application, for a conference, the server processor often runs the decryption thread 20, processing thread 27, encryption thread 28 and sending thread 29 required to implement the conference. Among them, the decryption thread 20 is bound to the first shared memory 31, the processing thread 27 is bound to the second shared memory 32, the encryption thread 28 is bound to the third shared memory 33, and the sending thread 29 is bound to the fourth shared memory 34. The first shared memory 31, the second shared memory 32, the third shared memory 33 and the fourth shared memory 34 are four different storage spaces in the memory of the server.

[0126] The network card 30 of the server receives the audio and video data generated during the conference, and stores the audio and video data in the first shared memory 31. The decryption thread 20 detects the first shared memory 31, detects the audio and video data from the first shared memory 20, obtains the audio and video data, and decrypts the audio and video data to obtain decrypted data. At this time, the decryption thread 20 can also be used as a data generation module to store the decrypted data in the second shared memory 32. The processing thread 27 detects the second shared memory 32, detects the decrypted data from the second shared memory 32, obtains the decrypted data, and processes the decrypted data to obtain a processing result. At this time, the processing thread 27 can also be used as a data generation module to store the processing result in the third shared memory 33. The encryption thread 28 detects the third shared memory, detects the processing result from the third shared memory 33, obtains the processing result, and encrypts the processing result to obtain encrypted data. At this time, the encryption thread 28 can also be used as a data generation module to store the encrypted data into the fourth shared memory 34. The sending thread 29 detects the fourth shared memory 34, detects the encrypted data from the fourth shared memory 34, obtains the encrypted data, and sends the encrypted data to other devices through the communication interface of the device.

[0127] The above process is a description of an audio and video data processing process. When there are a large number of meetings, a large number of decryption threads 20, processing threads 27, encryption threads 28 and sending threads 29 are running on the processor core of the server, resulting in high power consumption of the server processor. However, audio and video conferencing applications do not always have audio and video data, that is, the server may not receive audio and video data for a long time, so it is possible to control some processor cores in the server to work in low power consumption mode through the method of the embodiment of the present application to reduce the power consumption of the server processor.

[0128] In an embodiment of the present application, the state of the thread running on the first processor core is detected, and the state of the threads on the first processor core is all suspended, and the first processor core is controlled to work in a low power consumption mode. By working in the low power consumption mode, the operating frequency of the first processor core is very low, and the required power consumption is correspondingly small, thereby reducing the power consumption of the first processor core. Before controlling the first processor core to work in the low power consumption mode, the threads in the non-suspended state on the first processor core are also migrated to other processor cores in a normal working state, so as to control the first processor core to enter the low power consumption mode as soon as possible. Furthermore, since the threads on the first processor core can be set to a suspended state, the first processor core can release the computing resources occupied by the threads in the suspended state, thereby saving computing resources.

[0129] See also Figure 8 The embodiment of the present application provides a resource management device 800, the device 800 is applied to Figure 2 , Figure 3 or Figure 4 In the device of the illustrated embodiment, the device includes at least one processor core, including:

[0130] A processing unit 801 is configured to detect a state of a thread running on a first processor core, where the first processor core is any one of the at least one processor core;

[0131] The control unit 802 is used to control the first processor core to operate in a low power consumption mode when the processing unit 801 detects that the thread running on the first processor core meets a preset condition, wherein the operating frequency of the first processor core when the first processor core operates in the low power consumption mode is less than a frequency threshold.

[0132] Optionally, the detailed process of the processing unit 801 detecting the thread state can be found in Figure 4 The relevant contents of step 401 in the illustrated embodiment. For the detailed process of the control unit 802 controlling the first processor core, please refer to Figure 4 Relevant content in step 402 in the illustrated embodiment.

[0133] Optionally, the preset condition includes that the states of the threads running on the first processor core are all in a suspended state.

[0134] Optionally, the threads running on the first processor core include a first thread, which is bound to a shared memory included in the device. The shared memory is a storage space in the memory of the device, and the first thread is used to detect whether the shared memory stores data. When the first thread detects that the duration of time when the shared memory has no data exceeds a first time threshold, the state of the first thread is set to a suspended state.

[0135] Optionally, the control unit 802 is used to control the first processor core to operate in a low power consumption mode when the processing unit 801 detects that the duration of each thread on the first processor core being in a suspended state exceeds a second time threshold.

[0136] Optionally, the processing unit 801 is also used to: when it is detected that the duration of the second thread in the suspended state exceeds a second time threshold, migrate the second thread to the second processor core, the second thread is any thread running on the first processor core, the second processor core is a processor core in the device that is already working in a low power consumption mode, and the load of the second processor core is lower than the load threshold.

[0137] Optionally, the detailed process of the processing unit 801 migrating the second thread can be found in Figure 4 Relevant content in step 402 in the illustrated embodiment.

[0138] Optionally, the processing unit 801 is also used to: when the usage rate of the first processor core is lower than the usage rate threshold, migrate the third thread to the third processor core, the third thread is a thread in a non-suspended state on the first processor core, the usage rate of the first processor core is used to indicate the effective utilization rate of the computing resources of the first processor core, and the third processor core is a processor core in the device operating in a normal working mode.

[0139] Optionally, the detailed process of the processing unit 801 migrating the third thread can be found in Figure 4 Relevant content in step 402 in the illustrated embodiment.

[0140] Optionally, the processing unit 801 is further used to merge threads in a non-suspended state on multiple processor cores in the device into some processor cores among the multiple processor cores.

[0141] Optionally, the control unit 802 is also used to: when there is data in the shared memory, control the first processor core to operate in a normal working mode, and set the state of the first thread to a normal working state, wherein the operating frequency of the first processor core when the first processor core operates in the normal working mode is greater than or equal to a frequency threshold.

[0142] Optionally, the detailed process of the control unit 802 controlling the first processor and the first thread can be found in Figure 4 Relevant content in step 403 in the illustrated embodiment.

[0143] Optionally, the device 800 also includes: a receiving unit 803, used to receive a notification command triggered by a data generating module included in the device, the notification command is triggered by the data generating module when storing data in the shared memory, the notification command includes an identifier of the shared memory, and the notification command includes a command for indicating that there is data in the shared memory.

[0144] Optionally, the notification command includes at least one of a software signal and a hardware signal.

[0145] Optionally, the processor core included in the device is a virtual processor core or a physical processor core.

[0146] It should be understood that the device 800 of the embodiment of the present application can be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), and the PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. It can also be implemented by software. Figure 4 When the resource management method is shown, the device 800 and its various modules may also be software modules.

[0147] The device 800 according to the embodiment of the present application may correspond to executing the method described in the embodiment of the present application, and the above and other operations and / or functions of each unit in the device 800 are respectively to implement Figure 4 For the sake of brevity, the corresponding process of the method shown will not be repeated here.

[0148] In an embodiment of the present application, the processing unit detects the state of the thread running on the first processor core, and the first processor core is any one of the at least one processor core. When it is detected that the thread running on the first processor core meets the preset condition, the control unit controls the first processor core to operate in a low power consumption mode, wherein the operating frequency of the first processor core when the first processor core operates in the low power consumption mode is less than a frequency threshold. When the control unit controls the first processor core to operate in the low power consumption mode, the threads running on the first processor core will not occupy computing resources, and the operating frequency of the first processor core is less than the frequency threshold, so that the power consumption of the first processor core is very low, saving computing resources of the processor where the first processor core is located and reducing the power consumption of the processor.

[0149] See also Fig. 9, the present application embodiment provides a schematic diagram of a device 900. The device 900 may be a device in any of the above embodiments, for example, the device 900 is Figure 4 The device in the embodiment shown. The device 900 includes at least one processor 901, a memory unit 902, a storage medium 903, a communication interface 904 and a bus system 905. The processor 901, the memory unit 902, the storage medium 903, and the communication interface 904 communicate through the bus system 905.

[0150] For any one of the at least one processor 901, the processor 901 includes at least one processor core 9011, and each processor core 9011 runs at least one thread 9012. The memory unit 902 includes at least one shared memory 9021, and each shared memory 9021 is a memory space in the memory unit 902. There is a binding relationship between each thread 9012 in the at least one thread 9012 and a shared memory 9021.

[0151] The processor core 9011 in the processor 901 can call the computer execution instructions (for example, program codes) stored in the memory unit 902 to implement Figure 4 The operation steps performed by the scheduling module in the illustrated embodiment include, for example, detecting the state of a thread running on a first processor core, where the first processor core is any one of the at least one processor core 9011; when detecting that the thread running on the first processor core meets a preset condition, controlling the first processor core to operate in a low power consumption mode, wherein the operating frequency of the first processor core when the first processor core operates in the low power consumption mode is less than a frequency threshold.

[0152] Optionally, the computer execution instructions and the operating system are stored in the storage medium 903. When the device 900 starts running, the processor core 9011 in the processor 901 can load the computer execution instructions and the operating system stored in the storage medium 903 into the memory unit 902, and call and run the computer execution instructions in the memory unit 902 in the operating environment provided by the operating system.

[0153] Optionally, the processor 901 may be a CPU, a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application. As an embodiment, the processor 901 may include one or more CPUs, such as Fig. 9The processor 901 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0154] In addition to the data bus, the bus system 905 in the device 900 may also include a power bus, a control bus, a status signal bus, etc. However, for the sake of clarity, various buses are labeled as the bus system 905 in the figure.

[0155] The communication interface 904 is used to communicate with other devices. For example, the processor 901 communicates with the perception system and the positioning system through the communication interface 904 to obtain the position and motion attribute information of obstacles around the moving object.

[0156] The storage medium 903 may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. Among them, the nonvolatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0157] In addition to the data bus, the bus system 905 may also include a power bus, a control bus, a status signal bus, an in-vehicle bus (such as a controller area network (CAN) bus), etc. However, for the sake of clarity, various buses are labeled as the bus system 905 in the figure.

[0158] It should be understood that the device 900 according to the embodiment of the present application may correspond to the apparatus 800 in the embodiment of the present application, and may correspond to the device 900 executing the method according to the embodiment of the present application. Figure 4 The corresponding subjects in the device 900, and the above and other operations and / or functions of each module in the device 900 are respectively to achieve Figure 4 For the sake of brevity, the corresponding processes of each method in are not repeated here.

[0159] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0160] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A resource management method, It is characterized in that The method is applied in a device, the device includes at least one processor core, the threads running on the first processor core include a first thread, the first processor core is any one of the at least one processor core, the first thread is bound to a shared memory included in the device, the first thread is used to detect whether the shared memory stores data, and the shared memory is a memory space in the memory of the device, including: Detecting a state of a thread running on the first processor core, wherein when the first thread detects that a duration of time when the shared memory has no data exceeds a first time threshold, the state of the first thread is set to a suspended state; When it is detected that the states of the threads running on the first processor core are all in a suspended state, the first processor core is controlled to operate in a low power consumption mode, wherein the operating frequency of the first processor core is less than a frequency threshold when the first processor core operates in the low power consumption mode.

2. The method according to claim 1, It is characterized in that The controlling the first processor core to operate in a low power consumption mode includes: When it is detected that the duration of each thread on the first processor core being in the suspended state exceeds a second time threshold, the first processor core is controlled to operate in a low power consumption mode.

3. The method according to claim 1 or 2, It is characterized in that Before controlling the first processor core to operate in the low power consumption mode, the method further includes: When it is detected that the duration of the second thread in the suspended state exceeds a second time threshold, the second thread is migrated to a second processor core, the second thread is any thread running on the first processor core, the second processor core is a processor core in the device that has been working in a low power consumption mode, and the load of the second processor core is lower than a load threshold.

4. The method according to claim 1 or 2, It is characterized in that Before controlling the first processor core to operate in the low power consumption mode, the method further includes: When the usage rate of the first processor core is lower than the usage rate threshold, the third thread is migrated to the third processor core, the third thread is a thread in a non-suspended state on the first processor core, the usage rate of the first processor core is used to indicate the effective utilization rate of the computing resources of the first processor core, and the third processor core is a processor core in the device operating in a normal working mode.

5. The method according to claim 1 or 2, It is characterized in that Before controlling the first processor core to operate in the low power consumption mode, the method further includes: Threads in a non-suspended state on multiple processor cores in the device are merged into some processor cores among the multiple processor cores.

6. The method according to claim 1 or 2, It is characterized in that After controlling the first processor core to operate in the low power consumption mode, the method further includes: When there is data in the shared memory of the device, the first processor core is controlled to operate in a normal working mode, and the state of the first thread is set to a normal working state, wherein the operating frequency of the first processor core when the first processor core operates in the normal working mode is greater than or equal to a frequency threshold.

7. The method according to claim 1 or 2, It is characterized in that The processor core included in the device is a virtual processor core or a physical processor core.

8. A resource management device, It is characterized in that The apparatus is applied to a device, the device includes at least one processor core, the threads running on the first processor core include a first thread, the first processor core is any one of the at least one processor core, the first thread is bound to a shared memory included in the device, the first thread is used to detect whether the shared memory stores data, and the shared memory is a memory space in the memory of the device, including: a processing unit, configured to detect a state of a thread running on the first processor core, wherein when the first thread detects that a duration of time when the shared memory has no data exceeds a first time threshold, the state of the first thread is set to a suspended state; A control unit, used to control the first processor core to operate in a low power consumption mode when the processing unit detects that the states of the threads running on the first processor core are all in a suspended state, wherein the operating frequency of the first processor core is less than a frequency threshold when the first processor core operates in the low power consumption mode.

9. The device as claimed in claim 8, It is characterized in that The control unit is used to control the first processor core to operate in a low power consumption mode when the processing unit detects that the duration of each thread on the first processor core being in a suspended state exceeds a second time threshold.

10. The device according to claim 8 or 9, It is characterized in that The processing unit is further used for: When it is detected that the duration of the second thread in the suspended state exceeds a second time threshold, the second thread is migrated to a second processor core, the second thread is any thread running on the first processor core, the second processor core is a processor core in the device that has been working in a low power consumption mode, and the load of the second processor core is lower than a load threshold.

11. The device according to claim 8 or 9, It is characterized in that The processing unit is further used for: When the usage rate of the first processor core is lower than the usage rate threshold, the third thread is migrated to the third processor core, the third thread is a thread in a non-suspended state on the first processor core, the usage rate of the first processor core is used to indicate the effective utilization rate of the computing resources of the first processor core, and the third processor core is a processor core in the device operating in a normal working mode.

12. The device according to claim 8 or 9, It is characterized in that The processing unit is further used for: Threads in a non-suspended state on multiple processor cores in the device are merged into some processor cores among the multiple processor cores.

13. A processor, It is characterized in that The processor comprises a processor core, and the processor core is used to implement the operation steps of the method according to any one of claims 1 to 7.

14. A device, It is characterized in that The device includes a processor, the processor includes a processor core, and the processor core is used to implement the operation steps of the method according to any one of claims 1 to 7.

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