Cycle-dependent switching between program-verify techniques

Abstract

The present invention is entitled "Cycle-Dependent Switching Between Program-Verify Techniques". The present invention discloses a memory device for verifying whether a memory cell has been programmed. The memory device may be configured to verify the data state of a group of memory cells of a selected word line using a verification technique that is part of a group of verification techniques. One or more verification techniques may be utilized based on the iteration of the verification operation to be performed. The memory device may be further configured to perform a next iteration of the program-verify operation using the verification technique to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next iteration of the program-verify operation will be repeated until the group of memory cells has been verified.

Description

Background Art

[0001] The present technology relates to the operation of memory devices.

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc. In an EEPROM or flash NAND array architecture, the memory cells can be arranged in a matrix of rows and columns so that the gate of each memory cell is coupled to a word line through a row. The memory cells can be arranged together in strings so that the memory cells in a given string are coupled together in series from source to drain between a common source line and a common bit line. Summary of the invention

[0003] One aspect of the present invention relates to a storage device for verifying whether a memory cell has been programmed. The memory cell may be part of a memory cell array of a non-volatile memory. The control circuit may be configured to verify the data state of a group of memory cells of a selected word line using a verification technique that is part of a group of verification techniques. One or more verification techniques may be utilized based on the iteration of the verification operation to be performed. The storage device may be further configured to perform a next iteration of a program-verify operation using the verification technique to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next iteration of the program-verify operation may be repeated until the group of memory cells has been verified.

[0004] Another aspect of the present invention relates to a method for verifying whether one or more memory cells of a non-volatile memory have been programmed. The method includes verifying the data state of a group of memory cells of a selected word line using one or more verification techniques as part of a group of verification techniques. One or more verification techniques can be selected for use based on the iteration of the verification operation to be performed. The method also includes using the one or more verification techniques to perform a next iteration of the program-verify operation to verify whether the one or more memory cells are programmed, wherein the use of the one or more verification techniques and the next iteration of performing the program-verify operation will be repeated until the group of memory cells has been verified.

[0005] Yet another aspect of the present invention relates to a non-volatile memory device including a control circuit for verifying whether a memory cell has been programmed. The memory cell may be part of a memory cell array of a non-volatile memory. The control circuit may be configured to use one or more verification techniques as part of a program-verify operation to be performed on one or more memory cells, the one or more memory cells being part of a group of memory cells of a selected word line. The verification techniques may be utilized based on the iteration of the verification operation to be performed. The control circuit may use one or more verification techniques to perform the next iteration of the program-verify operation to verify whether the one or more memory cells are programmed. Using one or more verification techniques and performing the next iteration of the program-verify operation may be repeated until the group of memory cells has been verified. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various aspects of the present invention and, together with the description, serve to explain its principles. Where convenient, the same reference numerals will be used throughout the drawings to refer to the same or similar elements.

[0007] Figure 1A A block diagram of an exemplary memory device is shown.

[0008] Figure 1B A block diagram of an exemplary control circuit including a programming circuit, a counting circuit, and a determination circuit is shown.

[0009] Figure 2 Shown is a schematic diagram of a three memory string architecture in accordance with the principles of the present disclosure.

[0010] Figure 3 A block of memory cells in an exemplary two-dimensional configuration of the memory array of FIG. 1 is shown.

[0011] Figure 4A A cross-sectional view of an exemplary floating gate memory cell in a NAND string is shown.

[0012] Figure 4B A view taken along line 429 is shown. Figure 4A A cross-sectional view of the structure.

[0013] Figure 5A A cross-sectional view of an exemplary charge trapping memory cell in a NAND string is shown.

[0014] Figure 5B A view taken along line 429 is shown. Figure 5A A cross-sectional view of the structure.

[0015] Fig. 6A An exemplary block diagram of the sensing block SB1 of FIG. 1 is shown.

[0016] Figure 6B Another exemplary block diagram of the sensing block SB1 of FIG. 1 is shown.

[0017] Fig. 7A A perspective view of a group of blocks in an exemplary three-dimensional configuration of the memory array of FIG. 1 is shown.

[0018] Figure 7B Shows Fig. 7A An exemplary cross-sectional view of a portion of one of the blocks.

[0019] Figure 7C Shows Figure 7B A graph of the memory hole diameters in a stack.

[0020] Fig.7D Shows Figure 7B A close up view of region 622 of the stack.

[0021] Fig. 8A Shows Figure 7B Top view of an exemplary word line layer WLL0 of the stack.

[0022] Figure 8B Shows Figure 7B Top view of an exemplary top dielectric layer DL19 of the stack.

[0023] Fig. 9A Shows Fig. 8A Example NAND strings in sub-blocks SBa-SBd.

[0024] Fig. 9B Another exemplary view of NAND strings in a sub-block is shown.

[0025] Fig.10 Vth distributions of memory cells in an exemplary programming operation having at least four data states are shown.

[0026] FIG. 11A to FIG. 11G An exemplary memory device for verifying whether a memory cell has been programmed by selectively switching between different types of verification techniques is shown.

[0027] Fig.12 is a graph showing voltages for different verify techniques used to verify the data state of a memory cell.

[0028] Fig.13 is a flow chart illustrating a method for selectively switching between verification techniques to verify whether a group of memory cells have been programmed, according to the principles of the present disclosure. DETAILED DESCRIPTION

[0029] The following discussion relates to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used as limiting the scope of the present disclosure, including the claims. In addition, it will be appreciated by those skilled in the art that the following description has broad application, and the discussion of any embodiment is intended only as an example of that embodiment and is not intended to imply that the scope of the present disclosure (including the claims) is limited to that embodiment.

[0030] As described, in an EEPROM or Flash NAND array architecture, memory cells may be arranged in a matrix of rows and columns such that the gate of each memory cell is coupled to a word line through a row. The memory cells may be arranged together in a string array such that the memory cells in a given string are coupled together in series from source to drain between a common source line and a common bit line.

[0031] In order to program the memory cells included in the memory string array, a programming operation may be performed to apply a series of programming voltages to the memory cells after the memory cells are set in an erased state. Each programming voltage is provided in a programming loop (also referred to as a programming-verification iteration). For example, the programming voltage may be applied to a word line connected to a control gate of the memory cell. In one approach, incremental step pulse programming is performed, wherein the programming voltage increases in step size in each programming loop. When programming of a memory cell is completed, the memory cell may be locked out from further programming while continuing to program other memory cells in subsequent programming loops.

[0032] Each memory cell may be associated with a data state according to the write data in the program command. The memory cell may be in an erased data state (referred to herein as an erased state), or may be programmed to a programmed data state (referred to herein as a programmed state) that is different from the erased state. For example, in a memory device with two bits per cell, there are four data states, including an erased state and three programmed data states, which are referred to as A, B, and C data states (see FIG. 9 ). In a memory device with three bits per cell, there are eight data states, including an erased state and seven programmed data states, which are referred to as A data state, B data state, C data state, D data state, E data state, F data state, and G data state (see Fig.10 In a four-bit per cell memory device, there are sixteen data states, including an erased state and fifteen programmed data states, referred to as Er, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F data states (see Fig.10 ).

[0033] When a program command is issued, the write data is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state to which the cell will be programmed. Each memory cell is considered to have completed programming when the sensing operation determines that the associated verification voltage meets (e.g., is higher than) the threshold voltage (Vth). The sensing operation can determine whether the memory cell has a Vth higher than the associated verification voltage by applying the associated verification voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state such that the Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state such that the Vth is higher than the control gate voltage.

[0034] When programming a memory cell, it is important to perform programming-verification operations in a fast and accurate manner. As described below, many techniques or configurations can achieve fast programming or accurate programming, but cannot achieve both. In order to accurately program a memory cell, the Vth distribution of each data state must be fully spaced apart. This reduces the possibility that the higher voltage of one Vth distribution overlaps the voltage of another Vth distribution. This overlap may occur due to interference (such as noise, temperature variation of integrated circuits, etc.). In addition, the overlap of Vth distributions may cause runtime errors (for example, a bit with a value of zero may be mistakenly read as having a value of one). Therefore, it is useful to have a narrow Vth distribution that is less likely to be affected by interference and less likely to cause runtime errors.

[0035] However, given that memory cells are programmed at different rates, controlling the Vth distribution width may be difficult. For example, a first memory cell that is programmed faster than a second memory cell will require fewer programming pulses to complete programming. This causes the first Vth distribution of the first memory cell to be different from the second Vth distribution of the second memory cell. This may bring the Vth distributions closer together, thereby increasing the likelihood that the memory cells will be affected by disturbances.

[0036] One solution is to implement a multi-step verification (MSV) operation. An MSV operation is a two-step operation in which a different verification voltage is applied during each step. Once the threshold voltage of a memory cell reaches a first verification voltage, the control voltage is changed to slow down the faster programmed memory cell. However, an MSV operation can result in degraded performance (e.g., relative to a one-step programming operation) due to electron migration or interference on the memory cell. In addition, an MSV operation is inefficient because it requires additional steps in order to program the memory cell.

[0037] Another solution for creating a narrower Vth distribution is to implement a quick pass write (QPW) technique. The QPW technique involves adjusting the programming pulse step voltage as the memory cell approaches a programmed state. Thus, when the faster programmed memory cell is within the threshold range of the programmed state, the programming pulse step voltage is adjusted to slow down the rate at which the memory cell is programmed. However, this slows down the programming of all bits that remain to be programmed, thereby increasing the total programming time.

[0038] Some modifications of QPW techniques allow for faster programming times, but at the expense of accuracy. Coarse QPW techniques may include smart QPW (SQPW) operations, floating QPW (FQPW) techniques, etc. To provide an example, SQPW techniques may involve skipping a portion of a verify operation in order to reduce the total time for programming a memory cell. However, skipping a portion of a verify operation may reduce the accuracy of programming, thereby increasing the likelihood that the memory cell will be affected by a disturbance that may cause a runtime error.

[0039] For these reasons, and other reasons that will become apparent to one of ordinary skill in the art upon reading this specification and corresponding drawings, there is a need in the art for ways to create narrow Vth distributions without reducing the programming throughput of a memory device.

[0040] Some embodiments described herein may include systems and / or methods for performing iterations of a verify operation to verify data states of memory cells in a selected word line, wherein a fast programming verify technique or a precision-based verify technique is selected and implemented for each iteration of the verify operation. For example, the system and / or method may select a verification technique (e.g., a fast programming verify technique or a precision-based verify technique) based on the iteration of the verify operation being performed, based on whether the location of the memory cell is part of the upper tail or lower tail of a natural threshold voltage distribution (NVD) (e.g., using a fast programming verify technique) or part of the middle portion of the NVD (e.g., using a precision-based verify technique), etc.

[0041] Thus, the systems and / or methods described herein can effectively and efficiently reduce the Vth distribution of memory cells. In addition, the systems and / or methods save resources (e.g., processing resources, memory resources, etc.) by reducing the program-verify operation execution time relative to a worse system or method (e.g., using only fast program-verify techniques or using only precision-based verification techniques). Reducing the total program-verify time saves resources (e.g., power resources, processing resources, memory resources, etc.) that would otherwise be spent programming and verifying memory cells using only precision-based verification techniques.

[0042] Figure 1A1 is a block diagram of an exemplary memory device. The memory device 100 may include one or more memory dies 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and is addressable by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks SB1, SB2, ..., SBp (sense circuitry) and allows pages of memory cells to be read or programmed in parallel. Typically, the controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120, and between the controller and the one or more memory dies 108 via a line 118.

[0043] The memory structure may be a 2D memory structure or a 3D memory structure. The memory structure may include one or more memory cell arrays, the one or more memory cell arrays including a 3D array. The memory structure may include a monolithic three-dimensional memory structure in which multiple memory levels are formed above (but not in) a single substrate such as a wafer, without an intervening substrate. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of a memory cell array having an active area disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0044] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. State machine 112 provides chip-level control of memory operations.

[0045] The storage area 113 may, for example, be provided for programming parameters. The programming parameters may include a programming voltage, a programming voltage bias, a location parameter indicating the location of a memory cell, a contact wire connector thickness parameter, a verification voltage, etc. The location parameter may indicate the location of the memory cell within the entire NAND string array, the location of the memory cell within a specific NAND string group, the location of the memory cell on a specific plane, etc. The contact wire connector thickness parameter may indicate the thickness of the contact wire connector, the substrate or material constituting the contact wire connector, etc.

[0046] An on-chip address decoder 114 provides an address interface between the address interface used by the host or memory controller and the hardware address used by decoders 124 and 132. A power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module may include drivers for the word lines, SGS and SGD transistors, and source lines. In one approach, the sense block may include a bit line driver. The SGS transistor is a select gate transistor at the source end of the NAND string, and the SGD transistor is a select gate transistor at the drain end of the NAND string.

[0047] In some embodiments, some of the components may be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) may be considered to be at least one control circuit, which at least one control circuit or controller is configured to perform the actions described herein. For example, the control circuit may include any one of the control circuit 110, the state machine 112, the decoder 114 / 132, the power control module 116, the sense blocks SBb, SB2, ..., SBp, the read / write circuit 128, the controller 122, etc., or a combination thereof. The control circuit may include a programming circuit configured to perform a programming operation on a group of memory cells, wherein the group of memory cells includes memory cells assigned to represent one data state of a plurality of data states and memory cells assigned to represent another data state of a plurality of data states;

[0048] The programming operation includes a plurality of program-verify iterations; and in each program-verify iteration, the programming circuit performs programming on one word line, after which the programming circuit applies a verification signal to the one word line. The control circuit may further include a counting circuit configured to obtain a count of memory cells that pass a verification test for one data state. The control circuit may further include a determination circuit configured to determine a specific program-verify iteration among the plurality of program-verify iterations based on an amount by which the count exceeds a threshold, in which a verification test for another data state is performed on the memory cells assigned to represent another data state.

[0049] For example, Figure 1B is a block diagram of an exemplary control circuit 150 including a programming circuit 151 , a counting circuit 152 , and a determination circuit 153 .

[0050] The off-chip controller 122 may include a processor 122c, a storage device (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct multiple read errors caused when the upper tail of the Vth distribution becomes too high. However, there may be uncorrectable errors in some cases. The technology provided herein reduces the possibility of uncorrectable errors.

[0051] The storage device includes code such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein.Alternatively or additionally, the processor may access code from the storage device 126a of the memory structure, such as a reserved area of ​​memory cells in one or more word lines.

[0052] For example, the controller can use code to access the memory structure, such as for programming operations, read operations and erase operations. The code may include startup code and control code (e.g., a set of instructions). Boot code is software that initializes the controller and enables the controller to access the memory structure during the boot or startup process. The controller can use code to control one or more memory structures. When powered on, the processor 122c takes out the boot code from ROM 122a or storage device 126a for execution, and the boot code initializes the system components and loads the control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes a driver that performs basic tasks, such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0053] In general, the control code may include instructions to perform the functions described herein, including the steps of the flow charts discussed further below, and provide voltage waveforms, including those discussed further below.

[0054] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smart phone, a tablet computer, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid-state memory), and the one or more processor-readable storage devices store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0055] In addition to NAND flash memory, other types of non-volatile memory may be used.

[0056] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, a flash memory device may be configured in a NAND configuration or a NOR configuration.

[0057] The memory device may be formed of passive components and / or active components in any combination. By way of non-limiting example, passive semiconductor memory components include ReRAM device components, which in some embodiments include resistivity switching storage elements, such as antifuses or phase change materials, and optional steering elements, such as diodes or transistors. In addition, by way of non-limiting example, active semiconductor memory components include EEPROM and flash memory device components, which in some embodiments include components containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0058] Multiple memory elements may be configured so that they are connected in series or so that each element may be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically includes memory elements connected in series. A NAND string is an example of a group of transistors connected in series that includes a memory cell and a SG transistor.

[0059] A NAND memory array can be configured so that the array consists of multiple memory strings, where the string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located in and / or above a substrate can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0060] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the major surface of a substrate supporting the memory elements. The substrate may be a wafer on or in which the layers of the memory elements are formed, or it may be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0061] The memory elements may be arranged in a single memory device level in an ordered array, such as in multiple rows and / or columns. However, the memory elements may be arranged in an unconventional configuration or a non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as a bit line and a word line.

[0062] The three-dimensional memory array is arranged so that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., x, y and z directions, where the z direction is substantially vertical and the x and y directions are substantially parallel to the major surface of the substrate).

[0063] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), each column having a plurality of memory cells. The columns may be arranged in a two-dimensional configuration, such as in an xy plane, resulting in a three-dimensional arrangement of memory elements, wherein the elements are located on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements may also constitute a three-dimensional memory array.

[0064] By way of non-limiting example, in a three-dimensional array of NAND strings, memory elements may be coupled together to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, with some NAND strings containing memory elements in a single memory level and other strings containing memory elements that span multiple memory levels. Three-dimensional memory arrays may also be designed in NOR configurations as well as ReRAM configurations.

[0065] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers of each memory device level that make up the array are typically formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intervening layers between the memory device levels.

[0066] The two-dimensional arrays may then be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory may be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. In addition, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0067] Figure 2 Schematic diagrams of exemplary BiCS memory architectures utilizing interleaved memory strings are shown. For example, reference numeral 201 shows a schematic diagram of an exemplary BiCS 4 memory architecture, reference numeral 203 shows a schematic diagram of an exemplary BiCS 5 memory architecture, and reference numeral 205 shows a schematic diagram of an exemplary BiCS 6 memory architecture. In some embodiments, as shown, a BiCS memory architecture can include an array of interleaved NAND strings.

[0068] Referring to the memory architecture 201, rows 207-0 to 207-7 in the string architecture 201 are shown. The memory string may include a group of memory cells (e.g., corresponding to a group of memory holes). Each row is shown as having four ends for the memory string. The memory string may be connected to an adjacent string at an end (not visible below this view). A first group of rows 207-0 to 207-3 are shown on the left side of the dummy row 208. A second group of rows 207-4 to 207-7 are shown on the right side of the dummy row 208. The dummy row 208 separates two groups of rows in the staggered eight rows. The source line 209 is positioned at the edge of the first group and away from the dummy row 208. The source line 210 is positioned at the edge of the second group and away from the dummy row 208 and the source line 209.

[0069] Memory architectures 203 and 205 may be similar to the architecture of string architecture 201, except that additional groups are added. String architecture 203 may be twice the size of architecture 201, and may include sixteen rows of strings, where each group of four rows is separated by a dummy row. String architecture 205 may be larger than both memory architecture 201 and memory architecture 203. String architecture 205 may include twenty rows of strings, where each group of four rows is separated by a dummy row 208.

[0070] In some embodiments, the memory architecture 201, 203, and / or 205 may include a chip below array structure. For example, the memory architecture 201, 203, and / or 205 may include a chip below array structure, whereby the control circuit is below the memory array including the group of memory strings. With the chip below array structure, the memory strings may include direct strap contacts to the source lines for read and erase operations.

[0071] In some embodiments, the memory architecture 205 can be a BiCS 6 memory architecture. For example, in a BiCS 6 memory architecture, there can be five NAND string groups. (NAND string group 212-1, NAND string group 212-2, NAND string group 212-3, NAND string group 212-3, and NAND string group 212-4). NAND string group 212-0 and NAND string group 212-4 can be referred to as outer NAND string groups. NAND string group 212-1, NAND string group 212-2, and NAND string group 212-3 can be collectively referred to as inner NAND string groups. NAND string group 212-2 can be referred to as the innermost NAND string group.

[0072] In some embodiments, the BiCS 6 memory architecture can be a 3-D memory architecture including one or more 3-D blocks. In this case, the 3-D block can be logically segmented into multiple sub-blocks corresponding to the NAND string groups. The 3-D block can also be segmented into multiple planes. Additional block descriptions are also provided herein.

[0073] Although one or more embodiments relate to a BiCS memory architecture, it should be understood that this is provided by way of example. In practice, the techniques described herein may be implemented on any number of different memory architectures, such as a tubular BiCS (P-BiCS), a vertical recessed array transistor (VRAT) architecture, and / or any other type of EEPROM or flash memory architecture.

[0074] Figure 3Blocks of memory cells in an exemplary two-dimensional configuration of the memory array 126 of FIG. 1 are shown. The memory array may include many blocks. Each exemplary block 300, 310 includes multiple NAND strings and corresponding bit lines, such as BL0, BL1, ... shared between blocks. Each NAND string is connected to a drain select gate (SGD) at one end, and the control gate of the drain select gate is connected via a common SGD line. The NAND string is connected to a source select gate at its other end, which is in turn connected to a common source line 320. Sixteen word lines, such as WL0 to WL15, extend between the source select gate and the drain select gate. In some cases, dummy word lines that do not contain user data may also be used in memory arrays adjacent to select gate transistors. Such dummy word lines can shield edge data word lines from certain edge effects.

[0075] One type of nonvolatile memory that can be provided in a memory array is floating gate memory. Figure 4A and Figure 4B Other types of nonvolatile memory may also be used. For example, a charge trap memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. See Figure 5A and Figure 5B . A triple layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a limited area. This stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split gate configuration, in which a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0076] In another approach, an NROM cell is used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends over the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0077] Figure 4AA cross-sectional view of an exemplary floating gate memory cell in a NAND string is shown. The bit line or NAND string direction goes into the page, and the word line direction is from left to right. For example, word line 424 extends across the NAND string, which includes corresponding channel regions 406, 416 and 426. Memory cell 400 includes control gate 402, floating gate 404, tunnel oxide layer 405 and channel region 406. Memory cell 410 includes control gate 412, floating gate 414, tunnel oxide layer 415 and channel region 416. Memory cell 420 includes control gate 422, floating gate 421, tunnel oxide layer 425 and channel region 426. Each memory cell is in a different corresponding NAND string. An inter-poly dielectric (IPD) layer 428 is also shown. The control gate is part of the word line. In Figure 4B A cross-sectional view along the contact line connector 429 is provided in FIG.

[0078] The control gate wraps around the floating gate, increasing the surface contact area between the control gate and the floating gate. This results in higher IPD capacitance, which results in a higher coupling ratio, which makes programming and erasing easier. However, when NAND memory devices are scaled down, the spacing between adjacent cells becomes smaller, so there is almost no room for the control gate and IPD between two adjacent floating gates.

[0079] As another alternative, Figure 5A and Figure 5B As shown, a flat or planar memory cell has been developed in which the control gate is flat or planar; that is, it does not wrap around the floating gate, and its only contact with the charge storage layer is from above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is made thinner. Alternatively, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the problem of ballistic electron transport, in which during programming, electrons can travel through the floating gate after tunneling through the tunnel oxide.

[0080] Figure 5B The contact line connector 529 is shown Figure 5A 530 includes an SGS transistor 531, exemplary memory cells 500, 533, ..., 534 and 535, and an SGD transistor 536. As an example of each memory cell, the memory cell 400 includes a control gate 402, an IPD layer 428, a floating gate 404 and a tunnel oxide layer 505, which is similar to Figure 5AThe channel in the IPD layer in the SGS and SGD transistors allows the control gate layer and the floating gate layer to communicate. For example, the control gate layer and the floating gate layer can be polysilicon, and the tunnel oxide layer can be silicon oxide. The IPD layer can be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0081] The NAND string may be formed on a substrate including a p-type substrate region 555, an n-type well 556, and a p-type well 557. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch may be directly applied to the channel region of the substrate.

[0082] Fig. 6A An exemplary block diagram of the sense block SB1 of FIG. 1 is shown. In one approach, the sense block includes a plurality of sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuits 650a, 651a, 652a, and 553a are associated with data latches 650b, 551b, 652b, and 653b, respectively. In one approach, different corresponding sense blocks may be used to sense different subsets of bit lines. This allows the processing load associated with the sense circuits to be divided and processed by corresponding processors in each sense block. For example, a sense circuit controller 660 in SB1 may communicate with the group of sense circuits and latches. The sense circuit controller may include a precharge circuit 661 that provides a voltage to each sense circuit for setting a precharge voltage. In one possible approach, for example, via Figure 6B The data bus 603 and the local bus such as LBUS1 or LBUS2 in the circuit separately provide voltage to each sensing circuit. In another possible method, for example, via Figure 6B The contact line 605 in the sense circuit provides a common voltage to each sense circuit at the same time. The sense circuit controller may also include a memory 662 and a processor 663. The memory 662 may store code that can be executed by the processor to perform the functions described herein. These functions may include reading a latch associated with the sense circuit, setting a bit value in the latch, and providing a voltage for setting a precharge level in a sense node of the sense circuit. Further exemplary details of the sense circuit controller 650a and the sense circuit 651a are provided below.

[0083] For example, the sense circuit controller may communicate with the different sense circuits in a time multiplexed manner, for example. In one approach, the contact wire 605 may be connected to a voltage clamp in each sense circuit.

[0084] The sensing circuit 651a includes a latch 651b, which includes a trip latch 646, an offset verification latch 647, and a data state latch 648. The voltage clamp 641 can be used to set a precharge voltage at the sensing node 642. The sensing node to bit line (BL) switch 643 selectively allows the sensing node to communicate with the bit line 645, and the voltage clamp 644 can set a voltage on the bit line. The bit line 645 is connected to one or more memory cells, such as memory cell MC2. The local bus LBUS2 allows the sensing circuit controller to communicate with components in the sensing circuit, such as in some cases communicating with the latch 651b and the voltage clamp. In order to communicate with the sensing circuit 651a, the sensing circuit controller provides a voltage to the transistor 606 via the contact line 601 to connect LBUS2 to DBUS.

[0085] Sense circuit 650a may be a first sense circuit including first trip latch 626 , and sense circuit 651a may be a second sense circuit including second trip latch 646 .

[0086] The sensing circuit 650a is an example of a first sensing circuit including a first sensing node 622, wherein the first sensing circuit is associated with the first memory cell MC1 and the first bit line 625. The sensing circuit 651a is an example of a second sensing circuit including a second sensing node 642, wherein the second sensing circuit is associated with the second memory cell MC2 and the second bit line 645.

[0087] In some embodiments, the memory cell may include a tag register including a set of latches storing a tag bit. In some embodiments, the number of tag registers may correspond to the number of data states. In some embodiments, one or more tag registers may be used to control the type of verification technique used when verifying the memory cell. In some embodiments, the output of the tag bit may modify the associated logic of the device, such as an address decoding circuit, so that a specified cell block is selected. Body operations (e.g., erase operations, etc.) may be performed using a tag set in a tag register, or a combination of a tag register and an address register, as in implicit addressing, or alternatively performed by direct addressing using only an address register.

[0088] Figure 6B 1 shows another exemplary block diagram of the sensing block SB1 of FIG. 1. The sensing circuit controller 660 communicates with a plurality of sensing circuits including the exemplary sensing circuits 650a and 651a, such as Fig. 6AAs shown. The sensing circuit 650a includes a latch 650b, which includes a trip latch 626, an offset verification latch 627, and a data state latch 628. The sensing circuit also includes a voltage clamp 621, such as a transistor, which sets a precharge voltage at a sensing node 622. A sensing node to bit line (BL) switch 623 selectively allows the sensing node to communicate with a bit line 625, for example, the sensing node is electrically connected to the bit line so that the sensing node voltage can be attenuated. The bit line 625 is connected to one or more memory cells, such as memory cell MC1. The voltage clamp 624 can set the voltage on the bit line, such as during a sensing operation or during a programming voltage. The local bus LBUS1 allows the sensing circuit controller to communicate with components in the sensing circuit, such as in some cases communicating with the latch 650b and the voltage clamp. In order to communicate with the sensing circuit 650a, the sensing circuit controller provides a voltage to the transistor 604 via the contact line 602 to connect LBUS1 to the data bus DBUS 603. Communication may include sending data to the sensing circuit and / or receiving data from the sensing circuit.

[0089] Fig. 7A 1 is a perspective view of a group of blocks 700 in an exemplary three-dimensional configuration of the memory array 126 of FIG. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (storage elements), and a peripheral region 704 with circuits for use with the blocks. For example, the circuit may include a voltage driver 705 that can be connected to the control gate layer of the block. In one approach, the control gate layers at a common height in the block are driven together. The substrate 701 can also carry the circuit below the block together with one or more lower metal layers, which are patterned in conductive paths to carry the signals of the circuit. These blocks are formed in the middle region 702 of the memory device. In the upper region 703 of the memory device, one or more upper metal layers are patterned in conductive paths to carry the signals of the circuit. Each block includes a stacked region of memory cells, wherein the stacked alternating layers represent word lines. In one possible approach, each block has an opposite layered side, and vertical contacts extend upward from the layered side to the upper metal layer to form a connection with the conductive path. Although four blocks are shown as an example, two or more blocks extending in the x-direction and / or the y-direction may be used.

[0090] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends in one or more upper metal layers (the word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends in one or more upper metal layers (the bit line direction). The z-direction represents the height of the memory device.

[0091] Figure 7B Depicted Fig. 7A An exemplary cross-sectional view of a portion of one of the blocks of FIG. The block includes a stack 710 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0-WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. In addition, a region including a stack of NAND strings NS1 and NS2 is shown. Each NAND string contains a memory hole 718 or 719 that is filled with material that forms a memory cell adjacent to the word line. In FIG. Fig.7D The stacked region 722 is shown in more detail in FIG.

[0092] The stack includes a substrate 711, an insulating film 712 on the substrate, and a portion of a source line SL. NS1 has a source terminal 713 at the bottom 714 of the stack and a drain terminal 715 at the top 716 of the stack. Contact line connectors (e.g., slits, such as metal-filled slits) 717 and 720 can be provided periodically across the stack as interconnects extending through the stack, such as to connect the source line to a specific contact line above the stack. The contact line connector can be used during the formation of the word line and subsequently filled with metal. A portion of the bit line BL0 is also shown. A conductive via 721 connects the drain terminal 715 to BL0.

[0093] Figure 7C Shows Figure 7B The vertical axis is plotted against Figure 7B The stack alignment is shown, and the width (wMH), eg, diameter, of the memory holes 718 and 719 is shown. Fig. 7A The word line layers WLL0-WLL10 of are repeated as examples and are at corresponding heights z0-z10 in the stack. In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth to diameter ratio of about 25 to 30 is common. The memory hole may have a circular cross-section. Due to the etching process, the memory hole width may vary along the length of the hole. Typically, the diameter of the memory hole tapers from its top to its bottom. That is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, so that the diameter of the memory hole widens slightly before tapering from its top to its bottom.

[0094] Due to the non-uniformity of the width of the storage holes, the programming speed (including the programming slope and the erase speed of the memory cells) may vary based on their position along the storage holes (e.g., based on their height in the stack). For smaller diameter memory holes, the electric field across the tunnel oxide is relatively strong, making the programming and erase speeds relatively high. One approach is to define a group of adjacent word lines for which the memory holes have similar diameters (e.g., within a defined diameter range), and apply an optimized verification scheme for each word line in the group. Different groups may have different optimized verification schemes.

[0095] Fig.7D Shows Figure 7B 722 of the stack. Memory cells are formed at different levels of the stack at the intersection of the word line layer and the memory hole. In this example, SGD transistors 780 and 781 are provided above the dummy memory cells 782 and 783 and the data memory cell MC. Multiple layers may be deposited along the sidewalls (SW) of the memory hole 730 and / or within each word line layer (e.g., using atomic layer deposition). For example, each column (e.g., a column formed by the material within the memory hole) may include a charge trapping layer or film 763 (such as SiN or other nitride), a tunnel layer 664, a polysilicon body or channel 765, and a dielectric core 766. The word line layer may include a blocking oxide / block high-k material 760, a metal barrier layer 761, and a conductive metal 762 (such as tungsten) as a control gate. For example, control gates 790, 791, 792, 793, and 794 are provided. In this example, all layers except the metal are provided in the memory hole. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars may form a pillar-shaped active area (AA) of the NAND string.

[0096] When programming a memory cell, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and travel through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0097] Each of the memory holes may be filled with a plurality of annular layers, the annular layers including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are located between the core region and a word line in each of the memory holes.

[0098] The NAND string can be considered to have a floating channel because the length of the channel is not formed on the substrate. In addition, the NAND string is provided by multiple word line layers stacked on top of each other and separated from each other by dielectric layers.

[0099] Fig. 8A Shows Figure 7B 00143] A top view of an exemplary word line layer WLL0 of a stack of. As mentioned, a 3D memory device may include a stack of alternating conductive layers and dielectric layers. The conductive layers provide control gates for SG transistors and memory cells. The layer for the SG transistors is the SG layer, and the layer for the memory cells is the word line layer. In addition, memory holes are formed in the stack and filled with charge trapping material and channel material. Thus, a vertical NAND string is formed. The source line is connected to the NAND string below the stack and the bit line is connected to the NAND string above the stack.

[0100] The block BLK in the 3D memory device can be divided into sub-blocks, wherein each sub-block includes a NAND string group with a common SGD control line. For example, refer to the SGD line / control gate SGD0, SGD1, SGD2 and SGD3 in the sub-blocks SBa, SBb, SBc and SBd, respectively. In addition, the word line layer in the block can be divided into regions. Each region is in a corresponding sub-block and can extend between contact line connectors (e.g., slits), which are periodically formed in the stack to process the word line layer during the manufacturing process of the memory device. The treatment may include replacing the sacrificial material of the word line layer with metal. Generally speaking, the distance between the contact line connectors should be relatively small to consider the distance that the etchant can travel laterally to remove the sacrificial material, and the metal can travel to fill the gap created by removing the sacrificial material. For example, the distance between the contact line connectors can allow several rows of memory holes to exist between adjacent contact line connectors. The layout of the memory holes and contact line connectors should also consider the limit of the number of bit lines that can extend across the region when each bit line is connected to a different memory cell. After processing the wordline layer, the contact line connectors may optionally be filled with metal to provide interconnection through the stack.

[0101] In this example, there are four rows of memory holes between adjacent contact line connectors. A row here is a group of memory holes aligned in the x-direction. In addition, the rows of memory holes are arranged in a staggered pattern to increase the density of the memory holes. The word line layer or word line is divided into regions WLL0 a, WLL0 b, WLL0 c, and WLL0 d, each of which is connected by a contact line 813. In one approach, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. Contact line 813 is in turn connected to the voltage driver of the word line layer. Region WLL0a has exemplary memory holes 810 and 811 along contact line 812. Region WLL0b has exemplary memory holes 814 and 815. Region WLL0 c has exemplary memory holes 816 and 817. Region WLL0 d has exemplary memory holes 818 and 819. Memory holes are also Figure 8BEach memory hole can be part of a corresponding NAND string. For example, memory holes 810, 814, 816, and 818 can be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0102] Each circle represents a cross section of a memory hole at a word line layer or SG layer. The exemplary circles shown with dashed lines represent memory cells provided by the material in the memory hole and the adjacent word line layer. For example, memory cells 820 and 821 are in WLL0a, memory cells 824 and 825 are in WLL0b, memory cells 826 and 827 are in WLL0c, and memory cells 828 and 829 are in WLL0d. These memory cells are at a common height in the stack.

[0103] Contact line connectors (e.g., slots, such as metal-filled slots) 801, 802, 803, and 804 can be located between and adjacent to the edges of regions WLL0a-WLL0d. The contact line connectors provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack can be connected to a wire above the stack, where the wire is connected to a voltage driver in a peripheral region of the memory device. See also Fig. 9A learn Fig. 8A Further details of sub-blocks SBa-SBd.

[0104] Figure 8B Shows Figure 7B 1. A top view of an exemplary top dielectric layer DL19 of a stack of . The dielectric layer is divided into regions DL19a, DL19b, DL19c, and DL19d. Each region can be connected to a corresponding voltage driver. This allows a group of memory cells in one region of the word line layer to be programmed simultaneously, where each memory cell is in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line to allow or prohibit programming during each programming voltage.

[0105] Region DL19a has exemplary memory holes 810 and 811 along contact line 812a that coincides with bit line BL0. Many bit lines extend over and connect to the memory holes, as indicated by the "X" symbol. BL0 connects to a group of memory holes that include memory holes 811, 815, 817, and 819. Another exemplary bit line BL1 connects to a group of memory holes that include memory holes 810, 814, 816, and 818. Also shown is Fig. 8AThe contact line connectors (eg, slots, metal filled slots) 801, 802, 803, and 804 in the stack as they extend vertically through the stack. The bit lines may be numbered in the order BL0-BL23 across the DL19 layer in the x-direction.

[0106] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells at the right hand edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in an adjacent row of cells adjacent to the first row at the right hand edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells at the left hand edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in an adjacent row of memory cells adjacent to the first row at the left hand edge.

[0107] Fig. 9A Shows Fig. 8A An exemplary NAND string in a sub-block SBa-SBe of FIG. Figure 7B The structure of is consistent with that of . The conductive layers in the stack are shown for reference on the left hand side. Each sub-block includes multiple NAND strings, of which one exemplary NAND string is shown. For example, SBa includes exemplary NAND string NS0, SBb includes exemplary NAND string NS1, SBc includes exemplary NAND string NS2, SBd includes exemplary NAND string NS3, and SBe includes exemplary NAND string NS4.

[0108] In addition, NS0_SBa includes SGS transistors 900 and 901 , dummy memory cells 902 and 903 , data memory cells 904 , 905 , 906 , 907 , 908 , 909 , 910 , 911 , 912 , 913 and 914 , dummy memory cells 915 and 916 , and SGD transistors 917 and 918 .

[0109] NS1_SBb includes SGS transistors 920 and 921 , dummy memory cells 922 and 923 , data memory cells 924 , 925 , 926 , 927 , 928 , 929 , 930 , 931 , 932 , 933 , and 934 , dummy memory cells 935 and 936 , and SGD transistors 937 and 938 .

[0110] NS2_SBc includes SGS transistors 940 and 941 , dummy memory cells 942 and 943 , data memory cells 944 , 945 , 946 , 947 , 948 , 949 , 950 , 951 , 952 , 953 , and 954 , dummy memory cells 955 and 956 , and SGD transistors 957 and 958 .

[0111] NS3_SBd includes SGS transistors 960 and 961 , dummy memory cells 962 and 963 , data memory cells 964 , 965 , 966 , 967 , 968 , 969 , 970 , 971 , 972 , 973 , and 974 , dummy memory cells 975 and 976 , and SGD transistors 977 and 978 .

[0112] NS4_SBe includes SGS transistors 980 and 981 , dummy memory cells 982 and 983 , data memory cells 984 , 985 , 986 , 987 , 988 , 989 , 980 , 981 , 982 , 983 , and 984 , dummy memory cells 985 and 986 , and SGD transistors 987 and 988 .

[0113] At a given height in the block, the memory cells in each sub-block are at a common height. For example, a group of memory cells (including memory cell 904) are in a plurality of memory cells formed along a tapered memory hole in a stack of alternating conductive layers and dielectric layers. A group of memory cells is at a specific height z0 in the stack. Another group of memory cells (including memory cell 924) connected to one word line (WLL0) is also at a specific height. In another approach, another group of memory cells (e.g., including memory cell 912) connected to another word line (e.g., WLL8) is at another height (z8) in the stack.

[0114] Fig. 9B Another exemplary view of a NAND string in a sub-block is shown. The NAND string includes NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe with 48 word lines (e.g., WL0-WL47). Each sub-block includes a group of NAND strings extending in the x direction and having a common SGD line (e.g., SGD0, SGD1, SGD2, SGD3, or SGD4). In this simplified example, there is only one SGD transistor and one SGS transistor in each NAND string. The NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe are located in sub-blocks SBa, SBb, SBc, SBd, and SBe, respectively. In addition, an exemplary group of word lines G0, G1, and G2 is shown.

[0115] Fig.10 Waveforms of an exemplary programming operation are shown. The horizontal axis shows the programming loop number, and the vertical axis shows the programming voltage value and the programming verification value. The programming voltage (Vpgm) may include a word line voltage (WLVpgm) and / or a bit line voltage (BLVpgm). In general, a programming operation may involve applying a pulse train to a selected word line, where the pulse train includes a plurality of program-verify (PV) iterations. The programming portion of a PV iteration includes a programming voltage, and the verification portion of a PV iteration includes one or more verification voltages.

[0116] For each programming voltage, a square wave is shown for simplicity, but other shapes are possible, such as a multi-level shape or a ramp shape. In addition, incremental step pulse programming (ISPP) is used in this example, in which the programming voltage is incremented in each consecutive programming cycle. This example uses ISPP in a single programming step in which programming is completed. ISPP can also be used in each programming step of a multi-step operation.

[0117] The pulse train typically includes programming voltages that are gradually increased in magnitude using a voltage bias (dVpgm) in each programming-verification iteration. The voltage bias may be, for example, a word line voltage bias. A new pulse train may be applied in each programming step of a multi-step programming-verification operation, starting with an initial programming voltage (e.g., initial Vpgm) and ending with a final programming voltage (e.g., final Vpgm) that does not exceed a threshold voltage Vth (e.g., a maximum allowed value). The initial programming voltage may be the same or different in different programming steps. The final programming voltage may also be the same or different in different programming steps. The voltage bias may be the same or different in different programming steps. In some cases, a smaller voltage bias is used in the final programming step to reduce the Vth distribution width.

[0118] Pulse train 1000 includes a series of programming voltages 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1008, 1009, 1010, 1011, 1012, 1013, 1014, and 1015 applied to a word line selected for programming, and an associated group of non-volatile memory cells. In the example shown, one, two, or three verification voltages are provided after each programming voltage, for example, based on the number of target data states being verified. The number of target data states being verified may, for example, correspond to the number of memory cells associated with the word line. The programming voltage and the corresponding verification voltage may be separated by applying 0V to the selected word line between the programming voltage and the verification voltage.

[0119] In the example shown, the A-state verification voltage VvA (e.g., waveform or programming signal 1016) may be applied after each of the first programming voltage 1001, the second programming voltage 1002, and the third programming voltage 1003, respectively. The A-state verification voltage VvA and the B-state verification voltage VvB (e.g., programming signal 1017) may be applied after each of the fourth programming voltage 1004, the fifth programming voltage 1005, and the sixth programming voltage 1006, respectively. The A-state verification voltage VvA, the B-state verification voltage VvB, and the C-state verification voltage VvC (e.g., programming signal 1018) may be applied after each of the seventh programming voltage 1007 and the eighth programming voltage 1008, respectively. The B-state verification voltage VvB and the C-state verification voltage VvC (e.g., programming signal 1019) may be applied after each of the ninth programming voltage 1009, the tenth programming voltage 1010, and the eleventh programming voltage 1011, respectively. Finally, the C-state verification voltage VvC (eg, program signal 1020 ) may be applied after each of the twelfth, thirteenth, fourteenth, and fifteenth programming voltages 1012 , 1013 , 1014 , and 1015 , respectively.

[0120] In some embodiments, the memory device 100 (e.g., using the state machine 112 of the control circuit 110, the controller 122, and / or the control circuit 150) can use different programming voltages and / or different programming voltage biases to perform verification operations. In some embodiments, the programming voltage and the programming voltage bias used to perform the programming operation can include a word line voltage and a word line voltage bias, respectively. Additionally or alternatively, the programming voltage and the programming voltage bias used to perform the programming operation can include a bit line voltage and a bit line voltage bias, respectively.

[0121] FIG. 11A to FIG. 11G An exemplary memory device for verifying whether a memory cell has been programmed by selectively switching between different types of verification techniques is shown. For example, FIG. 11A to FIG. 11G One or more exemplary embodiments 1100 of a non-volatile memory device 1102 including a control circuit 1104 and a memory cell array 1106 are shown. The memory cell array 1106 may include a group of memory cells connected via word lines and bit lines. The control circuit 1104 may include a state machine capable of communicating with the memory cells in the memory cell array 1106. The selected word line (shown as WL n ) may include memory cells (MC) A, MC B, MC C, and MC D. The selected word line may be connected to a set of bit lines, the set of bit lines including bit lines (BL) 0, BL 1, BL 2, and BL 3. Control circuit 1104 may verify the memory cells using different verification techniques for different iterations of the verification operation, as will be further described herein.

[0122] like Fig.11A 1108, the control circuit 1104 may identify a set of data states for the set of memory cells of the selected word line. In some embodiments, the control circuit 1104 may receive programming command data (e.g., from a controller associated with a non-volatile memory device), and the programming command data may specify the data state to which the memory cell and / or each corresponding memory cell is to be programmed. In addition or alternatively, the control circuit may identify the data state by performing one or more read operations (sometimes referred to as sensing operations). For example, the control circuit may perform a read operation that includes providing a signal to a data latch of the memory cell. The signal may cause the data latch to provide a return signal to the control circuit that is capable of identifying the data state. The control circuit may perform a read operation for each corresponding memory cell connected to the selected word line.

[0123] As shown by reference numeral 1110, control circuitry 1104 may perform a programming operation to begin programming memory cells of a selected word line. A description of a programming operation is provided elsewhere herein.

[0124] like Fig. 11B As shown in reference numeral 1112, the control circuit 1104 can be preconfigured to use the fast programming verification technique for the first iteration of the verification operation. For example, the control circuit 1104 can be preconfigured so that when an initialization procedure (e.g., a startup procedure) is executed, the control circuit 1104 can be initialized to utilize the fast programming verification technique. In some embodiments, the initialization procedure can also initialize one or more internal data states and / or related parameters.

[0125] The set of verification techniques may, for example, include one or more fast programming verification techniques and one or more precision-based verification techniques. The one or more fast programming verification techniques may include a coarse quick pass write (QPW) technique, a floating QPW (FQPW) technique, a smart QPW (SQPW) technique, etc. The one or more precision-based verification techniques may include an iQPW verification technique and / or a similar type of accurate programming technique. The fast programming verification technique may not be as accurate as the precision-based verification technique, but may have a faster execution time, while the precision-based verification technique may be more accurate, but may have a slower execution time.

[0126] In some embodiments, the control circuit 1104 may be configured to utilize a fast programming verification technique for the first iteration based on the iteration of the verification operation. For example, for each data state being verified, the control circuit 1104 may be configured to use different verification techniques for different iterations of the verification operation. As a specific example, the control circuit 1104 may be configured to use a fast programming verification technique for the first and last iterations of the verification operation of each memory cell. In this example, the control circuit 1104 may be configured to use a precision-based programming technique for the iteration that occurs between the first and last iterations. In some embodiments, such as when the memory cell is a quad-level cell (QLC), the control circuit 1104 may be configured to use a fast programming verification technique for the first and second iterations of the verification operation and for the penultimate iteration and the final iteration. By using the fast programming verification technique for the outermost iterations (e.g., the first and last iterations), when the position of the threshold voltage distribution (Vth) of the memory cell in the natural threshold voltage distribution (NVD) corresponds to the upper and lower tails of the NVD, the control circuit 1104 utilizes the verification technique.

[0127] In some embodiments, the control circuit 1104 can utilize a fast programming verification technique by referencing a data structure (e.g., a lookup table) associated with the memory cells of the selected word line. For example, in order to utilize a verification technique to verify data state A, the control circuit 1104 can refer to a lookup table value associated with memory cell A. The lookup table may include a set of lookup table values ​​for associating a particular iteration of a verification operation with a particular verification technique (e.g., a fast programming verification technique, a precision-based verification technique, etc.). For example, the lookup table may include a first lookup table value (e.g., a bit value of one) corresponding to a fast programming verification technique and a second lookup table value (e.g., a bit value of zero) corresponding to a precision-based verification technique. In some embodiments, the lookup table may correspond to the group of memory cells. In some embodiments, multiple lookup tables may be implemented and may correspond to the group of memory cells.

[0128] For example, the control circuit 1104 may reference a first field of the lookup table. The first field corresponding to the first iteration of the verification operation may store a lookup table value of one, where the lookup table value corresponds to a fast programming verification technique. Therefore, because the first field in the lookup table has a lookup table value of one, the control circuit 1104 is able to use the fast programming verification technique to verify whether memory cell A has been programmed to data state A.

[0129] In some embodiments, the control circuit 1104 may utilize a fast programming verification technique based on a reference tag register. For example, if the memory cell is a TLC and the lookup table is a tag register, there may be a tag bit reserved for each data state (e.g., there may be seven tag bits corresponding to seven data states). Because some data states do not begin verification until a programming iteration of certain configurations is executed, the tag bit may be incremented from a value of zero to a value of one based on the programming iteration of certain configurations being executed. As a specific example, the tag register may have the following value: [0 0 0 0 0 0 0]. After executing the first iteration, the tag register may be incremented to have the following value: [1 0 0 0 0 0 0]. This signal is used to perform a fast programming verification technique after the first programming iteration. For example, if the verification of data state B is configured to start during the fourth iteration, the tag register after the fourth iteration of programming may be updated to have the following value: [1 1 0 0 0 0 0]. In this way, the tag register allows the control circuit 1104 to determine when to begin executing the fast programming verification technique.

[0130] Utilizing a verification technique may refer to being configured with, selecting, or identifying one or more verification voltage values ​​corresponding to the verification technique. For example, fast programming verification techniques and precision-based verification techniques may involve using different verification voltages, different bit line voltage biases, different sensing times, etc. to verify memory cells. Fast programming verification techniques may include a first set of bit line voltage biases or a first set of sensing times. Precision-based verification techniques may include a second set of bit line voltage biases or a second set of sensing times. Voltage biases or sensing times may be used to control (e.g., speed up, slow down, etc.) a set of verification voltages provided to memory cells via selected word lines. In some embodiments, such as when the verification technique involves slowing down the speed at which memory cells are programmed, the verification technique may include one or more programming voltages (e.g., Vpgm), one or more programming voltage biases (e.g., dVpgm), etc. As described elsewhere herein (e.g., in conjunction with Fig.13 etc.) provides additional information on implementation verification techniques.

[0131] In some embodiments, the control circuit 1104 may be configured with (or have access to) a voltage bias value or a sensing time (charging time) value for a corresponding verification technique. In some embodiments, a data structure accessible to the control circuit 1104 may associate the voltage bias value or the sensing time value with: an iteration counter identifying the current iteration of the verification operation, an iteration stop counter identifying the final iteration (or predicted final iteration) of the verification operation, a memory cell identifier of the memory cell to be verified, a data state identifier of the data state to which the memory cell is being programmed, etc. In addition or alternatively, the voltage bias value or the sensing time value may be stored using a separate data structure or data storage device.

[0132] In some embodiments, control circuit 1104 may be configured with instructions to specify an initial verification voltage. Thus, control circuit 1104 may not have to reference a data structure to identify an appropriate voltage bias or sensing time to apply until a second iteration of the verification operation. In this way, control circuit 1104 saves resources (e.g., processing resources, power resources, etc.) relative to having to reference a data structure to identify an initial verification voltage.

[0133] As shown by reference numeral 1114, the control circuit 1104 may perform a first iteration of the verification operation using a fast programming verification technique. For example, the control circuit 1104 may apply a first bit line voltage bias to a bit line (e.g., BL 0) connected to the memory cell A, may apply an initial verification voltage to the selected word line, and / or may verify whether the memory cell A has a threshold voltage Vth that is higher than the initial verification voltage. By applying the first bit line voltage bias to the memory cell A, the control circuit 1104 causes a change in the voltage received at the control gate of the memory cell A (e.g., a control gate voltage (VCG), a verification voltage, etc.).

[0134] In some embodiments, the control circuit 1104 can selectively prohibit certain memory cells from receiving a verify voltage. For example, certain memory cells are unlikely to have completed programming after one iteration. Therefore, the control circuit 1104 can be configured to prohibit these memory cells from receiving a verify pulse until a subsequent iteration of the verify operation. In this way, resources (e.g., processing resources, power resources, etc.) are saved, which would otherwise be wasted in attempting to verify memory cells that have not yet been fully programmed.

[0135] In some embodiments, the control circuit 1104 can be configured to utilize a fast programming verification technique during the first and last iterations of verifying the data state of each respective memory cell. In some embodiments, the control circuit 1104 can be configured to utilize a fast programming verification technique based on the position of the Vth in the NVD corresponding to the lower tail or the upper tail. In some embodiments, the control circuit 1104 can be configured to utilize a precision-based verification technique during the second to the second-to-last iterations of the verification operation.

[0136] In some embodiments, the total number of verify operations to be performed for each data state may be predetermined or predicted. In this case, the control circuit 1104 may reference an iteration counter so that the control circuit 1104 can perform an action based on the particular iteration of the verify operation being performed. In some embodiments, the control circuit 1104 may update the iteration counter based on performing a programming operation (or a verify operation). For example, the control circuit 1104 may reference a data structure and may increment the iteration counter to track the current iteration of the verify operation. The data structure may be part of a flag register or may be supported by another device or component.

[0137] In the example shown, control circuit 1104 may update the iteration counter from a value of zero to a value of one. By updating the iteration counter, control circuit 1104 may use the value stored by the iteration counter to identify which field in the corresponding flag register to read in order to identify an appropriate verification voltage value for a verification operation. For example, if the iteration counter has a value of one, control circuit 1104 may be configured to perform a read operation to read the first field of one or more flag registers.

[0138] As described, the iteration counter can track a value representing the total number of verification operation iterations that have been performed. Additionally or alternatively, the iteration counter can track a value representing the number of times verification of a particular data state of a memory cell has been attempted. In some embodiments, the control circuit 1104 can determine the position of the lower tail of the NVD based on the detection result.

[0139] In this manner, control circuit 1104 performs a first iteration of a verify operation using a fast program verify technique.

[0140] like Fig. 11C As shown in the reference numeral 1116, the control circuit 1104 can be configured to use the precision-based verification technique for the second iteration of the verification operation. For example, the control circuit 1104 can be configured to utilize the precision-based verification technique by referencing a lookup table or a flag register to verify that the current iteration is not the first iteration of the verification operation, and verifying during the current iteration that the Vth of the memory does not have a position in the NVD that corresponds to the lower tail of the NVD (as further described herein). The precision-based verification technique can utilize a second set of verification voltages, a second set of bit line voltage biases, a second set of sensing times, etc.

[0141] In some embodiments, the control circuit 1104 can determine to utilize a precision-based verification technique based on reference to a data structure (e.g., a lookup table) associated with the memory cell. For example, to utilize a verification technique to verify whether memory cell A has been programmed to data state A, the control circuit 1104 can reference a second field of the lookup table. The second field corresponding to the second iteration of the verification operation can store a lookup table value of zero, where the lookup table value corresponds to a precision-based verification technique. Therefore, because the second field in the lookup table has a lookup table value of zero, the control circuit 1104 is able to use a precision-based verification technique to verify whether memory cell A has been programmed to data state A.

[0142] In some embodiments, the control circuit 1104 may determine whether the current iteration of the verify operation is the first iteration. For example, the control circuit 1104 may reference a flag register having flag bit values ​​corresponding to the data state, and may determine that the current iteration is not the first iteration based on one or more of the flag bit values ​​having a value of one (e.g., a value of zero may indicate that the current iteration is the first iteration and may be incremented to a value of one after the first iteration has completed). This may allow the control circuit 1104 to confirm that the current iteration is not the first iteration of the verify technique. As will be shown below by one or more techniques, the control circuit 1104 may then perform a second verification to verify whether the current iteration is the final iteration of the verify operation, and if the current iteration is not the final iteration, a precision-based verification technique may be performed.

[0143] In some embodiments, the control circuit 1104 may determine whether the current iteration of the verification operation may be the final iteration. For example, the control circuit 1104 may refer to an iteration counter that is incremented after each successive iteration of the verification operation has been completed. In this case, the control circuit 1104 may be configured with a value identifying the total number of iterations, and the iteration counter value may be compared to a value identifying the final iteration (or identifying the total number of iterations) to determine whether the current iteration is the final iteration. If the current iteration is the final iteration, the control circuit 1104 may perform a fast programming verification technique. If the current iteration is not the final iteration, the control circuit 1104 may perform a precision-based verification technique.

[0144] In the example shown, the iteration counter may have a value identifying the current iteration as the second iteration. The control circuit 1104 may compare the iteration counter to a configuration value identifying the final iteration, determine that the current iteration is not the final iteration, and may perform a precision-based verification technique based on this determination as further described herein.

[0145] In some embodiments, the control circuit 1104 can determine which memory cells have not yet completed programming for the corresponding data state. For example, the control circuit 1104 can determine the specific memory cells that have not yet completed the program-verify operation for each data state. In this case, the control circuit 1104 (for example, by using or referring to a counting circuit) can perform a detection operation to count the number of memory cells that have not yet completed programming.

[0146] If the number of memory cells remaining to be programmed fails to meet the threshold criteria, the control circuit 1104 may perform a fast programming verification technique. For example, if the threshold criteria is that at least two memory cells remain to be programmed, and only one memory cell has not yet been programmed, the number of memory cells fails to meet the threshold criteria and the control circuit 1104 may perform a fast programming verification technique. If the number of memory cells remaining to be programmed meets the threshold criteria, the control circuit 1104 may perform a precision-based verification technique. For example, if the threshold criteria is that at least two memory cells remain to be programmed, and five memory cells remain to be programmed, the number of memory cells meets the threshold criteria and the control circuit 1104 may perform a precision-based verification technique.

[0147] In the example shown, the control circuit 1104 can compare the number of memory cells remaining to be programmed to the total number of memory cells for each data state. In this case, the control circuit 1104 can determine to perform a precision-based verification technique based on the number of memory cells that have not yet completed programming satisfying a threshold criterion, such as a criterion that at least two memory cells remain to be programmed.

[0148] In some implementations, the control circuitry 1104 can determine which memory cells have completed programming for respective data states. For example, the control circuitry 1104 can determine which memory cells have completed programming, rather than determining which memory cells have not yet completed programming.

[0149] The control circuit 1104 may perform a second iteration of the verification operation, as indicated by reference numeral 1118. For example, the control circuit 1104 may perform the second iteration of the verification operation by applying a first bit line voltage bias in a second set of bit line voltage biases to a bit line connected to the memory cell A, applying a second verification voltage in the set of verification voltages to a selected word line, and / or verifying whether the memory cell A has a threshold voltage higher than the second verification voltage.

[0150] In some embodiments, the control circuit 1104 may update the iteration counter based on performing the second iteration of the verification operation. For example, the control circuit 1104 may increment the iteration counter to track the current iteration of the verification operation. In the example shown, the control circuit 1104 may update the iteration counter from a value of one to a value of two.

[0151] In this manner, control circuit 1104 performs a second iteration of the verification operation using a precision-based verification technique.

[0152] like Fig.11D As shown in reference numeral 1120, the control circuit 1104 may be configured to use a precision-based verification technique for a third iteration of the verification operation. For example, the control circuit 1104 may be configured to utilize the precision-based verification technique by referencing a lookup table or a tag register to verify that the current iteration is not the first iteration of the verification operation, and verifying during the current iteration that the Vth of the memory does not have a position in the NVD that corresponds to the lower tail of the NVD. The precision-based verification technique may utilize a second set of bit line voltage biases or a second set of sensing times.

[0153] In some embodiments, the control circuit 1104 can determine to utilize a precision-based verification technique based on reference to a data structure (e.g., a lookup table) associated with the memory cell. For example, to utilize a verification technique to verify whether memory cell A has been programmed to data state A, the control circuit 1104 can reference a third field of the lookup table. The third field corresponding to the third iteration of the verification operation can store a lookup table value of zero, where the lookup table value corresponds to a precision-based verification technique. Therefore, because the third field in the lookup table has a lookup table value of zero, the control circuit 1104 is able to use a precision-based verification technique to verify whether memory cell A has been programmed to data state A.

[0154] In some embodiments, the control circuit 1104 may determine whether the current iteration of the verification operation may be the final iteration. For example, the control circuit 1104 may refer to an iteration counter that is incremented after each successive iteration of the verification operation has been completed. In this case, the control circuit 1104 may be configured with a value identifying the total number of iterations, and the iteration counter value may be compared to a value identifying the final iteration (or identifying the total number of iterations) to determine whether the current iteration is the final iteration. If the current iteration is the final iteration, the control circuit 1104 may perform a fast programming verification technique. If the current iteration is not the final iteration, the control circuit 1104 may perform a precision-based verification technique.

[0155] In the example shown, the iteration counter may have a value identifying the current iteration as the third iteration. The control circuit 1104 may compare the iteration counter to a configuration value identifying the final iteration, determine that the current iteration is not the final iteration, and may perform a precision-based verification technique based on the determination.

[0156] In some embodiments, the control circuit 1104 may determine which memory cells have not yet completed programming for the corresponding data state. For example, the control circuit 1104 may determine, for each data state, specific memory cells that have not yet completed the program-verify operation. In this case, the control circuit 1104 (e.g., by using or referring to a counting circuit) may perform a detection operation to count the number of memory cells that have not yet completed programming. In the example shown, the control circuit 1104 may compare the number of memory cells that remain to be programmed with the total number of memory cells for each data state. In this case, the control circuit 1104 may determine to perform a precision-based verification technique based on the number of memory cells that have not yet completed programming meeting a threshold criterion (such as a criterion that at least two memory cells remain to be programmed).

[0157] In some embodiments, control circuitry 1104 can reference corresponding flag registers of other memory cells (eg, memory cell B, memory cell C, and memory cell D) and can determine that each memory cell is not to be verified during a fourth iteration of the verify operation.

[0158] As indicated by reference numeral 1122, the control circuit 1104 may perform a third iteration of the verification operation using a precision-based verification technique. For example, the control circuit 1104 may perform the third iteration of the verification operation by applying a second bit line voltage bias in the second set of bit line voltage biases to a bit line connected to the memory cell A, applying a third verification voltage in the set of verification voltages to a selected word line, and / or verifying whether the memory cell A has a threshold voltage higher than the third verification voltage.

[0159] In some implementations, the control circuit 1104 can update the iteration counter based on performing the third iteration of the verify operation. For example, the control circuit 1104 can increment the iteration counter from a value of two to a value of three.

[0160] As such, control circuit 1104 performs a third iteration of the verification operation using the precision-based verification technique.

[0161] like Fig.11E As shown in reference numeral 1124, the control circuit 1104 may be configured to use the fast programming verification technique and the precision-based verification technique for the fourth iteration of the verification operation. For example, the control circuit 1104 may be configured to use the fast programming verification technique to verify whether the memory cell B has been programmed to the data state B, and may be configured to use the precision-based verification technique to verify whether the memory cell A has been programmed to the data state A.

[0162] In some embodiments, the control circuit 1104 may determine to utilize a precision-based verification technique to verify whether memory cell A has been programmed to data state A, and to utilize a fast programming verification technique to verify whether memory cell B has been programmed to data state B. This determination may be made by reference to a data structure (e.g., a lookup table) associated with the memory cells. For example, the control circuit 1104 may reference the fourth field of the first row of the lookup table. The fourth field of the first row corresponding to the fourth iteration of the verification operation may store a lookup table value of zero, where the lookup table value corresponds to the precision-based verification technique.

[0163] Additionally, the control circuit 1104 may reference the fourth field of the second row of the lookup table. The fourth field of the second row corresponding to the fourth iteration of the verify operation may store a lookup table value of one, where the lookup table value corresponds to the fast programming verify technique. Therefore, because the fourth field in the first row has a lookup table value of zero and the fourth field of the second row has a lookup table value of one, the control circuit 1104 is able to verify memory cell A using the precision-based verification technique and verify memory cell B using the fast programming verify technique.

[0164] In some embodiments, the control circuit 1104 may determine whether a current iteration of the verification operation may be a final iteration, as described above. In the example shown, the iteration counter may have a value identifying the current iteration as the fourth iteration. The control circuit 1104 may compare the iteration counter with a first configuration value identifying the final iteration to verify data state A, may determine that the current iteration is not the final iteration, and may perform a precision-based verification technique based on the determination.

[0165] In some embodiments, the control circuit 1104 can determine which memory cells have not yet completed programming for the corresponding data state, as described above. In the example shown, the control circuit 1104 can compare the number of memory cells that remain to be programmed to a given data state with the total number of memory cells for that data state. In this case, the control circuit 1104 can determine to perform a precision-based verification technique based on the number of memory cells that have not yet completed programming meeting a threshold criterion, such as a criterion that at least two memory cells remain to be programmed.

[0166] In some embodiments, control circuitry 1104 can reference corresponding flag registers of other memory cells (eg, memory cell C and memory cell D) and can determine that each memory cell is not to be verified during a fourth iteration of the verify operation.

[0167] As shown by reference numeral 1126, the control circuit 1104 may perform a fourth iteration of the verification operation using the fast programming verification technique and the precision-based verification technique. For example, the control circuit 1104 may perform the fourth iteration of the verification operation by applying a second bit line voltage bias in the second set of bit line voltage biases to a bit line connected to the memory cell A, applying a fourth verification voltage in the set of verification voltages to a selected word line, and / or verifying whether the memory cell A has a threshold voltage higher than the fourth verification voltage.

[0168] In some embodiments, the control circuit 1104 may update the iteration counter based on performing the fourth iteration of the verification operation. For example, the control circuit 1104 may reference the data structure and may increment the iteration counter to track the current iteration of the verification operation. In the example shown, the control circuit 1104 may update the iteration counter from a value of three to a value of four.

[0169] In this manner, the control circuit 1104 performs a fourth iteration of the verification operation using the fast program verification technique and the precision-based verification technique.

[0170] like Fig.11F As shown in reference numeral 1128, the control circuit 1104 may be configured to use the fast programming verification technique and the precision-based verification technique for the fifth iteration of the verification operation. For example, the control circuit 1104 may be configured to use the fast programming verification technique to verify whether the memory cell A has been programmed to data state A and to verify whether the memory cell C has been programmed to data state C. In addition, the control circuit 1104 may be configured to use the precision-based verification technique to verify whether the memory cell B has been programmed to data state B.

[0171] In some embodiments, the control circuit 1104 can determine to utilize a fast programming verification technique to verify whether memory cell A has been programmed to data state A. This determination can be made by referencing a data structure (e.g., a lookup table) associated with the memory cell. For example, the control circuit 1104 can refer to the fifth field of the first row of the lookup table. The fifth field of the first row corresponding to the fifth iteration of the verification operation can store a lookup table value of one, where the lookup table value corresponds to the fast programming verification technique.

[0172] In addition, the control circuit 1104 may reference the fifth field of the second row of the lookup table. The fifth field of the second row corresponding to the fifth iteration of the verification operation may store a lookup table value of zero, where the lookup table value corresponds to the precision-based verification technique. In addition, the control circuit 1104 may reference the fifth field of the third row of the lookup table. The fifth field of the third row corresponding to the fifth iteration of the verification operation may store a lookup table value of one, where the lookup table value corresponds to the fast programming verification technique. Therefore, because the fifth fields in the first and third rows have a lookup table value of one and the fifth field of the second row has a lookup table value of zero, the control circuit 1104 can verify memory cell A and memory cell C using the fast programming verification technique, and can verify memory cell B using the precision-based verification technique.

[0173] In some embodiments, the control circuit 1104 may determine whether the current iteration of the verification operation may be the final iteration, as described above. In the example shown, the iteration counter may have a value that identifies the current iteration as the fifth iteration. The control circuit 1104 may compare the iteration counter with the first configuration value that identifies the final iteration to verify data state A, may determine that the current iteration is the final iteration, and may perform a fast programming verification technique based on the determination. In addition, the control circuit may perform similar analysis on memory cell B and memory cell C, respectively.

[0174] In some embodiments, the control circuit 1104 may determine which memory cells have not yet completed programming for the corresponding data state, as described above. In the example shown, the control circuit 1104 may compare the number of memory cells that remain to be programmed to data state A (e.g., one) with the total number of memory cells of the data state. In this case, the control circuit 1104 may determine to perform a precision-based verification technique based on the number of memory cells that have not yet completed programming (e.g., one) failing to meet a threshold criterion (such as a criterion that at least two memory cells remain to be programmed). The control circuit 1104 may determine to perform a fast programming verification operation based on the determination. The control circuit 1104 may perform a similar analysis on memory cell B and memory cell C, respectively (e.g., except that the criterion may be met and a precision-based verification technique may be performed).

[0175] In some embodiments, control circuit 1104 can reference corresponding flag registers of other memory cells (eg, memory cell D, etc.) and can determine that each memory cell is not to be verified during a fifth iteration of the verify operation.

[0176] As shown by reference numeral 1130, the control circuit 1104 may perform a fifth iteration of the verification operation using a fast programming verification technique and a precision-based verification technique. For example, the control circuit 1104 may verify the memory cell A by applying a second bit line voltage bias in the first set of bit line voltage biases to a bit line connected to the memory cell A, applying a fifth verification voltage in the set of verification voltages to a selected word line, and / or verifying whether the memory cell A has a threshold voltage higher than the fifth verification voltage. The control circuit 1104 may perform similar actions to verify the memory cell B and the memory cell C.

[0177] In some implementations, the control circuit 1104 can update the iteration counter based on performing a fifth iteration of the verify operation. For example, the control circuit 1104 can increment the iteration counter from a value of four to a value of five.

[0178] Although not shown, control circuitry 1104 may also perform a sixth, seventh, eighth, and ninth iteration of the verify operation. Control circuitry 1104 may perform these iterations in a manner consistent with that described herein for other iterations of the verify operation.

[0179] like Fig.11G As shown in reference numeral 1132, the control circuit 1104 may be configured to use a fast program verification technique for the final iteration of the verification operation. For example, the control circuit 1104 may be configured to use a fast program verification technique to verify whether the memory cell D has been programmed to data state D.

[0180] In some embodiments, the control circuit 1104 can determine to utilize the fast programming verification technique based on reference to a data structure (e.g., a lookup table) associated with the memory cell. For example, the control circuit 1104 can reference the tenth field of the fourth row of the lookup table. The tenth field corresponding to the tenth iteration of the verification operation can store a lookup table value of one, where the lookup table value corresponds to the fast programming verification technique. Therefore, because the tenth field in the fourth row of the lookup table has a lookup table value of one, the control circuit 1104 is able to use the fast programming verification technique to verify whether the memory cell D has been programmed to the data state D.

[0181] In some embodiments, the control circuit 1104 may determine whether a current iteration of the verify operation may be a final iteration, as described above. In the example shown, the iteration counter may have a value identifying the current iteration as the tenth iteration. The control circuit 1104 may compare the iteration counter to a configuration value identifying the final iteration for each respective data state (e.g., iteration ten for data state D). The control circuit 1104 may determine that the current iteration is the final iteration based on the comparison, and thus may perform a fast programming verify technique.

[0182] In some embodiments, the control circuit 1104 can determine which memory cells have not yet completed programming for data state D, as described above. In the example shown, the control circuit 1104 can compare the number of memory cells that remain to be programmed to data state D (e.g., one) to the total number of memory cells of that data state. In this case, the control circuit 1104 can determine to perform a precision-based verification technique based on the number of memory cells that have not yet completed programming (e.g., one) failing to meet a threshold criterion, such as a criterion that at least two memory cells remain to be programmed. The control circuit 1104 can determine to perform a fast programming verification operation based on this determination.

[0183] In some embodiments, the control circuit 1104 can be configured to utilize a fast programming verification technique to verify the memory cell D based on the iteration of the verification operation being a sixth iteration. For example, the control circuit 1104 can compare the iteration counter value with the configured final iteration value and can be configured to utilize the fast programming verification technique based on the iteration counter value matching the final iteration value.

[0184] The control circuit 1104 may perform a final iteration of the verification operation, as indicated by reference numeral 1134. For example, the control circuit 1104 may perform the final iteration of the verification operation by applying a third bit line voltage bias in the second set of bit line voltage biases to a bit line connected to the memory cell D, applying a sixth verification voltage in the set of verification voltages to a selected word line, and / or verifying whether the memory cell D has a threshold voltage higher than the sixth verification voltage.

[0185] In some implementations, the control circuit 1104 may update the iteration counter based on the last iteration of performing the verify operation. For example, the control circuit 1104 may increment the iteration from a value of five to a value of six.

[0186] Thus, the control circuit 1104 selectively switches between the fast programming verification technique and the precision-based verification technique when verifying the memory cells in the selected word line. By applying different verification techniques to the memory cells during different iterations of the verification operation, the control circuit 1104 reduces the total programming-verification time while maintaining the programming accuracy associated with using the precision-based verification technique. By reducing the total time used to program and verify the memory cells, the control circuit 1104 saves resources (e.g., power resources, processing resources, memory resources, etc.) that would otherwise be spent programming and verifying the memory cells using only the precision-based verification technique.

[0187] Fig.12is a graph showing voltages of different verification techniques for verifying the data state of a memory cell. As shown in the top portion of the page, a coarse QPW technique may be implemented for the upper and lower tails of the NVD, and an iQPW technique may be implemented for the middle portion of the NVD. By implementing the coarse QPW technique for the tail of the NVD, and by implementing the iQPW technique for the middle of the NVD, the NVD is shifted to the right (as shown by the dotted line).

[0188] As shown, some of the reference verification voltage levels corresponding to the coarse QPK are different from the voltage levels corresponding to the iQPK. For example, as shown, for data states B and E, the reference verification voltage values ​​of the iQPK are slightly higher (relative to the corresponding coarse QPK reference verification voltage values). The reference verification voltage is also Fig. 11B Using VvA 1 and VvA 2 To show.

[0189] By verifying memory cells using multiple verification techniques, the memory cells may be verified quickly and accurately, and the Vth of data states of corresponding memory cells may be narrower (eg, relative to poor verification, relative to using only fast program verification techniques, etc.).

[0190] Fig.13 1 is a flow chart illustrating a method for selectively switching between verification techniques to verify whether a group of memory cells have been programmed according to the principles of the present disclosure. Step 1302 identifies a memory cell in a selected word line. Step 1304 selects a verification technique from a set of available verification techniques for the memory cell, wherein the selection is based on the iteration of the verification operation being performed. The set of available verification techniques may, for example, include a fast programming verification technique (comprising: a fast programming verification technique comprising ... Fig.13 The box on the right hand side of Fig.13 ) etc.

[0191] If a fast programming verification technique is selected, step 1306 applies a verification voltage value associated with a first verification sub-cycle of the fast programming verification technique. The verification voltage value associated with the first verification sub-cycle may include a word line verification voltage value, a bit line voltage bias value, a sensing time value, etc. For example, a first threshold voltage may be used to precharge a word line with a predetermined margin below a second threshold voltage (e.g., when a programmed cell is being verified relative to the second threshold voltage). For another example, one or more bit line voltage biases may be used to precharge the associated one or more bit lines to be suitable for sensing. This may allow a sensing operation (e.g., a read operation) to be performed on the memory cell.

[0192] Step 1308 determines whether the threshold voltage distribution (Vth) of the memory cell meets (eg, is greater than) a first verification voltage threshold. For example, a sensing operation (eg, a read operation) may be performed on the memory cell to determine whether the Vth of the memory cell meets the first verification voltage threshold.

[0193] If Vth does not meet the first verification voltage threshold, then step 1308 is repeated by applying a bit line voltage bias or a sensing time to the bit line. If the Vth of the memory cell does not meet the first verification voltage threshold, then step 1310 performs the next iteration of the programming operation (e.g., this may first include incrementing Vpgm using the dVpgm value). In some embodiments, step 1310 may be performed only if no memory cell's Vth meets the first verification voltage threshold.

[0194] If the Vth of the memory cell satisfies the first verification voltage threshold, step 1312 applies a verification voltage value associated with a second verification sub-cycle of the fast programming verification technique. The verification voltage value associated with the second verification sub-cycle may include a word line verification voltage value, a bit line voltage bias value, a sensing time value, etc., wherein the verification voltage value in the second verification sub-cycle is offset from the verification voltage value in the second verification sub-cycle. For example, the second threshold voltage can be used to precharge the word line to a level relative to which sensing is to be performed. For another example, one or more bit line voltage biases can be used to precharge the associated one or more bit lines to be suitable for sensing.

[0195] Step 1314 determines whether the Vth of the memory cell meets (eg, is greater than) a second verification voltage threshold. For example, a sensing operation may be performed on the memory cell to determine whether the Vth of the memory cell meets the second verification voltage threshold.

[0196] If the Vth of the memory cell does not meet the first verification voltage threshold, step 1310 performs the next iteration of the programming operation (e.g., this may first include incrementing Vpgm using the dVpgm value). If the Vth of the memory cell meets the first verification voltage threshold, step 1312 applies a verification voltage value associated with a second verification sub-cycle of the fast programming verification technique.

[0197] The verification voltage value associated with the second verification sub-cycle may include a word line verification voltage value, a bit line voltage bias value, a sensing time value, etc., wherein the verification voltage value in the second verification sub-cycle is offset from the verification voltage value in the second verification sub-cycle. For example, the second threshold voltage may be used to precharge the word line to a level relative to which sensing is to be performed. For another example, one or more bit line voltage biases may be used to precharge one or more bit lines to a voltage suitable for sensing.

[0198] Step 1314 determines whether the Vth of the memory cell meets the second verification voltage threshold. If the Vth of the memory cell does not meet the second verification voltage threshold, step 1310 performs the next iteration of the programming operation. If the Vth of the memory cell does meet the second verification voltage threshold, step 1316 prohibits the memory cell from receiving additional verification voltages.

[0199] If a precision-based verification technique is selected, step 1318 applies a verification voltage value associated with a first verification sub-cycle of the precision-based verification technique. The verification voltage value associated with the first verification sub-cycle of the precision-based verification technique may include a word line verification voltage value, a bit line voltage bias value, a sensing time value, etc. For example, a first threshold voltage may be used to precharge a word line with a predetermined margin below a second threshold voltage (e.g., when a programmed cell is being verified relative to the second threshold voltage). For another example, one or more bit line voltage biases may be used to precharge the associated one or more bit lines to be suitable for sensing. This may allow a sensing operation (e.g., a read operation) to be performed on the memory cell.

[0200] Step 1320 compares the Vth of the memory cell to a first verification voltage threshold. For example, a sensing operation (eg, a read operation) may be performed on the memory cell to compare the Vth of the memory cell to the first verification voltage threshold.

[0201] Step 1322 applies a verification voltage value associated with the second verification sub-cycle. Step 1324 includes comparing the Vth of the memory cell to the second verification threshold. Step 1326 includes determining whether the Vth of the memory cell meets both verification voltage thresholds. If not, step 1328 may perform the next iteration of the programming operation. Although not shown, if, for example, the Vth of the memory cell meets the first verification threshold but does not meet the second verification threshold, dVpgm may be increased. If so, step 1316 prohibits the memory cell from receiving additional verification voltages.

[0202] As used herein, a verify operation may be a verify portion of a program-verify operation.

[0203] The above specific embodiments of the present invention have been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments are selected to best explain the principles of the present invention and its practical application, so that other technical personnel in the field can best utilize the present invention in various embodiments and in various modifications suitable for the intended specific use. The scope of the present invention is intended to be limited by the appended claims.

[0204] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to implement functions such as programming and reading. The associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0205] Those skilled in the art will recognize that the present technology is not limited to the two-dimensional and three-dimensional exemplary structures described, but encompasses all related memory structures within the spirit and scope of the present technology as described herein and as understood by those skilled in the art.

[0206] The above specific embodiments of the present invention have been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments are selected to best explain the principles of the present invention and its practical application, so that other technical personnel in the field can best utilize the present invention in various embodiments and in various modifications suitable for the intended specific use. The scope of the present invention is intended to be limited by the appended claims.

[0207] Various terms are used to refer to specific system components. Different companies may refer to components by different names—this document does not intend to distinguish between components that differ in name but function the same. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended manner and, therefore, should be understood to mean "including, but not limited to..." In addition, the terms "couple" or "couples" are intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, that connection may be made through a direct connection or through an indirect connection via other devices and connections.

[0208] Additionally, when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there can be intervening layers. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, or there can be one or more intervening layers. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0209] As described herein, the controller includes individual circuit components, an application specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a processor with control software, a field programmable gate array (FPGA), or a combination thereof.

Claims

1. A non-volatile memory device, comprising: a control circuit for verifying whether a memory cell has been programmed, wherein the memory cell is part of a memory cell array of the non-volatile memory device, and wherein the control circuit is configured to: verifying data states of a group of memory cells of a selected word line using a verify technique as part of a group of verify techniques, wherein the verification technique is utilized based on an iteration of a program-verify operation being performed; performing a next iteration of the program-verify operation using the verification technique to verify whether one or more memory cells in the group of memory cells of the selected word line have been programmed, wherein the next iteration of using the verification technique and performing the program-verify operation is repeated until the group of memory cells have been verified; wherein the verification technique is a fast program-verify technique using a one-step verification or a precision-based verification technique using a plurality of verification steps; The verification technique is the fast program-verify technique for a first iteration and a last iteration of the program-verify operation, and the precision-based verification technique for an intermediate set of iterations of the program-verify operation.

2. The nonvolatile memory device according to claim 1 , wherein when using the verification technique, the control circuit is configured to: A flag bit corresponding to a currently verified data state included in a flag register is set, wherein a field in the flag register includes a first value corresponding to a fast programming verification technique and a second value corresponding to a precision-based verification technique.

3. The nonvolatile memory device according to claim 1 , wherein the control circuit is further configured to: An iteration counter is incremented based on performing the next iteration of the program-verify operation such that the iteration counter identifies a number of iterations of the program-verify operation that have been performed, wherein the iteration counter corresponds to a lower tail of a natural voltage threshold distribution NVD.

4. A non-volatile memory device comprising: a control circuit for verifying whether a memory cell has been programmed, wherein the memory cell is part of a memory cell array of the non-volatile memory device, and wherein the control circuit is configured to: verifying data states of a group of memory cells of a selected word line using a verify technique as part of a group of verify techniques, wherein the verification technique is utilized based on an iteration of a program-verify operation being performed; performing a next iteration of the program-verify operation using the verification technique to verify whether one or more memory cells in the group of memory cells of the selected word line have been programmed, wherein the next iteration of using the verification technique and performing the program-verify operation is repeated until the group of memory cells have been verified; wherein the verification technique is a fast program-verify technique using a one-step verification or a precision-based verification technique using a plurality of verification steps; The fast programming verification technique is used for the memory cell based on the threshold voltage distribution Vth of the memory cell having a position in the natural threshold voltage distribution NVD corresponding to the upper tail or the lower tail of the NVD.

5. A non-volatile memory device comprising: a control circuit for verifying whether a memory cell has been programmed, wherein the memory cell is part of a memory cell array of the non-volatile memory device, and wherein the control circuit is configured to: verifying data states of a group of memory cells of a selected word line using a verify technique as part of a group of verify techniques, wherein the verification technique is utilized based on an iteration of a program-verify operation being performed; performing a next iteration of the program-verify operation using the verification technique to verify whether one or more memory cells in the group of memory cells of the selected word line have been programmed, wherein the next iteration of using the verification technique and performing the program-verify operation is repeated until the group of memory cells have been verified; wherein the verification technique is a fast program-verify technique using a one-step verification or a precision-based verification technique using a plurality of verification steps; Wherein based on a threshold voltage distribution Vth of a memory cell having a position in a natural threshold voltage distribution NVD corresponding to a middle portion of the NVD, the precision-based verification technique is applied to the memory cell.

6. A method of verifying whether one or more memory cells of a non-volatile memory have been programmed, the method comprising: verifying data states of a group of memory cells of a selected word line using one or more verification techniques as part of a group of verification techniques, wherein the one or more verification techniques are selected for use based on an iteration of a program-verify operation to be performed; performing a next iteration of the program-verify operation using the one or more verification techniques to verify whether one or more memory cells in the group of memory cells of the selected word line are programmed, wherein using the one or more verification techniques and performing the next iteration of the program-verify operation is repeated until the group of memory cells has been verified; wherein the verification technique is a fast programming verification technique using a one-step verification or a precision-based verification technique using multiple verification steps; The verification technique is the fast program-verify technique for a first iteration and a last iteration of the program-verify operation, and the precision-based verification technique for an intermediate set of iterations of the program-verify operation. 7 . The method of claim 6 , wherein the fast programming verification technique is a coarse quick pass writing (QPW) technique, and wherein the precision-based verification technique is an iQPW technique.

8. The method of claim 6, wherein utilizing the one or more authentication techniques comprises: A flag bit corresponding to a currently verified data state included in a flag register is set, wherein a field in the flag register includes a first value corresponding to a fast programming verification technique and a second value corresponding to a precision-based verification technique.

9. The method according to claim 6, further comprising: An iteration counter is incremented based on performing the next iteration of the program-verify operation such that the iteration counter identifies a number of iterations of the program-verify operation that have been performed, wherein the iteration counter corresponds to a lower tail of a natural voltage threshold distribution NVD.

10. A method of verifying whether one or more memory cells of a non-volatile memory have been programmed, the method comprising: verifying data states of a group of memory cells of a selected word line using one or more verification techniques as part of a group of verification techniques, wherein the one or more verification techniques are selected for use based on an iteration of a program-verify operation to be performed; performing a next iteration of the program-verify operation using the one or more verification techniques to verify whether one or more memory cells in the group of memory cells of the selected word line are programmed, wherein using the one or more verification techniques and performing the next iteration of the program-verify operation is repeated until the group of memory cells has been verified; wherein the verification technique is a fast programming verification technique using a one-step verification or a precision-based verification technique using multiple verification steps; Wherein based on a threshold voltage distribution Vth of a memory cell having a position in a natural threshold voltage distribution NVD corresponding to a middle portion of the NVD, the precision-based verification technique is applied to the memory cell.

11. A device comprising: A control circuit for verifying whether a memory cell has been programmed, wherein the memory cell is part of a memory cell array of a non-volatile memory, and wherein the control circuit is configured to: using one or more verification techniques as part of a program-verify operation to be performed on one or more memory cells that are part of a group of memory cells of a selected word line, wherein the one or more verification techniques are utilized based on an iteration of the program-verify operation to be performed; as well as performing a next iteration of the program-verify operation using the one or more verification techniques to verify whether the one or more memory cells are programmed, wherein the next iteration of using the one or more verification techniques and performing the program-verify operation is repeated until the group of memory cells has been verified; Wherein when using the one or more verification techniques, the control circuit is configured to: For a memory cell in the one or more memory cells, the one or more verification techniques are used based on whether the position of the memory cell is within a first position range associated with an upper tail of a natural threshold voltage distribution NVD, within a second position range associated with a middle portion of the NVD, or within a third position range associated with a lower tail of the NVD. 12 . The apparatus of claim 11 , wherein the one or more verification techniques include a rapid programming verification technique and a precision-based verification technique.

13. The apparatus of claim 11, wherein the first position range and the third position range are associated with a coarse quick pass write (QPW) technique, and the second position range is associated with an iQPW technique.

14. The apparatus of claim 11 , wherein when using the one or more authentication techniques, the control circuit is configured to: A flag bit corresponding to a currently verified data state included in a flag register is set, wherein a field in the flag register includes a first value corresponding to a fast programming verification technique and a second value corresponding to a precision-based verification technique.

15. The device of claim 11, wherein the control circuit is further configured to: An iteration counter is incremented based on performing the next iteration of the program-verify operation such that the iteration counter identifies a number of iterations of the program-verify operation that have been performed, wherein the iteration counter corresponds to a lower tail of a natural voltage threshold distribution NVD.

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