Detection method and structure for physical short-circuit defect between first metal layer and its lower gate layer

Abstract

The present invention relates to a method for detecting a defect of a physical short circuit between a first metal layer and a lower gate layer thereof, and to a defect detection technology. A first detection structure and a second detection structure are arranged in parallel in a detection area or a cutting path area of ​​a wafer, each detection structure comprises a P-type active area, a detection gate structure and a contact hole located on the P-type active area, gate contact holes located at both ends of the detection gate structure, metal wires connecting the contact holes located on the P-type active area, and metal wires connecting the gate contact holes. The detection gate structure of the first detection structure at least partially overlaps with the metal wires located thereon, and the detection gate structure of the second detection structure has no overlapping area with the metal wires located thereon. The defect of a short circuit between a first metal layer and a lower gate layer on a wafer due to physical contact can be detected and locked, and the time for defect discovery is shortened. The first detection structure and the second detection structure are formed synchronously in the formation process of a semiconductor device, and the process is simple and the cost is low.

Description

Technical Field

[0001] The present invention relates to semiconductor integrated circuit manufacturing technology, and in particular to a defect detection technology. Background Art

[0002] In the semiconductor chip manufacturing process, defect detection is an indispensable and critical step in the semiconductor chip manufacturing process. By discovering defects through defect detection and shortening the time from defect occurrence to discovery, the yield of semiconductor chips can be improved and production costs can be reduced. In addition, with the downward trend of technology nodes, the molding requirements of devices are becoming more and more stringent, and defect detection is becoming increasingly important.

[0003] In the process of manufacturing semiconductor chips, defects may occur in each process. In the prior art, defect detection is usually performed after each process step. However, single-step detection cannot reflect the defect problems caused by the mutual influence between each process step. For example, for the short-circuit defect between the first metal layer and the lower gate layer, the prior art mainly relies on the single-layer thickness measurement for monitoring. This method has great limitations and cannot fully reflect the defect problems caused by the mutual influence between the layers. For example, the grinding process fluctuation causes the interlayer dielectric layer to be too thin and the first metal layer is over-etched to a deep depth. Although the single-layer process is outliers, it does not exceed the specification and is generally laid out normally. However, the actual result of the combination of the two is likely to cause the first metal layer and the lower gate layer to be physically contacted and short-circuited, that is, a physical short-circuit defect occurs. Moreover, this type of upper and lower layer defects are also difficult to be discovered by direct defect comparison scanning methods. Generally, the problem can only be discovered in the final yield test. There is also the problem of difficulty in troubleshooting the cause, resulting in a large yield loss and increasing the time for defect discovery.

[0004] Semiconductor integrated circuits are usually formed on wafers. With the development of technology, the size of wafers, i.e. the diameter, has grown from 4 inches, 6 inches, 8 inches to 12 inches. The edge of the wafer is an area where defects are more likely to occur. As the size of the wafer increases, defects are more likely to occur at the edge of the wafer. For example, the thickness of the interlayer dielectric layer of the chip at the edge of the wafer is greatly affected by process fluctuations such as grinding. Therefore, defect detection at the edge of the wafer is particularly important. Summary of the invention

[0005] The present invention provides a method for detecting a physical short-circuit defect between a first metal layer and a lower gate layer thereof, comprising: S1: providing a wafer, wherein the wafer comprises a plurality of exposure units, wherein each exposure unit comprises a plurality of chip units, wherein the plurality of chip units are separated by a cutting path, and a first P-type active region and a second P-type active region are formed in a detection region or a cutting path region of the wafer, and the first P-type active region and the second P-type active region are arranged in parallel; S2: forming a first detection gate structure on the first P-type active region, and forming a second detection gate structure on the second P-type active region, wherein both ends of the first detection gate structure extend outside the first P-type active region, and the portion of the first detection gate structure extending outside the first P-type active region constitutes a first detection gate structure; The connecting area of ​​the second detection gate structure is extended to the outside of the second P-type active area; the two ends of the second detection gate structure extend to the outside of the second P-type active area, and the part of the second detection gate structure extending to the outside of the second P-type active area constitutes the connecting area of ​​the second detection gate structure; S3: forming an interlayer dielectric layer and performing a planarization process; S4: forming contact holes in the interlayer dielectric layer, the contact holes include a first contact hole located on the first P-type active area, a second contact hole located on the second P-type active area, a first gate contact hole located in the connecting area of ​​the first detection gate structure, and a second gate contact hole located in the connecting area of ​​the second detection gate structure, and the spacing between the first contact hole and the first detection gate structure adjacent thereto is equal to the spacing between the second contact hole and the The spacing between the second detection gate structure adjacent to it; S5: forming a first layer of metal on the interlayer dielectric layer, the first layer of metal including a first metal wire connected to the first contact hole, a second metal wire connected to the second contact hole, a third metal wire connected to the first gate contact hole and a fourth metal wire connected to the second gate contact hole, and performing a flattening process, wherein the first metal wire at least partially overlaps with the first detection gate structure below it, and the second metal wire has no overlapping area with the second detection gate structure below it, so that the first P-type active area, the first detection gate structure, the first contact hole, the first gate contact hole, the first metal wire and the third metal wire form a first detection structure, so that the second P-type active area, the second detection gate structure , a second contact hole, a second gate contact hole, a second metal line and a fourth metal line form a second detection structure, and the first detection structure and the second detection structure are arranged in parallel to form a detection structure; and S6: using a scanning electron microscope to perform defect detection, adjusting the voltage contrast of the scanning electron microscope, adjusting the imaging corresponding to the first metal line and the second metal line to bright contrast, and imaging the detection structure to obtain a voltage contrast imaging diagram of the first detection structure and the first layer of metal in the second detection structure. If only the metal line in the first detection structure connected to the contact hole located on the connection area of ​​the gate structure appears to be bright contrast, it is determined that a physical short circuit defect occurs between the first layer of metal in the first detection structure and its underlying gate.

[0006] Furthermore, in step S1, in the process of forming the first P-type active area and the second P-type active area, a first active area for forming a semiconductor device is formed in the chip unit; in step S2, in the process of forming the first detection gate structure and the second detection gate structure, a gate structure of the semiconductor device is formed on the first active area; in step S4, the contact holes in the interlayer dielectric layer also include contact holes formed on the first active area; in step S5, the first layer of metal also includes metal wires connecting the contact holes located on the first active area to form a semiconductor device located in the chip unit.

[0007] Furthermore, the first detection gate structure and the second detection gate structure include a superimposed structure of a gate dielectric layer and a metal gate.

[0008] Furthermore, the first detection gate structure includes a plurality of gates arranged in parallel; and the second detection gate structure includes a plurality of gates arranged in parallel.

[0009] Furthermore, the first P-type active region and the second P-type active region are formed in the n-well.

[0010] Furthermore, the detection structure is arranged at a corner of the exposure unit.

[0011] Furthermore, the detection structure is arranged in an exposure unit at the edge of the wafer.

[0012] Furthermore, the detection structure is disposed in both the exposure unit located at the edge of the wafer and the exposure unit near the center of the wafer.

[0013] Furthermore, the number of exposure units provided with the detection structure at the edge of the wafer is greater than the number of exposure units provided with the detection structure near the center of the wafer.

[0014] The present invention also provides a detection structure for a physical short-circuit defect between a first layer of metal and a lower layer of gate, comprising: a first P-type active region and a second P-type active region, which are located in an n-well in a detection area or a cutting path area of ​​a wafer, and the first P-type active region and the second P-type active region are arranged in parallel; a first detection gate structure and a first contact hole, which are located on the first P-type active region, and the two ends of the first detection gate structure extend outside the first P-type active region, and the portion of the first detection gate structure extending outside the first P-type active region constitutes a connection region of the first detection gate structure; a second detection gate structure and a second contact hole, which are located on the second P-type active region, and the two ends of the second detection gate structure extend outside the second P-type active region, and the portion of the second detection gate structure extending outside the second P-type active region constitutes a connection region of the second detection gate structure; the first gate contact hole and the second gate contact hole The first gate contact hole is located in the connection area of ​​the first detection gate structure, and the second gate contact hole is located in the connection area of ​​the second detection gate structure; the interlayer dielectric layer fills the first detection gate structure, the second detection gate structure, the first contact hole, the second contact hole, and the area between the first gate contact hole and the second gate contact hole; the first metal wire, the second metal wire, the third metal wire and the fourth metal wire are formed on the interlayer dielectric layer, the first metal wire connects the first contact hole, the second metal wire connects the second contact hole, the third metal wire connects the first gate contact hole, and the fourth metal wire connects the second gate contact hole, and the first metal wire at least partially overlaps with the first detection gate structure, the second metal wire has no overlapping area with the second detection gate structure, and the spacing between the first contact hole and the first detection gate structure adjacent to it is equal to the spacing between the second contact hole and the second detection gate structure adjacent to it.

[0015] Furthermore, the first detection gate structure and the second detection gate structure include a superimposed structure of a gate dielectric layer and a metal gate.

[0016] Furthermore, the detection structure is arranged at a corner position of the exposure unit in the wafer.

[0017] Furthermore, the detection structure is arranged in an exposure unit at the edge of the wafer.

[0018] Furthermore, the detection structure is disposed in both the exposure unit located at the edge of the wafer and the exposure unit near the center of the wafer.

[0019] Furthermore, the number of exposure units provided with detection structures at the edge of the wafer is greater than the number of exposure units provided with detection structures near the center of the wafer.

[0020] According to an embodiment of the present invention, a method and structure for detecting a physical short-circuit defect between a first layer of metal and a lower layer of gate therebetween are provided. A first detection structure and a second detection structure are arranged in parallel in a detection area or a cutting path area of ​​a wafer. Each detection structure includes a P-type active area, a detection gate structure and a contact hole located on the P-type active area, gate contact holes located at both ends of the detection gate structure, metal wires connecting the contact holes located on the P-type active area, and metal wires connecting the gate contact holes. The detection gate structure of the first detection structure at least partially overlaps with the metal wires located thereon, and the detection gate structure of the second detection structure has no overlapping area with the metal wires located thereon. The defect of a short circuit between a first layer of metal on a wafer and a lower layer of gate thereon due to physical contact can be detected and locked, thereby shortening the time for defect discovery. The first detection structure and the second detection structure are formed simultaneously during the formation process of the semiconductor device, with a simple process and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 FIG. 4 is a schematic diagram of a wafer according to an embodiment of the present invention.

[0022] Figure 2 for Figure 1 An enlarged schematic diagram of an exposure unit in FIG.

[0023] Figure 3 The figure is a schematic structural diagram of a semiconductor device on a wafer according to an embodiment.

[0024] Figure 4 Schematic diagram of the structure of a detection structure on a wafer according to an embodiment.

[0025] Figure 5 FIG. 4 is a schematic plan view of a detection structure on a wafer according to an embodiment of the present invention.

[0026] Figure 6 FIG. 1 is a schematic diagram of a physical short defect between a first metal layer and a lower gate layer according to an embodiment of the present invention.

[0027] The main components in the figure are described as follows:

[0028] 100, wafer; 110, first P-type active region; 120, second P-type active region; 112, first contact hole; 114, first metal line; 111, first detection gate structure; 122, second contact hole; 124, second metal line; 121, second detection gate structure; 130, interlayer dielectric layer; 105, detection structure. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0030] In one embodiment of the present invention, a method for detecting a physical short-circuit defect between a first layer of metal and a lower layer of gate therein is provided, comprising: S1: providing a wafer, wherein the wafer comprises a plurality of exposure units, wherein each exposure unit comprises a plurality of chip units, wherein the plurality of chip units are separated by cutting paths, and a first P-type active region and a second P-type active region are formed in a detection region or a cutting path region of the wafer, and the first P-type active region and the second P-type active region are arranged in parallel; S2: forming a first detection gate structure on the first P-type active region, and forming a second detection gate structure on the second P-type active region, wherein both ends of the first detection gate structure extend outside the first P-type active region, and the first detection gate structure extends outside the first P-type active region. The first detection gate structure is formed by forming a connection area of ​​the first detection gate structure; both ends of the second detection gate structure extend outside the second P-type active area, and the part of the second detection gate structure extending outside the second P-type active area constitutes the connection area of ​​the second detection gate structure; S3: forming an interlayer dielectric layer and performing a planarization process; S4: forming contact holes in the interlayer dielectric layer, the contact holes include a first contact hole located on the first P-type active area, a second contact hole located on the second P-type active area, a first gate contact hole located in the connection area of ​​the first detection gate structure, and a second gate contact hole located in the connection area of ​​the second detection gate structure, and the spacing between the first contact hole and the first detection gate structure adjacent thereto is equal to the spacing between the first contact hole and the second detection gate structure adjacent thereto. S5: forming a first metal layer on the interlayer dielectric layer, the first metal layer comprising a first metal wire connected to the first contact hole, a second metal wire connected to the second contact hole, a third metal wire connected to the first gate contact hole, and a fourth metal wire connected to the second gate contact hole, and performing a planarization process, wherein the first metal wire at least partially overlaps with the first detection gate structure under it, and the second metal wire has no overlapping area with the second detection gate structure under it, so that the first P-type active area, the first detection gate structure, the first contact hole, the first gate contact hole, the first metal wire and the third metal wire form a first detection structure, so that the second P-type active area, the second detection gate structure, the first contact hole, the first gate contact hole, the first metal wire and the third metal wire form a first detection structure, and the second P-type active area, the second detection gate structure, the first contact hole, the first gate contact hole, the first metal wire and the third metal wire form a first detection structure. The first detection structure and the second detection structure are arranged in parallel to form a detection structure; and S6: using a scanning electron microscope to perform defect detection, adjusting the voltage contrast of the scanning electron microscope, adjusting the imaging corresponding to the first metal line and the second metal line to bright contrast, and imaging the detection structure to obtain a voltage contrast imaging diagram of the first layer of metal in the first detection structure and the second detection structure. If only the metal line in the first detection structure connected to the contact hole located on the connection area of ​​the gate structure appears to be bright contrast, it is determined that a physical short circuit defect occurs between the first layer of metal in the first detection structure and its underlying gate.

[0031] For details, please refer to Figures 1 to 5 , Figure 1is a schematic diagram of a wafer according to an embodiment, Figure 2 for Figure 1 An enlarged schematic diagram of an exposure unit in FIG. Figure 3 is a schematic structural diagram of a semiconductor device on a wafer according to an embodiment, Figure 4 is a schematic structural diagram of a detection structure on a wafer according to an embodiment, Figure 5 is a schematic plan view of a detection structure on a wafer according to an embodiment, Figure 4 For along Figure 5 A cross-sectional view at the dotted line AA in FIG. A method for detecting a physical short-circuit defect between a first metal layer and a lower gate layer, comprising:

[0032] Step S1: Provide a wafer 100, wherein the wafer 100 includes a plurality of exposure units 101, each of which includes a plurality of chip units (die) 103, and the plurality of chip units (die) 103 are separated by cutting lines 104, such as Figure 4 As shown, a first P-type active region 110 and a second P-type active region 120 are formed in the inspection region or the dicing road region 104 of the wafer 100, and the first P-type active region 110 and the second P-type active region 120 are arranged in parallel;

[0033] In one embodiment, the wafer 100 is a wafer of a silicon substrate. Figure 1 As shown, the wafer 100 includes a plurality of exposure units 101, such as Figure 2 As shown, each exposure unit 101 includes a plurality of chip units (die) 103, the chip unit 103 is a formation area of ​​a semiconductor device, the boundary area of ​​the chip unit (die) 103 and the edges around the exposure unit 101 are cutting road areas 104, and the cutting road areas 104 can also be called scribe grooves.

[0034] In one embodiment, the first P-type active region 110 and the second P-type active region 120 are formed in an n-well.

[0035] Step S2: Figure 4 As shown, a first detection gate structure 111 is formed on the first P-type active region 110, and a second detection gate structure 121 is formed on the second P-type active region 120. Figure 5 As shown, both ends of the first detection gate structure 111 extend outside the first P-type active region 110, and the portion of the first detection gate structure 111 extending outside the first P-type active region 110 constitutes a connection region 1111 of the first detection gate structure 111; both ends of the second detection gate structure 121 extend outside the second P-type active region 120, and the portion of the second detection gate structure 121 extending outside the second P-type active region 120 constitutes a connection region 1211 of the second detection gate structure 121;

[0036] In one embodiment, the first detection gate structure 111 and the second detection gate structure 121 include a stacked structure of a gate dielectric layer and a metal gate.

[0037] In one embodiment, the connection region 1111 of the first detection gate structure 111 and the connection region 1211 of the second detection gate structure 121 are located in the silicon oxide region.

[0038] like Figure 4 As shown, in one embodiment, the first detection gate structure 111 includes a plurality of gates arranged in parallel; and the second detection gate structure 121 includes a plurality of gates arranged in parallel.

[0039] Step S3: forming an interlayer dielectric layer 130 and performing a planarization process;

[0040] Step S4: forming contact holes in the interlayer dielectric layer 130, the contact holes including a first contact hole 112 located on the first P-type active region 110, a second contact hole 122 located on the second P-type active region 120, a first gate contact hole 113 located in the connection region 1111 of the first detection gate structure 111, and a second gate contact hole 123 located in the connection region 1211 of the second detection gate structure 121, and a spacing between the first contact hole 112 and the first detection gate structure 111 adjacent thereto is equal to a spacing between the second contact hole 122 and the second detection gate structure 121 adjacent thereto;

[0041] Of course, the above “equal to” may have a certain deviation. In one embodiment, the deviation is 20%; preferably, the deviation is 10%; more preferably, the deviation is 5%.

[0042] Step S5: forming a first metal layer on the interlayer dielectric layer 130, the first metal layer including a first metal line 114 connected to the first contact hole 112, a second metal line 124 connected to the second contact hole 122, a third metal line 134 connected to the first gate contact hole 113, and a fourth metal line 144 connected to the second gate contact hole 123, and performing a planarization process, wherein the first metal line 114 at least partially overlaps with the first detection gate structure 111 below it, and the second metal line 124 has no overlapping area with the second detection gate structure 121 below it. domain, so that the first P-type active region 110, the first detection gate structure 111, the first contact hole 112, the first gate contact hole 113, the first metal line 114 and the third metal line 134 form a first detection structure 210, and the second P-type active region 120, the second detection gate structure 121, the second contact hole 122, the second gate contact hole 123, the second metal line 124 and the fourth metal line 144 form a second detection structure 220, and the first detection structure 210 and the second detection structure 220 are arranged in parallel to form a detection structure 105;

[0043] Step S6: Use a scanning electron microscope (SEM) to perform defect detection, adjust the voltage contrast of the scanning electron microscope, adjust the imaging corresponding to the first metal line 114 and the second metal line 124 to bright contrast, and image the detection structure to obtain the voltage contrast imaging diagram of the first layer of metal in the first detection structure and the second detection structure. If only the metal line in the first detection structure 210 connected to the contact hole located on the connection area of ​​the gate structure (that is, the third metal line 134 connected to the first gate contact hole 113 located in the connection area 1111 of the first detection gate structure 111) appears in a relatively bright contrast, it is determined that a physical short circuit defect occurs between the first layer of metal in the first detection structure and its underlying gate.

[0044] Specifically, a scanning electron microscope (SEM) is used for defect detection, and the voltage contrast of the scanning electron microscope is adjusted. The imaging of the corresponding first metal line 114 and the second metal line 124 is adjusted to bright contrast at a low voltage of 1 keV, and the detection structure is imaged at a low voltage of 1 keV to obtain a voltage contrast imaging diagram of the first layer of metal in the first detection structure and the second detection structure.

[0045] Among them, according to the working principle of the scanning electron microscope (SEM), when the electrons with a certain energy of the scanning electron microscope are emitted to the surface of the semiconductor sample (such as the detection structure including the first detection structure 210 and the second detection structure 220), secondary electrons will be scattered from the sample surface and a certain potential will be generated. The magnitude of this potential depends on the secondary electron yield A, and A is equal to the number of secondary electrons / the number of incident electrons. When A<1, the surface potential is negative; when A>1, the surface potential is positive. When the surface potential is positive, since the PN junction formed between the P-type active area and the n-well is forward-biased, the potential on the contact hole on the P-type active area is lowered, so a large number of electrons in the n-well are easily attracted to the sample surface and scattered as secondary electrons. A large number of secondary electrons are collected by the detection device, so the voltage contrast image of the first metal wire 114 and the second metal wire 124 connected to the contact hole on the P-type active area in the scanning electron microscope is bright. The contact holes on the gate structure are isolated from the semiconductor substrate by the intermediate gate dielectric layer, and only a small amount of secondary electrons are scattered from the surface of the contact holes. Therefore, the voltage contrast image of the third metal line 134 and the fourth metal line 144 connected to the contact holes located in the connection area of ​​the gate structure should be very dark under normal circumstances.

[0046] For the present invention, if the third metal line 134 has a relatively bright contrast and the fourth metal line 144 has a dark contrast, that is, only the metal line connected to the contact hole located on the connection area of ​​the gate structure in the first detection structure 210 has a relatively bright contrast, then it means that there is a physical contact and short-circuit defect (that is, a physical short-circuit defect) between the first layer of metal and the lower layer of the gate in the first detection structure, and there is no short-circuit defect between the first layer of metal and the lower layer of the gate in the second detection structure. Since there is no overlapping area between the first layer of metal and the lower layer of the gate structure in the second detection structure, there will be no short-circuit due to physical contact, and the gate structure and the contact hole located on the second P-type active area are not too close. Short circuit, because the spacing between the first contact hole 112 and the first detection gate structure 111 adjacent thereto is equal to the spacing between the second contact hole 122 and the second detection gate structure 121 adjacent thereto, the gate structure on the first P-type active area and the contact hole located on the first P-type active area will not be short circuited due to being too close, so it can be determined that the metal line connected to the contact hole located on the connection area of ​​the gate structure in the first detection structure 210 has a bright contrast due to a physical short circuit defect between the first layer of metal in the first detection structure and its lower layer of gate. That is, it can be determined that a physical short circuit defect occurs between the first layer of metal in the first detection structure and its lower layer of gate. Please refer to Figure 6 , Figure 6 FIG. 1 is a schematic diagram of a physical short circuit defect between a first metal layer and a lower gate layer according to an embodiment of the present invention. Figure 6 In the first detection structure, the thinning of the interlayer dielectric layer 130 combined with the over-etching of the first metal layer causes a physical short defect 115 between the first metal layer and its underlying gate; and for the same reason, in the second detection structure, no physical short defect occurs between the first metal layer and the underlying gate.

[0047] If both the third metal line 134 and the fourth metal line 144 show a relatively bright contrast, it can be determined that the gate structure in the second detection structure and the contact hole located on the second P-type active area are short-circuited due to being too close. Since the spacing between the first contact hole 112 and the first detection gate structure 111 adjacent thereto is equal to the spacing between the second contact hole 122 and the second detection gate structure 121 adjacent thereto, the gate structure on the first P-type active area and the contact hole located on the first P-type active area are also short-circuited due to being too close, resulting in the third metal line 134 and the fourth metal line 144 showing a relatively bright contrast.

[0048] If the third metal line 134 and the fourth metal line 144 are both dark contrast, there is no defect in the second detection structure that the gate structure and the contact hole located on the second P-type active area are short-circuited due to being too close. Similarly, there is no defect that the gate structure on the first P-type active area and the contact hole located on the first P-type active area are short-circuited due to being too close, and there is no physical short-circuit defect between the first layer of metal and the lower layer of gate in the first detection structure.

[0049] In one embodiment, in step S1, during the process of forming the first P-type active region 110 and the second P-type active region 120, as shown in FIG. Figure 3 As shown, a first active region (eg, Figure 3 In step S2, during the formation of the first detection gate structure 111 and the second detection gate structure 121, in the first active region (such as Figure 3 A gate structure of a semiconductor device (such as Figure 3 In step S4, the contact hole in the interlayer dielectric layer 130 also includes a contact hole formed in the first active region (such as Figure 3 The contact holes (such as the active regions 150 and 160) on the Figure 3 In step S5, the first metal layer also includes connecting the first active area (such as Figure 3 The contact holes (such as the active regions 150 and 160) on the Figure 3 The metal lines (such as the contact holes 152 and 162 in Figure 3 154 and 164 in the chip unit 103) to form a semiconductor device located in the chip unit 103. In one embodiment, the gate structure of the semiconductor device (such as Figure 3 The gate structures 151 and 161 in the chip unit 103 include a superimposed structure of a gate dielectric layer and a metal gate. In one embodiment, the first P-type active area 110, the first detection gate structure 111, the first contact hole 112, the first gate contact hole 113, the first metal line 114 and the third metal line 134 of the first detection structure 210, and the second P-type active area 120, the second detection gate structure 121, the second contact hole 122, the second gate contact hole 123, the second metal line 124 and the fourth metal line 144 of the second detection structure 220 are formed by adding corresponding patterns in a mask forming a corresponding structure of a semiconductor device located in the chip unit 103. Therefore, the process is simple and the cost is low.

[0050] In one embodiment, the detection structure 105 is disposed at a corner of the exposure unit 101. Figure 2In the embodiment, the detection structure 105 is located at a corner of the exposure unit 101, so that the wafer edge condition can be easily detected.

[0051] In one embodiment, the detection structure 105 is disposed in the exposure unit 101 at the edge of the wafer, so that the condition of the wafer edge can be easily detected. Figure 1 In the embodiment, the detection structure 105 is disposed in the exposure unit 101 located at the edge of the wafer. Preferably, the detection structure 105 is disposed in both the exposure unit 101 located at the edge of the wafer and the exposure unit 101 near the center of the wafer, so as to detect the conditions of the wafer edge and the center of the wafer at the same time. Since defects are prone to occur at the wafer edge, preferably, the number of exposure units 101 disposed with the detection structure 105 at the edge of the wafer is greater than the number of exposure units 101 disposed with the detection structure 105 near the center of the wafer, so as to increase the detection strength of the wafer edge. Figure 1 As shown, the number of exposure units 101 provided with detection structures 105 at the edge of the wafer is 8, and the number of exposure units 101 provided with detection structures 105 near the center of the wafer is 1. These 9 points are selected as detection points, 8 points at the edge and 1 point in the middle. Through voltage contrast adjustment, the first layer of metal wire connected to the contact hole on the P-type active area is adjusted to bright contrast under a low voltage of 1kev. At this time, the first layer of metal connected to the contact hole on the gate is normally dark contrast. By imaging the test structure under a low voltage of 1kev, 9 voltage contrast imaging images of the first layer of metal are obtained to simultaneously detect the physical short-circuit defect between the first layer of metal and the lower layer of the gate at the edge of the wafer and the center of the wafer, and increase the detection strength of the wafer edge.

[0052] As mentioned above, after the first layer of metal is formed, adding a scanning electron microscope defect detection step can identify whether a physical short circuit defect occurs between the first layer of metal and its underlying gate, thereby reducing the difficulty of defect cause troubleshooting and reducing the time for defect cause troubleshooting. In addition, whether a physical short circuit defect occurs between the first layer of metal and its underlying gate can be discovered during the semiconductor product manufacturing process, without having to wait until the final yield test to discover the problem. Therefore, the time interval from the occurrence to the discovery of the physical short circuit defect is greatly reduced.

[0053] In one embodiment of the present invention, a detection structure for a physical short-circuit defect between a first metal layer and a lower gate layer is also provided. Figures 1 to 5As shown, it includes: a first P-type active area 110 and a second P-type active area 120, which are located in the detection area of ​​the wafer or the n-well in the cutting road area 104, and the first P-type active area 110 and the second P-type active area 120 are arranged in parallel; a first detection gate structure 111 and a first contact hole 112, which are located on the first P-type active area 110, and the two ends of the first detection gate structure 111 extend outside the first P-type active area 110, and the part of the first detection gate structure 111 extending outside the first P-type active area 110 constitutes a first detection gate The second detection gate structure 121 and the second contact hole 122 are located on the second P-type active area 120, and the two ends of the second detection gate structure 121 extend outside the second P-type active area 120, and the portion of the second detection gate structure 121 extending outside the second P-type active area 120 constitutes the connection area 1211 of the second detection gate structure 121; the first gate contact hole 113 and the second gate contact hole 123, the first gate contact hole 113 is located at the connection area 1211 of the first detection gate structure 111 The second gate contact hole 123 is located in the connection area 1211 of the second detection gate structure 121; the interlayer dielectric layer 130 fills the first detection gate structure 111, the second detection gate structure 121, the first contact hole 112, the second contact hole 122, and the area between the first gate contact hole 113 and the second gate contact hole 123; the first metal line 114, the second metal line 124, the third metal line 134 and the fourth metal line 144 are formed on the interlayer dielectric layer 130, and the first metal line 114 is connected to the first contact hole 113. The first detection gate structure 111 is connected to the detection gate structure 112, the second metal wire 124 is connected to the second contact hole 122, the third metal wire 134 is connected to the first gate contact hole 113, the fourth metal wire 144 is connected to the second gate contact hole 123, and the first metal wire 114 at least partially overlaps with the first detection gate structure 111, the second metal wire 124 has no overlapping area with the second detection gate structure 121, and the spacing between the first contact hole 112 and the first detection gate structure 111 adjacent thereto is equal to the spacing between the second contact hole 122 and the second detection gate structure 121 adjacent thereto.

[0054] Of course, the above “equal to” may have a certain deviation. In one embodiment, the deviation is 20%; preferably, the deviation is 10%; more preferably, the deviation is 5%.

[0055] In one embodiment, the first detection gate structure 111 and the second detection gate structure 121 include a stacked structure of a gate dielectric layer and a metal gate.

[0056] In one embodiment, the first detection gate structure 111 includes a plurality of gates arranged in parallel; and the second detection gate structure 121 includes a plurality of gates arranged in parallel.

[0057] In one embodiment, the detection structure 105 is disposed at a corner of the exposure unit 101 in the wafer. Figure 2 In the embodiment, the detection structure 105 is located at a corner of the exposure unit 101, so that the wafer edge condition can be easily detected.

[0058] In one embodiment, the detection structure 105 is disposed in the exposure unit 101 at the edge of the wafer, so that the condition of the wafer edge can be easily detected. Figure 1 In the embodiment, the detection structure 105 is arranged in the exposure unit 101 located at the edge of the wafer. Preferably, the detection structure 105 is arranged in both the exposure unit 101 located at the edge of the wafer and the exposure unit 101 near the center of the wafer, so as to detect the conditions of the wafer edge and the center of the wafer at the same time. Since defects are prone to occur at the edge of the wafer, preferably, the number of exposure units 101 arranged with the detection structure 105 at the edge of the wafer is greater than the number of exposure units 101 arranged with the detection structure 105 near the center of the wafer, so as to increase the detection strength of the wafer edge.

[0059] The parallel arrangement is arranged in parallel along the X-axis direction of the wafer 100 , or in parallel along the Y-axis direction of the wafer 100 .

[0060] As described above, a first detection structure and a second detection structure are arranged in parallel in the detection area or cutting path area of ​​the wafer, each detection structure includes a P-type active area, a detection gate structure and a contact hole located on the P-type active area, gate contact holes located at both ends of the detection gate structure, metal wires connecting the contact holes located on the P-type active area, and metal wires connecting the gate contact holes, and the detection gate structure of the first detection structure at least partially overlaps with the metal wires located thereon, and the detection gate structure of the second detection structure has no overlapping area with the metal wires located thereon, so that defects caused by short circuits between the first layer of metal on the wafer and the lower layer of the gate due to physical contact can be detected and locked, thereby shortening the time for defect discovery, and the first detection structure and the second detection structure are formed simultaneously during the formation process of the semiconductor device, with a simple process and low cost.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting a physical short-circuit defect between a first metal layer and a lower gate layer, characterized in that: include: S1: providing a wafer, wherein the wafer includes a plurality of exposure units, each exposure unit includes a plurality of chip units, the plurality of chip units are separated by cutting paths, a first P-type active region and a second P-type active region are formed in a detection region or a cutting path region of the wafer, and the first P-type active region and the second P-type active region are arranged in parallel; S2: forming a first detection gate structure on the first P-type active region, and forming a second detection gate structure on the second P-type active region, wherein both ends of the first detection gate structure extend outside the first P-type active region, and a portion of the first detection gate structure extending outside the first P-type active region constitutes a connection region of the first detection gate structure; Both ends of the second detection gate structure extend outside the second P-type active region, and the portion of the second detection gate structure extending outside the second P-type active region constitutes a connection region of the second detection gate structure; S3: forming an interlayer dielectric layer and performing a planarization process; S4: forming contact holes in the interlayer dielectric layer, the contact holes including a first contact hole located on the first P-type active region, a second contact hole located on the second P-type active region, a first gate contact hole located in the connection region of the first detection gate structure, and a second gate contact hole located in the connection region of the second detection gate structure, and a spacing between the first contact hole and the first detection gate structure adjacent thereto is equal to a spacing between the second contact hole and the second detection gate structure adjacent thereto; S5: forming a first metal layer on the interlayer dielectric layer, the first metal layer comprising a first metal wire connected to the first contact hole, a second metal wire connected to the second contact hole, a third metal wire connected to the first gate contact hole, and a fourth metal wire connected to the second gate contact hole, and performing a planarization process, wherein the first metal wire at least partially overlaps with the first detection gate structure under it, and the second metal wire has no overlapping area with the second detection gate structure under it, so that the first P-type active area, the first detection gate structure, the first contact hole, the first gate contact hole, the first metal wire and the third metal wire form a first detection structure, and the second P-type active area, the second detection gate structure, the second contact hole, the second gate contact hole, the second metal wire and the fourth metal wire form a second detection structure, and the first detection structure and the second detection structure are arranged in parallel to form a detection structure; as well as S6: Use a scanning electron microscope to perform defect detection, adjust the voltage contrast of the scanning electron microscope, adjust the imaging corresponding to the first metal line and the second metal line to bright contrast, and image the detection structure to obtain a voltage contrast imaging diagram of the first layer of metal in the first detection structure and the second detection structure. If only the metal line in the first detection structure connected to the contact hole located on the connection area of ​​the gate structure shows a relatively bright contrast, it is determined that a physical short circuit defect occurs between the first layer of metal in the first detection structure and the underlying gate.

2. The method for detecting the physical short-circuit defect between the first metal layer and the lower gate layer according to claim 1, characterized in that: In step S1, in the process of forming the first P-type active area and the second P-type active area, a first active area for forming a semiconductor device is formed in the chip unit; in step S2, in the process of forming the first detection gate structure and the second detection gate structure, a gate structure of the semiconductor device is formed on the first active area; in step S4, the contact holes in the interlayer dielectric layer also include contact holes formed on the first active area; in step S5, the first layer of metal also includes metal wires connecting the contact holes located on the first active area to form a semiconductor device located in the chip unit.

3. The method for detecting the physical short-circuit defect between the first metal layer and the lower gate layer according to claim 1, characterized in that: The first detection gate structure and the second detection gate structure include a stacked structure of a gate dielectric layer and a metal gate.

4. The method for detecting the physical short-circuit defect between the first metal layer and the lower gate layer according to claim 1, characterized in that: The first detection gate structure includes a plurality of gates arranged in parallel; the second detection gate structure includes a plurality of gates arranged in parallel.

5. The method for detecting the physical short-circuit defect between the first metal layer and the underlying gate layer according to claim 1, characterized in that: A first P-type active region and a second P-type active region are formed in the n-well.

6. The method for detecting the physical short-circuit defect between the first metal layer and the underlying gate layer according to claim 1, characterized in that: The detection structure is arranged at a corner position of the exposure unit.

7. The method for detecting the physical short-circuit defect between the first metal layer and the underlying gate layer according to claim 1, characterized in that: The detection structure is arranged in an exposure unit at the edge of the wafer.

8. The method for detecting the physical short-circuit defect between the first metal layer and the underlying gate layer according to claim 7, characterized in that: The detection structure is arranged in both the exposure unit located at the edge of the wafer and the exposure unit close to the center of the wafer.

9. The method for detecting the physical short-circuit defect between the first metal layer and the underlying gate layer according to claim 8, characterized in that: The number of exposure units provided with the detection structure at the edge of the wafer is greater than the number of exposure units provided with the detection structure near the center of the wafer.

10. A detection structure for physical short-circuit defects between a first metal layer and a lower gate layer, characterized in that: include: The first P-type active region and the second P-type active region are located in an n-well in a detection area or a cutting road area of ​​the wafer, and the first P-type active region and the second P-type active region are arranged in parallel; The first detection gate structure and the first contact hole are located on the first P-type active region, both ends of the first detection gate structure extend outside the first P-type active region, and the portion of the first detection gate structure extending outside the first P-type active region constitutes a connection region of the first detection gate structure; The second detection gate structure and the second contact hole are located on the second P-type active region, both ends of the second detection gate structure extend outside the second P-type active region, and the portion of the second detection gate structure extending outside the second P-type active region constitutes a connection region of the second detection gate structure; a first gate contact hole and a second gate contact hole, the first gate contact hole being located in a connection region of the first detection gate structure, and the second gate contact hole being located in a connection region of the second detection gate structure; The interlayer dielectric layer fills the first detection gate structure, the second detection gate structure, the first contact hole, the second contact hole, and the area between the first gate contact hole and the second gate contact hole; A first metal line, a second metal line, a third metal line and a fourth metal line are formed on an interlayer dielectric layer, the first metal line is connected to a first contact hole, the second metal line is connected to a second contact hole, the third metal line is connected to a first gate contact hole, the fourth metal line is connected to a second gate contact hole, the first metal line at least partially overlaps with a first detection gate structure, the second metal line has no overlapping area with a second detection gate structure, and the spacing between a first contact hole and an adjacent first detection gate structure is equal to the spacing between a second contact hole and an adjacent second detection gate structure.

11. The detection structure for physical short-circuit defects between the first metal layer and the lower gate layer according to claim 10, characterized in that: The first detection gate structure and the second detection gate structure include a stacked structure of a gate dielectric layer and a metal gate.

12. The detection structure for physical short-circuit defects between the first metal layer and the lower gate layer according to claim 10, characterized in that: The detection structure is arranged at a corner position of an exposure unit in a wafer.

13. The detection structure for physical short-circuit defects between the first metal layer and the lower gate layer according to claim 10, characterized in that: The detection structure is arranged in an exposure unit at the edge of the wafer.

14. The detection structure for physical short-circuit defects between the first metal layer and the lower gate layer according to claim 13, characterized in that: The detection structure is arranged in both the exposure unit located at the edge of the wafer and the exposure unit close to the center of the wafer.

15. The detection structure for physical short-circuit defects between the first metal layer and the lower gate layer according to claim 14, characterized in that: The number of exposure units provided with detection structures at the edge of the wafer is greater than the number of exposure units provided with detection structures near the center of the wafer.

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