Balanced three-value multiplexer circuit based on memristor

Abstract

The invention discloses a balanced three-value multiplexer circuit based on a memristor. The circuit comprises a balanced three-value decoder, three balanced three-value two-input minimum gates and a balanced three-value three-input maximum gate. The balanced three-value decoder inputs a balanced three-value signal and outputs three binary signals, which are respectively input into three balanced three-value two-input minimum gates, each of which is implemented by two memristors, and the other input end respectively inputs one input signal. The balanced three-value three-input maximum gate is implemented by three memristors, and the three input ends are respectively connected to the output ends of the balanced three-value two-input minimum gate, and the output end of the balanced three-value three-input maximum gate is the output end of the balanced three-value multiplexer. The structure of the invention is clear and simple, and it is easy to implement. The circuit model is of great significance to the application research in many fields such as multi-value digital logic circuit design.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, and relates to a three-value digital logic circuit structure, and in particular to the design and implementation of a physically realizable memristor-based balanced three-value multiplexer circuit. Background Art

[0002] In recent years, the semiconductor industry has been increasingly unable to meet the demand for further reduction in device size in integrated circuits, making Moore's Law seem to have stagnated. Therefore, it is necessary to study new materials and devices that are compatible with traditional CMOS. The memristor was proposed by Professor Shaotang Cai in 1971, and the physical device was first developed by HP Labs in 2008. It has now become one of the measures to cope with the continuous shrinking of modern electronic circuits. As the fourth type of basic passive circuit element, the memristor has been widely studied in the fields of digital logic circuits, nonlinear circuits, neuromorphic networks, etc. due to its advantages such as nanometer size, non-volatility, and compatibility with CMOS technology.

[0003] In the research of memristor digital logic circuits, many implementation methods have emerged, such as memristor essential implied logic (IMPLY), memristor / CMOS hybrid logic, memristor-assisted logic (MAGIC), CMOS / memristor threshold logic, CMOS-like memristor complementary logic, parallel input processing memristor logic, etc. It is worth noting that the above studies are all based on binary representation methods, while three-valued logic, as a multi-valued logic, has more logical possibilities and can meet various different logic requirements. In addition, three-valued digital logic circuits also have the advantages of lower circuit complexity and higher information density. Therefore, they have attracted the attention of relevant researchers in recent years.

[0004] There are two ways to represent three-valued logic: unbalanced three-valued and balanced three-valued. Unbalanced three-valued includes positive three-valued {0,1,2} and negative three-valued {0,-1,-2}. Due to the relativity of logical symbols, the two are similar in technical solutions. Balanced three-valued is represented by {-1,0,1}. Due to the symmetry of its symbols, the integer range represented by a k-bit balanced ternary number is also symmetrical, that is, balanced three-valued logic can represent the entire integer range without a sign bit. In addition, balanced three-valued operations also have significant advantages. They are similar to binary logic and simpler than unbalanced three-valued logic. For example, multiplication operations have no carry and can achieve the unification of addition and subtraction operations. Therefore, introducing memristors into the design of digital logic circuits and studying memristor balanced three-valued digital logic circuits is expected to further improve the information storage density of circuit systems and promote the further development of modern information circuits. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention proposes a balanced three-value multiplexer circuit based on a memristor.

[0006] The technical solution adopted by the present invention to solve the technical problem is as follows:

[0007] The invention comprises a balanced three-value decoder, three balanced three-value two-input minimum gates and one balanced three-value three-input maximum gate, and requires fourteen memristors and five NMOS transistors in total.

[0008] The balanced three-value decoder U1 is implemented by five memristors and five NMOS tubes. Its function is to input a balanced three-value selection signal S and output three binary signals S. -1 , S0, S1, the specific input and output logic relationship is as follows: if the input is logic "-1", S -1 The output is a positive level, that is, logic "1", and the other two outputs are negative levels, that is, logic "-1"; if the input is logic "0", the S0 output is a positive level, that is, logic "1", and the other two outputs are negative levels, that is, logic "-1"; if the input is logic "1", the S1 output is a positive level, that is, logic "1", and the other two outputs are negative levels, that is, logic "-1".

[0009] Each balanced three-value two-input minimum gate is implemented by two memristors, and its function is to find the logical minimum value of the two input terminals.

[0010] The balanced three-value three-input maximum value gate is implemented by three memristors, and its function is to find the logical maximum value of the three input terminals.

[0011] The input end of the balanced three-value decoder U1 is used as the selection signal input end of the balanced three-value multiplexer. -1 One of the input terminals of the first balanced three-value two-input minimum gate U2 is connected, and the other input terminal of the first balanced three-value two-input minimum gate U2 is connected to the first input signal I -1 . The second output terminal S0 of the balanced three-value decoder U1 is connected to one of the input terminals of the second balanced three-value two-input minimum gate U3, and the other input terminal of the second balanced three-value two-input minimum gate U3 is connected to the second input signal I0. The third output terminal S1 of the balanced three-value decoder U1 is connected to one of the input terminals of the third balanced three-value two-input minimum gate U4, and the other input terminal of the third balanced three-value two-input minimum gate U4 is connected to the third input signal I1. The output terminals of the first balanced three-value two-input minimum gate U2, the second balanced three-value two-input minimum gate U3, and the third balanced three-value two-input minimum gate U4 are respectively connected to the three input terminals of the balanced three-value three-input maximum gate U5, and the output terminal OUT of the balanced three-value three-input maximum gate U5 is the output terminal of the balanced three-value multiplexer.

[0012] Depending on the logic state of the selection signal S, the output state of the memristor-based balanced three-value multiplexer is equal to the different input signal states:

[0013] The input end of the balanced three-value decoder U1 is logic "-1", and the output end of the balanced three-value multiplexer circuit is the first input signal I -1 ;

[0014] The input end of the balanced three-value decoder U1 is logic "0", and the output end of the balanced three-value multiplexer circuit is the second input signal I0;

[0015] The input end of the balanced three-value decoder U1 is logic "1", and the output end of the balanced three-value multiplexer circuit is the third input signal I1.

[0016] The beneficial effects of the present invention are: a balanced three-value multiplexer circuit model based on memristor is designed, which has a clear and simple structure and is easy to implement. The circuit model has important application research in many fields such as multi-value digital logic circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a circuit block diagram of a balanced three-value multiplexer based on a memristor according to the present invention;

[0018] Figure 2 It is a circuit schematic diagram of a balanced three-value multiplexer based on a memristor of the present invention. DETAILED DESCRIPTION

[0019] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0020] The circuit block diagram of the balanced three-value multiplexer based on memristor designed by the present invention is as follows: Figure 1 As shown, it is composed of a balanced three-value decoder U1, a first balanced three-value two-input minimum gate U2, a second balanced three-value two-input minimum gate U3, a third balanced three-value two-input minimum gate U4, and a balanced three-value three-input maximum gate U5.

[0021] The logic state in the balanced three-value multiplexer circuit is a voltage value, where the voltage V is defined DD is 1V, corresponding to logic "1"; GND is 0V, corresponding to logic "0"; -V DD It is -1V, corresponding to logic "-1".

[0022] The balanced three-value decoder U1 includes three parts: a first output circuit, a second output circuit, and a third output circuit, which are implemented by five memristors and five NMOS tubes. Its function is to input a balanced three-value signal and output three binary signals. The specific input and output logic relationship is shown in the following table:

[0023]

[0024] Among them, S is the selection signal, S -1 , S0, and S1 are the three output signals of the balanced three-value decoder U1. For the first output circuit part, the threshold voltage of the first NMOS tube T1 is 0.8V. When the input terminal S is connected to -V DD When the input is logic "-1", the first NMOS tube T1 is turned off, and the first output terminal S -1 The pull-up resistor formed by the first memristor M1 is connected to V DD , that is, the output is logic "1"; when the input terminal S is grounded or connected to V DD When the input is logic "0" or logic "1", the first NMOS tube T1 is turned on, and the first output terminal S -1 Connected to -V through the first NMOS tube T1 DD , the output is logic “-1”.

[0025] For the second output circuit part, the threshold voltages of the second NMOS transistor T2 and the third NMOS transistor T3 are both 1.5V. DD When the input is logic "-1", the second NMOS tube T2 is turned off and the third NMOS tube T3 is turned on. According to the resistance change law of the memristor, the current flows into the negative electrode of the third memristor M3 and flows out of the positive electrode, and the resistance will increase to R OFF , the current flows into the positive electrode and out of the negative electrode of the second memristor M2, and the resistance value will decrease to R ON , due to R OFF >>R ON , the voltage at the second output terminal S0 is calculated by the voltage division of the two memristors:

[0026]

[0027] That is, the output is logic "-1".

[0028] When the input terminal S is grounded, that is, the input is logic "0", the second NMOS transistor T2 and the third NMOS transistor T3 are both turned off, and the second output terminal S0 is connected to V through the pull-up resistor formed by the third memristor M3. DD , that is, the output is logic "1". When the input terminal S is connected to V DD When the input is logic "1", the second NMOS tube T2 and the third NMOS tube T3 are both turned on, and the second output terminal S0 is connected to -V through the second NMOS tube T2 and the third NMOS tube T3. DD , the output is logic “-1”.

[0029] For the third output circuit part, the threshold voltages of the fourth NMOS transistor T4 and the fifth NMOS transistor T5 are 1.5V and 0.8V respectively. DD When the input is logic "-1" or "0", the fourth NMOS tube T4 is turned off, the fifth NMOS tube T5 is turned on, and the third output terminal S1 is connected to -V through the fifth NMOS tube T5. DD , the output is logic "-1". When the input terminal S is connected to V DD When the input is logic "1", the fourth NMOS transistor T4 is turned on, the fifth NMOS transistor T5 is turned off, and the third output terminal S1 is connected to V through the pull-up resistor formed by the fifth memristor M5. DD , that is, the output is logic "1".

[0030] Then, if the input S is logic "-1", S -1 The output is a positive level, that is, logic "1", and the other two outputs are negative levels, that is, logic "-1"; if the input S is logic "0", the S0 output is a positive level, that is, logic "1", and the other two outputs are negative levels, that is, logic "-1"; if the input S is logic "1", the S1 output is a positive level, that is, logic "1", and the other two outputs are negative levels, that is, logic "-1".

[0031] Each balanced three-value two-input minimum gate is implemented by two memristors, and its function is to find the logical minimum value of the two input terminals.

[0032] The balanced three-value three-input maximum value gate is implemented by three memristors, and its function is to find the logical maximum value of the three input terminals.

[0033] The input-output relationship table of the memristor-based balanced three-value multiplexer circuit of the present invention is shown in the following table:

[0034]

[0035] Among them, S is the selection signal, I -1 , I0, and I1 are three input signals. According to the state of the selection signal S, the output end is equal to different input end states.

[0036] When the selection signal S is logic "-1", Figure 1 The output terminal S of the balanced three-value decoder U1 -1 = is logic "1", and the outputs of S0 and S1 are logic "-1". At this time, the state of the output of the first balanced three-value two-input minimum gate U2 is equal to I -1 The outputs of the second balanced three-value two-input minimum gate U3 and the third balanced three-value two-input minimum gate U4 are both logic "-1", so the three inputs of the balanced three-value three-input maximum gate U5 are I -1The logical state is logic "-1", logic "-1", so the output is I -1 The logical value of .

[0037] When the selection signal S is logic "0", Figure 1 The output terminal S0 of the balanced three-value decoder U1 is logic "1", S -1 The output of S1 is logic "-1". At this time, the state of the output of the second balanced three-value two-input minimum gate U3 is equal to the state of the input of I0, and the outputs of the first balanced three-value two-input minimum gate U2 and the third balanced three-value two-input minimum gate U4 are both logic "-1". Therefore, the three inputs of the balanced three-value three-input maximum gate U5 are logic "-1", the logic state of I0, and logic "-1", so the output is the logic value of I0.

[0038] When the selection signal S is logic "1", Figure 1 The output terminal S1 of the balanced three-value decoder U1 is logic "1", S -1 The output of S0 is logic "-1". At this time, the state of the output of the third balanced three-value two-input minimum gate U4 is equal to the state of the input of I1, and the outputs of the first balanced three-value two-input minimum gate U2 and the second balanced three-value two-input minimum gate U3 are both logic "-1". Therefore, the three inputs of the balanced three-value three-input maximum gate U5 are logic "-1", logic "-1", and logic states of I1, so the output is the logic value of I1.

[0039] The detailed circuit schematic diagram corresponding to the above circuit block diagram is as follows Figure 2 shown.

[0040] Among them, the balanced three-value decoder U1 is composed of the first memristor M1, the second memristor M2, the third memristor M3, the fourth memristor M4, the fifth memristor M5, the first NMOS tube T1, the second NMOS tube T2, the third NMOS tube T3, the fourth NMOS tube T4, and the fifth NMOS tube T5. The first output circuit is composed of the first memristor M1 and the first NMOS tube T1; the second output circuit is composed of the second memristor M2, the third memristor M3, the second NMOS tube T2, and the third NMOS tube T3; the third output circuit is composed of the fourth memristor M4, the fifth memristor M5, the fourth NMOS tube T4, and the fifth NMOS tube T5. The negative electrode of the first memristor M1 is connected to the power supply V DD The positive electrode of the first memristor M1 is connected to the drain of the first NMOS tube T1 and serves as the S of the balanced three-value decoder U1. -1Output terminal. The gate of the first NMOS tube T1, the gate of the second NMOS tube T2, the cathode of the second memristor M2 and the gate of the fourth NMOS tube T4 are connected and serve as the input terminal S of the memristor-based balanced three-value multiplexer of the present invention. The source of the first NMOS tube T1 is connected to the power supply -V DD The positive electrode of the second memristor M2, the drain of the second NMOS tube T2 and the source of the third NMOS tube T3 are connected, and the source of the second NMOS tube T2 is connected to the power supply -V DD The positive electrode of the third memristor M3 is connected to the drain of the third NMOS tube T3 and serves as the S0 output terminal of the balanced three-value decoder U1. The negative electrode of the third memristor M3 is connected to the power supply V DD The gate of the third NMOS tube T3 is connected to the power supply V DD The drain of the fourth NMOS tube T4, the positive electrode of the fourth memristor M4 and the gate of the fifth NMOS tube T5 are connected, and the source of the fourth NMOS tube T4 is connected to the power supply -V DD The negative electrode of the fourth memristor M4 is connected to the power supply V DD The positive electrode of the fifth memristor M5 is connected to the drain of the fifth NMOS tube T5 and serves as the S1 output terminal of the balanced three-value decoder U1. The negative electrode of the fifth memristor M5 is connected to the power supply V DD The source of the fifth NMOS tube T5 is connected to the power supply -V DD connected.

[0041] The sixth memristor M6 and the seventh memristor M7 form a first balanced three-value two-input minimum gate U2, the eighth memristor M8 and the ninth memristor M9 form a second balanced three-value two-input minimum gate U3, and the tenth memristor M 10 and the eleventh memristor M 11 The third balanced three-value two-input minimum gate U4 is formed, and the twelfth memristor M 12 、The thirteenth memristor M 13 and the fourteenth memristor M 14 The negative electrode of the sixth memristor M6 is connected to the S of the balanced three-value decoder U1. -1 The output end is connected to the positive electrode of the sixth memristor M6, the positive electrode of the seventh memristor M7 and the twelfth memristor M 12 The positive electrode of the seventh memristor M7 is connected to the positive electrode of the I -1 The cathode of the eighth memristor M8 is connected to the S0 output terminal of the balanced three-value decoder U1, and the anode of the eighth memristor M8, the anode of the ninth memristor M9 and the anode of the thirteenth memristor M 13 The positive electrode of the ninth memristor M9 is connected to the positive electrode of the ninth memristor M9, and the negative electrode of the ninth memristor M9 serves as the input terminal of I0. 10 The negative electrode is connected to the S1 output terminal of the balanced three-value decoder U1, and the tenth memristor M10 The positive electrode of the eleventh memristor M 11 The positive electrode and the fourteenth memristor M 14 The positive electrode of the eleventh memristor M 11 The negative electrode of is used as the input terminal of I1. 12 The negative electrode of the thirteenth memristor M 13 The negative electrode and the fourteenth memristor M 14 is connected to the negative electrode of and serves as the output terminal OUT of the memristor-based balanced three-value multiplexer circuit.

[0042] Those skilled in the art should realize that the above embodiments are only used to verify the present invention, and are not intended to limit the present invention. As long as they are within the scope of the present invention, any changes or modifications to the above embodiments will fall within the protection scope of the present invention.

Claims

1. A balanced three-value multiplexer circuit based on a memristor, characterized in that: It includes a balanced three-value decoder U1, a first balanced three-value two-input minimum gate U2, a second balanced three-value two-input minimum gate U3, a third balanced three-value two-input minimum gate U4 and a balanced three-value three-input maximum gate U5; The input end of the balanced three-value decoder U1 serves as the selection signal input end of the balanced three-value multiplexer; The first output terminal of the balanced three-value decoder U1 S -1 One of the input terminals of the first balanced three-value two-input minimum gate U2 is connected, and the other input terminal of the first balanced three-value two-input minimum gate U2 is connected to the first input signal I -1 ; The second output terminal of the balanced three-value decoder U1 S 0 is connected to one of the input terminals of the second balanced three-value two-input minimum gate U3, and the other input terminal of the second balanced three-value two-input minimum gate U3 is connected to the second input signal I0; The third output terminal of the balanced three-value decoder U1 S 1 is connected to one of the input terminals of the third balanced three-value two-input minimum gate U4, and the other input terminal of the third balanced three-value two-input minimum gate U4 is connected to the third input signal I1; The output ends of the first balanced three-value two-input minimum gate U2, the second balanced three-value two-input minimum gate U3, and the third balanced three-value two-input minimum gate U4 are respectively connected to the three input ends of the balanced three-value three-input maximum gate U5, and the output end of the balanced three-value three-input maximum gate U5 is the output end of the balanced three-value multiplexer circuit; The balanced three-value decoder U1 is implemented by five memristors and five NMOS tubes, and outputs a balanced three-value signal of one input as three binary signals; the first balanced three-value two-input minimum gate U2, the second balanced three-value two-input minimum gate U3, and the third balanced three-value two-input minimum gate U4 are each composed of two memristors, and are used to find the logical minimum value of the two input terminals; The balanced three-value three-input maximum value gate U5 is implemented by three memristors and is used to find the logical maximum value of the three input terminals; The input and output signals of the balanced three-value multiplexer circuit follow the following relationship: The input end of the balanced three-value decoder U1 is logic -1, and the output end of the balanced three-value multiplexer circuit is the first input signal I -1 ; The input end of the balanced three-value decoder U1 is logic 0, and the output end of the balanced three-value multiplexer circuit is the second input signal I0; The input end of the balanced three-value decoder U1 is logic 1, and the output end of the balanced three-value multiplexer circuit is the third input signal I1; The balanced three-value decoder U1 is composed of the first memristor M 1. Second memristor M 2. The third memristor M 3. The fourth memristor M 4. The Fifth Memristor M 5. The first NMOS tube T 1. Second NMOS tube T 2. The third NMOS tube T 3. The fourth NMOS tube T 4. Fifth NMOS tube T 5 constitutes; the first memristor M 1's negative terminal is connected to the power supply V DD Connected, the first memristor M 1's positive electrode and the first NMOS tube T 1 and serves as the balanced three-value decoder U1. S -1 Output terminal; first NMOS tube T 1's gate, the second NMOS tube T 2's gate, the second memristor M 2 and the negative electrode of the fourth NMOS tube T 4 is connected to the gate of the transistor 4 and serves as the input terminal S of the balanced three-value multiplexer based on the memristor; the first NMOS transistor T 1 source and power supply -V DD Connected to; second memristor M 2's positive electrode, the second NMOS tube T 2 and the drain of the third NMOS tube T 3 is connected to the source of the second NMOS tube T 2 source and power supply -V DD Connected; third memristor M The positive electrode of 3 and the third NMOS tube T 3 and serves as the balanced three-value decoder U1. S 0 output, third memristor M The negative terminal of 3 is connected to the power supply V DD Connected, the third NMOS tube T 3 gate and power supply V DD Connected; the fourth NMOS tube T Drain of 4, fourth memristor M 4 and the positive electrode of the fifth NMOS tube T 5, the gate of the fourth NMOS tube T 4 source and power supply -V DD Connected, the fourth memristor M The negative terminal of 4 is connected to the power supply V DD Connected; Fifth Memristor M The positive electrode of 5 and the fifth NMOS tube T 5 and serves as the balanced three-value decoder U1. S 1 output, fifth memristor M 5 negative pole and power supply V DD Connected, the fifth NMOS tube T 5 source and power supply -V DD connected.

2. The memristor-based balanced three-value multiplexer circuit according to claim 1, characterized in that: The input and output logic relationship of the balanced three-value decoder U1 follows the following relationship: The input of the balanced three-value decoder U1 is logic -1, and the first output S -1 Output is logic 1, the second output S 0. The third output terminal S 1 is logic -1; The input of the balanced three-value decoder U1 is logic 0, and the second output S 0 output is logic 1, the first output S -1 , the third output terminal S 1 is logic -1; The input of the balanced three-value decoder U1 is logic 1, and the third output S 1 output is logic 1, the first output S -1 , the second output terminal S 0 is logical -1.

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