Method and apparatus for wireless communication

Abstract

A method for wireless communication, comprising: receiving a synchronization signal block from a base station, the synchronization signal block comprising coded bits corresponding to a physical broadcast channel payload; decoding the coded bits according to polarization decoding processing to generate polarized decoded bits; decoding the polarized decoded bits according to cyclic redundancy check decoding processing to generate physical broadcast channel payload bits; obtaining a portion of timing-related bits from the physical broadcast channel payload bits according to bit mapping, the timing-related bits being used to indicate the timing of the synchronization signal block in a synchronization signal burst from the base station; and processing the synchronization signal block according to the portion of timing-related bits. By utilizing the present invention, a portion of timing-related bits can be obtained more efficiently, thereby reducing decoding complexity and power consumption.

Description

[0001] This invention is a divisional application of an invention patent with an application date of October 8, 2018, application number “201880004826.1”, and invention name “Input bit allocation method and device”.

[0002] Cross-references

[0003] This application claims priority to U.S. Provisional Application No. 62 / 566,977, filed on October 2, 2017, entitled “NR PBCH Coding Design”; U.S. Provisional Application No. 62 / 583,564, filed on November 9, 2017, entitled “NR PBCH Design for Partial Content Extraction”; U.S. Provisional Application No. 62 / 592,209, filed on November 29, 2017, entitled “PBCH Bit Mapping Design” and U.S. Provisional Application No. 62 / 592,389, filed on November 29, 2017, entitled “PBCH Bit Mapping Design Before First PBCH Scrambling”, the entire contents of the above applications are incorporated herein by reference. Technical Field

[0004] The present invention relates to wireless communications, and more particularly to physical broadcast channel (PBCH) data processing in wireless communication networks. Background Art

[0005] This background section is provided to generally present the context of the present invention. The work of the inventors named herein, the extent of the work described in this background section, and aspects of this description, did not constitute prior art at the time of filing, and are neither explicitly nor implicitly admitted to be prior art to the present invention.

[0006] The fifth generation (5G) wireless communication network uses beamforming technology to concentrate transmission in a specific direction and extend coverage. For example, in a wireless communication system, a beam sweep can be performed to cover the service area. The system information and frame timing information carried on the PBCH can be repeatedly broadcast in different directions during the beam sweep process. In 5G New Radio (NR) measurements, the user equipment (UE) may need to decode the PBCH to extract the frame timing information. However, when there are multiple cells that need to be measured at the same time, the decoding complexity overhead may be too high for the UE. Summary of the invention

[0007] A method for wireless communication, comprising: receiving a synchronization signal block from a base station, the synchronization signal block comprising coded bits corresponding to a physical broadcast channel payload; decoding the coded bits according to a polarization decoding process to generate polarized decoded bits; decoding the polarized decoded bits according to a cyclic redundancy check decoding process to generate physical broadcast channel payload bits; obtaining a portion of timing-related bits from the physical broadcast channel payload bits according to a bit mapping, the timing-related bits being used to indicate the timing of the synchronization signal block in a synchronization signal burst from the base station; and processing the synchronization signal block according to the portion of timing-related bits.

[0008] A method for wireless communication, comprising: receiving a synchronization signal block from a base station, the synchronization signal block comprising coded bits corresponding to a physical broadcast channel payload; decoding the coded bits according to a polarization decoding process to generate polarization decoded bits; obtaining a portion of timing-related bits from the polarization decoded bits according to a bit allocation of the polarization decoding process before decoding the polarization decoded bits according to a cyclic redundancy check decoding process, the timing-related bits being used to indicate the timing of the synchronization signal block in a synchronization signal burst from the base station; and processing the synchronization signal block according to the portion of timing-related bits.

[0009] A device for wireless communication, comprising a processing circuit, wherein the processing circuit is configured to: receive a synchronization signal block from a base station, the synchronization signal block comprising encoded bits corresponding to a physical broadcast channel payload; decode the encoded bits according to a polarization decoding process to generate polarized decoded bits; decode the polarized decoded bits according to a cyclic redundancy check decoding process to generate physical broadcast channel payload bits; obtain a portion of timing-related bits from the physical broadcast channel payload bits according to a bit mapping, the timing-related bits being used to indicate the timing of the synchronization signal block in a synchronization signal burst from the base station; and process the synchronization signal block according to the portion of timing-related bits.

[0010] A device for wireless communication, comprising a processing circuit, wherein the processing circuit is configured to: receive a synchronization signal block from a base station, the synchronization signal block comprising coded bits corresponding to a physical broadcast channel payload; decode the coded bits according to a polarization decoding process to generate polarization decoded bits; before decoding the polarization decoded bits according to a cyclic redundancy check decoding process, obtain a portion of timing-related bits from the polarization decoded bits according to a bit allocation of the polarization decoding process, the timing-related bits being used to indicate the timing of the synchronization signal block in a synchronization signal burst from the base station; and process the synchronization signal block according to the portion of timing-related bits.

[0011] By utilizing the present invention, bits related to some timing sequences can be acquired more efficiently, thereby reducing decoding complexity and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various exemplary embodiments provided by the present invention will be described in detail below with reference to the accompanying drawings, in which like numbers refer to like elements, wherein:

[0013] Figure 1 An exemplary wireless communication system according to an embodiment of the present invention is shown.

[0014] Figure 2 An exemplary synchronization signal block (SSB) transmission configuration according to an embodiment of the present invention is shown.

[0015] Figure 3 An exemplary SSB according to an example of the present invention is shown.

[0016] Figure 4 An exemplary PBCH payload according to an exemplary embodiment of the present invention is shown.

[0017] Figure 5 A polar graph illustrating exemplary polar bit allocation according to an embodiment of the present invention is shown.

[0018] Figure 6 A polarization diagram illustrating another exemplary polarization bit allocation according to an embodiment of the present invention is shown.

[0019] Figure 7 An exemplary system for allocating bits associated with selected timing according to an embodiment of the present invention is shown.

[0020] Fig. 8A FIG. 4 shows a PBCH interleaver pattern according to an embodiment of the present invention.

[0021] Figure 8B An exemplary table for mapping PBCH payload to input bits of an encoder according to an embodiment of the present invention is shown.

[0022] Fig. 9 A flow chart of an exemplary polarization bit allocation process according to an embodiment of the present invention is shown.

[0023] Fig.10 An exemplary apparatus according to an embodiment of the invention is shown. DETAILED DESCRIPTION

[0024] Figure 1 An exemplary wireless communication system 100 according to an embodiment of the present invention is shown. The system 100 includes a UE 110 and a base station (BS) 120. The system 100 may adopt the 5G wireless communication technology developed by the 3rd Generation Partnership Project (3GPP) or other wireless technologies developed by other organizations. The system 100 may include Figure 1 Other BSs and UEs are shown in FIG.

[0025] In some examples, 5G NR millimeter wave (mmW) frequency band and beamforming technology can be used in system 100. Accordingly, UE 110 and BS 120 can perform beamforming transmission or reception. In beamforming transmission, the energy of the wireless signal can be focused in a specific direction to cover the target service area. Therefore, compared with omnidirectional antenna transmission, a higher antenna transmission gain can be achieved. Similarly, in beamforming reception, the wireless signal energy received from a specific direction can be combined to obtain a higher antenna reception gain than omnidirectional antenna reception. The improved antenna transmission or reception gain can compensate for the path loss or penetration loss in mmW signal transmission.

[0026] BS 120 may be a BS implementing a gNB node, wherein the gNB node is defined in the 5G NR air interface standard developed by 3GPP. BS 120 may be configured to control one or more antenna arrays to form a directional transmit or receive beam for transmitting or receiving wireless signals.

[0027] exist Figure 1 In an embodiment of the present invention, BS 120 can control the antenna array to form transmission beams 1301-1364 to cover cell 128. Beams 1301-1364 can be generated in different directions. In different examples, beams 1301-1364 can be generated simultaneously, or at different time intervals. In one example, BS 120 is configured to perform beam scanning 127 to transmit downlink (DL) layer 1 (Layer 1, L1) / layer 2 (Layer 2, L2) control channel and / or data channel signals. During beam scanning 127, beams 1301-1364 can be continuously formed in a time division multiplexing (Time Division Multiplex, TDM) manner to cover cell 128. In the time interval for transmitting each beam in beams 1301-1364, each transmission beam can be used to transmit a set of L1 / L2 control channel data and / or data channel data. Beam scanning 127 can be repeatedly performed according to a specific period.

[0028] In another example, in addition to performing beam scanning, beams 1301-1364 may be generated in other ways. For example, multiple beams in different directions may be generated simultaneously. In other examples, a beam may be repeatedly generated in one direction. Each beam may have a different beam width than beams 1301-1364. The maximum number of beams generated by a BS may be different, such as 4, 8, 64, etc., corresponding to different configurations and BS performance.

[0029] In one example, beams 1301-1364 of cell 128 may be associated with SSB 129 (also referred to as SS / PBCH blocks). Each SSB 129 may correspond to a group of resource elements (RE) carried on several consecutive OFDM symbols in a system based on orthogonal frequency division multiplexing (OFDM). Each SSB 129 may include a PBCH 141, which carries information bits of system information and frame timing information. In some examples, this group of information bits may be referred to as a master information block (MIB). Each SSB 129 may be associated with an SSB index (SS Block Index, SBI). The SBI indicates the timing of each SSB, so the SBI is also called the SSB timing index. Figure 1 As shown, SSB 129 is associated with indexes from #0 to #63.

[0030] For example, BS 120 may periodically transmit a series of SSBs 129 (referred to as an SS burst 130). Figure 1 In the embodiment shown, the SS burst 130 may be transmitted by performing beam scanning 127. Each SSB 129 of the SS burst 130 may be transmitted using one of the beams 1301-1364. Each SBI indicates the timing or position of each SSB within the SS burst 130. In addition, the MIB of the PBCH transmitted within the SS burst 130 may remain unchanged, for example, at least for a certain number of consecutive SSBs. In another embodiment, the BS 120 may not employ multiple beams. For example, the BS 120 may not transmit using beamforming transmissions to cover the cell 128. In this configuration, the SSBs 129 are transmitted continuously in the time domain, but each transmission is performed toward each direction within the cell 128.

[0031] UE 110 may be a mobile phone, a laptop computer, a vehicle-mounted mobile communication device, a utility meter fixed at a specific location, etc. Similarly, UE 110 may use one or more antenna arrays to generate directional transmission or reception beams for transmitting or receiving wireless signals.

[0032] Figure 2 An exemplary SSB transmission configuration 200 according to an embodiment of the present invention is shown. A series of 8 frames 203 are shown in a broadcast channel (BCH) transmission time interval (TTI) 201. The BCH TTI may have a duration of 80ms. A series of SS bursts 210 may be transmitted in frames 203 at a period 202 of 20ms. In various examples, the transmission period of the SS bursts may be 5, 10, 20, 40, 80, and 160ms, etc. Each SS burst 210 is contained in a half-frame time window (5ms). Depending on the configuration, the half-frame time window may be the first half-frame or the second half-frame.

[0033] Each SS burst 210 may contain a series of SSBs 220, where each SSB 220 is associated with one SBI. Depending on the subcarrier spacing (numerology) configuration, the number and position (timing) of SSBs within the SS burst 210 may be different. For example, the maximum number L of candidate SSB positions may be 4, 8, or 64 in different configurations. Accordingly, the SBI may be represented by 2, 3, or 6 bits. Figure 2 An example is shown in which the SS burst configuration corresponds to 64 SSBs. The 64 SSBs are transmitted at 64 candidate positions and have SBIs #0-#63. In addition, whether the SS burst is located in the first half frame or the second half frame can be indicated by a Half-Radio Frame (HRF) indication bit (C0), wherein the HRF indication bit is located in each SSB 220 of the SS burst 210. Therefore, the HRF indication bit and the SBI bit of the SSB can represent the timing information of the SSB.

[0034] Figure 3 300 according to an embodiment of the present invention. The SSB 300 may include a primary synchronization signal (PSS) 301, a secondary synchronization signal (SSS) 302, and a PBCH 303 (represented by the shaded areas marked with numbers 301, 302, and 303, respectively). Figure 3As shown, the above signals can be carried in REs on the time-frequency resource grid. In addition, SSB 300 can carry a demodulation reference signal (DMRS) (not shown) in a subset of REs in the shaded area 303. In one example, the REs carrying DMRS are not used to carry PBCH signals.

[0035] In one embodiment, SSB 300 may be distributed over 4 OFDM symbols in the time domain and occupy 20 resource blocks (RBs) in the frequency domain. Figure 3 As shown, 4 OFDM symbols are numbered from 0 to 3, and the 20 RB bandwidth contains 240 subcarriers, wherein the 240 subcarriers are numbered from 0 to 239. In particular, PSS 301 may occupy symbol 0 and REs at subcarriers 56-182, SSS 302 may occupy symbol 2 and REs at subcarriers 56-182, and PBCH 303 may be located in symbols 1-3 and occupy 20 RBs at symbols 1 and 3 and 8 RBs (96 subcarriers) at symbol 2.

[0036] In one embodiment, SSB 300 is configured to transmit the data by using DMRS (not in Figure 3 ) and PBCH 303 to carry the bits of the SBI. For example, for an SBI having a maximum of 6 bits, the 3 least significant bits (Least Significant Bit, LSB) of the SBI may be carried by the DMRS, and the 3 most significant bits (Most Significant Bit, MSB) of the SBI may be carried by the PBCH 303. In one embodiment, a physical (Physical, PHY) layer cell identification (Identification, ID) may be determined by decoding the PSS 301 and the SSS 302, and the cell ID indicates the cell to which the SSB 300 is associated.

[0037] Figure 4An exemplary PBCH payload 420 according to an exemplary embodiment of the present invention is shown. The PBCH payload 420 may include system information 421 and timing information 422. The timing information 422 may include a 10-bit system frame number (SFN) 423, an HRF indication bit (C0) 424 (also known as a half-frame indication bit), and 3 MSBs (b5, b4, b3) 425 of the SBI. In addition, a first portion 426 of the PBCH payload 420 may be received from a transport layer, and a second portion 427 of the PBCH payload 420 may be generated at a PHY layer. The first portion 426 may include system information 421 and 6 MSBs (S4-S9) of the SFN, while the second portion 427 may include 4 LSBs (S0-S3) of the SFN, an HRF indication bit (C0), and 3 MSBs (b3-b5) of the SBI. In addition, the transport layer and the PHY layer may be protocol stack layers of the system 100 defined in the 3GPP 5G standard.

[0038] For each transmission of SSB, the PBCH payload may be formulated at the PHY layer. The bits of the first portion 426 received from the transport layer do not change within a BCH TTI. For each SS burst contained within a half-frame, the SFN bits S0-S3 and the HRF indication bit (C0) do not change.

[0039] SBI indicates the timing information of each SSB. The MSB (b5, b4, b3) of SBI can be located in PBCH, and the LSB of SBI can be located in DMRS (not in Figure 4). In one example, LSB detection of SBI can be performed using sequence matching (where 8 matching permutations may be required for 3 LSBs), so the decoding process is not necessary for LSB detection. In contrast to LSB detection, MSB detection of SBI can be performed using a full PBCH decoding method, which may be roughly at a similar level to Physical Downlink Control Channel (PDCCH) monitoring in terms of decoding complexity and power consumption. However, in 5G NR measurements, NR UEs may not have to decode the full PBCH. In other words, 5G NR measurements may only require a portion of timing-related information (such as the MSB (b5, b4, b3) of SBI and the HRF indication bit (C0)) instead of the full PBCH. Therefore, by efficiently acquiring the timing-related bits corresponding to the MSB (b5, b4, b3) of SBI and the HRF indication bit (C0), the decoding complexity of the NR PBCH design can be minimized.

[0040] In one embodiment, based on the assumption that the UE will decode these bits earlier, a portion of the timing-related bits of the PBCH payload (i.e., b5, b4, b3, C0) can be allocated at the front position of the encoder input. That is, in the UE's decoder, the above 4 bits (b5, b4, b3, C0) can be decoded earlier than other bits. Once the UE obtains the above 4 bits (b5, b4, b3, C0), the decoding process can be terminated without further decoding other bits, thereby achieving power saving. Such a process can be called an early termination process.

[0041] Figure 5 A polarization diagram 500 is shown for an exemplary polarization bit allocation according to an embodiment of the present invention. As shown, a sequence 510 of input bits U1-U8 is arranged on the left side of the polarization diagram 500, and a sequence 520 of coded bits X1-X8 is arranged on the right side of the polarization diagram 500. The polarization diagram 500 includes 8 bit channels 501-508, wherein each bit channel is between a pair of input and coded bits. Each pair of input and coded bits and each bit channel share the same index from 1 to 8. In addition, as shown, the bit channels 501-508 can be selectively coupled to each other through an exclusive OR (XOR) operation 530.

[0042] In one embodiment, the bit channels 501-508 are arranged in the polarization diagram 500 in an order of increasing reliability, wherein the reliability of the bit channels in the front is lower than the reliability of the bit channels in the back. For example, the reliability of bit channel 502 may be higher than the reliability of bit channel 501, the reliability of bit channel 503 may be higher than the reliability of bit channel 502, and so on. However, please note that the increasing order of reliability is not strict and may not always be in a continuous increasing order. In one example, the reliability of bit channel 502 may be lower than the reliability of bit channel 501, or the reliability of bit channel 505 may be lower than the reliability of bit channel 504. However, as Figure 5 As shown, generally speaking, the bit channels with lower reliability (ie, 501-504) are arranged at the front of the polarization diagram 500, while the bit channels with higher reliability (ie, 505-508) are arranged at the back of the polarization diagram 500.

[0043] In one embodiment, a portion of the timing-related bits (i.e., b5, b4, b3, C0) of the PBCH payload may be allocated to the available bit channels at the front of the polarization diagram. By allocating the above four timing-related bits to the bit channels at the front of the polarization diagram, decoding complexity and power consumption may be reduced. This is because the decoder is able to decode the above four timing-related bits first. Once the decoder decodes the above four timing-related bits (i.e., the MSB (b5, b4, b3) of the SBI and the HRF indication bit (C0)), the decoding process may end as appropriate without decoding the entire transmission. In other words, when decoding is performed sequentially, bits at the front positions in the bit sequence received by the UE may be decoded earlier than bits at the rear positions in the bit sequence. Accordingly, when the above four timing-related bits (i.e., b5, b4, b3, C0) are allocated at the front positions of the input bit sequence of the encoder during the encoding process, the decoder may then decode the above four timing-related bits earlier than other bits. Therefore, the decoder may end the decoding process after obtaining the above four timing-related bits to reduce power consumption.

[0044] It may be noted that some previous positions of the encoder input may not be available. Figure 5In the example of , U1 and U3 are shown as frozen bits and are therefore not available for allocating timing-related bits. In this case, the timing-related bits can be allocated at the positions with the smallest available indexes (U2, U4, U5, and U6). Therefore, the allocation process in this embodiment can include four steps: (1) identifying and skipping frozen bits and unavailable positions in the encoder's input bit sequence; (2) selecting a portion of timing-related bits from the PBCH payload; (3) selecting some available positions with the smallest available indexes in the encoder's input bit sequence for the selected timing-related bits; and (4) allocating the selected timing-related bits to the encoder's selected input bit positions. In addition, although Figure 5 Only 8 bit channels are shown, but it will be appreciated that any number of channels may be used, such as 512 bit channels with corresponding input and encoded bits.

[0045] In another embodiment including 512 bit channels in the polar diagram, the input bits with the highest reliability in the encoder's input bit sequence can be selected for the PBCH payload containing system information and timing information. The four timing-related bits of the PBCH payload (i.e., b5, b4, b3, C0) can be allocated to the front of the selected input bits. Therefore, the allocation process in this embodiment can include four steps: (1) identifying and skipping frozen bits and unavailable positions in the encoder's input bit sequence; (2) selecting a portion of timing-related bits from the PBCH payload; (3) selecting some available positions with the highest reliability in the encoder's input bit sequence for the PBCH payload; and (4) allocating the selected timing-related bits to the front of the selected input bit positions of the encoder. In this case, reliability and early termination can be met in the decoding process.

[0046] Figure 6 FIG. 2 shows a polarization diagram illustrating exemplary polarization bit allocation according to another embodiment of the present invention. Figure 5 Similarly, a sequence 610 of input bits U1-U8 is arranged on the left side of polar diagram 600, while a sequence 620 of coded bits X1-X8 is arranged on the right side of polar diagram 600. Polar diagram 600 includes 8 bit channels 601-608, each of which is between a pair of input and coded bits. Each pair of input and coded bits and each bit channel share the same index from 0 to 7. In addition, as shown, bit channels 601-608 can be selectively coupled to another channel via an XOR operation 630. Although the diagram only includes 8 bit channels, it should be understood that any number of channels can be used, such as 512 bit channels with corresponding input and coded bits.

[0047] In one embodiment, bit channels 601-608 are arranged in order of increasing reliability in polar diagram 600, with channels of lower reliability in the first half and channels of higher reliability in the second half. For example, the reliability of bit channel 602 may be higher than the reliability of bit channel 601, the reliability of bit channel 603 may be higher than the reliability of bit channel 602, and so on. However, please note that the increasing order of reliability is not strict and may not always be in a continuous increasing order. In one example, the reliability of bit channel 602 may be lower than the reliability of bit channel 601, or the reliability of bit channel 605 may be lower than the reliability of bit channel 604. However, as Figure 6 As shown, generally speaking, the bit channels with lower reliability (ie, 601-604) are arranged in the front half of the polarization diagram 600, while the bit channels with higher reliability (ie, 605-608) are arranged in the back half of the polarization diagram 600.

[0048] It may be noted that some of the sequence of input bits U1-U8 may not be available for allocating timing-dependent bits. Figure 6 In the example of , U1 and U3 are shown as frozen bits and are therefore not available for allocating timing-related bits. In this case, timing-related bits can be allocated at available locations, such as U2 and U4-U8.

[0049] In practice, the encoder reserves some available input bit positions for the four timing-related bits (i.e., b5, b4, b3, C0), and then assigns the four timing-related bits (i.e., b5, b4, b3, C0) to the predetermined input bit positions. Accordingly, the decoder can decode the received four timing-related bits using a sequence matching process similar to the process used when detecting the LSB of the SBI in the DMRS. Because the predetermined positions for the four timing-related bits are known to the decoder, the decoding algorithm can be simplified, thereby saving power and time in decoding.

[0050] In one embodiment, the encoder may predetermine the available input bits based on the reliability of the corresponding channels. For example, the encoder may select the available input bits with the highest reliability in the front part (such as the first half) of the encoder. Since the bit channels 601-608 are generally arranged in the order of increasing reliability in the polar diagram 600, in the first half 601-604, the bit channel 604 has the highest reliability. Accordingly, in Figure 6In the example of , input bit U4 associated with channel 604 can be reserved as one of the input bits for timing-related bits. Once U4 is reserved, the next available input bit with the highest reliability in the first half U1-U4 is U2, because U3 is a frozen bit. Note that the order of channel reliabilities is known to the decoder. That is, the encoder and decoder can use the same reliability order. In addition, although Figure 6 Only 8 bit channels are shown, but it will be appreciated that any number of channels may be used, such as 512 bit channels with corresponding input and encoded bits.

[0051] In another example where 512 bit channels are included in the polar diagram, 4 timing-dependent bits (i.e., b5, b4, b3, C0) of the PBCH payload are assigned to predetermined input bit positions 255, 254, 253, and 247, where the predetermined input bit positions are associated with the 4 most reliable bit channels in the first half (256 bit channels) of the 512 bit channels in the polar diagram. Note that the first half (256 bits) of the coded bits (512 bits) of the encoder are the result of an XOR operation between the first half input bits and the second half input bits. Accordingly, when the UE receives the coded PBCH bits, the UE can again perform an XOR operation between the first half coded bits and the second half coded bits. Therefore, the first half coded bits without the XOR effect can be extracted by the UE. The extracted first half coded bits can be equivalent to the first half input bits of the encoder. In addition, the predetermined positions of the 4 timing-dependent bits in the first half input bits of the encoder are known to the UE. Therefore, the UE can select 4 timing-related bits from the extracted first half of the coded bits according to the predetermined positions, and then a simplified matching algorithm can be performed to detect the above 4 timing-related bits. For example, the UE decoder can perform a sequence matching algorithm to determine a match, wherein the sequence matching algorithm can compare the above 4 timing-related bits with 16 matching arrangements. Therefore, the decoding complexity and power consumption can be reduced, or under such conditions, the decoder is even unnecessary. Therefore, the allocation process in this embodiment can include 4 steps: (1) identifying and skipping frozen bits and unavailable positions in the encoder's input bit sequence; (2) selecting a portion of timing-related bits from the PBCH payload; (3) selecting some available input bits with the highest reliability in the first half of the encoder's input bits as predetermined positions for the selected portion of timing-related bits; and (4) allocating each selected timing-related bit to the encoder's predetermined input bit position.

[0052] Figure 7An exemplary system 700 for allocating selected timing-related bits according to an embodiment of the present invention is shown. As shown in the figure, the system 700 may include a PBCH payload generation module 710, a bit scrambling module 720, a cyclic redundancy check (CRC) encoding module 730, an interleaver module 740, and an encoder 750. As shown in the figure, the interleaver module 740 also includes a polarization bit allocator 735.

[0053] In practice, the PBCH payload generation module 710 may receive an input bit 701 sequence from a higher layer (such as a transport layer). The PBCH payload generation module 710 may generate a PBCH payload 711 based on the input bit 701. In particular, the input bit 701 sequence may be To indicate that is the number of system information bits, for example, for 24 system information bits, It can be 24. Additional timing-related bits can be generated by the PBCH payload generation module 710. The above timing-related bits may be included with the input bit sequence to form a PBCH payload 711. Accordingly, the PBCH payload 711 may include a 0 ,a 1 ,…,a A-1 ,in is the length of the PBCH payload 711. In the PBCH payload 711, the 10 ,a 11 ,a 12 ,a 13 The bit at is the selected timing-related bit, wherein the selected timing-related bit is used by the decoder to perform early termination.

[0054] Subsequently, the PBCH payload 711 is received by the bit scrambling module 720, which generates a scrambled PBCH payload 721 based on the PBCH payload 711. The CRC encoding module 730 then receives the scrambled PBCH payload 721 and encodes the scrambled PBCH payload 721 using a CRC code. Output data 731 of the CRC encoding module 730 is then transmitted to the interleaver module 740.

[0055] The interleaver module 740 may transform the output data 731 of the CRC encoding module 730 into an interleaved PBCH payload 741, including the distributed CRC code and the PBCH payload. The polarization bit distributor 735 within the interleaver module 740 may also map each bit of the interleaved PBCH payload 741 to a corresponding input bit position of the encoder 750. The encoder 750 encodes the interleaved PBCH payload 741 (e.g., performs polarization encoding) and generates a sequence of encoded bits 751.

[0056] In one embodiment, the polarization bit allocator 735 may first identify and skip the frozen bits and unavailable input bit positions of the encoder 750, and then allocate the selected timing-related bits in the interleaved PBCH payload 741 to the input bit position with the smallest available index (such as the front input bit position). In this case, when the UE receives such an encoded PBCH payload, the UE may decode the encoded PBCH payload. Because the selected timing-related bits in the encoded PBCH payload are located at the smallest available index, the decoder may extract and decode the selected timing-related bits earlier than other bits. Therefore, when only the selected timing-related bits need to be known, the decoding process may end earlier. Accordingly, the decoding complexity and power consumption of the UE may be reduced.

[0057] In another embodiment, after identifying and skipping frozen bits and unavailable positions of the encoder 750, the polarization bit allocator 735 may select some input bit positions with the highest reliability in the input bit sequence of the encoder 750 for allocating the interleaved PBCH payload 741. The polarization bit allocator 735 may then allocate the selected timing-related bits in the interleaved PBCH payload 741 to the front of the selected input bit positions. In this case, transmission reliability and early termination may be satisfied.

[0058] In another embodiment, after identifying and skipping the frozen bits and unavailable positions of the encoder 750, the polarization bit allocator 735 may reserve some available input bit positions for the selected timing-related bits in the interleaved PBCH payload 741. In one example, the polarization bit allocator 735 may reserve some available input bit positions based on the channel reliability of the corresponding input bits of the encoder. The polarization bit allocator 735 may select the available input bits with the highest reliability in the first half of the encoder 750, and then allocate the selected timing-related bits to the predetermined input bit positions of the encoder 750. In this case, the UE receiving such an encoded PBCH payload may perform a sequence matching algorithm on the 4 selected timing-related bits at the predetermined positions. Because the UE knows the predetermined positions for the selected timing-related bits, the UE may not need to decode the entire encoded PBCH payload. That is, the predetermined positions of the selected timing-related bits are known to the UE, so the UE can compare the selected timing-related bits with several matching arrangements to determine a match. Once the selected timing-related bits match a permutation, the selected timing-related bits can be detected without performing a complete PBCH decoding. In addition, a decoder may not be required in the sequence matching process.

[0059] Although the polarization bit allocator 735 is shown as part of the interleaver module 740, it should be understood that the polarization bit allocator 735 can be included in whole or in part in any of the modules 710, 720, 730, 740, and 750. In other words, the functionality of the polarization bit allocator 735 can be performed in a separate module, or as part of any of the modules 710, 720, 730, 740, and 750, or distributed across any number of modules.

[0060] Fig. 8A An exemplary PBCH interleaver pattern 800 is shown. Such a PBCH interleaver pattern can be used by the interleaver module 740 to assign selected timing-related bits to input bit positions of the encoder 750. For example, the selected timing-related bits c0, b5, b4, and b3 are located at positions a, b1, b2, and b3 in the sequence of the PBCH payload 711, respectively. 10 、a 11 、a 12 and a 13, wherein the PBCH payload 711 is generated by the PBCH payload generation module 710. After the PBCH payload 711 passes through the scrambling module 720 and the CRC encoding module 730, the positions of the selected timing-related bits C0, b5, b4 and b3 can remain unchanged. Therefore, when C0, b5, b4 and b3 are input to the interleaver module 740, they are still respectively located at a 10 、a 11 、a 12 and a 13 According to Fig. 8A The interleaver mode in the interleaver module 740 has an input bit a 10 801, a 11 802, a 12 803 and a 13 804 (i.e. C0, b5, b4 and b3) are interleaved to G 0 811, G 5 812, G 3 813 and G 2 814. Each interleaved bit will be mapped to the corresponding input bit position of the encoder 750 by the polarization bit distributor 735. In addition, the interleaver module 740 also interleaves other information bits in the PBCH. For example, information bit a 0 805 is interleaved to G 16 815.

[0061] Figure 8B An exemplary mapping function 820 of the polarization bit allocator 735 according to an embodiment of the present invention is shown. As described above, the mapping function of the polarization bit allocator 735 can be used to allocate selected timing-dependent bits to input bit positions of the encoder 750. Figure 8B In the example of , it is also assumed that there are 512 input bit positions in the encoder 750, and some of them are frozen bits and therefore cannot be used to allocate bits. For example, the input bit position 245 is a frozen bit and cannot be used to allocate information bits.

[0062] according to Figure 8B , 4 interleaved timing-related bits G 0 821, G 2 822, G 3 823 and G 5 824 are respectively mapped by polarization bit distributor 735 to input bit positions 247 (831), 253 (832), 254 (833) and 255 (834) of encoder 750. As shown in the figure, each other information bit is also mapped to a corresponding input bit position of encoder 750. For example, G 16825 is mapped to input bit position 473 (835). In addition, please note that each of the 4 selected timing-related bits is allocated at the front of the input bit position sequence of encoder 750 so that the above 4 selected timing-related bits can be decoded earlier than other information bits. Therefore, once the above 4 selected timing-related bits are decoded, the decoding process can be ended earlier. The decoding process that ends early is shorter than the decoding process of the complete PBCH decoding, so the decoding complexity and power consumption can be reduced.

[0063] Fig. 9 FIG. 9 is a flowchart of an exemplary polarization bit allocation process 900 according to an embodiment of the present invention. The process may be performed by the system 700 and may refer to Figure 7 Aspects of the process 900 are explained. The process 900 starts at S910 and proceeds to S920.

[0064] In step S920, a PBCH payload is generated based on the input bits. The PBCH payload may include system information bits and timing-related information bits. Figure 7 , for example, the PBCH payload may be generated by the PBCH payload generation module 710. The input bits may come from a higher layer, such as a transport layer. The PBCH payload generation module 710 generates the PBCH payload based on the input bits in a manner consistent with the NR specification (NR Spec) in 38.212 section 7.1.1. After generating the PBCH payload, the process 900 may proceed to step S930.

[0065] At step S930, the generated PBCH payload is scrambled, encoded and interleaved. Figure 7 , for example, the generated PBCH payload may be scrambled by the bit scrambling module 720. Thus, a scrambled PBCH payload may be generated by the bit scrambling module 720. The scrambled PBCH payload may then be encoded by the CRC encoding module 730. The output data of the CRC encoding module 730 includes the scrambled PBCH payload with a CRC code, wherein the CRC code may be generated based on the scrambled PBCH payload. Subsequently, the interleaver module 740 receives the output data of the CRC encoding module 730 and may convert it into an interleaved PBCH payload, wherein the interleaved PBCH payload includes the distributed CRC code and the PBCH payload. After generating the interleaved PBCH payload, the process 900 may proceed to step S940.

[0066] At step S940, each bit of the interleaved PBCH payload may be assigned to a corresponding input bit position of the encoder according to a mapping function. Figure 7For example, each bit of the interleaved PBCH payload may be mapped to a corresponding input bit position of the encoder 750 by the polarization bit allocator 735. The polarization bit allocator 735 may use at least three mapping functions to map the interleaved PBCH payload.

[0067] The first mapping function may include: (1) identifying and skipping frozen bits and unavailable positions in an input bit sequence of an encoder; (2) selecting a portion of timing-related bits from a PBCH payload; (3) selecting some available input bit positions with the smallest available indexes in the input bit sequence of the encoder for the selected timing-related bits; and (4) allocating the selected timing-related bits to the selected positions in the input bit sequence of the encoder.

[0068] The second mapping function may include: (1) identifying and skipping frozen bits and unavailable positions in the encoder's input bit sequence; (2) selecting a portion of timing-related bits from the PBCH payload; (3) selecting some available input bit positions with the highest reliability in the encoder's input bit sequence for the PBCH payload; and (4) allocating the selected timing-related bits to the front of the encoder's selected input bit positions.

[0069] The third mapping function may include: (1) identifying and skipping frozen bits and unavailable positions in the input bit sequence of the encoder; (2) selecting a portion of timing-related bits from the PBCH payload; (3) selecting some available input bit positions with the highest reliability in the first half of the input bit sequence of the encoder for the selected timing-related bits; and (4) allocating the selected timing-related bits to the selected positions in the input bit sequence of the encoder.

[0070] After assigning each bit of the interleaved PBCH payload to a corresponding input bit position of the encoder, process 900 may proceed to step S950.

[0071] At step S950, an input bit sequence is encoded. The input bit sequence includes an interleaved PBCH payload with or without frozen bits. Before the polar encoder encodes the input bit sequence, each bit of the interleaved PBCH payload may be allocated to a corresponding input bit position of the polar encoder by a polar bit allocator. After the encoding process is completed, process 900 may proceed to step S960.

[0072] At step S960, it is determined whether another PBCH payload is needed. If it is determined that another PBCH payload is needed, the process 900 will return to step S920 to generate another PBCH payload based on the input bits. Otherwise, the process 900 will proceed to step S970 and end at S970.

[0073] Note that although process 900 is described as a series of steps, in various examples, the steps may be performed in a different order or in parallel. In addition, in some examples, not all steps need to be performed.

[0074] Fig.10 An exemplary device 1000 according to an embodiment of the present invention is shown. The device 1000 may be configured to perform various functions described in accordance with one or more embodiments or examples of the present invention. Therefore, the device 1000 may provide a means for implementing the techniques, processes, functions, components, and systems described in the present invention. For example, the device 1000 may be used to implement the functions of the UE 110 and the BS 120 in the various embodiments and examples described in the present invention. In some embodiments, the device 1000 may be a general purpose computer, while in other embodiments, the device 1000 may be a device including specially designed circuits to implement the various functions, components, or processes described in the present invention. The device 1000 may include a processing circuit 1010, a memory 1020, and a radio frequency (RF) module 1030.

[0075] In various examples, the processing circuit 1010 may include circuits configured to perform the functions and processes described in the present invention, which may be implemented in conjunction with software or not. In various examples, the processing circuit may be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable gate array (FPGA), a digitally enhanced circuit, or an equivalent device or a combination thereof.

[0076] In some other examples, the processing circuit 1010 may be a central processing unit (CPU), configured to execute program instructions to perform various functions and processes described in the present invention. Accordingly, the memory 1020 may be configured to store program instructions. When executing program instructions, the processing circuit 1010 may perform the functions and processes described in the present invention. The memory 1020 may also store other programs or data, such as an operating system (OS) and an application program. The memory 1020 may include a read-only memory (ROM), a random access memory (RAM), a flash memory, a solid-state memory, a hard disk drive, and an optical drive.

[0077] RF module 1030 receives processed data signals from processing circuit 1010 and transmits the above signals via antenna 1040, and vice versa. RF module 1030 may include a digital to analog converter (DAC), an analog to digital converter (ADC), an upconverter (frequency upconverter), a downconverter (frequency downconverter), a filter, and an amplifier for receiving and transmitting operations. In some examples, RF module 1030 may include a multi-antenna circuit (such as an analog signal phase / amplitude control unit) for beamforming operations. Antenna 1040 may include one or more antenna arrays.

[0078] The apparatus 1000 may optionally include other components, such as input and output devices and additional signal processing circuits, etc. Accordingly, the apparatus 1000 may be capable of performing other additional functions, such as executing applications and processing additional communication protocols.

[0079] Although aspects of the present invention have been described in conjunction with specific exemplary embodiments, substitutions, modifications and variations may be made to the above examples. Therefore, the embodiments described in the present invention are intended to be illustrative rather than restrictive, and changes may be made without departing from the scope of the claims.

Claims

1. A method for wireless communication, comprising: receiving a synchronization signal block from a base station, the synchronization signal block comprising encoded bits corresponding to a physical broadcast channel payload; Decoding the encoded bits according to a polarization decoding process to produce polarization decoded bits; decoding the polarized decoded bits according to a cyclic redundancy check decoding process to generate physical broadcast channel payload bits; Obtaining a portion of timing-related bits from the physical broadcast channel payload bits according to the bit mapping, wherein the timing-related bits are used to indicate the timing of the synchronization signal block in the synchronization signal burst from the base station; as well as The synchronization signal block is processed according to the portion of timing-related bits.

2. The method for wireless communication according to claim 1, characterized in that: The part of timing-related bits includes a half-frame indication bit and three bits of the index of the synchronization signal block.

3. The method for wireless communication according to claim 2, characterized in that: The bitmap comprises: The portion of timing-related bits is mapped to the first bit with bit indexes 10, 11, 12 and 13 in the physical broadcast channel payload bits.

4. The method for wireless communication according to claim 3, characterized in that: The first bits with bit indices 10, 11, 12 and 13 in the physical broadcast channel payload bits are mapped to second bits with bit indices 0, 5, 3 and 2 in the polarized decoded bits, respectively.

5. A method for wireless communication, comprising: receiving a synchronization signal block from a base station, the synchronization signal block comprising encoded bits corresponding to a physical broadcast channel payload; Decoding the encoded bits according to a polarization decoding process to produce polarization decoded bits; Before decoding the polarized decoded bits according to a cyclic redundancy check decoding process, obtaining a portion of timing-related bits from the polarized decoded bits according to bit allocation of the polarized decoding process, wherein the timing-related bits are used to indicate a timing of the synchronization signal block in a synchronization signal burst from the base station; as well as The synchronization signal block is processed according to the portion of timing-related bits.

6. The method for wireless communication according to claim 5, characterized in that: The part of timing-related bits includes a half-frame indication bit and three bits of the index of the synchronization signal block.

7. The method for wireless communication according to claim 5, characterized in that: The obtaining of a portion of timing-related bits comprises: The portion of timing-dependent bits is obtained by decoding the first four information bit positions in the sequential decoding of the polar decoding process.

8. The method for wireless communication according to claim 7, characterized in that: The part of timing-related bits includes a half-frame indication bit and three bits of the index of the synchronization signal block.

9. The method for wireless communication according to claim 5, characterized in that: The obtaining a portion of timing-related bits according to the bit allocation of the polarization decoding process includes: identifying a portion of the coded bits corresponding to a first half of the polarized decoded bits according to the bit allocation; and A matching process is performed on the identified portion of encoded bits to obtain the portion of timing-related bits.

10. A device for wireless communication, comprising: A processing circuit, the processing circuit being configured to: receiving a synchronization signal block from a base station, the synchronization signal block comprising encoded bits corresponding to a physical broadcast channel payload; Decoding the encoded bits according to a polarization decoding process to produce polarization decoded bits; decoding the polarized decoded bits according to a cyclic redundancy check decoding process to generate physical broadcast channel payload bits; Obtaining a portion of timing-related bits from the physical broadcast channel payload bits according to the bit mapping, wherein the timing-related bits are used to indicate the timing of the synchronization signal block in the synchronization signal burst from the base station; as well as The synchronization signal block is processed according to the portion of timing-related bits.

11. The device according to claim 10, characterized in that The part of timing-related bits includes a half-frame indication bit and three bits of the index of the synchronization signal block.

12. The device according to claim 11, characterized in that The bitmap comprises: The portion of timing-related bits is mapped to the first bit with bit indexes 10, 11, 12 and 13 in the physical broadcast channel payload bits.

13. The device according to claim 12, characterized in that The first bits with bit indices 10, 11, 12 and 13 in the physical broadcast channel payload bits are mapped to second bits with bit indices 0, 5, 3 and 2 in the polarized decoded bits, respectively.

14. A device for wireless communication, comprising: A processing circuit, the processing circuit being configured to: receiving a synchronization signal block from a base station, the synchronization signal block comprising encoded bits corresponding to a physical broadcast channel payload; Decoding the encoded bits according to a polarization decoding process to produce polarization decoded bits; Before decoding the polarized decoded bits according to a cyclic redundancy check decoding process, obtaining a portion of timing-related bits from the polarized decoded bits according to bit allocation of the polarized decoding process, wherein the timing-related bits are used to indicate a timing of the synchronization signal block in a synchronization signal burst from the base station; as well as The synchronization signal block is processed according to the portion of timing-related bits.

15. The device according to claim 14, characterized in that The part of timing-related bits includes a half-frame indication bit and three bits of the index of the synchronization signal block.

16. The device according to claim 14, characterized in that The processing circuit is configured to: The portion of timing-dependent bits is obtained by decoding the first four information bit positions in the sequential decoding of the polar decoding process.

17. The device according to claim 16, characterized in that The part of timing-related bits includes a half-frame indication bit and three bits of the index of the synchronization signal block.

18. The device according to claim 14, characterized in that The processing circuit is configured to: identifying a portion of the coded bits corresponding to a first half of the polarized decoded bits according to the bit allocation; and A matching process is performed on the identified portion of encoded bits to obtain the portion of timing-related bits.

19. A memory storing program instructions, wherein when the program instructions are executed by a device, the device executes the steps of the method for wireless communication according to any one of claims 1 to 9.

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