Memristor-based circuits and methods

Abstract

A memristor-based circuit is described in which a voltage generator is arranged to apply a series of voltage pulses to the memristor to gradually change the resistance of the memristor. A comparator is arranged to: receive an input electrical value; receive an electrical value based on the resistance of the memristor; compare the received values; and, based on the comparison, enable the voltage generator to apply the voltage pulses to the memristor until a defined condition is met. This circuit can be used to enable the memristor to be programmed to a desired resistance value, for example for use as a non-volatile memory. The circuit can also enable the resistance of one memristor to be copied to another memristor. By counting the number of applied voltage pulses, the circuit can be used as an encoder or analog-to-digital converter. Other variations of the circuit enable the construction of decoders or digital-to-analog converters, as well as authentication circuits.

Description

Technical Field

[0001] The present invention relates to a memristor-based circuit and method, for example, for replicating memristor resistance, performing encoding and decoding, and for authentication. Background Art

[0002] Memristors are circuit elements of particular interest for use in the design of high-density nonvolatile memories, neuromorphic systems, logic design, and more recently, sensors and solar cells. This is due to their nonvolatility and high-resolution programmability. Conventional techniques for tuning the resistance of memristors to a predetermined value involve programming. However, these programming techniques require external processing to accurately tune the memristor. While precise, these programming methods also suffer from the drawback of being unable to program devices with high on / off ratios.

[0003] Additionally, analog-to-digital converters (ADCs) are widely used in modern electronics to represent the (encoded) value of an analog signal in digital form for subsequent storage and / or logic processing by conventional microcontrollers.There is a problem in manufacturing simple, compact, low-power encoders and decoders.

[0004] There is also a need to be able to securely mark chips or other electronic circuits for authentication purposes, ie, to identify unauthorized clones and to identify authentic clones. Summary of the Invention

[0005] The present invention has been devised in view of the above-mentioned problems.

[0006] Therefore, one aspect of the present invention provides a memristor-based circuit comprising:

[0007] Memristor;

[0008] a voltage generator arranged to apply a series of voltage pulses to the memristor so as to incrementally change the resistance of the memristor; and

[0009] a comparator arranged to receive an input electrical value, receive an electrical value based on the resistance of the memristor, compare the received values, and based on the comparison enable application of the voltage pulse by the voltage generator to the memristor until a defined condition is met.

[0010] Another aspect of the present invention provides an encoder comprising:

[0011] Memristor;

[0012] a voltage generator arranged to apply a series of voltage pulses to the memristor so as to incrementally change the resistance of the memristor;

[0013] a comparator arranged to receive an input electrical value, receive an electrical value based on the resistance of the memristor, compare the received values, and based on the comparison enable application of the voltage pulse by the voltage generator to the memristor until a defined condition is met; and

[0014] A counter is arranged to count the number of voltage pulses applied to the memristor and output the number.

[0015] Another aspect of the present invention provides a decoder comprising:

[0016] Memristor;

[0017] a voltage generator arranged to apply a series of voltage pulses to the memristor so as to incrementally change the resistance of the memristor; and

[0018] A counter is arranged to receive a digital number as input and is arranged to cause the voltage generator to apply said number of voltage pulses to the memristor.

[0019] Another aspect of the present invention provides an authentication circuit connectable to a memristor provided in an external circuit, the authentication circuit comprising:

[0020] a voltage generator arranged to apply a series of voltage pulses to the memristor so as to incrementally change the resistance of the memristor;

[0021] a comparator arranged to receive an input electrical value, receive an electrical value based on the resistance of the memristor, compare the received values, and based on the comparison enable application of the voltage pulse by the voltage generator to the memristor until a defined condition is met; and

[0022] a counter arranged to count the number of voltage pulses applied to the memristor and to output said number,

[0023] Wherein the input electrical value comprises a challenge, and wherein the output quantity comprises a response of the memristor based on the external circuit.

[0024] Another aspect of the present invention provides an authentication circuit connectable to a memristor provided in an external circuit, the authentication circuit comprising:

[0025] a voltage generator arranged to apply a series of voltage pulses to the memristor so as to incrementally change the resistance of the memristor; and

[0026] a counter arranged to receive a digital number as input and arranged to cause the voltage generator to apply said number of voltage pulses to the memristor,

[0027] wherein the quantity received as the input comprises a challenge, and wherein an electrical value of a resulting resistance of the memristor based on the external circuit comprises a response.

[0028] Another aspect of the present invention provides a method comprising:

[0029] receiving input electrical values;

[0030] applying a series of voltage pulses to a memristor to incrementally change the resistance of the memristor;

[0031] receiving an electrical value based on the resistance of the memristor; and

[0032] The received values ​​are compared and based on the comparison, the voltage pulse is enabled to be applied to the memristor until a defined condition is met.

[0033] Another aspect of the present invention provides a method comprising:

[0034] receiving input electrical values;

[0035] applying a series of voltage pulses to a memristor to incrementally change the resistance of the memristor;

[0036] receiving an electrical value based on the resistance of the memristor;

[0037] comparing the received values ​​and, based on the comparison, enabling application of the voltage pulse to the memristor until a defined condition is met; and

[0038] The number of voltage pulses applied to the memristor is counted and the number is output.

[0039] Another aspect of the present invention provides a method comprising:

[0040] Receives quantity as input;

[0041] applying a series of voltage pulses to a memristor to incrementally change the resistance of the memristor;

[0042] counting such that the number of voltage pulses applied to the memristor is equal to the number received as input; and

[0043] An electrical value based on the resulting resistance of the memristor is output.

[0044] Further aspects of the invention are defined in the dependent claims.

[0045] Embodiments of the present invention can provide a simple and efficient lightweight memristor replicator structure that is capable of copying the resistance of a source memristor to a target memristor by repeatedly applying programming pulses. Such circuits can be used to back up analog data, for example from a memristor sensor, before or during conversion of the analog data into digital form. The proposed circuit structure is very versatile and can be used not only to replicate memristors, but also to generate non-linear digital codes and decode the codes back to the source memristor / voltage (within quantization limits). Due to the non-linear encoding, the architecture also provides a certain level of inherent security features. Memristors can provide physical unclonability, so embodiments of the present invention can be used in applications such as chip marking / identification, and to prevent unauthorized manufacturing. Due to its simple and versatile nature, embodiments of the present invention can be used in remote and low-power devices that require a certain level of security, such as in remote sensor nodes, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0047] Figure 1 (a) and 1(b) show the structure of the TiO2-based memristor and the corresponding circuit symbol, respectively;

[0048] Figure 2 is a schematic circuit diagram of a memristor circuit according to an embodiment of the present invention;

[0049] Figure 3 is a schematic circuit diagram of a memristor replicator circuit according to an embodiment of the present invention;

[0050] Figure 4 is a schematic circuit diagram of a memristor-based encoder (or analog-to-digital converter (ADC)) circuit according to an embodiment of the present invention;

[0051] Figure 5 is a schematic circuit diagram of a memristor-based decoder (or digital-to-analog converter (DAC)) circuit according to an embodiment of the present invention;

[0052] Figure 6 is a more detailed circuit diagram of a memristor-based replicator / encoder / decoder according to another embodiment of the present invention;

[0053] Figure 7 a graph showing the encoded digital output for different memristor sizes;

[0054] Figure 8 a graph showing encoded digital output for different programming pulse voltages; and

[0055] Figure 9(a) and 9(b) is a graph showing the effect of encoding values ​​on different programming pulse widths.

[0056] In the drawings, the same components are denoted by the same reference numerals, and repeated description of the same components is omitted. DETAILED DESCRIPTION

[0057] A memristor is a device in the art whose resistance (also called memristance) is changed by a current flowing through the device. The resistance has a minimum value R ON and the maximum value R OFF The resistance can be tuned by applying an appropriate voltage or current and is non-volatile (the resistance value is 'remembered'), allowing memristors to be used as memory elements. The resistance can also be affected by external factors, allowing memristors to be used as sensor elements.

[0058] Memristors can be made from various materials, such as: TiO2 (e.g. with doped and undoped regions and with Pt electrodes); Ag / Ag5In5Sb 60 Te 30 / Ta; Ag-a-LSMO-Pt (Ag nanofibers in amorphous manganate films); other semiconductor metal oxides, such as aluminum oxide, copper oxide, silicon oxide, zinc oxide, tantalum oxide, hafnium oxide; amorphous perovskite oxides (such as a-SrTiO3); and other ferroelectric and doped polymer materials, as well as graphene oxide. The embodiments of the present invention are not limited to any particular material, provided that the memristive property exists. Components that are memristors are described herein as memristors. In the following description, by way of example only, the embodiments are based on TiO2 memristors.

[0059] Memristors typically exhibit nonlinear behavior. According to one model, the total resistance of a memristor is determined by the resistance of two regions: the undoped region (TiO2) and the doped region (TiO 2-X ),like Figure 1 (a). If the initial resistance of the memristor is R init , then for x=0, R init =R on (low resistance state), and for x=D, R init =R off (High resistance state) The lengths (x and D) depicted in this figure will be used in the remainder of this description.

[0060] In practical memristive devices, memristance depends on the highly nonlinear tunneling effect. Therefore, any change in the tunnel barrier width will change the anti-memristance and appear to vary exponentially with x. MGiven in Equation 1.

[0061]

[0062] in x on ≤x≤x off and x on and x off are the lower and upper limits of the undoped region.

[0063] Figure 1 (b) shows the symbol of a memristor. Here, P and N are its 'positive' and 'negative' terminals respectively. When the instantaneous voltage V P >V off When the memristor switches to the high resistance state (R off ), and when V P <V on When it switches to the low resistance state (R on ), as in Equation 2 for V in =V P As defined. When V on <V P <V off When , the state of the memristor does not change, that is, it is in the 'hold' state.

[0064]

[0065] where K off , K on , α on , α off is a constant, and V on and V off is the threshold voltage. Function F off (x) and F on (x) represents the correlation of the derivative of the state variable x. These functions behave as window functions that constrain the state variable to be x∈[x on ,x off ] boundaries.

[0066] Apply write voltage V W (0 <V off <V W ) to move the memristor's potential barrier from R ON To R off shift, and apply the read voltage V R (V ON <V R <V off ) to read the resistance / voltage drop across the memristor, as given in Equation 2.

[0067] refer to Figure 2, depicts a basic circuit, wherein the voltage generator 10 is arranged to include a memristor M D and the load resistor R DL A voltage is applied across the voltage divider circuit. D Initialized to a low resistance state R ON Next, the voltage generator 10 receives the clock signal clk input at the terminal 12, and the clock signal clk is input at the time T prog High level and time T hold The low level of the generator 10 is repeatedly switched between the substantially rectangular wave and the low level of the generator 10. prog and T hold Output programming voltage V prog and holding voltage V hold Considering the load R DL , V prog Adjust to be high enough so that V W Appears in the memristor M D Similarly, V hold is adjusted high enough to make V R Appears in the memristor M D In this way, the memristor M D A series of voltage pulses is applied, which incrementally changes the resistance of the memristor.

[0068] The comparator 14 receives an input electrical value, in this case an input voltage, at a terminal 16. The comparator 14 also receives an input electrical value, in this case an input voltage, from a terminal 16 comprising a memristor M. D During the period T when the programming voltage pulse is not applied to the memristor hold During this time, a comparator compares the two received voltages, optionally with a weighting factor. When a defined condition is met, such as the voltage at the voltage divider equals or exceeds the input voltage at terminal 16, the output of the comparator causes the voltage generator 10 to stop applying further programming voltage pulses, and the resistance of the memristor is now fixed.

[0069] In this way, the memristor M D The resistance of a can be accurately and reproducibly 'programmed' to a value that depends on the value of the input voltage; different input voltages will produce different resistances.

[0070] Figure 3 Draws Figure 2 An improvement of the circuit wherein the input terminal 16 is connected to a source memristor M S and source load resistor R SL The original memristor is now the target memristor M D In the preferred embodiment, the load resistor R SL and R DLare matched, and the source memristor M S and the target memristor M D Also matched. Source memristor M S A sensor having a set resistance (memristor) value, such as a source memristor, may be one whose resistance value is related to the property being sensed.

[0071] Voltage V hold is applied to the source memristor M S Terminal 18, and the memristor M D Initialized to a low resistance state R ON When the clock signal is now applied to terminal 12, the resistance of the target memristor is increased by the programming voltage pulse (during the period T prog During V prog ) changes incrementally until the two voltages input to the comparator 14 are equal (at T hold The result is a source memristor M S The resistance is copied to the target memristor M D .

[0072] If different component values ​​are used in the circuit, the memristor resistance will not necessarily be the same, but the resistance of the target memristor will be related to the resistance of the source memristor. This embodiment illustrates how resistance can be used as an input electrical value to be copied to another resistor. However, embodiments of the present invention can use other input electrical values, such as voltage or current. The resulting output can also be resistance, voltage, current, or other electrical values.

[0073] for Figure 3 In an embodiment, if the source memristor is, for example, a sensor, the above-described replication process can be used to read and store the sensed value at a particular time. The target memristor can be one of an array of such memristors that are selectable and each is sequentially programmed over time to store the sensed value for subsequent retrieval. Of course, it is not necessary to have a source memristor, and one could simply program, for example, Figure 2 Any electrical value such as the input voltage in a circuit can be read and stored.

[0074] This technique for reading and storing electrical values ​​is advantageous because it does not require extensive digital circuitry and can therefore be compact and low-power. This makes it particularly well-suited for remote sensing applications.

[0075] exist Figure 4 Another embodiment of the present invention is shown in FIG. Figure 2 The circuit is the same as the one above, but with the addition of a counter 20. The counter 20 is applied to the memristor M D The programming voltage pulse V progThe circuit counts the number of digits until programming stops and then outputs the number, for example as an n-bit binary number. This output number is related to the input analog electrical value (e.g., voltage) at terminal 16. Thus, the circuit acts as an analog-to-digital converter (ADC). The circuit also acts as an encoder, thereby converting the input value into a unique number. The encoding is nonlinear because it depends on, for example, the memristor M D properties such as electrical characteristics (and depends on, for example, V prog 、T prog This makes the encoding secure because the actual output value is meaningless without knowing the properties of the memristor, i.e., without at least close or prior knowledge of these properties and parameters, the quantity cannot be decoded back to obtain the original input value, and even the trend of the quantity is useless due to nonlinearity. Therefore, the generated code (quantity) is effectively unique to the specific memristor used to generate it, and is therefore locked to that specific device.

[0076] Any embodiment described herein may of course be combined with any other embodiment or features thereof as appropriate. Figure 3 The source memristor divider can be connected with Figure 4 This would enable the source memristor value to be read, backed up, and output as a digital value simultaneously, all with a single, simple circuit.

[0077] Next from Figure 4 The encoder circuit starts, Figure 5 The circuit provides a corresponding decoder. The number C is input to the counter 20 as the initial count value, and in this case the counter is configured as a down counter; the memristor M D Initialized to a low resistance state R ON When the clock signal clk is applied to terminal 12, the resistance of the target memristor is incrementally changed by the programming voltage pulse. Each time a voltage pulse is applied, the counter 20 is decremented. When the counter reaches zero, this is indicated by causing the voltage generator 10 to stop applying further programming voltage pulses and instead apply only V hold The output of the memristor M D has precisely C programming pulses applied to it. The voltage at terminal 22 of the voltage divider is now an analog value based on the input quantity C, i.e., the quantity C has been uniquely decoded (non-linearly) to the voltage at terminal 22. Thus, this circuit also functions as a digital-to-analog converter (DAC).

[0078] Figure 4 and 5 The circuits can also each be used as an authenticator for authentication checking purposes. The inputs are analog voltage and digital ( Figure 4and 5 ), and the corresponding outputs are digital and analog voltages. The input and output form a challenge-response pair (CRP). In one embodiment, the memristor M D It is arranged in an external circuit, such as a chip in an electronic device or in an IC card such as a bank card, and is connected to the rest of the corresponding circuit. The expected response (output) based on one or more challenges (inputs) is known to the entity seeking authentication. If the memristor is authentic, the correct response will be obtained (within a defined error margin) and the chip / electronic device can be verified as authentic. If the original memristor is not used, the correct response will not be obtained and authentication can be rejected. Unauthorized copies of memristors cannot be easily manufactured because the electronic properties of memristors strongly depend on manufacturing parameters and are nonlinear, as discussed further below. Therefore, chips / electronic devices can be marked and identified using memristors and cannot be cloned.

[0079] Figure 6 The method for converting the source memristor M to a specific quantization limit is shown. S Copy to the target memristor M D An embodiment of a specific architecture of a memristor M S 、M D and the load resistor R SL and R DL Two voltage dividers are formed. R SL and R DL appears to be closely matched. The voltage divider V INS and V IND The output voltage of is continuously compared by the comparator Comp. The described architecture is simple, power efficient, and requires a small number of logic gates, comparators, level shifters (also called voltage converters, and in fact a form of comparator, and performing the function of the voltage generator 10 in the previous embodiment), and edge sensitive counters. In a preferred embodiment, the level shifters are "gated", that is, they are switched on or off depending on whether power is supplied to the power input line of the level shifter (in Figure 6 'Strobe' in the .

[0080] A. Copy and Encode: Let f rep is the replica frequency of the clock (clk), and T rep =T prog +T hold =1 / f rep is the clock period. prog and T hold During this period, voltage V is applied alternately prog and V hold . V progis adjusted high enough so that even with a load R DL , V W Also only appears in the memristor M D Similarly, V hold Adjust high enough to make V R At the same time, it appears in the memristor M S and M D Therefore, by repeatedly applying these pulses based on Equation 2, the memristor M S The resistance is copied to the memristor M D In each T prog During this period, V prog M D The barrier from R on Region to R off The region shifts slightly but nonlinearly, and at subsequent T hold During this period, M D and M S The counter at the top counts the number of clock pulses required for replication.

[0081] The replication is performed by first applying the counter and the memristor M D The reset is started by applying a 'CLR' pulse to the negative terminal of the memristor. This pulse has sufficient amplitude so that the very short duration will reset the memristor M D Reset to R on The first stage of the counter is used to generate the pulses, and once CLR is complete, the counter is reused for encoding. During CLR: the level shifter is disabled via the strobe input; AND gates A2 and A3 block the input and generate a constant zero. Thus, the clock signal clk is prevented from reaching the level shifter. As a result, the level shifter is switched off at the memristor M. D The P terminal of the memristor generates 0, while the high CLR pulse at the N terminal of the memristor turns the memristor M D Reset to R on .

[0082] When CLR returns to 0, the level shifter and AND gates A2 and A3 are enabled and replication begins. A2 passes clk to the level shifter, which is reset in the same cycle (T rep ) in V prog With V hold Switch between. V prog In T prog During this period, the memristor M D The potential barrier is shifted, and the comparator Comp is at T hold During this period, the voltage obtained is combined with the memristor M S The voltage across the two ends is compared. holdDuring this period, the comparator keeps generating 1 until the memristor M D The voltage across the memristor M exceeds S This forces A3 and A4 to generate 0, which causes A1 to pass clk to the level shifter. As a result, the memristor M D The voltage across the memristor M increases gradually during each clock cycle until it exceeds the S The voltage across the two ends, at this time the comparator is at T hold This forces A3 and A4 to generate 1, and the level shifter is disabled via the strobe pulse. This prevents A1 from passing clk, thereby indicating the end of the copy. In essence, the circuit enters a 'locked' state, which is controlled by the memristor M D During the copying period, the counter counts the number of clock cycles required for copying, and the number of clock cycles is the memristor M S The proposed architecture thus performs nonlinear encoding of the analog voltage / resistance when replication occurs.

[0083] As mentioned above, when the copying (or code conversion) is complete, the level shifter is disabled by stopping the application of power (Vdd) to the "strobe" input. This means that the level shifter produces an output that is equal to 0V, rather than V hold ; Therefore, zero voltage is applied to the memristor M D , to avoid undesirably applying a sustained voltage across the memristor for a long period of time. A single PMOS or NMOS transistor can be used to implement power switching or gating.

[0084] Thereafter, the second phase of replication can be initiated by a CLR pulse which pulses the memristor M D A reset is performed, thereby taking the system out of lock state (level shifter enabled).

[0085] For a fixed V prog , the accuracy depends on T prog width, and a lower T prog Results in higher accuracy, but at the expense of increased copy / conversion time.

[0086] If the source memristor M S The resistance (or equivalently, the voltage V INS ) is stable, the copy / encoding process will terminate naturally. INS In applications where the V INS and V INDWhen V IND With V INS When a match occurs, the latch will 'lock in' the reading (counter value and / or memristor) at the first instant, which is appropriate for some applications. However, this may not be desirable in other cases, so another embodiment of the invention has a predetermined 'sense' period, and after the predetermined sense period has elapsed the clock is automatically stopped so that a reading can then be given. The detection period can be made relative to T rep Long enough so that V IND There will be time to match V INS .

[0087] B. Decoding: If during replication, the counter records the digital value C. Decoding is done by first switching the memristor M with CLR in C cycles. D cleared and by the same frequency f rep =1 / (T prog +T hold ) with the same V prog and V hold This is achieved by 'programming' the memristor. Part of the decoder logic appears in Figure 6 In the dotted box marked as 'decode' in FIG. A down counter (not shown) initialized to C is used to count the number of clock cycles. After decoding, V hold -V DL (where V DL It is R DL The voltage drop across it) divided by the current gives the corresponding encoding resistance within quantization limits.

[0088] C. Security and physical unclonability: The circuit architecture provides a certain level of inherent security by means of nonlinear coding. The code value C is V W 、T prog 、T hold and M D itself. Therefore, it is very challenging to guess what the resistance or voltage C represents without a complete understanding of these quantities. D Nearly exact matching of memristors presents further challenges and difficulties.

[0089] The architecture also provides physical unclonability by virtue of nonlinearity and its sensitivity to process and parameter variations. As shown by the experimental results, the nonlinear code depends largely on the memristor M Dphysical parameters of the , such as length dimension D, threshold voltage, etc. Any slight change in these parameters will be amplified by the counting-based encoding mechanism and result in different codes ( Figure 7 ). Therefore, any two manufactured chips may produce different codes for the same input voltage / resistance, making them very difficult to clone.

[0090] Although this architecture is suitable for replicating memristors, it can also be used for nonlinear encoding / decoding and for authentication based on challenge-response pairs (CRPs). S Yes, in Figure 6 In, V INS It can be used as an input voltage for questioning. After encoding, the contents of the counter can be used as a unique non-linear response. In addition, due to the physical non-cloning of the chip, this response will vary from chip to chip, thus also providing a provision for chip identification / marking. INS The analog input voltage at can be obtained from lightweight cryptographic hardware or a hash function generator (e.g., a linear feedback shift register) to improve security.

[0091] In the aforementioned embodiment of the present invention, the memristor M D Initialized to a low resistance state R ON , and the application of the voltage pulse will shift the resistor toward the high resistance state R OFF Gradually increases until the defined condition is met. However, by placing the memristor M D Initialized to high resistance state R OFF , then applying a voltage pulse (of opposite polarity to that in the previous embodiment) to change the resistance to a low resistance state R in negative increments ON Alternative embodiments of the present invention may operate equally until a defined condition is met (eg, detected by a comparator having inverted input terminals relative to the previous embodiment).

[0092] Experimental results: The above model is used to encode the memristor and simulate the circuit. The experiment is conducted using the 32nm technology node, where V prog =41mV, V hold =20mV, T prog =2.5ns, R SL =R DL =1KΩ, R ON =1KΩ, R off =100KΩ, D=3nm, K off =5e-4, K ON =-10,α on =3,α off =1, V ON = -0.2 and Voff =0.02. Table 1 shows that when M S The result when changing from 10KΩ to 90KΩ. Clearly, the encoded value is inherently nonlinear and has a significant impact on the resistance when copying it to the target memristor M. D Maintaining a low percentage error.

[0093] Table 1: Replication / coding (R on =1KΩ,R off =100KΩ).

[0094]

[0095] The circuit architecture inherently relies on Figure 7 The nonlinear coding shown is used to provide a certain level of security. This figure also shows that the memristor M D Slight changes in the physical parameters of the device result in different analog-to-digital conversion characteristics.

[0096] Figure 8 as well as Figure 9(a) and 9(b) The changes in V prog and T prog While keeping other parameters fixed, it can be seen that the behavior of the architecture is always nonlinear, that is, it prog or T prog And the difference between them is nonlinear.

[0097] Embodiments of a novel memristor replicator circuit architecture capable of replicating a source memristor to a target memristor have been disclosed herein. This architecture is also capable of generating nonlinear digital codes and can provide additional security features and physical unclonability. The architecture is lightweight and relies on only a few logic components, namely, two comparators (one used as a level shifter) and a counter. Experimental results show that this architecture outperforms existing designs in terms of chip area, power consumption, and performance reliability. The architecture is extremely versatile and can be used in applications for backing up analog data (e.g., sensed information), especially analog data in remote sensor nodes, nonlinear encoding, chip marking / identification, and for preventing unauthorized chip manufacturing.

Claims

1. A memristor-based circuit configured for use as an encoder and comprising: Memristor; a voltage generator arranged to apply a series of voltage pulses to the memristor so as to gradually change the resistance of the memristor; a comparator arranged to receive an input electrical value, receive an electrical value based on the resistance of the memristor, compare the received values, and based on the comparison enable application of the voltage pulse by the voltage generator to the memristor until a defined condition is satisfied, the comparator being configured such that once the defined condition is satisfied, an output of the comparator causes the voltage generator to cease generating further voltage pulses; as well as a counter arranged to count the number of voltage pulses applied to the memristor, and Output the quantity. 2 . The circuit of claim 1 , wherein the input electrical value comprises an input voltage, and the electrical value based on the resistance of the memristor is a voltage obtained from a voltage divider circuit including the memristor.

3. The circuit of claim 1 or 2, wherein the memristor is a target memristor, and further comprising a source memristor in a voltage divider circuit to provide the input voltage, wherein the resistance of the source memristor is copied into the resistance of the target memristor.

4. The circuit of claim 1 or 2, wherein the circuit is an authentication circuit comprising an encoder according to claim 1, without a memristor, wherein the authentication circuit is connectable to a memristor disposed in an external circuit, wherein an input electrical value comprises a challenge, and wherein an output quantity comprises a response of the memristor based on the external circuit.

5. The circuit of claim 4, wherein the external circuit comprises a chip marked or identified by the memristor.

6. An analog-to-digital converter comprising a circuit according to claim 1 or 2, wherein the input electrical value comprises an analog input and the pulse count value comprises a digital output.

7. A memristor-based circuit configured for use as a decoder and comprising: Memristor; a voltage generator arranged to apply a series of voltage pulses to the memristor so as to gradually change the resistance of the memristor; as well as a counter arranged to receive a number as input and arranged to cause the voltage generator to apply said number of voltage pulses to the memristor, And, wherein the counter is a down counter initialized to an input number, the down counter is configured to decrement each time the voltage generator applies a voltage pulse to the memristor, and the counter is configured to provide an output signal when the count value reaches zero to cause the voltage generator to stop applying the voltage pulse to the memristor and instead cause the voltage generator to apply a constant holding voltage to the memristor.

8. A digital-to-analog converter comprising the circuit of claim 7, wherein the received input quantity comprises a digital input and the electrical value based on the resistance of the memristor comprises an analog output.

9. An authentication circuit comprising a decoder according to claim 7, without a memristor, wherein the authentication circuit is connectable to a memristor provided in an external circuit, wherein a quantity received as an input comprises a challenge, and wherein an electrical value based on the resistance of the memristor of the external circuit comprises a response.

10. A method comprising: receiving input electrical values; applying a series of voltage pulses to the memristor using a voltage generator to gradually change the resistance of the memristor; receiving an electrical value based on the resistance of the memristor; using a comparator, comparing the received values ​​and, based on the comparison, enabling application of the voltage pulse to the memristor until a defined condition is satisfied, and providing an output to cause a voltage generator to cease generating further voltage pulses once the defined condition is satisfied; as well as The number of the voltage pulses applied to the memristor is counted and the number is output. 11 . The method of claim 10 , wherein the input electrical value comprises an input voltage, and the electrical value based on the resistance of the memristor is a voltage obtained from a voltage divider circuit including the memristor.

12. A method according to claim 10 or 11, wherein the memristor is a target memristor, and wherein a source memristor in a voltage divider circuit provides the input voltage and whereby the resistance of the source memristor is copied into the resistance of the target memristor.

13. A method comprising: Receives quantity as input; applying a series of voltage pulses to the memristor using a voltage generator to gradually change the resistance of the memristor; counting, using a counter, a number of voltage pulses applied to the memristor, and providing an output to cause a voltage generator to cease applying further voltage pulses and instead cause the voltage generator to apply a constant holding voltage to the memristor once the number of voltage pulses applied to the memristor equals the number received as input; and An electrical value based on the resulting resistance of the memristor is output.

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