Switched Capacitor Integrator Circuit with Reference, Offset Cancellation, and Differential-to-Single-Ended Conversion

Abstract

A dual integrator system (200) includes two integrators (220A-B), an output stage (270), and a switching network (240A-D). A first integrator and a second integrator receive differential Hall sensor signals (205, 210) and a reference voltage (210). The first integrator outputs a first integrator signal (225A) based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal (225B) based on the differential Hall sensor signal and the reference voltage. The first integrator includes a first offset cancellation feedback loop (235A), and the second integrator includes a second offset cancellation feedback loop (235B). The switching network is coupled to the first integrator and the second integrator and to the output stage, and alternately couples the first integrator and the second integrator to the output stage. In some embodiments, the first integrator and the second integrator each perform a reset operation, a sampling operation, an integration operation, a differential-to-single-ended conversion operation, and a hold operation.

Description

Background Art

[0001] By "rotating" the Hall sensor (e.g., by spatially rotating the Hall bias current to all Hall terminals), the large offset errors that plague Hall sensors used for magnetic field or current sensing can be significantly reduced. The Hall sensor output signal is averaged by a switching network and an integrator. In some embodiments where the Hall sensor output signal is continuously sampled, a sample and hold circuit and an output amplifier with a reference resistor network introduce a reference voltage.

[0002] Because the time required to transfer the integrator output to the sample-and-hold circuit and the integrator reset time limit the possible rotation speed of the Hall sensor, some signal chains include two integrators in parallel, so that one integrator holds the signal while the second integrator resets and integrates the Hall sensor output signal. However, the resulting signal chain occupies a large area on the semiconductor die and consumes a lot of power. In addition, the reference resistor network presents a relatively low resistance to the reference input, which makes it difficult to multiplex other functions to the reference pin for testing during the manufacturing process. The low input resistance also requires a low-impedance driver on the reference pin. Summary of the Invention

[0003] In one example, a circuit includes a switched capacitor module, an integrator, and two feedback loops. The switched capacitor module is configured to receive a positive differential input signal and a negative differential input signal and includes a switching network, a first sampling capacitor, and a second sampling capacitor. The integrator includes a positive input coupled to the first sampling capacitor and a negative input coupled to the second sampling capacitor, as well as a positive output and a negative output. The first feedback loop includes a first switch coupled between the positive input and the negative output of the integrator, a second switch coupled to the positive output, and a first feedback capacitor coupled between the second switch and the negative output. The second feedback loop includes a third switch coupled between the negative input and the positive output of the integrator, a fourth switch coupled to the negative input, and a second feedback capacitor coupled between the fourth switch and the positive output.

[0004] In some embodiments in the reset mode of operation, the switch network disconnects the first sampling capacitor from the positive differential input signal and disconnects the second sampling capacitor from the negative differential input signal, and couples the first sampling capacitor and the second sampling capacitor to each other. The first switch, the second switch, the third switch, and the fourth switch are closed. In some embodiments in the sampling mode of operation, the first switch and the third switch are closed, and the second switch and the fourth switch are open. The switch network provides the positive differential input signal to the first sampling capacitor and the negative differential input signal to the second sampling capacitor, and decouples the first sampling capacitor and the second sampling capacitor from each other.

[0005] In some embodiments in the integrating mode of operation, the first and third switches are open, and the second and fourth switches are closed. The switch network disconnects the first sampling capacitor from the positive differential input signal and the second sampling capacitor from the negative differential input signal, and couples the first and second sampling capacitors to each other.

[0006] In some examples, the circuit further includes five additional switches and an output stage. A fifth switch is coupled between the first feedback capacitor and the negative output. A sixth switch is configured to couple the second feedback capacitor to the positive output or to the positive input. A seventh switch is coupled between the negative output and the positive output. An eighth switch is coupled between the negative output and the input of the output stage. A ninth switch is configured to couple the first feedback capacitor to the output of the output stage or to a resistor, which is further coupled to the output of the output stage.

[0007] In some examples in a differential-to-single-ended conversion operating mode, the switch network disconnects the first sampling capacitor and the second sampling capacitor from the positive differential input signal and the negative differential input signal and couples the first sampling capacitor and the second sampling capacitor to each other. The first switch, the fifth switch, and the eighth switch are open, and the second switch, the third switch, the fourth switch, and the seventh switch are closed. The sixth switch couples the second feedback capacitor to the positive input, and the ninth switch couples the first feedback capacitor to the resistor.

[0008] In some embodiments, the circuit further includes a compensation capacitor coupled to the positive input and a tenth switch configured to couple the compensation capacitor to the output of the output stage or to ground. In the differential-to-single-ended conversion operating mode, the tenth switch couples the compensation capacitor to the output of the output stage. In operating modes other than the differential-to-single-ended conversion operating mode, the tenth switch couples the compensation capacitor to ground.

[0009] In some examples in the hold mode of operation, the switch network disconnects the first sampling capacitor and the second sampling capacitor from the positive differential input signal and the negative differential input signal, and couples the first sampling capacitor and the second sampling capacitor to each other. The first switch, the fifth switch, and the seventh switch are open, and the second switch, the third switch, the fourth switch, and the eighth switch are closed. The sixth switch couples the second feedback capacitor to the positive input, and the ninth switch couples the first feedback capacitor to the output of the output stage. In some embodiments, the resistor is a first resistor, and the output stage includes a buffer, a capacitor, and two resistors. The buffer has a positive input and a negative input, and an output of the output stage. The capacitor is coupled to the positive input of the buffer, and the eighth switch is coupled to the positive input of the buffer. The second resistor is coupled to the negative input of the buffer, and the third resistor is coupled between the negative input and the output of the buffer.

[0010] In some embodiments, the circuit includes a second switched capacitor module configured to receive a reference voltage. The second switched capacitor module includes a second switching network configured to receive the reference voltage and two capacitors. The second switching network is coupled between the positive and negative inputs and the negative output. In some embodiments, the circuit includes an offset cancellation switched capacitor module including two capacitors and a second switching network coupled between the positive and negative inputs and the positive and negative outputs. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0012] Figure 1 Shown is a Hall sensor signal chain with dual integrators.

[0013] Figures 2A-2B A block diagram of a dual integrator system is shown, along with a timing diagram illustrating the operating modes of the two integrators.

[0014] Figures 3A-3C For example, Figure 2A The operating modes of the integrators and the corresponding integrator configurations in the dual integrator system are shown.

[0015] Figure 4 Shown for example Figure 2A The integrator input stage of the dual integrator system shown has a reference voltage input.

[0016] Figure 5 Shown for example Figure 2A The integrator input stage of the dual integrator system shown has a reference voltage input and an offset feedback loop.

[0017] Figures 6A-6B Integrator configurations are shown for the differential to single-ended conversion mode of operation and the hold mode of operation.

[0018] Figure 7 An integrator system with reduced parasitic and transient errors during a differential to single-ended conversion mode of operation is shown. DETAILED DESCRIPTION

[0019] In the described dual-integrator system, a first integrator and a second integrator are each configured to receive a differential Hall sensor signal and a reference voltage. A switching network coupled to the first and second integrators and to the output stage is configured to alternately couple the first and second integrators to the output stage. When the first integrator performs a hold operation, the switching network couples the first integrator to the output stage and decouples the second integrator from the output stage. When decoupled from the output stage, the second integrator performs a reset operation, a sampling operation, an integration operation, and a differential-to-single-ended conversion operation.

[0020] Each integrator includes an offset cancellation feedback loop including a switched capacitor module coupled to an input and an output of the integrator. Each integrator also includes an additional switched capacitor module coupled to an input and an output of the integrator configured to receive a reference voltage. In an example in which a predetermined number N of sampling and integration operations are performed, the capacitances of the offset cancellation feedback loop and the additional switched capacitor module are selected such that only a 1 / N portion of the reference voltage or the offset voltage is integrated in each integration operation.

[0021] Figure 1 A Hall sensor signal chain 100 with dual integrators is shown. Signal chain 100 includes a Hall sensor 105, a Hall bias generator 110, a rotation controller 115, an amplifier stage 120, chopper integrators 140A-B, a stage 150 for sample and hold (S / H) and differential to single-ended conversion, and an output amplifier stage 160. Hall sensor 105 is coupled to rotation controller 115, which receives the Hall bias current from Hall bias generator 110. The output of rotation controller 115 is provided to amplifier stage 120. Amplifier stage 120 includes a first chopper 125, an amplifier 130, and a second chopper 135. The chopped and amplified output signal from amplifier stage 120 is provided to both chopper integrators 140A-B.

[0022] As described in the background, the time required to transfer the integrator output from either chopper integrator 140A or 140B to stage 150 limits the speed at which Hall sensor 105 can rotate. Switching network 145A-B switches between the two chopper integrators 140A-B, alternating which integrator is used to integrate the signal and which integrator is used to transfer the integrator output to stage 150. S / H and conversion stage 150 samples and holds the integrator output signal and converts it from a differential signal to a single-ended signal. Output amplifier stage 160 receives reference voltage Vref 165 and includes a reference resistor network. Signal Vout 170 is output from amplifier stage 160.

[0023] At least the amplifiers in integrators 140A-B must be chopped or include auto-zero stabilization to reduce the offset voltage introduced by the amplifiers. As shown in signal chain 100, amplifier stage 120 also includes a chopper to reduce the offset voltage introduced by amplifier 130. The chopping switches for the amplifiers and the reference resistor network in amplifier stage 160 occupy a large area on the semiconductor die and consume a lot of power. In addition, the reference resistor network causes the input pin of Vref 165 to present a low input resistance, which makes it difficult to multiplex other functions to the pin for testing during the manufacturing process. The fixed input resistance also requires a low impedance driver on the pin.

[0024] Figures 2A-2BA block diagram of a dual integrator system 200 is shown, along with a diagram illustrating the operating modes of the two integrators. For ease of explanation, reference is made to Figure 1 The signal chain 100 shown depicts a block diagram of a dual integrator system 200. Figure 2A , dual integrator system 200 includes two integrators 220A-B, each of which receives a differential input signal from amplifier stage 120 in signal chain 100, where Vin_p 205 represents the positive differential input signal and Vin_n 210 represents the negative differential input signal. Integrators 220A-B also each receive a reference voltage Vref 215. Integrator 220A includes a feedback loop to compensate for a voltage offset Voffset 235A introduced by integrator 220A. Similarly, integrator 220B includes a feedback loop to compensate for a voltage offset Voffset 235B introduced by integrator 220B.

[0025] Integrator 220A has two output signals: Vout_n 225A and Vout_p 230A. When switch 240A is closed, Vout_n 225A is provided to output stage 270. Switch 240A can be open when integrator 220A performs a reset function, a sample and integrate (S / I) function, and a differential to single-ended (D2S) conversion function, and closed when integrator 220A performs a hold function. Similarly, integrator 220B has two output signals: Vout_n 225B and Vout_p 230B. When switch 240B is closed, Vout_n 225B is provided to output stage 270. Integrators 220A-B alternate which integrator output is provided to output stage 270, as will be described with reference to FIG. Figure 2B Further described herein.

[0026] Integrators 220A-B also output feedback voltages Vfeedback 265A-B, respectively, which are coupled to the output of output stage 270 via switches 240C-D, respectively. When one of the integrators is in the hold mode of operation, the corresponding switch 240C or 240D couples the corresponding feedback voltage Vfeedback 265A or 265B to the output of output stage 270. When the integrator is not in the hold mode of operation, switches 240C-D disconnect Vfeedback 265A-B from the output of output stage 270. Output stage 270 includes a buffer 245, which provides the required output drive capability of system 200 and outputs a single-ended output signal Vout 260. Outputs Vout_n 225A-B are provided to a first input of buffer 245. Resistor 250 is coupled to a second input of buffer 245 and to ground. A second resistor 255 is coupled between the second input and the output of buffer 245.

[0027] exist Figure 2B , the figure illustrates an offset mode of operation of integrators 220A-B. Initially, integrator 220A performs hold function 275A and switch 240A is closed, coupling Vout_n 225A to output stage 270. While integrator 220A performs hold function 275A and switch 240A is closed, switch 240B opens, disconnecting integrator 220B from output stage 270. Integrator 220B performs reset function 280B, S / I function 285B, and D2S function 290B. In response to integrator 220B completing D2S function 290B, switch 240A opens, disconnecting integrator 220A from output stage 270, and switch 240B closes, coupling Vout_n 225B to output stage 270. Integrator 220B performs hold function 275B, while integrator 220A performs reset function 280A, S / I function 285A, and D2S function 290A. Integrators 220A-B may sample and integrate differential input signals Vin_p 205 and Vin_n 210 any suitable number of times N during S / I functions 285A-B. N may be selected based on the number of input signal phases.

[0028] Figures 3A-3C For example, Figure 2A The integrator operating modes and corresponding integrator configurations of the integrators 220A-B are shown. Figure 3A Integrator configuration 300A corresponding to a reset mode of operation is shown. Integrator 300 includes a switching network 320, input sampling capacitors 335A-B, integrator 340, output feedback capacitors 350A-B, and switches 345A-B and 355A-B. Switching network 320 includes switches 322, 328, and 330.

[0029] Switch 322 is coupled between an input node configured to receive the positive input differential signal Vin_p 305 and input sampling capacitor 335A and is open in the reset mode of operation. Switch 328 is coupled between an input node configured to receive the negative input differential signal Vin_n 310 and input sampling capacitor 335B and is open in the reset mode of operation. Switch 330 is coupled between input sampling capacitors 335A-B and is closed in the reset mode of operation.

[0030] Input sampling capacitor 335A is further coupled to the positive input of amplifier 340, and input sampling capacitor 335B is further coupled to the negative input of amplifier 340. Switch 355A is coupled between the positive input and negative output of amplifier 340. Switch 345A is coupled between the positive input of amplifier 340 and output feedback capacitor 350A, which is further coupled to the negative output of amplifier 340. Integrator output signal Vout_n 360 is available at the negative output of amplifier 340. Switch 355B is coupled between the negative input and positive output of amplifier 340. Switch 345B is coupled between the negative input of amplifier 340 and output feedback capacitor 350B, which is further coupled to the positive output of amplifier 340. Integrator output signal Vout_p 370 is available at the positive output of amplifier 340.

[0031] Configuration 300A resets integrator 300 by shorting its input sampling capacitors 335A-B and output feedback capacitors 350A-B so that there is no voltage across each of capacitors 335A-B and 350A-B. Switches 345A-B and 355A-B are closed during the reset mode of operation to short the output feedback capacitors 350A-B. Switch 330 is closed to short the input sampling capacitors 335A-B.

[0032] Figure 3B Integrator configuration 300B corresponding to a sampling mode of operation is shown. In configuration 300B, switches 322 and 328 are closed. Switch 330 is open, disconnecting input sampling capacitors 335A-B from each other. Switches 355A-B remain closed, but switches 345A-B are open, disconnecting output feedback capacitors 350A-B from the inputs of amplifier 340. When the integrator receives differential input signals Vin_p 305 and Vin_n 310, input sampling capacitors 335A-B store charge, such that at the end of the sampling operation, a voltage Vinput is present across each of input sampling capacitors 335A-B. Input sampling capacitor 335A has a positive voltage Vinput across it, and input sampling capacitor 335B has a negative voltage Vinput across it. Because switches 345A-B are open, output feedback capacitors 350A-B do not store charge and, in this example, have no voltage across them.

[0033] Figure 3CIntegrator configuration 300C is shown for an integrating mode of operation. In configuration 300C, switches 322 and 328 are open. Switch 330 is closed, connecting input sampling capacitors 335A-B together. Switches 345A-B are closed, connecting output feedback capacitors 350A-B to the input of amplifier 340 and to input sampling capacitors 335A-B. Switches 355A-B are open. The charge stored in input sampling capacitors 335A-B is transferred to output feedback capacitors 350A-B, such that at the end of the integrating operation, there is no voltage Vinput across input sampling capacitors 335A-B and a voltage Vo across output feedback capacitors 350A-B. A negative voltage Vo is present across output feedback capacitor 350A, and a positive voltage Vo is present across output feedback capacitor 350B.

[0034] Integrator 300 can perform any appropriate number N of S / I operations depending on the number of Hall rotation phases. At the start of the Nth sampling operation, for example, input sampling capacitors 335A-B store no charge and have no voltage across them. Output feedback capacitors 350A-B have accumulated charge, resulting in a voltage of (N-1)Vo across them. At the end of the Nth sampling operation, voltage Vinput is present across input sampling capacitors 335A-B. At the end of the Nth integration operation, voltage (N)Vo is present across output feedback capacitors 350A-B.

[0035] Figure 4 An integrator configuration 400 is shown with a reference voltage input. For ease of illustration, reference Figures 3A-3C Configuration 400 is described for the integrator 300 shown in configurations 300A-C. Switched capacitor module 405 includes the switch network 320 and input sampling capacitors 335A-B in integrator 300. A second switched capacitor module 410 includes a switch network 420 and capacitors 435A-B. Switch network 420 includes switches 422, 428, and 430. Switch 422 is coupled between an input node configured to receive reference voltage Vref 415 and capacitor 435A. Switch 428 is coupled between the negative output of amplifier 340 and capacitor 435B. Switch 430 is coupled between capacitors 435A-B.

[0036] Capacitor 435A is further coupled to the positive input of amplifier 340, and capacitor 435B is further coupled to the negative input of amplifier 340. Integrator 400 samples reference voltage Vref 415 relative to the common-mode voltage Vcm of output signal Vout_n 360. In contrast, if integrator 400 samples Vref 415 relative to ground, the integrator output would quickly reach the power rail voltage due to the limited integrator input swing. Alternatively, by sampling Vref 415 relative to Vcm of Vout_n 360, integrator 400 can increase the swing voltage of the Hall signal.

[0037] The capacitance values of capacitors 435A-B are selected based on the number N of S / I operations and the number of Hall rotation phases. For example, integrator 400 performs four S / I operations before continuing the hold operation. The capacitance values of capacitors 435A-B are selected to be one-fourth the capacitance value of output feedback capacitors 350A-B. For example, the capacitance value of capacitors 335A-B is twelve times the capacitance C (12C), the capacitance value of capacitors 350A-B is 4C, and the capacitance value of capacitors 435A-B is C. Output Vout_n 360 can be expressed as:

[0038]

[0039] Wherein Vdd represents the power supply voltage.

[0040] During each integration, the integrator 400 adds one-quarter of the difference between Vref 415 and Vout_n 360, Vdd / 2, so that after four integration operations, the entire difference between Vref 415 and Vdd / 2 is summed. By incorporating the reference voltage Vref 415 into the input of the integrator 340, the reference resistor network in the output amplifier stage 160 can be eliminated, thereby reducing the area required for the integrator 400 on the semiconductor die. In addition, increasing the input impedance of the reference voltage Vref 415 eliminates the need for another amplifier to provide low-impedance drive on the pin, which simplifies the integrator circuit.

[0041] Figure 5 An integrator configuration 500 with integrator offset cancellation is shown. For ease of illustration, reference is made to Figures 3A-3C The integrator 300 shown in configuration 300A-C and Figure 4The illustrated integrator 400 depicts configuration 500. Switched capacitor module 515 includes a switch network 520 and capacitors 535A-B. Switch network 520 includes switches 522, 528, and 530. Switch 522 is coupled between the positive output of amplifier 340 and capacitor 535A. Switch 528 is coupled between the negative output of amplifier 340 and capacitor 535B. Switch 530 is coupled between capacitors 535A-B. Capacitor 535A is further coupled to the positive input of amplifier 340, and capacitor 535B is further coupled to the negative input of amplifier 340.

[0042] refer to Figure 4 The same strategy described for integrator 400 in Figure 5 to incorporate reference voltage 415 is used to cancel the offset introduced by amplifier 340. In each integration step, integrator 500 adds a portion of the amplifier offset so that after the NS / Ith operation, the entire amplifier offset is incorporated and cancels the offset introduced by amplifier 340. By canceling the offset in this manner, the chopping switches and auto-zero stabilization circuitry can be eliminated from integrator 400, which reduces the area and power consumption of integrator 500.

[0043] Figures 6A-6B The integrator system configuration for differential to single-ended conversion mode of operation and hold mode of operation is shown. Figures 3A-3C The integrator 300 shown in configuration 300A-C describes Figures 6A-6B Although not included in the scoring system 600 for ease of illustration, Figure 4 The switched capacitor module 410 and Figure 5 The illustrated switched capacitor module 515 may be incorporated into the integrator system 600 without significant change in operation. Figure 6A An integrator system configuration 600A corresponding to a D2S mode of operation is shown, and Figure 6B An integrator system configuration 600B corresponding to a hold mode of operation is shown.

[0044] Integrator system 600 includes Figures 3A-3C Integrator 300 is shown, along with switches 605, 610, 620, 625, and 630, capacitor 635, resistors 615, 645, and 650, and buffer 640. Switch 605 is coupled to capacitor 350B and switches between the positive output and the positive input of amplifier 340. Switch 610 is coupled between capacitor 350A and the negative output of amplifier 340. Switch 620 is coupled to capacitor 350A and switches between resistor 615 and the output of buffer 640. Resistor 615 is further coupled to the output of buffer 640.

[0045] Switch 625 is coupled between the positive and negative outputs of amplifier 340. Switch 630 is coupled between the negative output of amplifier 340 and the positive input of buffer 640. Capacitor 635 is coupled to the positive input of buffer 640 and to ground. Resistor 645 is coupled to the negative input of buffer 640 and to ground. Resistor 650 is coupled to the negative input and output of buffer 640. A single-ended output signal Vout 660 is available from the output of buffer 640.

[0046] exist Figure 6A Integrator system configuration 600A corresponds to the D2S mode of operation. In configuration 600A, switches 322 and 328 are open, and switch 330 is closed. Switch 345A is closed, coupling capacitor 350A to the positive input of amplifier 340, and switch 355A is open. Switch 345B is closed, coupling capacitor 350B to the negative input of amplifier 340, and switch 605 couples capacitor 350B to the positive input of amplifier 340. Switch 355B is closed, coupling the positive and negative outputs of amplifier 340. Switch 610 is open, disconnecting capacitor 350A from the negative output of amplifier 340. Switch 620 couples capacitor 350A to resistor 615. Switch 625 is closed, coupling the positive and negative outputs of amplifier 340. Switch 630 is open, disconnecting the negative output of amplifier 340 from the positive input of buffer 640.

[0047] Configuration 600A redistributes the charge stored in output feedback capacitors 350A-B to achieve the full voltage swing at a single output node. After the final integration operation, integrator 600A couples output feedback capacitor 350B to the input of amplifier 340. The negative input and positive output of amplifier 340 are coupled together in a unity-gain feedback configuration. The closed-loop feedback pushes the charge stored on output feedback capacitor 350B to output feedback capacitor 350A. Because the output feedback capacitors have approximately the same capacitance and store approximately the same amount of charge, the voltage across output feedback capacitor 350A is approximately doubled to 2Vo.

[0048] To reduce variations in Vout_p 370 and Vout_n 360 during the transition from differential to single-ended output mode, switch 625 shorts the positive and negative outputs of amplifier 340, and switch 630 disconnects the negative output of amplifier 340 from the positive input of buffer 640. When switch 630 is open, capacitor 635 temporarily holds the value of output signal Vout 660. Resistor 615 reduces variations in output signal Vout 660 while charge is transferred from output feedback capacitor 350B to output feedback capacitor 350A. By incorporating the D2S functionality into integrator system 600, differential-to-single-ended conversion stage 150 and its amplifier can be eliminated from the integrator system, further reducing the area and power used by integrator system 600.

[0049] exist Figure 6B Integrator system configuration 600B corresponds to a hold mode of operation. In configuration 600B, switches 322 and 328 are open, and switch 330 is closed. Switch 345A is closed, coupling capacitor 350A to the positive input of amplifier 340, and switch 355A is open. Switch 345B is closed, coupling capacitor 350B to the negative input of amplifier 340, and switch 605 couples capacitor 350B to the positive input of amplifier 340. Switch 355B is closed, coupling the positive and negative outputs of amplifier 340. Switch 610 is open, disconnecting capacitor 350A from the negative output of amplifier 340. Switch 620 couples capacitor 350A to the output of buffer 640. Switch 625 is open, disconnecting the positive and negative outputs of amplifier 340. Switch 630 is closed, coupling the negative output of amplifier 340 to the positive input of buffer 640.

[0050] After completing the charge transfer from the output feedback capacitor 350B to the capacitor 350A during the D2S mode of operation, the integrator system 600 is reconfigured for the hold mode of operation in which the single-ended integrator output from the amplifier 340 is coupled to the input of the buffer 640 to hold the output signal. For the example with four S / I operations, the output signal Vout_n 360 from the amplifier 340 can be expressed as:

[0051]

[0052] Wherein Vdd represents the power supply voltage, Cs represents the capacitance of the input sampling capacitor 335A, and Cf represents the capacitance of the output feedback capacitor 350A.

[0053] The output signal Vout 660 can be expressed as:

[0054]

[0055] For the example where the capacitance of capacitors 335A-B is twelve times the capacitance C (12C), the capacitance of capacitors 350A-B is 4C, and the capacitance of capacitors 435A-B is C, the output signal Vout 660 may be expressed as:

[0056]

[0057] Figure 7 An integrator system 700 with parasitic capacitance compensation is shown. For ease of illustration, reference is made to Figures 3A-3C The integrator 300 and Figures 6A-6B The integrator 600 is shown to describe the integration system 700. Although not included in the integration system 700 for ease of explanation, Figure 4 The switched capacitor module 410 and Figure 5 The illustrated switched capacitor module 515 can be incorporated into the integrator system 700 without significant changes in operation. When the integrator system 700 operates in D2S mode and the output feedback capacitor 350B is coupled to the positive and negative inputs of the amplifier 340, changes in the bottom plate voltage of the capacitor 350B may cause charge loss due to parasitic capacitance associated with the bottom plate, represented as capacitor 770.

[0058] To compensate for parasitic capacitance, represented as capacitor 770, in the D2S mode of operation, a compensation capacitor 775 is coupled between the positive input of amplifier 340 and the output of buffer 640 via switch 780. The output signal Vout 790 from buffer 640 charges compensation capacitor 775, which reduces parasitic capacitance during the D2S mode of operation and transient errors in Vout 790. When not in the D2S mode of operation, switch 780 disconnects compensation capacitor 775 from the output of buffer 640 and connects it to ground.

[0059] The term "coupled" is used throughout this specification. The term can encompass any connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then device A is coupled to device B in the first instance, or in the second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not substantially alter the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A.

[0060] Modifications to the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A method for operating a dual integrator system, comprising: decoupling the first integrator from the output buffer; coupling a second integrator to the output buffer; maintaining a first output signal based on a first Hall sensor input signal via the second integrator and the output buffer; resetting the first integrator; Performing sampling and integration operations on the second Hall sensor input signal through the first integrator to generate a differential signal; converting the first integrator from a differential mode to a single-ended mode to convert the differential signal into a second output signal; decoupling the second integrator from the output buffer in response to the first integrator being switched to the single-ended mode; coupling the first integrator to the output buffer; as well as The second output signal is maintained based on the second Hall sensor input signal by the first integrator and the output buffer.

2. The method according to claim 1 , further comprising performing the sampling operation and the integration operation on the second Hall sensor input signal a predetermined number N of times by the first integrator, wherein: The predetermined number N is selected based on the number of Hall rotation phases N in the second Hall sensor input signal, and Converting the first integrator from the differential mode to the single-ended mode includes converting the first integrator in response to the first integrator performing the sampling operation and the integration operation for an Nth time.

3. The method of claim 2 , wherein performing the sampling operation and the integration operation on the second Hall sensor input signal a predetermined number N of times by the first integrator further comprises performing the sampling operation and the integration operation on a portion of a reference voltage signal a predetermined number N of times. 4 . The method of claim 3 , wherein the partial reference voltage signal comprises a 1 / N portion of a reference voltage signal, such that the differential signal comprises the 1 / N portion of the reference voltage signal integrated N times. 5 . The method of claim 2 , wherein performing the sampling operation and the integration operation on the second Hall sensor input signal a predetermined number N of times by the first integrator further comprises performing the sampling operation and the integration operation on a partial offset voltage signal a predetermined number N of times. 6 . The method of claim 5 , wherein the partial offset voltage signal comprises a 1 / N portion of an offset voltage associated with the first integrator, such that the differential signal comprises the 1 / N portion of the offset voltage integrated N times.

7. A dual integrator system comprising: a first integrator configured to receive a differential Hall sensor signal and a reference voltage, wherein the first integrator includes a first offset cancellation feedback loop and is further configured to output a first integrator signal based on the differential Hall sensor signal and the reference voltage; a second integrator configured to receive the differential Hall sensor signal and the reference voltage, wherein the second integrator includes a second offset cancellation feedback loop and is further configured to output a second integrator signal based on the differential Hall sensor signal and the reference voltage; Output stage; as well as A switching network is coupled to the first and second integrators and the output stage and is configured to alternately couple the first and second integrators to the output stage.

8. The system of claim 7 , wherein the first integrator is further configured to perform a reset operation, a sampling operation, an integration operation, a differential-to-single-ended conversion operation, and a hold operation, and wherein the second integrator is further configured to perform the reset operation, the sampling operation, the integration operation, the differential-to-single-ended conversion operation, and the hold operation.

9. The system of claim 8, wherein: The switching network is configured to decouple the second integrator from the output stage and couple the first integrator to the output stage in response to the first integrator performing the hold operation, and The second integrator is configured to perform the reset operation, the sampling operation, the integration operation, and the differential-to-single-ended conversion operation in response to being decoupled from the output stage.

10. The system of claim 9, wherein the second integrator is configured to perform the sampling operation and the integration operation a predetermined number N of times before performing the differential-to-single-ended conversion operation, and wherein the predetermined number N is selected based on the number of Hall rotation phases N in the differential Hall sensor signal. 11 . The system of claim 10 , wherein the second offset cancellation feedback loop comprises a switched capacitor module coupled to an input of the second integrator and an output of the second integrator.

12. The system of claim 11, wherein a capacitance of the switched capacitor module is selected based on the predetermined number N such that the capacitance of the switched capacitor module is a 1 / Nth fraction of an offset associated with the second integrator.

13. The system of claim 10, wherein the second integrator further comprises a switched capacitor module coupled to an input of the second integrator configured to receive the reference voltage and to an output of the second integrator.

14. The system of claim 13, wherein a capacitance of the switched capacitor module is selected based on the predetermined number N such that the capacitance of the switched capacitor module is a 1 / Nth fraction of the reference voltage.

15. A circuit comprising: a switched capacitor module configured to receive a positive differential input signal and a negative differential input signal, comprising a switching network, a first sampling capacitor, and a second sampling capacitor; an integrator having a positive input coupled to the first sampling capacitor, a negative input coupled to the second sampling capacitor, a positive output, and a negative output; The first feedback loop includes: a first switch coupled between the positive input and the negative output; a second switch coupled to the positive input; a first feedback capacitor coupled between the second switch and the negative output; and The second feedback loop includes: a third switch coupled between the negative input and the positive output; a fourth switch coupled to the negative input; and a second feedback capacitor coupled between the fourth switch and the positive output; a fifth switch coupled between the first feedback capacitor and the negative output; a sixth switch configured to couple the second feedback capacitor to the positive output or to the positive input; a seventh switch coupled between the negative output and the positive output; Output stage; an eighth switch coupled between the negative output and an input of the output stage; and A ninth switch is configured to couple the first feedback capacitor to an output of the output stage or to a resistor, wherein the resistor is further coupled to the output of the output stage.

16. The circuit of claim 15 , wherein in a reset mode of operation: the switching network disconnecting the first sampling capacitor and the second sampling capacitor from the positive differential input signal and the negative differential input signal and coupling the first sampling capacitor and the second sampling capacitor to each other; and The first switch, the second switch, the third switch, and the fourth switch are closed.

17. The circuit of claim 15 , wherein in a sampling mode of operation: The first switch and the third switch are closed; The second switch and the fourth switch are opened; and The switching network provides the positive differential input signal to the first sampling capacitor and the negative differential input signal to the second sampling capacitor, and decouples the first and second sampling capacitors from each other.

18. The circuit of claim 15, wherein in an integrating mode of operation: The first switch and the third switch are disconnected; The second switch and the fourth switch are closed; and The switch network disconnects the first and second sampling capacitors from the positive and negative differential input signals and couples the first and second sampling capacitors to each other.

19. The circuit of claim 15 , wherein in a differential to single-ended conversion mode of operation: the switching network disconnecting the first sampling capacitor and the second sampling capacitor from the positive differential input signal and the negative differential input signal and coupling the first sampling capacitor and the second sampling capacitor to each other; The first switch, the fifth switch, and the eighth switch are disconnected; The second switch, the third switch, the fourth switch and the seventh switch are closed; the sixth switch coupling the second feedback capacitor to the positive input; and The ninth switch couples the first feedback capacitor to the resistor.

20. The circuit of claim 19, further comprising: a compensation capacitor coupled to the positive input; as well as a tenth switch configured to couple the compensation capacitor to the output of the output stage or to ground, wherein in the differential to single-ended conversion mode of operation, the tenth switch couples the compensation capacitor to the output of the output stage, and wherein in an operating mode other than the differential to single-ended conversion mode of operation, the tenth switch couples the compensation capacitor to ground.

21. The circuit of claim 15, wherein in the hold mode of operation: the switching network disconnecting the first sampling capacitor and the second sampling capacitor from the positive differential input signal and the negative differential input signal and coupling the first sampling capacitor and the second sampling capacitor to each other; The first switch, the fifth switch, and the seventh switch are disconnected; The second switch, the third switch, the fourth switch and the eighth switch are closed; the sixth switch coupling the second feedback capacitor to the positive input; and The ninth switch couples the first feedback capacitor to the output of the output stage.

22. The circuit of claim 15, wherein the resistor comprises a first resistor, and wherein the output stage comprises: a buffer having a positive input, a negative input, and said output of said output stage; a capacitor coupled to the positive input of the buffer, wherein the eighth switch is coupled to the positive input of the buffer; a second resistor coupled to the negative input of the buffer; as well as A third resistor is coupled between the negative input and the output of the buffer.

23. The circuit of claim 15, wherein: The switched capacitor module includes a first switched capacitor module; The switch network includes a first switch network; and The circuit further includes a second switched capacitor module configured to receive a reference voltage, the second switched capacitor module including: a second switching network configured to receive the reference voltage and coupled between the positive input and the negative input and the negative output; a first capacitor; and Second capacitor.

24. The circuit of claim 15, wherein: The switched capacitor module includes a first switched capacitor module; The switch network includes a first switch network; and The circuit further includes a second switched capacitor module, the second switched capacitor module including: a second switching network coupled between the positive and negative inputs and the positive and negative outputs; a first capacitor; and Second capacitor.

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