A performance improvement method for CPU context switching

Abstract

The present application discloses a method for improving the performance of CPU context switching. The method includes baseline modeling of common processes running in an operating system; data analysis of the process switching of current concern and the baseline model, and conflict avoidance of the process switching of current concern; data iteration based on the principle of not affecting the common process baseline model, constructing an optimized scheduling algorithm for CPU context switching, and calculating the optimal time slice in real time; adjusting the CPU context switching in real time based on the optimal time slice. The technical solution of the present application can dynamically adjust the optimal time slice of the process in real time, greatly reducing the time and frequency of CPU context switching, and improving the performance of the CPU.

Description

Technical Field

[0001] The present application relates to the field of industrial control communication technology, and in particular to a method for improving the performance of CPU context switching. Background Art

[0002] Today's computer operating systems, such as Windows and Linux, are all multi-tasking operating systems. That is, multiple tasks can be executed at the "same time" without serial waiting. For example, you can run a player to listen to music while running WeChat and QQ to chat with friends. This kind of multi-tasking parallelism is not really running at the same time, but the CPU quickly switches between different execution tasks, giving people an "illusion".

[0003] The essence of this multi-tasking parallel work is that the CPU divides time into extremely small time slices, which can be accurate to the nanosecond level. Multiple tasks to be executed are assigned fixed time slices by the CPU and are executed sequentially. For example, the music player is executed in time slice A. After the time slice is reached, the music player task is suspended and other tasks are executed instead. It should be emphasized that before suspending the task, the CPU must save the resources executed by the music player so that the music player can know where to execute when it is executed again, in layman's terms, where the music is played. The more tasks are performed, the more frequently the CPU switches context, and the more CPU performance is lost.

[0004] Existing operating systems use and schedule CPUs in a fixed time slice format, that is, they allocate time slices at fixed intervals according to the clock cycle. When the current task time slice expires, it is suspended and polled again to be executed, and the cycle repeats. Therefore, the allocation of time slices is rigid, which wastes a lot of precious CPU resources. This method causes more and more losses when there are many parallel tasks. Summary of the invention

[0005] The present invention aims to optimize the context switching frequency of the computer core processor CPU, thereby improving the execution efficiency of the CPU. Based on the traditional CPU context switching method, data statistical analysis and linear modeling are integrated to control the CPU context switching within an intelligent and controllable range, thereby achieving the "optimal context switching ratio", saving precious CPU resources, and thus improving the performance of the CPU.

[0006] The present application specifically provides a method for improving CPU context switching performance, including:

[0007] Baseline modeling of common processes running in an operating system;

[0008] Perform data analysis on the process switching of current concern and the baseline model, and perform conflict avoidance on the process switching of current concern;

[0009] Based on the principle of not affecting the common process baseline model, data iteration is performed to build an optimized scheduling algorithm for CPU context switching and calculate the optimal time slice in real time;

[0010] Adjust CPU context switching in real time based on the optimal time slice.

[0011] In the method for improving the performance of CPU context switching as described above, the common processes running in the operating system, that is, the native operating system dependencies, the program switching time and the switching frequency used are recorded to form a baseline model of time and frequency.

[0012] As described above, in the method for improving the performance of CPU context switching, when performing data analysis on the process switching of current concern, it is necessary to compare the process switching of current concern with the baseline model to ensure that the CPU time slice usage of the original process is not affected during the data analysis.

[0013] The above-mentioned method for improving the performance of CPU context switching, wherein, under the condition of ensuring that the baseline model of the common process is not affected, the optimized scheduling algorithm for CPU context switching is obtained through data iteration as follows:

[0014]

[0015] Among them, Time_Slice is the calculated optimal time slice, k is the baseline modeling time slice of the public process, and b n is the CPU time slice when the current process performs voluntary context switching for the nth time, b n-1 It is the CPU time slice for the current process to perform voluntary context switching for the n-1th time.

[0016] As described above, the performance improvement method for CPU context switching, wherein, for a process that voluntarily switches contexts, it is necessary to suspend the process, store the current running status data of the process, and appropriately suppress it. The calculated optimal time slice is relatively long. The time interval for the next time the process obtains the right to use the CPU is determined based on the calculated optimal time slice. After the optimal time slice, the right to use the CPU is granted to the process, thereby ensuring that the process that voluntarily switches contexts will not occupy CPU resources for a long time.

[0017] In the above-mentioned method for improving the performance of CPU context switching, voluntary context switching refers to context switching caused by the process being unable to obtain required resources.

[0018] In the method for improving the performance of CPU context switching as described above, appropriate priority needs to be given to the process of involuntary context switching, and the calculated optimal time slice is relatively short. The time interval for the next time the process obtains the right to use the CPU is determined based on the calculated optimal time slice. After the optimal time slice, the right to use the CPU is granted to the process, thereby ensuring that the process of involuntary context switching can occupy CPU resources faster.

[0019] In the above-mentioned method for improving the performance of CPU context switching, involuntary context switching refers to a process being forcibly scheduled by the system due to the expiration of the time slice, thereby causing context switching.

[0020] The present application also provides a computer storage medium, characterized by comprising: at least one memory and at least one processor;

[0021] The memory is used to store one or more program instructions;

[0022] A processor is used to run one or more program instructions to execute any of the above-mentioned methods for improving CPU context switching performance.

[0023] The beneficial effects achieved by the present application are as follows: the technical solution of the present application can dynamically adjust the optimal time slice of the process in real time, greatly reduce the time and frequency of CPU context switching, and improve the performance of the CPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0025] Figure 1 This is a flow chart of a method for improving CPU context switching performance provided in Example 1 of the present application;

[0026] Figure 2 This is the CPU time slice allocation diagram before tuning;

[0027] Figure 3 This is the CPU time slice allocation diagram after optimization;

[0028] Figure 4 This is a diagram of CPU usage before tuning;

[0029] Figure 5 This is a diagram of CPU usage after optimization. DETAILED DESCRIPTION

[0030] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0031] Embodiment 1

[0032] like Figure 1 As shown, the first embodiment of the present application provides a method for improving the performance of CPU context switching, including:

[0033] Step 110: Perform baseline modeling on common processes running in the operating system;

[0034] Specifically, the common processes running in the operating system, that is, the native operating system dependencies, the switching time and switching frequency of the used programs are recorded to form a baseline model of time and frequency.

[0035] Step 120: Perform data analysis on the process switch currently concerned and the baseline model, and perform conflict avoidance on the process switch currently concerned;

[0036] When performing data analysis on the process switch of current concern, it is necessary to compare the process switch of current concern with the baseline model to ensure that the CPU time slice usage of the original process is not affected during data analysis. In other words, the data analysis process during data analysis needs to be adjusted in real time according to the different processes, in principle, without affecting the CPU usage of the original process.

[0037] Monitor and count all third-party processes, and perform corresponding conflict avoidance for different switching situations, including:

[0038] ① Voluntary context switch (cswch) refers to the context switch caused by the process being unable to obtain the required resources, such as insufficient I / O, insufficient memory, etc.;

[0039] "Appropriate suppression" is performed on processes that frequently undergo voluntary context switching, because even if such processes are allocated valuable CPU time slice resources, they will waste CPU resources due to lack of resources to continue.

[0040] ② Involuntary context switch (nvcswch): a process is forcibly scheduled by the system due to reasons such as the expiration of the time slice, resulting in context switch, such as a large number of processes competing for the CPU.

[0041] Processes that experience involuntary context switching are given "appropriate priority" because such processes can run smoothly and will not be suspended due to lack of resources.

[0042] Step 130: Based on the principle of not affecting the common process baseline model, data iteration is performed to construct an optimization scheduling algorithm for CPU context switching, the optimal time slice is calculated in real time, and the CPU context switching is adjusted in real time based on the optimal time slice;

[0043] For voluntary context switching and involuntary context switching, "appropriate inhibition" or "appropriate inhibition" is performed accordingly. Specifically, the time slice is optimized, and the calculated optimal time slice is the time interval for the current process of interest to regain the right to use the CPU;

[0044] Specifically, under the condition of not affecting the baseline model of the public process, the optimized scheduling algorithm for CPU context switching is obtained through data iteration:

[0045]

[0046] Among them, Time_Slice is the calculated optimal time slice, k is the baseline modeling time slice of the public process, and b n is the CPU time slice when the current process performs voluntary context switching for the nth time, b n-1 It is the CPU time slice for the current process to perform voluntary context switching for the n-1th time.

[0047] For the process of voluntary context switching (cswch), it is necessary to suspend the process, store the current running status data of the process, and perform "appropriate suppression". The calculated optimal time slice is relatively long. The time interval for the next CPU usage right of the process is determined according to the calculated optimal time slice. After the optimal time slice, the CPU usage right is granted to the process, thereby ensuring that the process of voluntary context switching will not occupy CPU resources for a long time.

[0048] For the process of involuntary context switching (nvcswch), since the process can run smoothly, but if it is executed according to the preset time slice allocated at fixed intervals of clock cycles, the process can only be suspended first, so that the process that can run smoothly cannot use the CPU resources in time, so it is necessary to perform "appropriate priority", and the calculated optimal time slice is also relatively short, that is, the waiting time of the process is short, and the time interval for the next time the process obtains the right to use the CPU is determined according to the calculated optimal time slice. After the interval of the optimal time slice, the right to use the CPU is granted to the process, thereby ensuring that the process of involuntary context switching can occupy the CPU resources faster;

[0049] Therefore, the technical solution of the present application can dynamically adjust the optimal time slice of the process in real time, greatly reduce the time and frequency of CPU context switching, and improve the performance of the CPU.

[0050] Figures 2 to 5 The example shows the CPU time slice allocation and utilization rate before and after the tuning scheme of this application; before the tuning, the time slice allocation is disorganized and the CPU utilization rate is over 80%, wasting CPU resources; after the tuning, the allocation and utilization of time slices tends to be linear, reducing performance consumption, and the CPU utilization rate is reduced to over 65%, an increase of about 15%.

[0051] Corresponding to the above embodiment, an embodiment of the present invention provides a computer storage medium, including: at least one memory and at least one processor;

[0052] The memory is used to store one or more program instructions;

[0053] The processor is used for running one or more program instructions to execute a performance improvement method for CPU context switching.

[0054] Corresponding to the above-mentioned embodiment, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer storage medium contains one or more program instructions, and the one or more program instructions are used by a processor to execute a performance improvement method for CPU context switching.

[0055] The embodiments disclosed in the present invention provide a computer-readable storage medium, in which computer program instructions are stored. When the computer program instructions are executed on a computer, the computer executes the above method.

[0056] In the embodiment of the present invention, the processor may be an integrated circuit chip having the ability to process signals. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0057] The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present invention can be directly embodied as a hardware decoding processor for execution, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The processor reads the information in the storage medium and completes the steps of the above method in combination with its hardware.

[0058] The storage medium may be a memory, which may be, for example, a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory.

[0059] Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory.

[0060] The volatile memory may be a random access memory (RAM) which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDRSDRAM), enhanced synchronous DRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus DRAM (DRRAM).

[0061] The storage media described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memory.

[0062] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the present invention can be implemented using a combination of hardware and software. When software is used, the corresponding functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by general or special-purpose computers.

[0063] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solution of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for improving CPU context switching performance, characterized in that: include: Baseline modeling of common processes running in an operating system; Perform data analysis on the process switching of current concern and the baseline model, and perform conflict avoidance on the process switching of current concern; Based on the principle of not affecting the common process baseline model, data iteration is performed to build an optimized scheduling algorithm for CPU context switching and calculate the optimal time slice in real time; Adjust CPU context switching in real time based on the optimal time slice; For voluntary context switching and involuntary context switching, the corresponding suppression or priority is performed, specifically, the time slice is optimized and allocated. The calculated optimal time slice is the time interval for the current process to regain the right to use the CPU. Under the condition of not affecting the baseline model of the public process, through data iteration, the optimized scheduling algorithm for CPU context switching is obtained as follows: in, is the calculated optimal time slice, Modeling time slices for baselines of common processes, It is the CPU time slice when the current process performs voluntary context switching for the nth time. It is the CPU time slice for the current process to perform voluntary context switching for the n-1th time.

2. The method for improving CPU context switching performance as claimed in claim 1, characterized in that: The common processes running in the operating system, namely the native operating system dependencies, the switching time and frequency of the used programs are recorded to form a baseline model of time and frequency.

3. The method for improving CPU context switching performance as claimed in claim 1, characterized in that: When performing data analysis on the process switching of the current concern, it is necessary to compare the process switching of the current concern with the baseline model to ensure that the CPU time slice usage of the original process is not affected during the data analysis.

4. The method for improving CPU context switching performance as claimed in claim 1, characterized in that: For a process that voluntarily switches context, it is necessary to suspend the process, store the current running status data of the process, and suppress it. The calculated optimal time slice is relatively long. The time interval for the next time the process obtains the right to use the CPU is determined based on the calculated optimal time slice. After the optimal time slice, the right to use the CPU is granted to the process, thereby ensuring that the process that voluntarily switches context will not occupy CPU resources for a long time.

5. The method for improving CPU context switching performance as claimed in claim 4, characterized in that: Voluntary context switching refers to context switching caused by the process being unable to obtain the required resources.

6. The method for improving CPU context switching performance as claimed in claim 5, characterized in that: For processes with involuntary context switching, priority needs to be given, and the calculated optimal time slice is also relatively short. The time interval for the next time the process obtains the right to use the CPU is determined based on the calculated optimal time slice. After the optimal time slice, the CPU usage right is granted to the process, thereby ensuring that the process with involuntary context switching can occupy CPU resources faster.

7. The method for improving CPU context switching performance as claimed in claim 6, characterized in that: Involuntary context switching means that the process is forcibly scheduled by the system because the time slice has expired, resulting in context switching.

8. A computer storage medium, characterized in that include: at least one memory and at least one processor; The memory is used to store one or more program instructions; A processor, used to run one or more program instructions to execute a performance improvement method for CPU context switching as described in any one of claims 1 to 7.

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