Data strobe clock output circuit

Abstract

The present technology includes a data strobe clock output circuit. The data strobe clock output circuit includes: a first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal, and output a first data strobe clock in response to the rising clock, the falling clock, and a mode signal; and a second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signal.

Description

Technical Field

[0001] The present disclosure relates to a data strobe clock output circuit, and more particularly, to a data strobe clock output circuit included in a controller for controlling a memory device. Background Art

[0002] A memory system may include a memory device capable of storing data and a controller capable of controlling the memory device.

[0003] The memory device may be configured as a volatile memory device in which data stored is lost when power is cut off, or a non-volatile memory device that retains the stored data even when power is cut off.

[0004] The controller may generate commands for controlling the memory device according to requests from a host and map addresses between the host and the memory device.

[0005] The controller and the memory device may communicate through a channel. The channel may include control lines, input / output lines, and data strobe clock lines. The control lines may transmit various signals for the controller to determine the mode of the memory device or select a chip. For example, the control lines may transmit signals such as a chip enable signal and a read enable signal. The input / output lines may transmit commands, data, or addresses, and the data strobe clock lines may transmit data strobe clocks. Data transmitted between the controller and the memory device may be latched into the controller or the memory device according to the data strobe clock. Summary of the Invention

[0006] A data strobe clock output circuit according to an embodiment of the present disclosure may include: a first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal, and output a first data strobe clock in response to the rising clock, the falling clock, and a mode signal; and a second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signal.

[0007] A data strobe clock output circuit according to an embodiment of the present disclosure may include: a clock modulator configured to output a modulated clock and a modulated inverted clock in response to a clock, an inverted clock, and a first enable signal; a trigger circuit configured to output a rising clock and a falling clock in response to the clock, the modulated clock, and the modulated inverted clock; an enable selector configured to output a sub-mode signal in response to a mode signal and a second enable signal; a first mode selector configured to output a pull-up clock and a pull-down clock in response to the rising clock, the falling clock, and the mode signal; a first driver configured to output a first data strobe clock in response to one or more of the pull-up clocks and one or more of the pull-down clocks; a second mode selector configured to invert the rising clock to generate a rising inverted clock, invert the falling clock to generate a falling inverted clock, and output a pull-up clock and a pull-down clock in response to the rising inverted clock, the falling inverted clock, and the sub-mode signal; and a second driver configured to output a second data strobe clock in response to one or more of the pull-up clocks and one or more of the pull-down clocks. Description of the Drawings

[0008] Figure 1 is a diagram for describing a memory system according to an embodiment of the present disclosure.

[0009] Figure 2 is a diagram for describing a data strobe clock output circuit according to an embodiment of the present disclosure.

[0010] Figure 3 is a diagram for describing a clock modulator according to an embodiment of the present disclosure.

[0011] Figure 4 is a diagram for describing a trigger circuit according to an embodiment of the present disclosure.

[0012] Figure 5 is a diagram for describing an enable selector according to an embodiment of the present disclosure.

[0013] Figure 6 is a diagram for describing a first mode selector according to an embodiment of the present disclosure.

[0014] Figure 7 is a diagram for describing a second mode selector according to an embodiment of the present disclosure.

[0015] Figure 8 is a diagram for describing a first driver according to an embodiment of the present disclosure.

[0016] Figure 9 is a diagram for describing a second driver according to an embodiment of the present disclosure.

[0017] Figure 10 This is a diagram for describing the operation of a data strobe clock output circuit according to an embodiment of the present disclosure.

[0018] Figure 11 This is a diagram for comparing a data strobe clock output circuit according to an embodiment of the present disclosure with another circuit.

[0019] Figure 12 This is a diagram for describing a memory system including a controller of the present disclosure.

[0020] Figure 13 This is a diagram for describing another memory system including a controller of the present disclosure. Detailed Description

[0021] Figure 1 This is a diagram for describing a memory system according to an embodiment of the present disclosure.

[0022] Referring to Figure 1 , the memory system 1000 may store, output, or erase data according to a request RQ from the host 2000. For example, the host 2000 may transmit data DATA together with a request RQ for programming to the memory system 1000, and the memory system 1000 may store the data DATA according to the request RQ.

[0023] The memory system 1000 may include a memory device 1100 capable of storing data and a controller 1200 capable of controlling the memory device 1100.

[0024] The memory device 1100 may include a memory cell array 110 and an input / output circuit 111. The memory cell array 110 may include a plurality of memory cells. In response to a first data strobe clock DQS1 and a second data strobe clock DQS2 input to a first pad PAD1 and a second pad PAD2, the input / output circuit 111 may receive commands, addresses, and data from the controller 1200 or output data through input / output lines DQ[0:N]. In addition to the memory cell array 110 and the input / output circuit 111, Figure 1 the illustrated memory device 1100 may include peripheral circuits (not shown) configured to perform programming operations, read operations, or erase operations.

[0025] The controller 1200 may include a central processing unit 120, a buffer memory 121, a host interface 123, and a memory interface 124. The central processing unit 120 may generally control the operation of the memory system 1000 according to a request RQ from the host 2000. The buffer memory 121 may store system data required for the operation of the controller 1200. For example, the buffer memory 121 may store system data such as address mapping information. The host interface 123 may exchange a request (RQ), an address, and data DATA between the controller 1200 and the host 2000. For example, the host interface 123 may include various interfaces such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0026] The memory interface 124 can exchange commands, addresses, and data between the controller 1200 and the memory device 1100, and output a first data strobe clock DQS1 and a second data strobe clock DQS2. For example, commands, addresses, and data can be transmitted through the input / output lines DQ[0:N] connected between the controller 1200 and the memory device 1100, and the first data strobe clock DQS1 and the second data strobe clock DQS2 can be output from the controller 1200 to the memory device 1100 through the data strobe lines. The memory interface 124 can include a data strobe clock output circuit (DQS output circuit) 125 configured to output the first data strobe clock DQS1 and the second data strobe clock DQS2. For example, when the controller 1200 transmits data to the memory device 1100, the memory interface 124 can load the data onto the input / output lines DQ[0:N], and output the first data strobe clock DQS1 and the second data strobe clock DQS2. The memory device 1100 can receive the first data strobe clock DQS1 through the first pad PAD1, and receive the second data strobe clock DQS2 through the second pad PAD2. In response to receiving the first data strobe clock DQS1 and the second data strobe clock DQS2 of the first pad PAD1 and the second pad PAD2, the memory device 1100 can sequentially receive the data loaded onto the input / output lines DQ[0:N]. For example, the data strobe clock output circuit 125 can output the first data strobe clock DQS1 and the second data strobe clock DQS2 with opposite phases to each other. For example, when the first data strobe clock DQS1 is high, the second data strobe clock DQS2 is low. The data loaded onto the input / output lines DQ[0:N] can be input to the memory device 1100 when the first data strobe clock DQS1 changes from low to high, and can be input to the memory device 1100 when the second data strobe clock DQS2 changes from high to low. The data strobe clock output circuit 125 can output the first data strobe clock DQS1 and the second data strobe clock DQS2 simultaneously, but can also output only the first data strobe clock DQS1. As used herein, the terms "simultaneously" and "concurrently" with respect to events (occurrences) mean that the events occur during overlapping intervals of time. For example, if a first event occurs during a first time period, and a second event occurs concurrently during a second time period, then the first time period and the second time period at least partially overlap each other such that there is a time when both the first event and the second event occur.

[0027] The above data strobe clock output circuit 125 is described as follows, for example.

[0028] Figure 2 is a diagram for describing a data strobe clock output circuit according to an embodiment of the present disclosure.

[0029] Referring to Figure 2 , the data strobe clock output circuit 125 may include a first output circuit 21 capable of outputting a first data strobe clock DQS1 and a second output circuit 22 capable of outputting a second data strobe clock DQS2. According to one embodiment, the size of the second output circuit 22 may be reduced by sharing some of the circuits included in the first output circuit 21.

[0030] The first output circuit 21 may receive a power supply voltage VCC and a ground voltage VSS, and output the first data strobe clock DQS1 in response to a clock CLK, an inverted clock CLKb, a first enable signal 1EN, and first to fourth mode signals 1MD to 4MD.

[0031] The first output circuit 21 may include a clock modulator 210, a trigger circuit 220, a first mode selector 240a, and a first driver 250a. The clock modulator 210 may receive a power supply voltage VCC and a ground voltage VSS, and output a modulated clock and a modulated inverted clock in response to the clock CLK, the inverted clock CLKb, and the first enable signal 1EN. The trigger circuit 220 may output a rising clock RDIN and a falling clock FDIN in response to the clock CLK, the inverted clock CLKb, the modulated clock, and the modulated inverted clock. The first mode selector 240a may output one or more pull-up clocks and one or more pull-down clocks in response to the rising clock RDIN, the falling clock FDIN, and the first to fourth mode signals 1MD to 4MD. The first to fourth mode signals 1MD to 4MD may be signals that vary according to a mode for determining the pulse widths of the first data strobe clock DQS1 and the second data strobe clock DQS2. Although the first to fourth mode signals 1MD to 4MD are shown in this embodiment, a larger number of mode signals may be used. The first driver 250a may output the first data strobe clock DQS1 in response to the pull-up clocks and the pull-down clocks received from the first mode selector 240a.

[0032] The second output circuit 22 may receive a power supply voltage VCC and a ground voltage VSS, and output the second data strobe clock DQS2 in response to a second enable signal 2EN and the first to fourth mode signals 1MD to 4MD.

[0033] The second output circuit 22 may include an enable selector 230, a second mode selector 240b, and a second driver 250b. The enable selector 230 may output first to fourth sub-mode signals in response to a second enable signal 2EN and first to fourth mode signals 1MD to 4MD. For example, when a high second enable signal 2EN is input to the enable selector 230, the second output circuit 22 may be activated, and a second data strobe clock DQS2 may be output. That is, when the second enable signal 2EN is high or at a high level, the second output circuit 22 may output the second data strobe clock DQS2 when the first data strobe clock DQS1 is output from the first output circuit 21. When the second enable signal 2EN is low or at a low level, the second output circuit 22 may be deactivated, and the second data strobe clock DQS2 may not be output.

[0034] The circuits included in each of the first output circuit 21 and the second output circuit 22 are described as follows, for example.

[0035] Figure 3 is a diagram for describing a clock modulator according to an embodiment of the present disclosure.

[0036] Referring to Figure 3 , the clock modulator 210 may be activated in response to a first enable signal 1EN, and modulate the pulse widths of a clock CLK and an inverted clock CLKb to output a modulated clock CLK_M and a modulated inverted clock CLKb_M. The clock modulator 210 may include a first modulator 31 that modulates the clock CLK and a second modulator 32 that modulates the inverted clock CLKb.

[0037] The width of the high pulse of the modulated clock CLK_M may be narrower than the width of the high pulse of the clock CLK, and the width of the low pulse of the modulated clock CLK_M may be wider than the width of the low pulse of the clock CLK.

[0038] The width of the high pulse of the modulated inverted clock CLKb_M may be narrower than the width of the high pulse of the inverted clock CLKb, and the width of the low pulse of the modulated inverted clock CLKb_M may be wider than the width of the low pulse of the inverted clock CLKb.

[0039] Figure 4 is a diagram for describing a trigger circuit according to an embodiment of the present disclosure.

[0040] Referring to Figure 4, the trigger circuit 220 can output a rising clock RDIN and a falling clock FDIN in response to the clock CLK, the modulation clock CLK_M, and the modulation inverted clock CLKb_M. The trigger circuit 220 can include a rising circuit 400 capable of outputting the rising clock RDIN and a falling circuit 410 capable of outputting the falling clock FDIN.

[0041] The rising circuit 400 can include a rising trigger circuit 401 and a rising buffer 402.

[0042] The rising trigger circuit 401 can output a first trigger clock 1TR in response to the clock CLK and the modulation clock CLK_M.

[0043] The rising buffer 402 can output the rising clock RDIN in response to the first trigger clock 1TR.

[0044] The falling circuit 410 can include a falling trigger circuit 411 and a falling buffer 412. The falling trigger circuit 411 can be configured similarly to the rising trigger circuit 401, and the falling buffer 412 can be configured similarly to the rising buffer 402.

[0045] The falling trigger circuit 411 can output a second trigger clock 2TR in response to the clock CLK and the modulation inverted clock CLKb_M.

[0046] The falling buffer 412 can output the falling clock FDIN in response to the second trigger clock 2TR.

[0047] Figure 5 is a diagram for describing an enable selector according to an embodiment of the present disclosure.

[0048] Referring to Figure 5 , the enable selector 230 can output first to fourth sub-mode signals 1MDc to 4MDc in response to a second enable signal 2EN and first to fourth mode signals 1MD to 4MD. For example, the enable selector 230 can include first to fourth enable circuits 51 to 54.

[0049] The first enabling circuit 51 may include a NAND gate 51a that outputs a logic value in response to a first mode signal 1MD and a second enabling signal 2EN, and an inverter 51b that inverts the logic value output from the NAND gate 51a to output a first sub-mode signal 1MDc. The second enabling circuit 52 to the fourth enabling circuit 54 may also include NAND gates 52a to 54a and enabling circuits 52b to 54b, and may be configured in the same manner as the first enabling circuit 51. The second enabling circuit 52 may output a second sub-mode signal 2MDc in response to a second mode signal 2MD and the second enabling signal 2EN, the third enabling circuit 53 may output a third sub-mode signal 3MDc in response to a third mode signal 3MD and the second enabling signal 2EN, and the fourth enabling circuit 54 may output a fourth sub-mode signal 4MDc in response to a fourth mode signal 4MD and the second enabling signal 2EN.

[0050] The first mode signal 1MD to the fourth mode signal 4MD may be signals that vary according to a mode for determining the pulse widths of the first data strobe clock DQS1 and the second data strobe clock DQS2. Although the first mode signal 1MD to the fourth mode signal 4MD are shown in this embodiment, a larger number of mode signals may be used.

[0051] Figure 6 It is a diagram for describing a first mode selector according to an embodiment of the present disclosure.

[0052] Referring to Figure 6 , the first mode selector 240a may output one or more pull-up clocks PU1 to PU4 and one or more pull-down clocks PD1 to PD4 in response to a rising clock RDIN, a falling clock FDIN, and the first mode signal 1MD to the fourth mode signal 4MD. For example, the first mode selector 240a may include a pull-up circuit 610 configured to output the pull-up clocks PU1 to PU4 and a pull-down circuit 620 configured to output the pull-down clocks PD1 to PD4.

[0053] The pull-up circuit 610 may include a first sub-pull-up circuit 611 to a fourth sub-pull-up circuit 614 that output a first pull-up clock PU1 to a fourth pull-up clock PU4. The first sub-pull-up circuit 611 to the fourth sub-pull-up circuit 614 may commonly receive a rising clock RDIN, and respectively receive a first mode signal 1MD to a fourth mode signal 4MD, to output the first pull-up clock PU1 to the fourth pull-up clock PU4. The first sub-pull-up circuit 611 may include a NAND gate 61a and an even number of inverters. The rising clock RDIN is input to a first input terminal of the NAND gate 61a and the first mode signal 1MD is input to a second input terminal of the NAND gate 61a. The even number of inverters output the logical value output from the NAND gate 61a as the first pull-up clock PU1. The remaining second sub-pull-up circuit 612 to the fourth sub-pull-up circuit 614 may also be configured in the same manner as the first sub-pull-up circuit 611. For example, the second sub-pull-up circuit 612 to the fourth sub-pull-up circuit 614 may include NAND gates 62a to 64a and inverters, and respectively output a second pull-up clock PU2 to a fourth pull-up clock PU4 in response to the rising clock RDIN and the second mode signal 2MD to the fourth mode signal 4MD input to the NAND gates 62a to 64a.

[0054] The pull-down circuit 620 may include a first sub-pull-down circuit 621 to a fourth sub-pull-down circuit 624 that output a first pull-down clock PD1 to a fourth pull-down clock PD4. The first sub-pull-down circuit 621 to the fourth sub-pull-down circuit 624 may commonly receive a falling clock FDIN, and respectively receive a first mode signal 1MD to a fourth mode signal 4MD, to output the first pull-down clock to the fourth pull-down clock. The first sub-pull-down circuit 621 may include a NAND gate 61b and an odd number of inverters or one inverter. The falling clock FDIN is input to a first input terminal of the NAND gate 61b, and the first mode signal 1MD is input to a second input terminal of the NAND gate 61b. The odd number of inverters or one inverter invert the logical value output from the NAND gate 61b, and output the inverted logical value as the first pull-down clock PD1. The remaining second sub-pull-down circuit 622 to the fourth sub-pull-down circuit 624 may be configured in the same manner as the first sub-pull-down circuit 621. For example, the second sub-pull-down circuit 622 to the fourth sub-pull-down circuit 624 may include NAND gates 62b to 64b and inverters, and respectively output a second pull-down clock PD2 to a fourth pull-down clock PD4 in response to the falling clock FDIN and the second mode signal 2MD to the fourth mode signal 4MD input to the NAND gates 62b to 64b.

[0055] Figure 7 is a diagram for describing a second mode selector according to an embodiment of the present disclosure.

[0056] Referring to Figure 7, the second mode selector 240b can output one or more pull-up clocks PU1 to PU4 and one or more pull-down clocks PD1 to PD4 in response to the rising inverted clock RDINb, the falling inverted clock FDINb, and the first sub-mode signal 1MDc to the fourth sub-mode signal 4MDc. For example, the second mode selector 240b can include a pull-up circuit 710 configured to output the pull-up clocks PU1 to PU4 and a pull-down circuit 720 configured to output the pull-down clocks PD1 to PD4. In one embodiment, the inverter 71 can receive the rising clock to output the rising inverted clock RDINb. In one embodiment, the inverter 72 can receive the falling clock FDIN to output the falling inverted clock FDINb.

[0057] The pull-up circuit 710 can include a first sub-pull-up circuit 711 to a fourth sub-pull-up circuit 714 that output the first pull-up clock PU1 to the fourth pull-up clock PU4. The first sub-pull-up circuit 711 to the fourth sub-pull-up circuit 714 can commonly receive the rising inverted clock RDINb and respectively receive the first sub-mode signal 1MDc to the fourth sub-mode signal 4MDc to output the first pull-up clock PU1 to the fourth pull-up clock PU4. The first sub-pull-up circuit 711 can include a NAND gate 71a and an even number of inverters. The rising inverted clock RDINb is input to the first input terminal of the NAND gate 71a, and the first sub-mode signal 1MDc is input to the second input terminal of the NAND gate 71a. The even number of inverters output the logical value output from the NAND gate 71a as the first pull-up clock PU1. The remaining second sub-pull-up circuit 712 to the fourth sub-pull-up circuit 714 can be configured in the same manner as the first sub-pull-up circuit 711. For example, the second sub-pull-up circuit 712 to the fourth sub-pull-up circuit 714 can include NAND gates 72a to 74a and inverters, and respectively output the second pull-up clock PU2 to the fourth pull-up clock PU4 in response to the rising inverted clock RDINb and the second sub-mode signal 2MDc to the fourth sub-mode signal 4MDc input to the NAND gates 72a to 74a.

[0058] The phases of the first pull-up clock PU1 to the fourth pull-up clock PU4 output by the pull-up circuit 710 of the second mode selector 240b can be opposite to the phases of the first pull-up clock PU1 to the fourth pull-up clock PU4 output from the pull-up circuit 610.

[0059] The pull-down circuit 720 may include a first sub-pull-down circuit 721 to a fourth sub-pull-down circuit 724 that output a first pull-down clock PD1 to a fourth pull-down clock PD4. The first sub-pull-down circuit 721 to the fourth sub-pull-down circuit 724 may commonly receive a falling inverted clock FDINb and respectively receive a first sub-mode signal 1MDc to a fourth sub-mode signal 4MDc to output the first pull-down clock PD1 to the fourth pull-down clock PD4. The first sub-pull-down circuit 721 may include a NAND gate 71b and an odd number of inverters or one inverter. The falling inverted clock FDINb is input to a first input terminal of the NAND gate 71b, and the first sub-mode signal 1MDc is input to a second input terminal of the NAND gate 71b. The odd number of inverters or one inverter inverts the logical value output from the NAND gate 71b and outputs the inverted logical value as the first pull-down clock PD1. The remaining second sub-pull-down circuit 722 to the fourth sub-pull-down circuit 724 may be configured in the same manner as the first sub-pull-down circuit 721. For example, the second sub-pull-down circuit 722 to the fourth sub-pull-down circuit 724 may include NAND gates 72b to 74b and inverters, and respectively output a second pull-down clock PD2 to a fourth pull-down clock PD4 in response to the falling inverted clock FDINb input to the NAND gates 72b to 74b and the second sub-mode signal 2MDc to the fourth sub-mode signal 4MDc.

[0060] Figure 8 is a diagram for describing a first driver according to an embodiment of the present disclosure.

[0061] Referring to Figure 8 , the first driver 250a may output a first data strobe clock DQS1 in response to a first pull-up clock PU1 to a fourth pull-up clock PU4 and a first pull-down clock PD1 to a fourth pull-down clock PD4 output from the first mode selector 240a. The first driver 250a may include a first pull-up pre-driver 81a, a first pull-down pre-driver 81b, a first pull-up main driver 82a, and a first pull-down main driver 82b.

[0062] The first pull-up pre-driver 81a may output a first pull-up code PUC<1> to a fourth pull-up code PUC<4> by trimming the first pull-up clock PU1 to the fourth pull-up clock PU4. The first pull-up main driver 82a may output a high pulse H having a power supply voltage level in response to the first pull-up code PUC<1> to the fourth pull-up code PUC<4>.

[0063] The first pull-up pre-driver 81a may include a first trimming circuit 1TC to a fourth trimming circuit 4TC. The first trimming circuit 1TC to the fourth trimming circuit 4TC respectively output a first pull-up code PUC<1> to a fourth pull-up code PUC<4> by trimming a first pull-up clock PU1 to a fourth pull-up clock PU4. The first pull-up main driver 82a may include a first high-pulse output circuit 1HSO to a fourth high-pulse output circuit 4HSO. The first high-pulse output circuit 1HSO to the fourth high-pulse output circuit 4HSO output a high pulse H in response to the first pull-up code PUC<1> to the fourth pull-up code PUC<4>. The first trimming circuit 1TC to the fourth trimming circuit 4TC may be configured identically to each other, and the first high-pulse output circuit 1HSO to the fourth high-pulse output circuit 4HSO may be configured identically to each other. The first trimming circuit 1TC may output a pull-up main code PUMC and a first pull-up trimming code 1PUTC to a third pull-up trimming code 3PUTC by trimming the first pull-up clock PU1, and the first high-pulse output circuit 1HSO may output a high pulse H in response to the pull-up main code PUMC and the first pull-up trimming code 1PUTC to the third pull-up trimming code 3PUTC. The remaining second trimming circuit 2TC to the fourth trimming circuit 4TC may also respectively output a second pull-up code PUC<2> to a fourth pull-up code PUC<4> including the pull-up main code PUMC and the first pull-up trimming code 1PUTC to the third pull-up trimming code 3PUTC by trimming a second pull-up clock PU2 to a fourth pull-up clock PU4. The second high-pulse output circuit 2HSO to the fourth high-pulse output circuit 4HSO may respectively output a high pulse H in response to the second pull-up code PUC<2> to the fourth pull-up code PUC<4>.

[0064] According to the mode, all of the first pull-up clock PU1 to the fourth pull-up clock PU4 may be activated, or only some of the first pull-up clock PU1 to the fourth pull-up clock PU4 may be activated, and only the circuits among the first trimming circuit 1TC to the fourth trimming circuit 4TC and the first high-pulse output circuit 1HSO to the fourth high-pulse output circuit 4HSO that are connected to the activated pull-up clock may be activated. For example, when the first pull-up clock PU1 is activated and the second pull-up clock PU2 to the fourth pull-up clock PU4 are deactivated, the first trimming circuit 1TC and the first high-pulse output circuit 1HSO may be activated, and the remaining second trimming circuit 2TC to the fourth trimming circuit 4TC and the second high-pulse output circuit 2HSO to the fourth high-pulse output circuit 4HSO may be deactivated.

[0065] The first pull-down pre-driver 81b can output the first pull-down code PDC<1> to the fourth pull-down code PDC<4> by fine-tuning the first pull-down clock PD1 to the fourth pull-down clock PD4. The first pull-down main driver 82b can output a low pulse L having a ground voltage level in response to the first pull-down code PDC<1> to the fourth pull-down code PDC<4>.

[0066] The first pull-down pre-driver 81b may include a first fine-tuning circuit 1TC’ to a fourth fine-tuning circuit 4TC’, and the first fine-tuning circuit 1TC’ to the fourth fine-tuning circuit 4TC’ output the first pull-down code PDC<1> to the fourth pull-down code PDC<4> by fine-tuning the first pull-down clock PD1 to the fourth pull-down clock PD4, respectively. The first pull-down main driver 82b may include a first low-pulse output circuit 1LSO’ to a fourth low-pulse output circuit 4LSO’, and the first low-pulse output circuit 1LSO’ to the fourth low-pulse output circuit 4LSO’ output a low pulse L in response to the first pull-down code PDC<1> to the fourth pull-down code PDC<4>. The first fine-tuning circuit 1TC’ to the fourth fine-tuning circuit 4TC’ may be configured identically to each other, and the first low-pulse output circuit 1LSO’ to the fourth low-pulse output circuit 4LSO’ may be configured identically to each other. The first fine-tuning circuit 1TC’ can output a pull-down main code PDMC and a first pull-down fine-tuning code 1PDTC to a third pull-down fine-tuning code 3PDTC by fine-tuning the first pull-down clock PD1, and the first low-pulse output circuit 1LSO’ can output a low pulse L in response to the pull-down main code PDMC and the first pull-down fine-tuning code 1PDTC to the third pull-down fine-tuning code 3PDTC. The remaining second fine-tuning circuit 2TC’ to the fourth fine-tuning circuit 4TC’ can also output the second pull-down code PDC<2> to the fourth pull-down code PDC<4> including the pull-down main code PDMC and the first pull-down fine-tuning code 1PDTC to the third pull-down fine-tuning code 3PDTC by fine-tuning the second pull-down clock PD2 to the fourth pull-down clock PD4, respectively. The second low-pulse output circuit 2LSO’ to the fourth low-pulse output circuit 4LSO’ can output a low pulse L in response to the second pull-down code PDC<2> to the fourth pull-down code PDC<4>, respectively.

[0067] According to the mode, all of the first to fourth pull-down clocks PD1 to PD4 can be activated, or only some of the first to fourth pull-down clocks PD1 to PD4 can be activated, and only the circuits among the first to fourth trimming circuits 1TC’ to 4TC’ and the first to fourth low-pulse output circuits 1LSO’ to 4LSO’ that are connected to the activated pull-down clocks can be activated. For example, when the first pull-down clock PD1 is activated and the second to fourth pull-down clocks PD2 to PD4 are deactivated, the first trimming circuit 1TC’ and the first low-pulse output circuit 1LSO’ can be activated, and the remaining second to fourth trimming circuits 2TC’ to 4TC’ and the second to fourth low-pulse output circuits 2LSO’ to 4LSO’ can be deactivated.

[0068] When the first pull-up main driver 82a outputs a high pulse H, the output node of the first pull-down main driver 82b can be floated, and when the first pull-down main driver 82b outputs a low pulse L, the output node of the first pull-up main driver 82a can be floated. Therefore, the first driver 250a can output the first data strobe clock DQS1.

[0069] Figure 9 FIG. is a diagram for describing a second driver according to an embodiment of the present disclosure.

[0070] Referring to Figure 9 , the second driver 250b can output a second data strobe clock DQS2 in response to the first to fourth pull-up clocks PU1 to PU4 and the first to fourth pull-down clocks PD1 to PD4 output from the second mode selector 240b. The second driver 250b can include a second pull-up pre-driver 91a, a second pull-down pre-driver 91b, a second pull-up main driver 92a, and a second pull-down main driver 92b.

[0071] The second pull-up pre-driver 91a can output first to fourth pull-up codes PUC<1> to PUC<4> by trimming the first to fourth pull-up clocks PU1 to PU4. The second pull-up main driver 92a can output a high pulse H having a power supply voltage level in response to the first to fourth pull-up codes PUC<1> to PUC<4>.

[0072] The second pull-up pre-driver 91a may include a first trimming circuit 1TC to a fourth trimming circuit 4TC, and the first trimming circuit 1TC to the fourth trimming circuit 4TC respectively output a first pull-up code PUC<1> to a fourth pull-up code PUC<4> by trimming a first pull-up clock PU1 to a fourth pull-up clock PU4. The second pull-up main driver 92a may include a first high-pulse output circuit 1HSO to a fourth high-pulse output circuit 4HSO, and the first high-pulse output circuit 1HSO to the fourth high-pulse output circuit 4HSO output a high pulse H in response to the first pull-up code PUC<1> to the fourth pull-up code PUC<4>. The first trimming circuit 1TC to the fourth trimming circuit 4TC may be configured identically to each other, and the first high-pulse output circuit 1HSO to the fourth high-pulse output circuit 4HSO may be configured identically to each other. The first trimming circuit 1TC may output a pull-up main code PUMC and a first pull-up trimming code 1PUTC to a third pull-up trimming code 3PUTC by trimming the first pull-up clock PU1, and the first high-pulse output circuit 1HSO may output a high pulse H in response to the pull-up main code PUMC and the first pull-up trimming code 1PUTC to the third pull-up trimming code 3PUTC. The remaining second trimming circuit 2TC to the fourth trimming circuit 4TC may also output a second pull-up code PUC<2> to a fourth pull-up code PUC<4> including the main code PUMC and the first pull-up trimming code 1PUTC to the third pull-up trimming code 3PUTC by trimming the second pull-up clock PU2 to the fourth pull-up clock PU4 respectively. The second high-pulse output circuit 2HSO to the fourth high-pulse output circuit 4HSO may output a high pulse H in response to the second pull-up code PUC<2> to the fourth pull-up code PUC<4> respectively.

[0073] According to the mode, all of the first pull-up clocks PU1 to the fourth pull-up clocks PU4 may be activated, or only some of the first pull-up clocks PU1 to the fourth pull-up clocks PU4 may be activated, and only the circuits among the first trimming circuit 1TC to the fourth trimming circuit 4TC and the first high-pulse output circuit 1HSO to the fourth high-pulse output circuit 4HSO that are connected to the activated pull-up clocks may be activated. For example, when the first pull-up clock PU1 is activated and the second pull-up clock PU2 to the fourth pull-up clocks PU4 are deactivated, the first trimming circuit 1TC and the first high-pulse output circuit 1HSO may be activated, and the remaining second trimming circuit 2TC to the fourth trimming circuit 4TC and the second high-pulse output circuit 2HSO to the fourth high-pulse output circuit 4HSO may be deactivated.

[0074] The second pull-down pre-driver 91b can output the first pull-down code PDC<1> to the fourth pull-down code PDC<4> by finely tuning the first pull-down clock PD1 to the fourth pull-down clock PD4. The second pull-down main driver 92b can output a low pulse L having a ground voltage level in response to the first pull-down code PDC<1> to the fourth pull-down code PDC<4>.

[0075] The second pull-down pre-driver 91b may include a first fine-tuning circuit 1TC’ to a fourth fine-tuning circuit 4TC’, and the first fine-tuning circuit 1TC’ to the fourth fine-tuning circuit 4TC’ output the first pull-down code PDC<1> to the fourth pull-down code PDC<4> by finely tuning the first pull-down clock PD1 to the fourth pull-down clock PD4, respectively. The second pull-down main driver 92b may include a first low-pulse output circuit 1LSO’ to a fourth low-pulse output circuit 4LSO’, and the first low-pulse output circuit 1LSO’ to the fourth low-pulse output circuit 4LSO’ output a low pulse L in response to the first pull-down code PDC<1> to the fourth pull-down code PDC<4>. The first fine-tuning circuit 1TC’ to the fourth fine-tuning circuit 4TC’ may be configured identically to each other, and the first low-pulse output circuit 1LSO’ to the fourth low-pulse output circuit 4LSO’ may be configured identically to each other. The first fine-tuning circuit 1TC’ can output a pull-down main code PDMC and a first pull-down fine-tuning code 1PDTC to a third pull-down fine-tuning code 3PDTC by finely tuning the first pull-down clock PD1, and the first low-pulse output circuit 1LSO’ can output a low pulse L in response to the pull-down main code PDMC and the first pull-down fine-tuning code 1PDTC to the third pull-down fine-tuning code 3PDTC. The remaining second fine-tuning circuit 2TC’ to the fourth fine-tuning circuit 4TC’ can also output the second pull-down code PDC<2> to the fourth pull-down code PDC<4> including the pull-down main code PDMC and the first pull-down fine-tuning code 1PDTC to the third pull-down fine-tuning code 3PDTC by finely tuning the second pull-down clock PD2 to the fourth pull-down clock PD4, respectively. The second low-pulse output circuit 2LSO’ to the fourth low-pulse output circuit 4LSO’ can output a low pulse L in response to the second pull-down code PDC<2> to the fourth pull-down code PDC<4>, respectively.

[0076] According to the mode, all of the first to fourth pull-down clocks PD1 to PD4 can be activated, or only some of the first to fourth pull-down clocks PD1 to PD4 can be activated, and only the circuits among the first to fourth trimming circuits 1TC’ to 4TC’ and the first to fourth low-pulse output circuits 1LSO’ to 4LSO’ that are connected to the activated pull-down clocks can be activated. For example, when the first pull-down clock PD1 is activated and the second to fourth pull-down clocks PD2 to PD4 are deactivated, the first trimming circuit 1TC’ and the first low-pulse output circuit 1LSO’ can be activated, and the remaining second to fourth trimming circuits 2TC’ to 4TC’ and the second to fourth low-pulse output circuits 2LSO’ to 4LSO’ can be deactivated.

[0077] When the second upper pull main driver 92a outputs a high pulse H, the output node of the second lower pull main driver 92b can be floated, and when the second lower pull main driver 92b outputs a low pulse L, the output node of the second upper pull main driver 92a can be floated. Accordingly, the second driver 250b can output the second data strobe clock DQS2.

[0078] Figure 10 is a diagram for describing the operation of a data strobe clock output circuit according to an embodiment of the present disclosure.

[0079] Referring to Figure 10 , the data strobe clock output circuit can output a first data strobe clock DQS1 and a second data strobe clock DQS2 having opposite phases based on the clock CLK.

[0080] When the data strobe clock generation operation starts (T1), Figure 3 's clock modulator 210 can output a modulated clock CLK_M and a modulated inverted clock CLKb_M by modulating the pulse widths of the clock CLK and the inverted clock CLKb. The high pulse of the modulated clock CLK_M is narrower than the high pulse of the clock CLK, and the low pulse of the modulated clock CLK_M is wider than the low pulse of the clock CLK. The high pulse of the modulated inverted clock CLKb_M is narrower than the high pulse of the inverted clock CLKb, and the low pulse of the modulated inverted clock CLKb_M is wider than the low pulse of the inverted clock CLKb.

[0081] From Figure 2 's first output circuit 21 outputs the following clocks.

[0082] The rising clock RDIN and the falling clock FDIN transition to high at the high edge of the modulated clock CLK_M and transition to low at the low edge of the modulated clock CLK_M.

[0083] The pull-up clock PU# can be selectively output in response to the first mode signal 1MD to the fourth mode signal 4MD and the rising clock RDIN. The pull-down clock PD# can be selectively output in response to the first mode signal 1MD to the fourth mode signal 4MD and the falling clock FDIN.

[0084] When the first mode signal 1MD and the second mode signal 2MD have the level of the ground voltage VSS and the third mode signal 3MD and the fourth mode signal 4MD have the level of the power supply voltage VCC, the third pull-up clock PU3 and the fourth pull-up clock PU4 can be output in response to the third mode signal 3MD and the fourth mode signal 4MD having the level of the power supply voltage VCC, and the first pull-up clock PU1 and the second pull-up clock PU2 are not output in response to the first mode signal 1MD and the second mode signal 2MD having the level of the ground voltage VSS. For example, the third pull-up clock PU3 and the fourth pull-up clock PU4 can be output as clocks with phases opposite to the phase of the rising clock RDIN, and the first pull-up clock PU1 and the second pull-up clock PU2 can be output as signals with a high level and not as clocks.

[0085] That is to say, when the first mode signal 1MD and the second mode signal 2MD have the level of the ground voltage VSS and the third mode signal 3MD and the fourth mode signal 4MD have the level of the power supply voltage VCC, in Figure 6 Among the first sub-pull-up circuit 611 to the fourth sub-pull-up circuit 614 included in the pull-up circuit 610 of the first mode selector 240a, the first sub-pull-up circuit 611 and the second sub-pull-up circuit 612 can be deactivated, and the third sub-pull-up circuit 613 and the fourth sub-pull-up circuit 614 can be activated.

[0086] When Figure 6 When the third sub-pull-up circuit 613 and the fourth sub-pull-up circuit 614 included in the pull-up circuit 610 of the first mode selector 240a are activated, the third trimming circuit 3TC and the fourth trimming circuit 4TC included in the first pull-up pre-driver 81a of the first driver 250a can be activated, and Figure 8 the third pull-up code PUC<3> and the fourth pull-up code PUC<4> of Figure 8 can be output.

[0087] Figure 8 The third high pulse output circuit 3HSO and the fourth high pulse output circuit 4HSO of

[0088] The pull-down clock PD# can be selectively output in response to the first mode signal 1MD to the fourth mode signal 4MD and the falling clock FDIN.

[0089] When the first mode signal 1MD and the second mode signal 2MD have the level of the ground voltage VSS and the third mode signal 3MD and the fourth mode signal 4MD have the level of the power supply voltage VCC, the third pull-down clock PD3 and the fourth pull-down clock PD4 can be output in response to the third mode signal 3MD and the fourth mode signal 4MD having the level of the power supply voltage VCC, and the first pull-down clock PD1 and the second pull-down clock PD2 are not output in response to the first mode signal 1MD and the second mode signal 2MD having the level of the ground voltage VSS. For example, the third pull-down clock PD3 and the fourth pull-down clock PD4 can be output as clocks having the same phase as the falling clock FDIN, and the first pull-down clock PD1 and the second pull-down clock PD2 can be output as signals having a high level and not as clocks.

[0090] That is to say, when the first mode signal 1MD and the second mode signal 2MD have the level of the ground voltage VSS and the third mode signal 3MD and the fourth mode signal 4MD have the level of the power supply voltage VCC, in Figure 6 Among the first sub-pull-down circuit 621 to the fourth sub-pull-down circuit 624 included in the pull-down circuit 620 of the first mode selector 240a, the first sub-pull-down circuit 621 and the second sub-pull-down circuit 622 can be deactivated, and the third sub-pull-down circuit 623 and the fourth sub-pull-down circuit 624 can be activated.

[0091] When Figure 6 When the third sub-pull-down circuit 623 and the fourth sub-pull-down circuit 624 included in the pull-down circuit 620 of the first mode selector 240a are activated, the third trimming circuit 3TC’ and the fourth trimming circuit 4TC’ included in the first pull-down pre-driver 81b of the first driver 250a can be activated, and Figure 8 the third pull-down code PDC<3> and the fourth pull-down code PDC<4> of Figure 8 can be output.

[0092] Figure 8 The third low-pulse output circuit 3LSO’ and the fourth low-pulse output circuit 4LSO’ of

[0093] Figure 2The second output circuit 22 can output a second data strobe clock DQS2 whose phase is opposite to that of the first data strobe clock DQS1 by using a rising inverted clock RDINb and a falling inverted clock FDINb in which the rising clock RDIN and the falling clock FDIN output from the first output circuit 21 are inverted.

[0094] The clocks output from the second output circuit 22 are described as follows.

[0095] The rising inverted clock RDINb has a phase in which the phase of the rising clock RDIN output from the first output circuit 21 is inverted.

[0096] The pull-up clock PU# can be selectively output in response to the first mode signal 1MD to the fourth mode signal 4MD and the rising inverted clock RDINb, and the pull-down clock PD# can be selectively output in response to the first mode signal 1MD to the fourth mode signal 4MD and the falling inverted clock FDINb. The first mode signal 1MD to the fourth mode signal 4MD input to the second output circuit 22 are the same as the first mode signal 1MD to the fourth mode signal 4MD input to the first output circuit 21.

[0097] For example, since the first mode signal 1MD and the second mode signal 2MD have the level of the ground voltage VSS, and the third mode signal 3MD and the fourth mode signal 4MD have the level of the power supply voltage VCC, the third pull-up clock PU3 and the fourth pull-up clock PU4 can be output in response to the third mode signal 3MD and the fourth mode signal 4MD having the level of the power supply voltage VCC, and the first pull-up clock PU1 and the second pull-up clock PU2 are not output in response to the first mode signal 1MD and the second mode signal 2MD having the level of the ground voltage VSS. For example, the third pull-up clock PU3 and the fourth pull-up clock PU4 can be output as clocks whose phases are opposite to the phase of the rising inverted clock RDINb, and the first pull-up clock PU1 and the second pull-up clock PU2 can be output as signals having a high level and not as clocks.

[0098] That is, when the first mode signal 1MD and the second mode signal 2MD have the level of the ground voltage VSS and the third mode signal 3MD and the fourth mode signal 4MD have the level of the power supply voltage VCC, among the first sub-pull-up circuit 711 to the fourth sub-pull-up circuit 714 included in the pull-up circuit 710 of the second mode selector 240b in Figure 7 the first sub-pull-up circuit 711 and the second sub-pull-up circuit 712 can be deactivated, and the third sub-pull-up circuit 713 and the fourth sub-pull-up circuit 714 can be activated.

[0099] When Figure 7When the third sub - pull - up circuit 713 and the fourth sub - pull - up circuit 714 included in the pull - up circuit 710 of the second mode selector 240b are activated, it is possible to activate Figure 9 the third trimming circuit 3TC and the fourth trimming circuit 4TC included in the second pull - up pre - driver 91a of the second driver 250b, and it is possible to output Figure 9 the third pull - up code PUC<3> and the fourth pull - up code PUC<4>.

[0100] Figure 9 The third high - pulse output circuit 3HSO and the fourth high - pulse output circuit 4HSO can output high pulses of the second data strobe clock DQS2 in response to the third pull - up code PUC<3> and the fourth pull - up code PUC<4>.

[0101] It is possible to selectively output the pull - down clock PD# in response to the first mode signal 1MD to the fourth mode signal 4MD and the falling clock FDIN.

[0102] When the first mode signal 1MD and the second mode signal 2MD have the level of the ground voltage VSS and the third mode signal 3MD and the fourth mode signal 4MD have the level of the power supply voltage VCC, it is possible to output the third pull - down clock PD3 and the fourth pull - down clock PD4 in response to the third mode signal 3MD and the fourth mode signal 4MD having the level of the power supply voltage VCC, and not to output the first pull - down clock PD1 and the second pull - down clock PD2 in response to the first mode signal 1MD and the second mode signal 2MD having the level of the ground voltage VSS. For example, the third pull - down clock PD3 and the fourth pull - down clock PD4 can be output as clocks having the same phase as the falling clock FDIN, and the first pull - down clock PD1 and the second pull - down clock PD2 can be output as signals having a high level and not as clocks.

[0103] That is to say, when the first mode signal 1MD and the second mode signal 2MD have the level of the ground voltage VSS and the third mode signal 3MD and the fourth mode signal 4MD have the level of the power supply voltage VCC, among Figure 7 the first sub - pull - down circuit 721 to the fourth sub - pull - down circuit 724 included in the pull - down circuit 720 of the second mode selector 240b, it is possible to deactivate the first sub - pull - down circuit 721 and the second sub - pull - down circuit 722, and it is possible to activate the third sub - pull - down circuit 723 and the fourth sub - pull - down circuit 724.

[0104] When Figure 7 the third sub - pull - down circuit 723 and the fourth sub - pull - down circuit 724 included in the pull - down circuit 720 of the second mode selector 240b are activated, it is possible to activate Figure 9The third trimming circuit 3TC’ and the fourth trimming circuit 4TC’ included in the second pull-down pre-driver 91b of the second driver 250b, and can output Figure 9 the third pull-down code PDC<3> and the fourth pull-down code PDC<4>.

[0105] Figure 9 The third low-pulse output circuit 3LSO’ and the fourth low-pulse output circuit 4LSO’ of can output a low pulse of the second data strobe clock DQS2 in response to the third pull-down code PDC<3> and the fourth pull-down code PDC<4>.

[0106] Figure 11 is a diagram for comparing a data strobe clock output circuit according to an embodiment of the present disclosure with another circuit.

[0107] Refer to Figure 11 , the data strobe clock output circuit 125 according to the present embodiment includes a first output circuit 21 that outputs a first data strobe clock DQS1 and a second output circuit 22 that outputs a second data strobe clock DQS2. The second output circuit 22 shares the rising clock RDIN and the falling clock FDIN generated by the first output circuit 21. Therefore, the second output circuit 22 does not include circuits 210b and 220b corresponding to the clock modulator 210 and the trigger circuit 220 included in the first output circuit 21, respectively. Therefore, since the size of the second output circuit 22 is reduced, the size of the data strobe clock output circuit 125 can be reduced, and the size of the controller including the data strobe clock output circuit 125 can be reduced.

[0108] Figure 12 is a diagram for describing a memory system including the controller of the present disclosure.

[0109] Refer to Figure 12 , the memory system 1000 may include a memory device 1100 that stores data, and a controller 1200 that communicates between the memory device 1100 and the host 2000.

[0110] The memory system 1000 may include a plurality of memory devices 1100, and the memory devices 1100 may be connected to the controller 1200 through at least one channel. For example, a plurality of memory devices 1100 may be connected to one channel, and even when a plurality of channels are connected to the controller 1200, the plurality of memory devices 1100 may be connected to each channel.

[0111] The controller 1200 may communicate between the host 2000 and the memory device 1100, and may include as Figure 1The data strobe clock output circuit 125 shown. The controller 1200 may control the memory device 1100 according to a request of the host 2000, or even without a request from the host 2000, the controller 1200 may perform background operations for improving the performance of the memory system 1000. The host 2000 may generate requests for various operations and output the generated requests to the memory system 1000. For example, the requests may include a programming request that may control a programming operation, a read request that may control a read operation, an erase request that may control an erase operation, and the like.

[0112] The host 2000 may communicate with the memory system 1000 through various interfaces, such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Device Interface (ESDI), or Integrated Drive Electronics (IDE).

[0113] Figure 13 is a diagram for describing another memory system including the controller of the present disclosure.

[0114] Referring to Figure 13 , the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a controller 1200, and a card interface 7100.

[0115] The controller 1200 may control data exchange between the memory device 1100 and the card interface 7100, and may include a data strobe clock output circuit 125 as Figure 1 shown.

[0116] The card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but is not limited thereto.

[0117] The card interface 7100 may interface data exchange between the host 60000 and the controller 1200 according to the protocol of the host 60000. According to one embodiment, the card interface 7100 may support the Universal Serial Bus (USB) protocol and the Inter-Chip (IC) USB protocol. Herein, the card interface 7100 may refer to hardware capable of supporting the protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0118] When the memory system 70000 is connected to the host interface 6200 of a host 60000 (e.g., a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box), the host interface 6200 may perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of a microprocessor (μP) 6100.

[0119] Cross - reference to related applications

[0120] This application claims priority to Korean Patent Application No. 10 - 2020 - 0081582, filed on Jul. 2, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A data strobe clock output circuit, the data strobe clock output circuit comprising: A first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal, and output a first data strobe clock in response to the rising clock, the falling clock, and a mode signal; And A second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signal, Wherein the second output circuit comprises: An enable selector configured to receive the second enable signal and output a sub-mode signal in response to the mode signal; A second mode selector configured to invert the rising clock to generate the rising inverted clock, invert the falling clock to generate the falling inverted clock, and output a pull-up clock and a pull-down clock in response to the rising inverted clock, the falling inverted clock, and the sub-mode signal; and A second driver configured to output the second data strobe clock in response to one or more of the pull-up clocks and one or more of the pull-down clocks.

2. The data strobe clock output circuit according to claim 1, wherein The first output circuit comprises: A clock modulator configured to output a modulated clock and a modulated inverted clock in response to the clock, an inverted clock having a phase opposite to the phase of the clock, and the first enable signal; A trigger circuit configured to output the rising clock and the falling clock in response to the clock, the modulated clock, and the modulated inverted clock; A first mode selector configured to output a pull-up clock and a pull-down clock in response to the rising clock, the falling clock, and the mode signal; and A first driver configured to output the first data strobe clock in response to one or more of the pull-up clocks and one or more of the pull-down clocks.

3. The data strobe clock output circuit according to claim 2, wherein The clock modulator comprises: A first modulator activated in response to the first enable signal and outputting the modulated clock by modulating the width of the clock; and A second modulator activated in response to the first enable signal and outputting the modulated inverted clock by modulating the width of the inverted clock.

4. The data strobe clock output circuit according to claim 3, wherein The first modulator is configured to output the modulated clock in which the width of the high pulse is narrower than the high pulse of the clock, and the width of the low pulse is wider than the low pulse of the clock, and The second modulator is configured to output the modulated inverted clock in which the width of the high pulse is narrower than the high pulse of the inverted clock, and the width of the low pulse is wider than the low pulse of the inverted clock.

5. The data strobe clock output circuit according to claim 2, wherein The trigger circuit comprises: An up circuit configured to output the up clock in response to the clock and the modulation clock; and A down circuit configured to output the down clock in response to the clock and the modulation inverted clock.

6. The data strobe clock output circuit according to claim 5, wherein The up circuit includes:[[]] An up trigger circuit configured to output a first trigger clock in response to the clock and the modulation clock; and An up buffer configured to output the up clock in response to the first trigger clock.

7. The data strobe clock output circuit according to claim 5, wherein The down circuit includes:[[]] A down trigger circuit configured to output a second trigger clock in response to the clock and the modulation inverted clock; and A down buffer configured to output the down clock in response to the second trigger clock.

8. The data strobe clock output circuit according to claim 2, wherein, The first mode selector includes:[[]] A pull-up circuit configured to receive the up clock and selectively output the pull-up clock in response to the mode signal; and A pull-down circuit configured to receive the down clock and selectively output the pull-down clock in response to the mode signal.

9. The data strobe clock output circuit according to claim 2, wherein, The first driver includes:[[]] A first pull-up pre-driver configured to selectively output a pull-up code including a pull-up main code and a pull-up trim code by fine-tuning one or more of the pull-up clocks; A first pull-up main driver configured to output a high pulse of the first data strobe clock in response to one or more of the pull-up codes; A first pull-down pre-driver configured to selectively output a pull-down code including a pull-down main code and a pull-down trim code by fine-tuning one or more of the pull-down clocks; and A first pull-down main driver configured to output a low pulse of the first data strobe clock in response to one or more of the pull-down codes.

10. The data strobe clock output circuit according to claim 1, wherein, When the second enable signal input to the enable selector is at a high level, the second output circuit is activated to output the second data strobe clock, and when the second enable signal is at a low level, the second output circuit is deactivated.

11. The data strobe clock output circuit according to claim 1, wherein, The second mode selector includes:[[]] A pull-up circuit configured to receive the inverted up clock and selectively output the pull-up clock in response to the sub-mode signal; and A pull-down circuit configured to receive the inverted down clock and selectively output the pull-down clock in response to the sub-mode signal.

12. The data strobe clock output circuit according to claim 1, wherein, The second driver includes:[[]] A second pull-up pre-driver configured to selectively output a pull-up code including a pull-up main code and a pull-up trim code by fine-tuning one or more of the pull-up clocks; A second pull-up main driver configured to output a high pulse of the second data strobe clock in response to one or more of the pull-up codes; A second pull-down pre-driver configured to selectively output a pull-down code including a pull-down main code and a pull-down fine-tuning code by fine-tuning one or more of the pull-down clocks; and A second pull-down main driver configured to output a low pulse of the second data strobe clock in response to one or more of the pull-down codes.

13. A data strobe clock output circuit, the data strobe clock output circuit comprising: A clock modulator configured to output a modulated clock and a modulated inverted clock in response to a clock, an inverted clock, and a first enable signal; A trigger circuit configured to output a rising clock and a falling clock in response to the clock, the modulated clock, and the modulated inverted clock; An enable selector configured to output a sub-mode signal in response to a mode signal and a second enable signal; A first mode selector configured to output a pull-up clock and a pull-down clock in response to the rising clock, the falling clock, and the mode signal; A first driver configured to output a first data strobe clock in response to one or more of the pull-up clocks output by the first mode selector and one or more of the pull-down clocks; A second mode selector configured to invert the rising clock to generate a rising inverted clock, invert the falling clock to generate a falling inverted clock, and output a pull-up clock and a pull-down clock in response to the rising inverted clock, the falling inverted clock, and the sub-mode signal; And A second driver configured to output a second data strobe clock in response to one or more of the pull-up clocks output by the second mode selector and one or more of the pull-down clocks.

14. The data strobe clock output circuit according to claim 13, wherein The clock modulator, the trigger circuit, the first mode selector, and the first driver are configured to be activated in response to the first enable signal, and the second mode selector and the second driver are configured to be activated in response to the second enable signal.

15. The data strobe clock output circuit according to claim 13, wherein, The clock modulator includes: A first modulator configured to output the modulated clock in response to the first enable signal and the clock; and A second modulator configured to output the modulated inverted clock in response to the first enable signal and the inverted clock.

16. The data strobe clock output circuit according to claim 13, wherein The trigger circuit includes: A rising circuit configured to output the rising clock in response to the clock and the modulated clock; and A falling circuit configured to output the falling clock in response to the clock and the modulated inverted clock.

17. The data strobe clock output circuit according to claim 13, wherein The first mode selector includes: A pull-up circuit configured to receive the rising clock and selectively output the pull-up clock in response to the mode signal; and A pull-down circuit configured to receive the falling clock and selectively output the pull-down clock in response to the mode signal.

18. The data strobe clock output circuit according to claim 13, wherein The first driver includes: A first pull-up pre-driver configured to selectively output a pull-up code including a pull-up main code and a pull-up fine-tuning code by fine-tuning one or more of the pull-up clocks output by the first mode selector; A first pull-up main driver configured to output a high pulse of the first data strobe clock in response to one or more of the pull-up codes; A first pull-down pre-driver configured to selectively output a pull-down code including a pull-down main code and a pull-down fine-tuning code by fine-tuning one or more of the pull-down clocks output by the first mode selector; and A first pull-down main driver configured to output a low pulse of the first data strobe clock in response to one or more of the pull-down codes.

19. The data strobe clock output circuit according to claim 13, wherein The second mode selector includes: A pull-up circuit configured to receive the rising inverted clock and selectively output the pull-up clock in response to the sub-mode signal; and A pull-down circuit configured to receive the falling inverted clock and selectively output the pull-down clock in response to the sub-mode signal.

20. The data strobe clock output circuit according to claim 13, wherein The second driver includes: A second pull-up pre-driver configured to selectively output a pull-up code including a pull-up main code and a pull-up fine-tuning code by fine-tuning one or more of the pull-up clocks output by the second mode selector; A second pull-up main driver configured to output a high pulse of the second data strobe clock in response to one or more of the pull-up codes; A second pull-down pre-driver configured to selectively output a pull-down code including a pull-down main code and a pull-down fine-tuning code by fine-tuning one or more of the pull-down clocks output by the second mode selector; and A second pull-down main driver configured to output a low pulse of the second data strobe clock in response to one or more of the pull-down codes.

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