Three-dimensional memory and methods of making three-dimensional memory

Abstract

The application provides a three-dimensional memory and a manufacturing method of the three-dimensional memory, in the three-dimensional memory, through a functional step structure design located in a stack structure and dividing the stack structure into a first core structure, a second core structure and a bridge structure, bilateral driving of the functional step structure to two side memory cell blocks is realized, resistance when driving the memory cell blocks is reduced, and a driving delay problem is obviously improved; the functional step structure is designed as a first step structure and a second step structure staggered with each other, so that the functional step structure is divided into whole and parts, the volume of the whole functional step structure is reduced, stress influence of the functional step structure on the first core structure and the second core structure is reduced, and structural stability is improved; the functional step structure is designed as the first step structure and the second step structure staggered with each other, synchronous trimming etching can also be performed, the number of masks and the number of step-by-step trimming etching are reduced.

Description

[0001] [RELATED APPLICATIONS]

[0002] This application is a divisional application of Chinese Patent Application No. CN202010468530.4, filed on May 28, 2020, entitled “Three-dimensional memory, manufacturing method of step structure, and manufacturing method of three-dimensional memory”. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor technology, and in particular to a three-dimensional memory and a manufacturing method of the three-dimensional memory. BACKGROUND

[0004] Three-dimensional memory is a technology of stacking data units. Currently, it can realize the stacking of more than 32 layers, or even 64 layers of data units. It overcomes the limitation of the practical expansion limit of planar memory, further improves the storage capacity, reduces the storage cost of each data bit, and reduces the energy consumption.

[0005] However, in the current three-dimensional memory, the driving of each storage unit block is single-sided driving, which has a certain time delay. At the same time, with the increase of the number of storage structure layers, the thickness of each layer of data units becomes thinner and thinner, which sharply enhances the resistance, causing the driving time delay (RC delay) caused by the resistance-capacitance effect. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a new functional step structure to solve the above technical problems.

[0007] To achieve the above object and other related objects, the present application provides a three-dimensional memory, comprising:

[0008] A laminated structure comprising alternately stacked dielectric layers and gate layers;

[0009] A functional step structure located in the laminated structure and dividing the laminated structure into a first core structure, a second core structure, and a bridge structure. In the stacking plane of the laminated structure, the first core structure and the second core structure are arranged along a first direction, and the bridge structure is located on one side of the functional step structure in a second direction perpendicular to the first direction, and the first core structure and the second core structure are connected through the bridge structure.

[0010] A storage string passing through the first core structure, the second core structure, and the bridge structure;

[0011] The functional step structure comprises a first step structure and a second step structure composed of the gate layers and the dielectric layers, and the first step structure and the second step structure are arranged along the first direction.

[0012] The gate layer where the first step structure is located and the gate layer where the second step structure is located are configured to receive an electrical signal.

[0013] Optionally, the three-dimensional memory further comprises:

[0014] A first conductive plug is electrically connected to the gate layer of the first step structure.

[0015] A second conductive plug is electrically connected to the gate layer of the second step structure. Optionally, the stack structure further comprises a virtual step region at the edge, and the three-dimensional memory further comprises a virtual step structure composed of the gate layer and the dielectric layer, which is arranged in the virtual step region of the stack structure.

[0016] Optionally, the first step structure and the second step structure each comprise a plurality of first steps extending in the first direction, and the top surface of each first step exposes the gate layer; in the stacking direction of the stack structure, the top surfaces of the same first step in the first step structure and the second step structure have a height difference.

[0017] Optionally, the first step structure and the second step structure each further comprise a plurality of second steps extending in the second direction.

[0018] Optionally, the number of the functional step structures is a plurality, and the plurality of functional step structures are arranged in sequence along the second direction; the three-dimensional memory further comprises a plurality of gate line separation structures extending through the stack structure and along the first direction, the plurality of gate line separation structures are arranged at intervals along the second direction and separate the plurality of functional step structures.

[0019] Meanwhile, to achieve the above object and other related objects, the present application further provides a manufacturing method of a step structure, which is used for manufacturing a functional step structure in a three-dimensional memory, comprising:

[0020] providing a substrate;

[0021] forming a stack structure on the substrate, the stack structure is stacked by a plurality of composite layers, and the stack structure comprises a first core region, a functional step region and a second core region arranged in sequence along a first direction;

[0022] dividing the functional step region of the stack structure to form a plurality of functional step sub-regions arranged at intervals along a second direction;

[0023] trimming and etching the plurality of functional step sub-regions of the stack structure respectively, so as to form one functional step structure in each functional step sub-region;

[0024] The second direction is perpendicular to the first direction in a stacking plane of the stack structure.

[0025] Optionally, each of the composite layers comprises a dielectric layer and a gate layer on the dielectric layer, and the step of forming the functional step structure in the functional step subregion by trimming etching comprises:

[0026] The functional step subregion is divided into a first functional step subregion and a second functional step subregion along the first direction, and the topmost composite layer in the second functional step subregion is removed by etching;

[0027] A plurality of mask groups are used to simultaneously perform trimming etching on the first functional step subregion and the second functional step subregion, and each etching simultaneously removes two composite layers in a partial region of the first functional step subregion and a partial region of the second functional step subregion, thereby forming a first step structure in the first functional step subregion and a second step structure in the second functional step subregion;

[0028] Each of the mask groups comprises a plurality of masks, and the plurality of masks in each of the mask groups gradually shrink towards the middle of the stack structure in the first direction and the second direction.

[0029] Optionally, the first step structure and the second step structure each comprise a plurality of first steps extending along the first direction, and a top surface of each of the first steps exposes the gate layer; in the stacking direction of the stack structure, there is a height difference of one composite layer between the top surfaces of the same first step in the first step structure and the second step structure.

[0030] In addition, to achieve the above object and other related objects, the application further provides a manufacturing method of a three-dimensional memory, comprising:

[0031] providing a substrate;

[0032] forming a stack structure on the substrate, the stack structure being stacked by a plurality of composite layers, and the stack structure comprising a first core region, a functional step region, and a second core region arranged in sequence along a first direction;

[0033] dividing the functional step region of the stack structure to form a plurality of functional step subregions arranged at intervals in a second direction;

[0034] trimming etching is performed on each of the plurality of functional step subregions of the stack structure to form a functional step structure in each of the functional step subregions, and the functional step structure comprises a plurality of first steps extending along the first direction;

[0035] a plurality of gate line separation structures extending through the stack structure along the first direction are formed in the stack structure, and the stack structure is divided;

[0036] a memory string is formed in the first core region, the second core region and the region of the stack structure other than the functional step region, and a memory array structure is obtained;

[0037] a conductive plug is formed, and the conductive plug is electrically connected to the top surface of the first step;

[0038] In the stacking plane of the stack structure, the second direction is perpendicular to the first direction.

[0039] Optionally, each of the composite layers comprises a dielectric layer and a gate layer on the dielectric layer, and the step of forming the functional step structure in the functional step region comprises:

[0040] The functional step region is divided into a first functional step sub-region and a second functional step sub-region along the first direction, and the topmost composite layer in the second functional step sub-region is etched and removed;

[0041] A plurality of mask groups are used to simultaneously trim and etch the first functional step sub-region and the second functional step sub-region, and each etching simultaneously removes two composite layers in a partial region of the first functional step sub-region and a partial region of the second functional step sub-region, thereby forming a first step structure in the first functional step sub-region and a second step structure in the second functional step sub-region;

[0042] Each of the mask groups comprises a plurality of masks, and the plurality of masks in each of the mask groups gradually shrink towards the middle of the stack structure in the first direction and the second direction.

[0043] Optionally, the first step structure and the second step structure each comprise a plurality of first steps, and the top surface of each of the first steps exposes the gate layer, and the step of forming the conductive plug comprises:

[0044] A first conductive plug is formed, and the first conductive plug is electrically connected to the gate layer exposed by the top surface of the first step in the first step structure;

[0045] A second conductive plug is formed, and the second conductive plug is electrically connected to the gate layer exposed by the top surface of the first step in the second step structure.

[0046] As described above, the three-dimensional memory of the present application has the following beneficial effects:

[0047] By the functional step structure design located in the stack structure and dividing the stack structure into the first core structure, the second core structure and the bridge structure, the bilateral driving of the functional step structure to the first core structure and the second core structure on both sides is realized, the resistance when the storage unit blocks in the first core structure and the second core structure are driven through the functional step structure is effectively reduced, and the driving delay problem is obviously improved. In addition, the functional step structure includes the first step structure and the second step structure arranged along the first direction, the functional step structure is divided into zero, the volume of the whole functional step structure is reduced, the stress influence of the functional step structure on the first core structure and the second core structure is reduced, and the structural stability is improved. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 A partial top view of a three-dimensional memory is shown as prior art.

[0049] Figure 2 A partial top view of a three-dimensional memory is shown as an embodiment of the present application.

[0050] Figure 3 A partial top view of a three-dimensional memory is shown as an embodiment of the present application.

[0051] Figure 4 A front view of a step structure is shown as an embodiment of the present application.

[0052] Figure 5 An isometric view of a step structure is shown as an embodiment of the present application.

[0053] Figure 7 A mask top view during etching of a step structure is shown as an embodiment of the present application.

[0054] Figure 6 、 8 A process flow chart of a step structure is shown as an embodiment of the present application.

[0055] Figure 14 A step schematic diagram of a manufacturing method of a three-dimensional memory is shown as an embodiment of the present application.

[0056] REFERENCE SIGNS

[0057] 1 substrate

[0058] 101-104 storage array structure

[0059] 2 stack structure

[0060] 2' initial stack structure

[0061] 21 dielectric layer

[0062] 22 gate layer

[0063] 231, 232, 233, 234, 201, 201' functional step structure

[0064] 202 first core structure

[0065] 203 second core structure

[0066] 204 bridge structure

[0067] 2011 first step structure

[0068] 2012 second step structure

[0069] 201a first step

[0070] 201b second step

[0071] A1 first core area

[0072] A2 second core area

[0073] B functional step area

[0074] B1, B2, B3, B4, Bm, Bi step sub-area

[0075] Bi1 first functional step sub-area

[0076] Bi2 second functional step sub-area

[0077] Block storage unit block

[0078] M1-M6 mask DETAILED DESCRIPTION

[0079] The inventor found that the distance from one side to the other side of the storage unit block (Block) is long when it is driven from one side, and there is a certain time delay, such as Figure 1 As shown in the storage array structures 101 and 102, the plurality of storage unit blocks are driven from one side of the step structure in the X direction, i.e. from the step structure on one side of the storage array structure, Figure 1 The functional step structure 231, 232 in the storage array structure 101 is driven from one side, Figure 1 The functional step structure 233, 234 in the storage array structure 102 is driven from one side; at the same time, with the superposition of the storage array layers, the thickness of each layer of data unit in the storage unit block is getting thinner and thinner, which makes the resistance increase sharply, causing the driving time delay (RCdelay) caused by the resistance-capacitance effect.

[0080] Based on this, the application provides a new three-dimensional memory structure design scheme, a functional step structure for driving a storage unit block in a subsequent storage array structure is arranged in the middle of the storage array structure, and the storage array structure is driven from the middle to both sides, according to a definition formula of resistance, the resistance when the storage unit block is driven is reduced to less than half of that when the storage unit block is driven on one side, and the driving delay problem is obviously improved.

[0081] The above description is only used to explain the application, and the application has other advantages and effects which can be easily understood by those skilled in the art according to the above description. The application can also be implemented or applied by different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the application.

[0082] Please refer to Figures 2 to 14 . It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the application, and the diagrams only show the components related to the application, not the number, shape and size of the components when actually implemented. The shape, number and proportion of the components when actually implemented can be randomly changed, and the layout pattern of the components can be more complex. The structure, proportion, size and the like shown in the diagrams attached to the specification are only used to illustrate the content disclosed in the specification, so as to be understood and read by those skilled in the art, and do not limit the conditions that the application can be implemented, and therefore do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effect and purpose that the application can produce, should still fall within the scope of the technical content disclosed by the application. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" in the specification are only for the convenience of clear description, and are not used to limit the scope of the application which can be implemented, and the change or adjustment of the relative relationship, without substantially changing the technical content, is also regarded as the scope of the application which can be implemented.

[0083] As shown in Figures 2-5 , the application provides a three-dimensional memory, which comprises:

[0084] a substrate 1;

[0085] a laminated structure 2 arranged on the substrate 1, comprising alternately stacked dielectric layers 21 and gate layers 22;

[0086] The functional step structure 201 is located in the laminated structure 2 and divides the laminated structure 2 into a first core structure 202, a second core structure 203 and a bridge structure 204. In the stacking plane (i.e., the XY plane) of the laminated structure 2, the first core structure 202 and the second core structure 203 are arranged along a first direction (i.e., the X-axis direction), and the bridge structure 204 is located on one side of the functional step structure 201 in a second direction (i.e., the Y-axis direction) perpendicular to the first direction. The first core structure 202 and the second core structure 203 are connected through the bridge structure 204.

[0087] The storage string (not shown in the figure) passes through the first core structure 202, the second core structure 203 and the bridge structure 204.

[0088] The functional step structure 201 includes a first step structure 2011 and a second step structure 2012 composed of the dielectric layer 21 and the gate layer 22, and the first step structure 2011 and the second step structure 2012 are arranged along the first direction.

[0089] The gate layer 22 where the first step structure 2011 is located and the gate layer 22 where the second step structure 2012 is located are used to receive electrical signals.

[0090] In detail, as shown in Figure 3 and Figure 5 , the number of functional step structures 201 is multiple, and the multiple functional step structures 201 are arranged in sequence along the second direction. Each functional step structure 201 is provided with a bridge structure 204 on each side along the second direction, and the bridge structures 204 are respectively connected with the first core structure 202 and the second core structure 203.

[0091] In detail, as shown in Figures 4-5 , each functional step structure 201 includes a first step structure 2011 and a second step structure 2012 arranged at intervals along the first direction. The first step structure 2011 and the second step structure 2012 respectively include a plurality of first steps 201a extending along the first direction. The top surface of each first step 201a exposes the gate layer 22. In the stacking direction (i.e., the Z-axis direction) of the laminated structure 2, the top surfaces of the same level of first steps 201a in the first step structure 2011 and the second step structure 2012 have a height difference.

[0092] Optionally, as shown in Figure 5 , the first step structure 2011 and the second step structure 2012 also respectively include a plurality of second steps 201b extending along the second direction.

[0093] In detail, the memory string passing through the first core structure 202, the second core structure 203, and the bridging structure 204, together with the corresponding stacked dielectric layer 21 and gate layer 22, forms a memory array structure; the three-dimensional memory also includes a plurality of gate line separator structures (not shown in the figure) passing through the stacked structure 2 and extending along a first direction, the plurality of gate line separator structures being arranged at intervals along a second direction, dividing the memory array structure into, as shown in the figure. Figure 5 The multiple storage cell blocks shown separate multiple functional step structures 201.

[0094] Specifically, the three-dimensional memory further includes:

[0095] The first conductive plug (not shown in the figure) is electrically connected to the gate layer 22 exposed on the top surface of the first step 201a in the first step structure 2011;

[0096] The second conductive plug (not shown in the figure) is electrically connected to the gate layer 22 exposed on the top surface of the first step 201a in the second step structure 2012.

[0097] The first conductive plug and the second conductive plug are used to receive electrical signals in order to realize the driving control of the storage array structure by external driving control signals.

[0098] Specifically, the three-dimensional memory includes multiple stacked structures 2, that is, multiple memory array structures, such as 2, 4, 6, 8, etc.; optionally, as... Figure 2 As shown, the three-dimensional memory includes two storage array structures, namely storage array structures 103 and 104. Storage array structures 103 and 104 are independent of each other. Functional step structure 201 drives storage array structure 103 on both sides, and functional step structure 201' drives storage array structure 104 on both sides.

[0099] In detail, within the stack plane of the stacked structure 2, the stacked structure 2 also includes a virtual functional step region (not shown in the figure) located at the edge. The three-dimensional memory also includes a virtual step structure composed of a dielectric layer 21 and a gate layer 22. The virtual step structure is disposed in the virtual functional step region, that is, the virtual step structure is disposed on the substrate 1 and along the four edges of the memory array structure 103 or 104, physically isolating the memory array structures 103 and 104.

[0100] Optionally, such as Figure 2 As shown, since the functional step structure 201 is placed in the middle of the storage array structure 103 (along the first direction), it squeezes and occupies the area of ​​the storage array structure 103, thereby increasing the area of ​​the three-dimensional memory. The steps in the virtual step structure can be designed to be very steep to reduce the area occupied by the entire three-dimensional memory.

[0101] Furthermore, this invention also provides a method for manufacturing a stepped structure, used to create such a structure. Figures 3-5 The functional step structure 201 shown is as follows: Figures 3-13 As shown, it includes the following steps:

[0102] S1, Provide substrate 1;

[0103] S2. An initial stacked structure 2' is formed on the substrate 1. The initial stacked structure 2' is composed of multiple composite layers stacked together. The initial stacked structure 2' includes a first core region A1, a functional step region B, and a second core region A2 arranged sequentially along the first direction (i.e., the X-axis direction).

[0104] S3. Divide the functional step area B of the initial stacked structure 2' into multiple functional step partitions B1, B2, B3, B4, ... and Bm (m is an integer greater than or equal to 2) arranged at intervals in the second direction;

[0105] S4. Trim and etch the multiple functional step partitions B1, B2, B3, B4, ... and Bm of the initial stacked structure 2' respectively, and form a functional step structure 201 in each functional step partition Bi (i is an integer from 1 to m).

[0106] In detail, in step S1, the substrate 1 can be a single-crystal silicon substrate, Ge substrate, SiGe substrate, SOI substrate or GOI substrate, etc. The appropriate semiconductor material can be selected according to the actual needs of the device, and no limitation is made here.

[0107] In detail, in step S2, as Figure 6 As shown, step S2, which forms the initial stacked structure 2' on the substrate 1, includes:

[0108] Multiple dielectric layers 21 and gate layers 22 are alternately formed on substrate 1. One dielectric layer 21 and one gate layer 22 constitute a composite layer, that is, the initial stacked structure 2' is composed of a composite layer arranged in multiple stacks.

[0109] The number of dielectric layer 21 and gate layer 22 can be flexibly selected and designed as needed; dielectric layer 21 can be made of materials such as silicon oxide and silicon oxynitride, and gate layer 22 can be made of materials such as tantalum and tungsten.

[0110] Meanwhile, in step S2, as Figure 6 As shown, along the first direction, the initial stacked structure 2' is divided into a first core area A1, a functional step area B, and a second core area A2 arranged in sequence.

[0111] Specifically, in step S3, a barrier layer is first formed in the functional step region B, and then the barrier layer is etched to divide the functional step region B of the initial stacked structure 2', as follows: Figure 3As shown, the functional step partitions B1, B2, B3, B4, … and Bm are formed in a plurality of intervals in the second direction.

[0112] In more detail, as shown in Figure 3 and Figure 5 , the functional step partitions B1, B2, B3, B4, … and Bm divide the initial stack structure 2' into a first core structure 202, a second core structure 203, and a bridge structure 204, wherein the barrier layer on the bridge structure 204 is retained, and the barrier layer on the functional step partition Bi is etched and removed; the bridge structure 204 is connected with the first core area A1 and the second core area A2 of the initial stack structure 2' respectively, i.e. the bridge structure 204 is connected with the first core structure 202 and the second core structure 203 respectively, and two adjacent functional step partitions are separated by one bridge structure 204.

[0113] In detail, the step S4 of forming the functional step structure 201 in the functional step partition Bi by trimming etching includes:

[0114] S41, along the first direction, the functional step partition Bi is divided into a first functional step sub-partition Bi1 and a second functional step sub-partition Bi2, and the topmost composite layer in the second functional step sub-partition Bi2 is etched and removed;

[0115] S42, simultaneously trimming etching the first functional step sub-partition Bi1 and the second functional step sub-partition Bi2 using a plurality of mask groups, each etching simultaneously removing two layers of composite layers in the first functional step sub-partition Bi1 and the second functional step sub-partition Bi2, forming a first step structure 2011 in the first functional step sub-partition Bi1, and forming a second step structure 2012 in the second functional step sub-partition Bi2.

[0116] In more detail, in step S41, the functional step partition Bi is further divided into a first functional step sub-partition Bi1 and a second functional step sub-partition Bi2; at the same time, the first etching is performed using the mask M1, as shown in Figure 7 and Figure 8 , the topmost composite layer in the second functional step sub-partition Bi2 is removed, i.e. the topmost dielectric layer 21 and the gate layer 22 in the second functional step sub-partition Bi2 are removed, and the corresponding etching range can be referred to the first mask M1 shown in Figure 7 . In this way, the stack structure 2 in the first functional step sub-partition Bi1 and the second functional step sub-partition Bi2 differs by one layer of composite layer, facilitating subsequent synchronous etching of the first functional step sub-partition Bi1 and the second functional step sub-partition Bi2 to obtain two independent step structures that are staggered and asymmetrically arranged, i.e. as shown in Figure 4 and Figure 5The first step structure 2011 and the second step structure 2012 are shown.

[0117] More specifically, in step S42, multiple mask groups are used to perform step-by-step trimming etching on the functional step partition Bi. Each etching simultaneously removes two composite layers from a portion of the first functional step sub-partition Bi1 and a portion of the second functional step partition Bi2. The etching range of the step-by-step trimming etching gradually shrinks towards the middle of the stacked structure 2 along the first and second directions.

[0118] Each mask group includes multiple masks, and the multiple masks in each mask group gradually shrink towards the middle of the stacked structure 2 in the first direction and the second direction. In the stack plane (XY plane) of the stacked structure 2, the second direction (Y-axis direction) is perpendicular to the first direction (i.e., the X-axis direction).

[0119] In one embodiment of the present invention, such as Figure 7 As shown, masks M2, M3, M4, M5 and M6 constitute a mask group. Masks M2, M3, M4, M5 and M6 are nested and gradually shrink towards the middle of the stacked structure 2 in the X-axis and Y-axis directions.

[0120] like Figures 7-13 As shown, in one embodiment of the present invention, the detailed process of the step-by-step trimming and etching step S42 includes:

[0121] 1) First, such as Figure 7 and Figure 9 As shown, a portion of the first functional step sub-region Bi1 and a portion of the second functional step sub-region Bi2 are simultaneously etched using mask M2. The corresponding etching range can be found in [reference needed]. Figure 7 The mask M2 shown is used to etch away the two composite layers, as shown. Figure 9 As shown;

[0122] 2) Secondly, such as Figure 7 and Figure 10 As shown, a portion of the first functional step sub-region Bi1 and a portion of the second functional step sub-region Bi2 are simultaneously etched using mask M3. The corresponding etching range can be found in [reference needed]. Figure 7 The mask M3 shown is used to etch away the two composite layers, as follows: Figure 10 As shown;

[0123] 3) Again, such as Figure 7 and Figure 11 As shown, a portion of the first functional step sub-region Bi1 and a portion of the second functional step sub-region Bi2 are simultaneously etched using mask M4. The corresponding etching range can be found in [reference needed]. Figure 7 The mask M4 shown is used to etch away the two composite layers, as shown. Figure 11 As shown;

[0124] 4) From this point onward, such as Figure 7 and Figure 12 As shown, a portion of the first functional step sub-region Bi1 and a portion of the second functional step sub-region Bi2 are simultaneously etched using mask M5. The corresponding etching range can be found in [reference needed]. Figure 7 Mask M5 is shown; the two composite layers are etched away, as shown. Figure 12 As shown;

[0125] 5) Finally, such as Figure 7 and Figure 13 As shown, a portion of the first functional step sub-region Bi1 and a portion of the second functional step sub-region Bi2 are simultaneously etched using mask M6. The corresponding etching range can be found in [reference needed]. Figure 7 Mask M6 is shown; the two composite layers are etched away, as shown. Figure 13 As shown.

[0126] Ultimately, we obtained the following: Figure 4 or Figure 13 The functional step structure 201 shown includes a first step structure 2011 formed in a first functional step sub-partition Bi1, and a second step structure 2012 formed in a second functional step sub-partition Bi2; in detail, as shown... Figures 4-5 As shown, the first step structure 2011 and the second step structure 2012 include a plurality of first steps 201a extending along a first direction. The first step structure 2011 and the second step structure 2012 are staggered and asymmetrically arranged. That is, the first step 201a in the first step structure 2011 is composed of a composite layer with an even number of layers from bottom to top, and the first step 201a in the second step structure 2012 is composed of a composite layer with an odd number of layers from bottom to top.

[0127] Simultaneously, since the multiple masks in each mask group are nested and contracted not only in the first direction (i.e., the X-axis direction) but also in the second direction (i.e., the Y-axis direction), the first step structure 2011 and the second step structure 2012 not only form multiple first steps 201a extending along the first direction, such as... Figure 5 As shown, multiple steps 201b extending along the second direction are also formed.

[0128] More in detail, such as Figure 5As shown, the first step structure 2011 and the second step structure 2012 include a plurality of first steps 201a extending along a first direction and a plurality of second steps 201b extending along a second direction, each second step 201b is provided with a plurality of first steps 201a, and the top surface of each first step 201a exposes a layer of the gate layer 22; the top surfaces of the same level of first steps 201a in the first step structure 2011 and the second step structure 2012 have a height difference of a layer of the composite layer.

[0129] In more detail, as shown in Figure 3 and Figure 5 The functional step area B is divided into a plurality of mutually independent functional step sub-areas Bi along the Y-axis direction, and the etching of the functional step structure 201 is performed in each functional step sub-area Bi, that is, the functional step structure 201 in the functional step area B is still connected with the first core area A1 and the second core area A2 on both sides; the etching range of each step-by-step trimming etching gradually shrinks towards the center of the functional step area B along the X-axis and Y-axis directions, forming a double-step structure (i.e., the first step structure 2011 and the second step structure 2012) staggered in the X-axis direction and a symmetric double-step structure in the Y-axis direction.

[0130] Each functional step structure 201 includes two independent step structures (i.e., the first step structure 2011 and the second step structure 2012), which can reduce the volume of each independent step structure, reduce the stress influence of each independent step structure on the storage array structure, and improve the structural stability; at the same time, the partial trimming etching process of the two independent step structures can be implemented synchronously, which facilitates the reduction of the number of masks and the number of etching times, and reduces the production cost.

[0131] In more detail, as shown in Figure 5 and Figure 13 Since the functional step structure 201 is still connected with the first core area A1 and the second core area A2 on both sides (the first step structure 2011 is connected with the first core area A1, and the second step structure 2012 is connected with the second core area A2), the functional step structure 201 at the middle position (along the X-axis direction) and the bridge structure 204 can simultaneously drive the storage cell blocks Block formed in the first core area A1 and the second core area A2 on both sides, that is, the bilateral driving of the storage cell blocks Block is realized; according to the definition formula of resistance R = pL / S, with the obvious shortening of the transmission distance, the resistance when driving the storage cell blocks Block is reduced to less than half of that when driving unilaterally, which obviously improves the driving delay problem.

[0132] It can be understood that each functional step structure 201 can also include other numbers of independent step structures, such as one, three, etc., which will not be described here.

[0133] Further, based on the manufacturing method of the step structure, the application also provides a manufacturing method of a three-dimensional memory, as shown in the figure, which comprises the following steps: Figure 14

[0134] Stp1, providing a substrate 1;

[0135] Stp2, forming an initial stack structure 2' on the substrate 1, the initial stack structure 2' is stacked by a plurality of composite layers, and the stack structure 2 comprises a first core area A1, a functional step area B and a second core area A2 arranged in sequence along a first direction;

[0136] Stp3, dividing the functional step area B of the initial stack structure 2' to form a plurality of functional step subareas B1, B2, B3, B4, … and Bm arranged at intervals in a second direction;

[0137] Stp4, trimming and etching the plurality of functional step subareas B1, B2, B3, B4, … and Bm of the initial stack structure 2' respectively, and forming a functional step structure 201 in each functional step subarea Bi (i is an integer from 1 to m);

[0138] Stp5, forming a plurality of gate line separation structures extending through the initial stack structure 2' along the first direction in the initial stack structure 2' to segment the stack structure 2;

[0139] Stp6, forming a storage string in the first core area A1, the second core area A2 and the functional step area B of the initial stack structure 2' except the functional step subarea Bi to obtain a storage array structure;

[0140] Stp7, forming a conductive plug, the conductive plug is electrically connected with the top surface of the first step 201a.

[0141] Wherein, steps Stp1-S tp4 are the same as the manufacturing method of the step structure, the functional step structure 201 formed comprises a first step structure 2011 and a second step structure 2012 which are independent of each other, the first step structure 2011 and the second step structure 2012 comprise a plurality of first steps 201a extending along the first direction, and the top surface of each first step 201a exposes the gate layer 22; the manufacturing process of the storage array structure and the formation process of the gate line separation structure can refer to the prior art, and will not be described here.

[0142] In detail, the step Stp7 of forming the conductive plug comprises:

[0143] ​Stp71, forming a first conductive plug, the first conductive plug being electrically connected with the gate layer 22 exposed by the top surface of the first step 201a in the first step structure 2011;

[0144] Stp72, forming a second conductive plug, the second conductive plug being electrically connected with the gate layer 22 exposed by the top surface of the first step 201a in the second step structure 2012.

[0145] In step Stp7, before forming the first conductive plug and the second conductive plug, a dielectric layer is formed on the first core area A1, the functional step area B and the second core area A2, then a step contact hole is etched in the dielectric layer, the step contact hole being in communication with the top surface of the first step 201a, and finally the step contact hole is filled with conductive material to form the first conductive plug and the second conductive plug; wherein the plurality of first conductive plugs are electrically connected with the top surfaces of the plurality of first steps 201a in the first step structure 2011 one by one, and the plurality of second conductive plugs are electrically connected with the top surfaces of the plurality of first steps 201a in the second step structure 2012 one by one, so as to facilitate external control signals to drive and control the gate layer 22 exposed by the top surface of the first step 201a.

[0146] Wherein, other steps such as the manufacturing of the virtual step structure, the etching and filling of the step contact hole, the connection between the conductive plug and the control line, etc. can refer to the prior art, and will not be described here.

[0147] In summary, in the three-dimensional memory, the manufacturing method of the step structure and the manufacturing method of the three-dimensional memory provided by the application, through the functional step structure located in the stack structure and dividing the stack structure into the first core structure, the second core structure and the bridge structure, the double-side driving of the functional step structure to the two-side storage unit blocks is realized, the resistance when driving the storage unit block through the functional step structure is effectively reduced, and the driving delay problem is obviously improved. In addition, the functional step structure is designed as the first step structure and the second step structure staggered with each other, so that the functional step structure is divided into whole and parts, the volume of the functional step structure is reduced, the stress influence of the functional step structure on the first core structure and the second core structure is reduced, and the structural stability is improved. At the same time, the functional step structure is designed as the first step structure and the second step structure staggered with each other, so that synchronous trimming etching can be performed, the number of masks and the number of step trimming etching are reduced. Through the design of the very steep step in the virtual step structure arranged around the storage array structure, the occupied area of the whole three-dimensional memory can be reduced.

[0148] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A three-dimensional memory, comprising: The three-dimensional memory comprises: a stack structure composed of alternatingly stacked dielectric layers and gate layers, the stack structure comprising a first core structure and a second core structure; a functional step structure between the first core structure and the second core structure of the stack structure, the step structure comprising a first step structure and a second step structure, the first step structure and the second step structure being arranged along a first direction, the first step structure and the second step structure facing each other in the first direction, and a top surface of a same step in the first step structure and the second step structure being different in height in a stacking direction of the stack structure; a bridge structure arranged between the first core structure and the second core structure of the stack structure, a plurality of the functional step structures being arranged in sequence along a second direction, two adjacent functional step structures being separated by one bridge structure, and the first core structure and the second core structure being electrically connected through the bridge structure; wherein the second direction is perpendicular to the first direction, the first direction and the second direction form a stacking plane, and the stacking direction is perpendicular to the stacking plane; the first step structure and the second step structure each comprise a plurality of first steps extending along the first direction, a first step in the first step structure being electrically connected to the first core structure, and a first step in the second step structure being electrically connected to the second core structure.

2. The three-dimensional memory of claim 1, wherein, The three-dimensional memory further comprises: a storage string passing through the first core structure, the second core structure and the bridge structure along a direction opposite to the stacking direction.

3. The three-dimensional memory of claim 1, wherein, The three-dimensional memory further comprises: a first conductive plug electrically connected to the gate layers of the first step structure; a second conductive plug electrically connected to the gate layers of the second step structure.

4. The three-dimensional memory of claim 1, wherein, The three-dimensional memory further comprises a virtual step structure composed of the gate layers and the dielectric layers, the virtual step structure being arranged at an edge of the stack structure.

5. The three-dimensional memory of claim 1, wherein, A top surface of each first step is exposed to the gate layers; in the stacking direction of the stack structure, a top surface of a same first step in the first step structure and the second step structure is different in height.

6. The three-dimensional memory of claim 1, wherein, The first step structure and the second step structure each further comprise a plurality of second steps extending along the second direction.

7. The three-dimensional memory of claim 1, wherein, The three-dimensional memory further comprises a plurality of gate line separation structures passing through the stack structure and extending along the first direction, the plurality of gate line separation structures being arranged in intervals along the second direction.

8. A method of making a three-dimensional memory, comprising: The three-dimensional memory comprises: providing a substrate; forming an initial stack structure on the substrate, the initial stack structure being stacked by a plurality of composite layers, the initial stack structure comprising a first core region, a functional step region and a second core region arranged in sequence along a first direction; dividing the functional step region of the initial stack structure to form a plurality of functional step sub-regions arranged in intervals along a second direction, and the first core region and the second core region being electrically connected through a bridge structure between two adjacent functional step sub-regions; The plurality of functional step partitions of the initial stack structure are respectively subjected to trimming etching, the functional step partitions are divided into two sub-partitions along the first direction, one layer of the composite layer in one of the sub-partitions is etched first, and then the two sub-partitions are etched synchronously, two layers of the composite layer are removed each time the synchronous etching is performed, and one functional step structure is formed in each of the functional step partitions; the functional step structure comprises a first step structure and a second step structure, the first step structure and the second step structure face each other in the first direction, and the first step structure and the second step structure have a height difference in the top surfaces of the same step. The second direction is perpendicular to the first direction in the stacking plane of the initial stack structure.

9. The method of claim 8, wherein The manufacturing method of the three-dimensional memory further comprises the steps of: forming a plurality of gate line separation structures extending through the initial stack structure along the first direction in the initial stack structure, and dividing the initial stack structure; forming a storage string in the first core area, the second core area and the area other than the functional step partitions in the functional step area of the initial stack structure to obtain a storage array structure; forming a conductive plug, the conductive plug being electrically connected with the top surface of the first step.

10. The method of claim 9, wherein Each layer of the composite layer comprises a dielectric layer and a gate layer on the dielectric layer, and the step of forming the functional step structure in the functional step partition comprises: dividing the functional step partition into a first functional step sub-partition and a second functional step sub-partition along the first direction, and etching to remove the topmost layer of the composite layer in the second functional step sub-partition; trimming etching the first functional step sub-partition and the second functional step sub-partition simultaneously using a plurality of mask groups, removing two layers of the composite layer in the partial area of the first functional step sub-partition and the partial area of the second functional step sub-partition at the same time each time etching, forming a first step structure in the first functional step sub-partition, and forming a second step structure in the second functional step sub-partition; wherein each mask group comprises a plurality of masks, and the plurality of masks in each mask group gradually shrink towards the middle of the stack structure in the first direction and the second direction; the first step structure and the second step structure each comprise a plurality of first steps extending along the first direction, a first step in the first step structure is electrically connected with the first core area, and a first step in the second step structure is electrically connected with the second core area.

11. The method of claim 10, wherein: In the stacking direction of the stack structure, the top surfaces of the first steps of the same level in the first step structure and the second step structure have a height difference, the top surface of each first step exposes the gate layer, and the step of forming the conductive plug comprises: forming a first conductive plug, the first conductive plug being electrically connected with the gate layer exposed by the top surface of the first step in the first step structure; forming a second conductive plug, the second conductive plug being electrically connected with the gate layer exposed by the top surface of the first step in the second step structure.

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