Reset Circuit

Abstract

A reset circuit includes: a bias current generation unit, a voltage detection unit, a voltage generation unit, a comparison unit, and an output unit, wherein: The bias current generation unit has its output terminal coupled to the voltage generation unit, the voltage detection unit, and the comparison unit, and is adapted to generate a bias current according to a preset power supply voltage and output it; The voltage detection unit has its output terminal coupled to the voltage generation unit, and is adapted to control the output voltage of the first output terminal of the voltage generation unit to change accordingly when detecting a change in the power supply voltage; The voltage generation unit has its first output terminal coupled to the first input terminal of the comparison unit and its second output terminal coupled to the second input terminal of the comparison unit; The second output terminal of the voltage generation unit is adapted to output a reference voltage; The comparison unit has its output terminal coupled to the input terminal of the output unit; The output unit outputs a reset signal at its output terminal. The above solution can achieve a quick reset of the circuit system.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a reset circuit. Background Art

[0002] A reset circuit is an essential module circuit for modern integrated circuit chips and is a circuit used to restore the circuit to its initial state. There are many types of reset circuits, and the reset circuits that can operate independently and directly affect the initial state are mainly power-on reset and power-off reset. Power-on reset and power-off reset can enable the chip to achieve reliable reset in a complex electromagnetic environment and play a key role in the entire circuit system.

[0003] Traditional reset circuits generally cover one or two of fast power-on reset, slow power-on reset, fast power-off reset, and slow power-off reset. It is difficult to take into account various power-on and power-off application scenarios, and the reset reliability problem of incomplete power-off and then power-on cannot be solved. Power-on reset refers to the reset generated during the process from no power supply to normal power supply; power-off reset refers to the reset generated during processes such as power voltage drop and voltage oscillation. Summary of the Invention

[0004] The embodiments of the present invention solve the technical problem that a reset cannot be effectively generated in various power-on and power-off application scenarios, and particularly relate to the reset reliability problem of incomplete power-off and then power-on.

[0005] To solve the above technical problem, an embodiment of the present invention provides a reset circuit, including: a bias current generation unit, a voltage detection unit, a voltage generation unit, a comparison unit, and an output unit, where: the output end of the bias current generation unit is coupled to the voltage generation unit, the voltage detection unit, and the comparison unit, and is adapted to generate a bias current according to a preset power supply voltage and output it; the output end of the voltage detection unit is coupled to the voltage generation unit, and is adapted to control the output voltage of the first output end of the voltage generation unit to change correspondingly when detecting a change in the power supply voltage; the first output end of the voltage generation unit is coupled to the first input end of the comparison unit, and the second output end of the voltage generation unit is coupled to the second input end of the comparison unit; the second output end of the voltage generation unit is adapted to output a reference voltage; the output end of the comparison unit is coupled to the input end of the output unit; the output end of the output unit outputs a reset signal.

[0006] Optionally, the bias current generating unit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, where: for the first PMOS transistor, its gate is grounded, its drain is coupled to the drain of the first NMOS transistor, and its source is connected to the power supply voltage; for the second PMOS transistor, its gate is coupled to the first output terminal of the bias current generating unit, and its drain is coupled to the first output terminal of the bias current generating unit and the drain of the second NMOS transistor; for the first NMOS transistor, its gate is coupled to the second output terminal of the bias current generating unit and the drain of the first NMOS transistor, and its source is grounded; for the second NMOS transistor, its gate is coupled to the gate of the first NMOS transistor, and its source is grounded.

[0007] Optionally, the voltage detection unit includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a third PMOS transistor, and a first capacitor, where: for the third NMOS transistor, its gate and drain are connected to the power supply voltage, and its source is connected to the upper plate of the first capacitor; for the fourth NMOS transistor, its gate is coupled to the input terminal of the voltage detection unit, its drain is coupled to the drain of the third PMOS transistor, and its source is grounded; for the fifth NMOS transistor, its gate is coupled to the drain of the third PMOS transistor, its drain is coupled to the output terminal of the voltage detection unit, and its source is grounded; for the third PMOS transistor, its gate is connected to the power supply voltage, and its source is coupled to the source of the third NMOS transistor; for the first capacitor, its lower plate is grounded.

[0008] Optionally, the substrate of the third PMOS transistor is coupled to the source of the third NMOS transistor.

[0009] Optionally, the voltage generating unit includes: a reset signal triggering module and a reference voltage generating module, where: for the reset signal triggering module, its first input terminal is coupled to the first input terminal of the voltage generating unit, its second input terminal is coupled to the second input terminal of the voltage generating unit, and its output terminal is coupled to the first output terminal of the voltage generating unit; for the reference voltage generating module, its input terminal is coupled to the first input terminal of the voltage generating unit, and its output terminal is coupled to the second output terminal of the voltage generating unit.

[0010] Optionally, the reset signal triggering module includes: a fourth PMOS transistor, a fifth PMOS transistor, and a second capacitor, where: for the fourth PMOS transistor, its gate is coupled to the first input terminal of the reset signal triggering module, its drain is coupled to the source of the fifth PMOS transistor, and its source is connected to the power supply voltage; for the fifth PMOS transistor, its gate is coupled to its drain, and its drain is coupled to the output terminal of the reset signal triggering module and the second input terminal of the reset signal triggering module; for the second capacitor, its upper plate is coupled to the second input terminal of the reset signal triggering module, and its lower plate is grounded.

[0011] Optionally, the reference voltage generating circuit includes: a sixth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, where: for the sixth PMOS transistor, its gate is coupled to the input terminal of the reference voltage generating circuit, its drain is coupled to the second output terminal of the reference voltage generating circuit, and its source is connected to the power supply voltage; for the sixth NMOS transistor, its gate is coupled to its drain, its drain is further coupled to the drain of the sixth PMOS transistor, and its source is coupled to the drain of the seventh NMOS transistor; for the seventh NMOS transistor, its gate is coupled to its drain, and its source is grounded.

[0012] Optionally, the comparison unit includes: a comparison module and an amplification module, where: for the comparison module, its first input terminal is coupled to the first input terminal of the comparison unit, its second input terminal is coupled to the second input terminal of the comparison unit, its output terminal is coupled to the input terminal of the amplification module, and its control terminal is coupled to the second output terminal of the current biasing unit; for the amplification module, its output terminal is coupled to the output terminal of the comparison unit.

[0013] Optionally, the comparison module includes: a seventh PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor, where: for the seventh PMOS transistor, its gate is coupled to its drain, its source is connected to the power supply voltage, and its drain is further coupled to the drain of the eighth NMOS transistor; for the eighth PMOS transistor, its gate is coupled to the gate of the seventh PMOS transistor, and its drain is coupled to the drain of the ninth NMOS transistor and the output terminal of the comparison module; for the eighth NMOS transistor, its gate is coupled to the first input terminal of the comparison module, and its source is coupled to the drain of the tenth NMOS transistor; for the ninth NMOS transistor, its gate is coupled to the second input terminal of the comparison module, and its source is coupled to the drain connection of the tenth NMOS transistor; for the tenth NMOS transistor, its gate is coupled to the control terminal of the comparison module, and its source is grounded.

[0014] Optionally, the amplification module includes: a ninth PMOS tube, wherein: the ninth PMOS tube has a gate coupled to the input end of the amplification module, a drain coupled to the output end of the amplification module, and a source connected to the power supply voltage.

[0015] Optionally, the comparison unit further includes: an eleventh NMOS tube, a gate of which is coupled to the control end of the comparison module, a drain of which is coupled to the drain of the ninth PMOS tube, and a source of which is grounded.

[0016] Optionally, the output unit includes: an inverter, an input end of which is coupled to the input end of the output unit, and an output end of which is coupled to the output end of the inverter.

[0017] Optionally, the inverter includes: a tenth PMOS tube and a twelfth NMOS tube, wherein: the tenth PMOS tube has a gate coupled to the input end of the inverter, a drain coupled to the output end of the inverter, and a source connected to the power supply voltage; the twelfth NMOS tube has a gate coupled to the gate of the tenth PMOS tube, a drain coupled to the drain of the tenth PMOS tube, and a source connected to ground.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] The voltage detection unit detects the change of the power supply voltage, and adjusts the output voltage of the first output terminal of the voltage generating unit. Since the two output terminals of the voltage generating unit are respectively connected to the two input terminals of the comparison unit, the comparison unit essentially compares the output voltages of the two output terminals of the voltage generating unit. When the output voltage of the first output terminal of the voltage generating unit changes, the comparison result output by the comparison unit changes accordingly, thereby generating a reset signal according to the change of the power supply voltage. The above reset circuit can respond quickly to the change of the power supply voltage, whether it is for fast power-on reset, slow power-on reset, fast power-off reset, or slow power-off reset, it can achieve fast and effective reset.

[0020] Furthermore, by setting a second capacitor, a delayed reset can be achieved. The second capacitor is charged by the second bias current, and the time when the upper plate voltage of the second capacitor reaches the output voltage of the second output terminal of the voltage generating unit from 0 can be regarded as the delayed reset time. By controlling the size of the second bias current and the size of the second capacitor, the delayed reset time can be adjusted accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the structure of a reset circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] As described above, the existing reset circuit cannot cover various power-on and power-off application scenarios in actual applications, and cannot achieve reset quickly and effectively.

[0023] In an embodiment of the present invention, the voltage detection unit detects the change of the power supply voltage, and adjusts the output voltage of the first output terminal of the voltage generation unit. Since the two output terminals of the voltage generation unit are respectively connected to the two input terminals of the comparison unit, the comparison unit essentially compares the output voltages of the two output terminals of the voltage generation unit. When the output voltage of the first output terminal of the voltage generation unit changes, the comparison result output by the comparison unit changes accordingly, thereby generating a reset signal according to the change of the power supply voltage. The above reset circuit can respond quickly to the change of the power supply voltage, whether it is for fast power-on reset, slow power-on reset, fast power-off reset, or slow power-off reset, it can achieve fast and effective reset.

[0024] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] The embodiment of the present invention provides a reset circuit, referring to Figure 1 , the reset circuit provided by the embodiment of the present invention is described in detail below.

[0026] In a specific implementation, the reset circuit may include: a bias current generating unit 11 , a voltage detecting unit 12 , a voltage generating unit 13 , a comparing unit 14 and an output unit 15 .

[0027] In the embodiment of the present invention, the output end of the bias current generating unit 11 is coupled to the voltage generating unit 13, the voltage detecting unit 12 and the comparing unit 14, and can generate a corresponding bias current according to the change of the power supply voltage VCC, thereby providing a bias current for the voltage detecting unit 12, the comparing unit 14, etc. The magnitude of the bias current is related to the power supply voltage VCC. When the power supply voltage VCC changes, the bias current will change accordingly.

[0028] The output terminal of the voltage detection unit 12 may be coupled to the voltage generation unit 13. When the voltage detection unit 12 detects that the power supply voltage VCC changes, the output voltage of the first output terminal of the voltage generation unit 13 may be controlled to change accordingly.

[0029] The first output terminal of the voltage generating unit 13 is coupled to the first input terminal of the comparison unit 14 , and the second output terminal of the voltage generating unit 13 is coupled to the second input terminal of the comparison unit 14 ; the second output terminal of the voltage generating unit 13 can output a reference voltage of a fixed value.

[0030] The first input terminal of the comparison unit 14 is coupled to the first output terminal of the voltage generation unit 13, the second input terminal of the comparison unit 14 is coupled to the second output terminal of the voltage generation unit 13, and the output terminal of the comparison unit 14 is coupled to the input terminal of the output unit 15; the comparison unit 14 can compare the output voltage of the first output terminal of the voltage generation unit 13 with the output voltage of the second output terminal of the voltage generation unit 13 to obtain a comparison result.

[0031] The output unit 15 performs an inverting process on the received comparison result output by the comparison unit 14, and the output terminal of the output unit 15 outputs the finally obtained reset signal.

[0032] The voltage detection unit 12 detects a change in the power supply voltage VCC and adjusts the output voltage of the first output terminal of the voltage generation unit 13. Since the two output terminals of the voltage generation unit 13 are respectively connected to the two input terminals of the comparison unit 14, the comparison unit 14 is essentially comparing the output voltages of the two output terminals of the voltage generation unit 13. When the output voltage of the first output terminal of the voltage generation unit 13 changes, the comparison result output by the comparison unit 14 changes accordingly, so as to generate a reset signal correspondingly according to the change of the power supply voltage VCC. The above reset circuit can quickly respond to the change of the power supply voltage VCC and achieve effective reset.

[0033] Next, the specific structure of the reset circuit provided in the above embodiment of the present invention will be described in detail.

[0034] In the embodiment of the present invention, the bias current generation unit 11 may include a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2, where:

[0035] The gate of the first PMOS transistor MP1 can be grounded to GND, the drain of the first PMOS transistor MP1 can be coupled to the drain of the first NMOS transistor MN1, and the source of the first PMOS transistor MP1 can be connected to the power supply voltage VCC;

[0036] The gate of the second PMOS transistor MP2 can be coupled to the first output terminal of the bias current generation unit 11, the drain of the second PMOS transistor MP2 can be coupled to the gate of the second PMOS transistor MP2, the first output terminal of the bias current generation unit 11, and the drain of the second NMOS transistor MN2; the drain voltage of the second PMOS transistor MP2 is VB2;

[0037] The gate of the first NMOS transistor MN1 can be coupled to the second output terminal of the bias current generation unit 11, and the gate of the first NMOS transistor MN1 is coupled to the drain of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 can be grounded to GND; the drain voltage of the first NMOS transistor is VB1;

[0038] The gate of the second NMOS transistor MN2 can be coupled to the gate of the first NMOS transistor MN1 and the second output terminal of the bias current generating unit 11, and the source of the second NMOS transistor MN2 can be grounded to GND.

[0039] The first PMOS transistor MP1 can be a PMOS transistor with a large aspect ratio. For example, the aspect ratio of the first PMOS transistor MP1 is 1:1000. The first PMOS transistor MP1 can be equivalent to a large resistor.

[0040] It should be noted that Figure 1 only one first PMOS transistor MP1 is exemplarily drawn in []. In specific applications, the first PMOS transistor MP1 can also be composed of multiple PMOS transistors connected in series. The aspect ratio of the first PMOS transistor MP1 can also be other values, not limited to the above examples.

[0041] The gate of the first NMOS transistor MN1 is connected to the drain of the first NMOS transistor MN1 to form a diode connection. An NMOS ultra-low current current source is formed by the equivalent large resistor of the first PMOS transistor MP1 and the first NMOS transistor MN1, and the second bias current is output via the second output terminal of the bias current generating unit 11.

[0042] The gate of the second PMOS transistor MP2 is coupled to the drain of the second PMOS transistor MP2 to form a diode connection. The drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2 and the gate of the second PMOS transistor MP2. Folding is achieved through the second NMOS transistor MN2 and the second PMOS transistor MP2 to form a PMOS ultra-low current current source, and the first bias current is output via the first output terminal of the bias current generating unit 11.

[0043] In the embodiment of the present invention, there is no substantial difference between the first bias current and the second bias current. After the second PMOS transistor MP2 forms a current mirror with the corresponding PMOS transistor in the voltage generating unit 13, the generated first bias current powers the corresponding PMOS transistor; after the second NMOS transistor MN2 forms a current mirror with the corresponding NMOS transistor in the voltage detecting unit 12 and the corresponding NMOS transistor in the comparing unit 14, the generated second bias current powers the corresponding NMOS transistor.

[0044] In the embodiment of the present invention, to meet the requirement of low power consumption, the bias current output by the bias current generating circuit can be as low as the nanoampere (nA) level.

[0045] In specific implementation, the power-down detection circuit can detect whether the power supply voltage VCC drops rapidly, that is, detect whether the power supply voltage VCC decreases rapidly.

[0046] In an embodiment of the present invention, the power-off detection circuit may include: a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a third PMOS transistor MP3, and a first capacitor C1, where:

[0047] The gate of the third NMOS transistor MN3 is connected to the power supply voltage VCC, the drain of the third NMOS transistor MN3 is connected to the power supply voltage VCC, and the source of the third NMOS transistor MN3 is connected to the upper plate of the first capacitor C1;

[0048] The lower plate of the first capacitor C1 is grounded to GND;

[0049] The gate of the fourth NMOS transistor MN4 is coupled to the input terminal of the voltage detection unit 12. The drain of the fourth NMOS transistor MN4 is coupled to the drain of the third PMOS transistor MP3 and the drain of the fifth NMOS transistor MN5. The source of the fourth NMOS transistor MN4 is grounded to GND. The fourth NMOS transistor MN4 and the second output terminal of the bias current generation unit 11 form a current mirror, that is, the second NMOS transistor MN2 and the fourth NMOS transistor MN4 form a current mirror, and the second bias current supplies power to the fourth NMOS transistor MN4;

[0050] The drain of the fifth NMOS transistor MN5 is coupled to the output terminal of the voltage detection unit 12, and the source of the fifth NMOS transistor MN5 is grounded to GND;

[0051] The gate of the third PMOS transistor MP3 is connected to the power supply voltage VCC. The drain of the third PMOS transistor MP3 is coupled to the drain of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5. The source of the third PMOS transistor MP3 is coupled to the source of the third NMOS transistor MN3.

[0052] In an embodiment of the present invention, the voltage input at the source of the third NMOS transistor MN3 is marked as VX1. Since the gate of the fourth NMOS transistor MN4 is coupled to the input terminal of the voltage detection unit 12, that is, the gate of the fourth NMOS transistor MN4 is coupled to the second output terminal of the bias current generation unit 11, the fourth NMOS transistor MN4 provides a second bias current for the third PMOS transistor MP3, and the drain voltage of the third PMOS transistor MP3 is marked as VX2.

[0053] The gate voltage of the fifth NMOS transistor MN5 is VX2. The source of the fifth NMOS transistor MN5 is grounded to GND, and the voltage output from the drain of the fifth NMOS transistor MN5 is marked as VX3. When the power supply voltage VCC drops rapidly, since the voltage of the first capacitor C1 does not change suddenly, the source voltage VX1 of the third NMOS transistor MN3 remains unchanged; while the gate voltage of the third PMOS transistor MP3 drops, causing the third PMOS transistor MP3 to conduct. The drain voltage of the third PMOS transistor MP3 rises from 0V. When it rises to the turn-on threshold voltage of the fifth NMOS transistor MN5, the fifth NMOS transistor MN5 conducts.

[0054] In a specific implementation, the voltage generation unit 13 may include a reset signal triggering module and a reference voltage generation module, where:

[0055] The first input terminal of the reset signal triggering module is coupled to the first input terminal of the voltage generation unit 13, that is, the first input terminal of the reset signal triggering module is coupled to the first output terminal of the bias current generation unit 11; the second input terminal of the reset signal triggering module is coupled to the second input terminal of the voltage generation unit 13, that is, the second input terminal of the reset signal triggering module is coupled to the output terminal of the voltage detection unit 12; the output terminal of the reset signal triggering module is coupled to the first output terminal of the voltage generation unit 13, that is, the output terminal of the reset signal triggering module is coupled to the first input terminal of the comparison unit 14;

[0056] The input terminal of the reference voltage generation module is coupled to the first input terminal of the voltage generation unit 13, that is, the input terminal of the reference voltage generation module is coupled to the first output terminal of the bias current generation unit 11; the output terminal of the reference voltage generation module is coupled to the second output terminal of the voltage generation unit 13, that is, the output terminal of the reference voltage generation module is coupled to the second input terminal of the comparison unit 14. The reference voltage generation module can generate a reference voltage with a fixed value.

[0057] In an embodiment of the present invention, the reset signal triggering module may include: a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a second capacitor C2, where:

[0058] The source of the fourth PMOS transistor MP4 is connected to the power supply voltage VCC. The gate of the fourth PMOS transistor MP4 is coupled to the first input terminal of the voltage generation unit 13. The drain of the fourth PMOS transistor MP4 is coupled to the source of the fifth PMOS transistor MP5;

[0059] The gate of the fifth PMOS transistor MP5 is coupled to the drain of the fifth PMOS transistor MP5, and the drain of the fifth PMOS transistor MP5 is coupled to the first output terminal of the voltage generation unit 13, the second input terminal of the voltage generation unit 13, and the upper plate of the second capacitor C2;

[0060] The lower plate of the second capacitor C2 is grounded to GND; the voltage of the upper plate of the second capacitor C2 is marked as VX3.

[0061] The gate of the fifth PMOS transistor MP5 is coupled to the drain of the fifth PMOS transistor MP5, forming a diode structure and connected to the upper plate of the second capacitor C2. The fourth PMOS transistor MP4 and the first output terminal of the bias current generation unit 11 form a current mirror, and the first bias current flows through the fifth PMOS transistor MP5 to the upper plate of the second capacitor C2. The voltage of the upper plate of the second capacitor C2 is marked as VX3. When the fifth NMOS transistor MN5 is turned on, the charge stored in the second capacitor C2 is released, and the voltage VX3 of the upper plate of the second capacitor C2 rapidly decreases to 0V.

[0062] In a specific implementation, by setting the second capacitor C2, a delay reset can be achieved. The time for the voltage of the upper plate of the second capacitor C2 to reach the output voltage of the second output terminal of the voltage generation unit 13 from 0V when charged by the second bias current can be regarded as the delay reset time. By controlling the magnitude of the second bias current and the size of the second capacitor C2, the delay reset time can be adjusted accordingly.

[0063] In an embodiment of the present invention, the reference voltage generation module may include: a sixth PMOS transistor MP6, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7, where:

[0064] The gate of the sixth PMOS transistor MP6 is coupled to the input terminal of the reference voltage generation module, the drain of the sixth PMOS transistor MP6 is coupled to the second output terminal of the voltage generation unit 13 and the drain of the sixth NMOS transistor MN6, and the source of the sixth PMOS transistor MP6 is connected to the power supply voltage VCC; the sixth PMOS transistor MP6 and the first output terminal of the bias current generation unit 11 form, that is, the second PMOS transistor MP2 and the sixth PMOS transistor MP6 form a current mirror, that is, the first bias current supplies power to the sixth PMOS transistor MP6;

[0065] The gate of the sixth NMOS transistor MN6 is coupled to the drain of the sixth NMOS transistor MN6, and the source of the sixth NMOS transistor MN6 is coupled to the drain of the seventh NMOS transistor MN7;

[0066] The gate of the seventh NMOS transistor MN7 is coupled to the drain of the seventh NMOS transistor MN7, and the source of the seventh NMOS transistor MN7 is grounded to GND.

[0067] In an embodiment of the present invention, the gate of the sixth NMOS transistor MN6 is coupled to the drain of the sixth NMOS transistor MN6 to form a diode structure. The gate of the seventh NMOS transistor MN7 is coupled to the drain of the seventh NMOS transistor MN7 to form a diode structure. Therefore, the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 can be equivalent to two diodes connected in series. Mark the drain voltage of the sixth PMOS transistor MP6 as VX4, that is, the reference voltage generated by the reference voltage generation module is VX4.

[0068] In a specific implementation, the comparator may include a comparison module and an amplification module, where:

[0069] The first input terminal of the comparison module is coupled to the first input terminal of the comparison unit 14, and the first input terminal of the comparison module can be regarded as the first input terminal of the comparison unit 14; the second input terminal of the comparison module is coupled to the second input terminal of the comparison module, and the second input terminal of the comparison module can be regarded as the second input terminal of the comparison unit 14; the output terminal of the comparison module is coupled to the input terminal of the amplification module, the control terminal of the comparison module is coupled to the control terminal of the comparison unit 14, and the control terminal of the comparison unit 14 is coupled to the second output terminal of the current bias power supply;

[0070] The output terminal of the amplification module can be coupled to the output terminal of the comparison unit 14, that is, the output terminal of the amplification module is regarded as the output terminal of the comparison unit 14.

[0071] In an embodiment of the present invention, the comparison module may include: a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, and a tenth NMOS transistor MN10, where:

[0072] The source of the seventh PMOS transistor MP7 is connected to the power supply voltage VCC, the gate of the seventh PMOS transistor MP7 is coupled to the gate of the eighth PMOS transistor MP8 and the drain of the seventh PMOS transistor MP7, and the drain of the seventh PMOS transistor MP7 is coupled to the drain of the eighth NMOS transistor MN8;

[0073] The source of the eighth PMOS transistor MP8 is connected to the power supply voltage VCC, the gate of the eighth PMOS transistor MP8 is coupled to the gate of the seventh PMOS transistor MP7, and the drain of the eighth PMOS transistor MP8 is coupled to the output terminal of the comparator and the drain of the ninth NMOS transistor MN9; the drain voltage of the eighth PMOS transistor MP8 is marked as VX5;

[0074] The gate of the eighth NMOS transistor MN8 is coupled to the first input terminal of the comparator, and the source of the eighth NMOS transistor MN8 is coupled to the drain of the tenth NMOS transistor MN10;

[0075] The gate of the ninth NMOS transistor MN9 is coupled to the second input terminal of the comparator, and the source of the ninth NMOS transistor MN9 is coupled to the drain of the tenth NMOS transistor MN10;

[0076] The source of the tenth NMOS transistor MN10 is grounded to GND; the tenth NMOS transistor MN10 is formed with the second output terminal of the bias current generation unit 11, that is, the second NMOS transistor MN2 and the tenth NMOS transistor MN10 form a current mirror, that is, the tenth NMOS transistor MN10 is powered by the second bias current.

[0077] In an embodiment of the present invention, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 form a differential pair, and the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 form an active current mirror.

[0078] In an embodiment of the present invention, the amplification module may include a ninth PMOS transistor MP9. The gate of the ninth PMOS transistor MP9 may be coupled to the input terminal of the amplification module, that is, the gate of the ninth PMOS transistor MP9 is regarded as the input terminal of the amplification module; the drain of the ninth PMOS transistor MP9 is coupled to the output terminal of the amplification module, and the drain of the ninth PMOS transistor MP9 can be regarded as the output terminal of the amplification module, and the source of the ninth PMOS transistor MP9 is connected to the power supply voltage VCC.

[0079] The drain voltage of the ninth PMOS transistor MP9 is labeled as VX6.

[0080] In an embodiment of the present invention, the comparison unit 14 may further include an eleventh NMOS transistor MN11. The gate of the eleventh NMOS transistor MN11 is coupled to the control terminal of the comparison module, the drain of the eleventh NMOS transistor MN11 is coupled to the drain of the ninth PMOS transistor MP9, and the source of the eleventh NMOS transistor MN11 is grounded to GND. The eleventh NMOS transistor MN11 is formed with the second output terminal of the bias current generation unit 11, that is, the second NMOS transistor MN2 and the eleventh NMOS transistor MN11 form a current mirror, that is, the eleventh NMOS transistor MN11 is powered by the first bias current.

[0081] In a specific implementation, the output unit 15 may include an inverter. The input terminal of the inverter is the input terminal of the output unit 15, and the output terminal of the inverter is the output terminal of the output unit 15. Through the inverter, the output of the comparison unit 14 is inverted.

[0082] Since digital circuits usually use low-level reset, the output of the previous stage module (i.e., the comparison unit 14) shows high-level reset. By adding an inverter, the final output shows low-level reset, thus ensuring the consistency of the entire reset circuit.

[0083] In an embodiment of the present invention, the inverter may include a tenth PMOS transistor MP10 and a twelfth NMOS transistor MN12, where:

[0084] The gate of the tenth PMOS transistor MP10 is coupled to the input terminal of the inverter, the drain of the tenth PMOS transistor MP10 is coupled to the output terminal of the inverter, and the source of the tenth PMOS transistor MP10 is connected to the power supply voltage VCC;

[0085] The gate of the twelfth NMOS transistor MN12 is coupled to the gate of the tenth PMOS transistor MP10, the drain of the twelfth NMOS transistor MN12 is coupled to the drain of the tenth PMOS transistor MP10, and the source of the twelfth NMOS transistor MN12 is grounded to GND.

[0086] That is to say, the gates of the tenth PMOS transistor MP10 and the twelfth NMOS transistor MN12 are both coupled to the input terminal of the inverter, and the drains of the tenth PMOS transistor MP10 and the twelfth NMOS transistor MN12 are both coupled to the output terminal of the inverter.

[0087] In an embodiment of the present invention, except that the substrate of the third PMOS transistor MP3 is coupled to the source of the third NMOS transistor MN3, the substrates of the remaining PMOS transistors (the first PMOS transistor MP1 to the second PMOS transistor MP2 and the fourth PMOS transistor MP4 to the tenth PMOS transistor MP10) are all connected to the power supply, and the substrates of the remaining NMOS transistors (the first NMOS transistor MN1 to the second NMOS transistor MN2 and the fourth NMOS transistor MN4 to the twelfth NMOS transistor MN12) are all grounded.

[0088] The specific working principle of the reset circuit provided in the above embodiment of the present invention will be described below.

[0089] The comparison unit 14 compares VX3 with VX4. When VX3 > VX4, VX5 is at a high level, VX6 is at a low level, and the output reset signal RESET is at a high level. When VX3 < VX4, VX5 is at a low level, VX6 is at a high level, and the output reset signal RESET is at a low level. When the reset signal RESET is at a low level, it indicates that the device is in the reset state; when the reset signal RESET is at a high level, it indicates that the reset is completed.

[0090] For the fast power-on scenario of the power supply voltage VCC:

[0091] The time for the power supply voltage VCC to complete power-on is at the microsecond (μs) level. As the power supply voltage VCC powers on, the bias current generation circuit starts to work synchronously, outputting the first bias current and the second bias current. The reference voltage generation module in the voltage generation unit 13 generates a stable reference voltage VX4. At the same time, the second bias current charges the second capacitor C2, causing the voltage VX3 of the upper plate of the second capacitor C2 to slowly rise from 0V. After a certain charging process, the voltage VX3 of the upper plate of the second capacitor C2 exceeds the reference voltage VX4, and the reset signal RESET becomes high level, completing the fast power-on reset.

[0092] For the scenario of fast power-on after the power supply voltage VCC quickly and incompletely powers off:

[0093] The power supply voltage VCC quickly and incompletely powering off means that the power supply voltage VCC has a power-off voltage difference of about 1V and does not drop to 0V potential. The power supply voltage VCC quickly and completely powering off means that the power supply voltage VCC quickly powers off to 0V potential. For the reset circuit, if it can achieve reset during incomplete power-off, then it can also achieve reset during complete power-off. Therefore, in the embodiments of the present invention, the scenario of the power supply voltage VCC quickly and incompletely powering off is considered.

[0094] In the stage of fast and incomplete power-off, after the power supply voltage VCC quickly powers off, VX1 remains unchanged, the third PMOS transistor MP3 conducts, causing VX2 to quickly jump to be approximately equal to VX1. Then, the fifth NMOS transistor MN5 conducts, quickly releasing the charge stored in the second capacitor C2, causing VX3 to quickly drop to 0V, and the reset signal RESET quickly switches to low level.

[0095] In the stage of fast power-on, the third PMOS transistor MP3 is cut off, the fourth NMOS transistor MN4 conducts, quickly reducing VX2 to 0V. VX4 remains unchanged, and the second capacitor C2 is charged through the second bias current, causing the voltage VX3 of the upper plate of the second capacitor C2 to slowly rise from 0V. After a certain charging process, the voltage VX3 of the upper plate of the second capacitor C2 exceeds the reference voltage VX4, and the reset signal RESET becomes high level, completing the fast power-on reset.

[0096] For the scenario of slow power-on after fast and incomplete power-off:

[0097] In the embodiments of the present invention, slow power-on after fast and incomplete power-off may mean that after fast and incomplete power-off, the power supply voltage VCC remains stable and then powers on at the millisecond (ms) level after a period of time.

[0098] During the fast incomplete power-down phase, after the power supply voltage VCC drops rapidly, VX1 remains unchanged, the third PMOS transistor MP3 conducts, causing VX2 to quickly jump to approximately the same value as VX1. After that, the fifth NMOS transistor MN5 conducts, quickly discharging the charge stored in the second capacitor C2, causing VX3 to quickly drop to 0V, and the reset signal RESET quickly switches to the low level.

[0099] During the slow power-up phase, when the power supply voltage VCC rises to a certain value, the third PMOS transistor MP3 turns off, the fourth NMOS transistor MN4 conducts, and VX2 quickly drops to 0V. VX4 remains unchanged, and the second capacitor C2 is charged through the second bias current, causing the voltage VX3 of the upper plate of the second capacitor C2 to slowly rise from 0V. After a certain charging process, the voltage VX3 of the upper plate of the second capacitor C2 exceeds the reference voltage VX4, and the reset signal RESET is at the high level, completing the slow power-up reset.

[0100] For the scenario of slow power-up after slow power-down:

[0101] During the slow power-down phase, when the power supply voltage VCC drops to a certain value, the third PMOS transistor MP3 conducts, and the voltage VX3 of the upper plate of the second capacitor C2 maintains a 0V potential.

[0102] During the slow power-up phase, when the power supply voltage VCC rises to a certain value, the third PMOS transistor MP3 turns off, the fourth NMOS transistor MN4 conducts, and VX2 quickly drops to 0V. VX4 remains unchanged, and the second capacitor C2 is charged through the second bias current, causing the voltage VX3 of the upper plate of the second capacitor C2 to slowly rise from 0V. After a certain charging process, the voltage VX3 of the upper plate of the second capacitor C2 exceeds the reference voltage VX4, and the reset signal RESET is at the high level, completing the slow power-up reset.

[0103] In summary, the reset circuit provided by the embodiment of the present invention can cover all scenarios of fast power-up reset, slow power-up reset, fast power-down reset, slow power-down reset, and incomplete power-down and then power-up.

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A reset circuit, characterized in that, it includes: a bias current generation unit, a voltage detection unit, a voltage generation unit, a comparison unit, and an output unit, where: the bias current generation unit, its output terminal is coupled to the voltage generation unit, the voltage detection unit, and the comparison unit, and is adapted to generate and output a bias current according to a preset power supply voltage; the voltage detection unit, its output terminal is coupled to the voltage generation unit, and is adapted to control the output voltage of the first output terminal of the voltage generation unit to change accordingly when detecting a change in the power supply voltage; the voltage detection unit includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a third PMOS transistor, and a first capacitor, where: for the third NMOS transistor, its gate and its drain are connected to the power supply voltage, and its source is connected to the upper plate of the first capacitor; for the fourth NMOS transistor, its gate is coupled to the input terminal of the voltage detection unit, its drain is coupled to the drain of the third PMOS transistor, and its source is grounded; for the fifth NMOS transistor, its gate is coupled to the drain of the third PMOS transistor, its drain is coupled to the output terminal of the voltage detection unit, and its source is grounded; for the third PMOS transistor, its gate is connected to the power supply voltage, and its source is coupled to the source of the third NMOS transistor; for the first capacitor, its lower plate is grounded; the voltage generation unit, its first output terminal is coupled to the first input terminal of the comparison unit, and its second output terminal is coupled to the second input terminal of the comparison unit; the second output terminal of the voltage generation unit is adapted to output a reference voltage; the voltage generation unit includes a reset signal trigger module and a reference voltage generation module, where: for the reset signal trigger module, its first input terminal is coupled to the first input terminal of the voltage generation unit, its second input terminal is coupled to the second input terminal of the voltage generation unit, and its output terminal is coupled to the first output terminal of the voltage generation unit; for the reference voltage generation module, its input terminal is coupled to the first input terminal of the voltage generation unit, and its output terminal is coupled to the second output terminal of the voltage generation unit; the reset signal trigger module includes: a fourth PMOS transistor, a fifth PMOS transistor, and a second capacitor, where: for the fourth PMOS transistor, its gate is coupled to the first input terminal of the reset signal trigger module, its drain is coupled to the source of the fifth PMOS transistor, and its source is connected to the power supply voltage; for the fifth PMOS transistor, its gate is coupled to its drain, and its drain is coupled to the output terminal of the reset signal trigger module and the second input terminal of the reset signal trigger module; for the second capacitor, its upper plate is coupled to the second input terminal of the reset signal trigger module, and its lower plate is grounded; the comparison unit, its output terminal is coupled to the input terminal of the output unit; the output unit, its output terminal outputs a reset signal.

2. The reset circuit according to claim 1, characterized in that, the bias current generation unit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, where: The first PMOS transistor has its gate grounded, its drain coupled to the drain of the first NMOS transistor, and its source connected to the power supply voltage; The second PMOS transistor has its gate coupled to the first output terminal of the bias current generating unit, and its drain coupled to the first output terminal of the bias current generating unit and the drain of the second NMOS transistor; The first NMOS transistor has its gate coupled to the second output terminal of the bias current generating unit and the drain of the first NMOS transistor, and its source grounded; The second NMOS transistor has its gate coupled to the gate of the first NMOS transistor, and its source grounded.

3. The reset circuit according to claim 1, characterized in that the substrate of the third PMOS transistor is coupled to the source of the third NMOS transistor.

4. The reset circuit according to claim 1, characterized in that the reference voltage generating circuit includes: a sixth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, wherein: The sixth PMOS transistor has its gate coupled to the input terminal of the reference voltage generating circuit, its drain coupled to the second output terminal of the reference voltage generating circuit, and its source connected to the power supply voltage; The sixth NMOS transistor has its gate coupled to its drain, and its drain is also coupled to the drain of the sixth PMOS transistor, and its source is coupled to the drain of the seventh NMOS transistor; The seventh NMOS transistor has its gate coupled to its drain, and its source grounded.

5. The reset circuit according to claim 1, characterized in that the comparison unit includes: a comparison module and an amplification module, wherein: The comparison module has its first input terminal coupled to the first input terminal of the comparison unit, its second input terminal coupled to the second input terminal of the comparison unit, its output terminal coupled to the input terminal of the amplification module, and its control terminal coupled to the second output terminal of the bias current generating unit; The amplification module has its output terminal coupled to the output terminal of the comparison unit.

6. The reset circuit according to claim 5, characterized in that the comparison module includes: a seventh PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor, wherein: The seventh PMOS transistor has its gate coupled to its drain, its source connected to the power supply voltage, and its drain also coupled to the drain of the eighth NMOS transistor; The eighth PMOS transistor has its gate coupled to the gate of the seventh PMOS transistor, and its drain coupled to the drain of the ninth NMOS transistor and the output terminal of the comparison module; The eighth NMOS transistor has its gate coupled to the first input terminal of the comparison module, and its source coupled to the drain of the tenth NMOS transistor; The ninth NMOS transistor has its gate coupled to the second input terminal of the comparison module, and its source coupled to the drain of the tenth NMOS transistor; The tenth NMOS transistor has its gate coupled to the control terminal of the comparison module, and its source grounded.

7. The reset circuit according to claim 5, characterized in that the amplification module includes: a ninth PMOS transistor, wherein: The ninth PMOS transistor has its gate coupled to the input terminal of the amplification module, its drain coupled to the output terminal of the amplification module, and its source connected to the power supply voltage.

8. The reset circuit according to claim 7, wherein, the comparison unit further includes: an eleventh NMOS transistor, whose gate is coupled to the control terminal of the comparison module, whose drain is coupled to the drain of the ninth PMOS transistor, and whose source is grounded.

9. The reset circuit according to claim 1, wherein, the output unit includes: an inverter, whose input terminal is coupled to the input terminal of the output unit, and whose output terminal is coupled to the output terminal of the inverter.

10. The reset circuit according to claim 9, wherein, the inverter includes: a tenth PMOS transistor and a twelfth NMOS transistor, wherein: for the tenth PMOS transistor, its gate is coupled to the input terminal of the inverter, its drain is coupled to the output terminal of the inverter, and its source is connected to the power supply voltage; for the twelfth NMOS transistor, its gate is coupled to the gate of the tenth PMOS transistor, its drain is coupled to the drain of the tenth PMOS transistor, and its source is grounded.

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