Three-dimensional memory devices and methods for forming the same

Abstract

In some aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with a source end of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure in the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

Description

BACKGROUND

[0001] The present disclosure relates to a memory device and a method of manufacturing the same.

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technology become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells. A 3D memory architecture includes a storage array and a peripheral circuit to facilitate operation of the storage array. SUMMARY

[0004] In an aspect of the disclosure, a 3D memory device includes a first semiconductor structure and a second semiconductor bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with a source terminal of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure in the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

[0005] In another aspect of the disclosure, a 3D memory device includes a first semiconductor structure having a core region and a non-array region. The first semiconductor structure includes an array of NAND memory strings in a sub-region of the core region, a semiconductor layer in contact with a source terminal of the array of NAND memory strings, an insulating layer in the non-array region, and a plurality of contact structures in the insulating layer and in another sub-region of the non-array region. The insulating layer electrically insulates the contact structures from the semiconductor layer. The 3D memory device also includes a second semiconductor structure bonded with the first semiconductor layer. The second semiconductor structure includes a transistor.

[0006] In another aspect of the disclosure, a method for forming a 3D memory device is provided. The method includes bonding a first semiconductor structure and a second semiconductor structure together, the first semiconductor structure having a core region and a non-array region. The method also includes depositing a doped amorphous silicon layer over the core region and the non-array region of the first semiconductor structure, removing a first portion of the doped amorphous silicon layer in the non-array region to form an opening exposing a first contact portion of the first semiconductor structure, converting a second portion of the doped amorphous silicon layer in the core region to a doped polysilicon layer, forming an insulating layer in the opening, and forming a second contact portion in the insulating layer. The second contact portion is in contact with the first contact portion.

[0007] Another aspect of the present disclosure provides a system. The system includes a memory device configured to store data. The memory device includes a first semiconductor structure having a NAND memory string array, a semiconductor layer in contact with source terminals of the NAND memory string array, an insulating layer in contact with the semiconductor layer, a contact structure in the insulating layer, wherein the insulating layer electrically insulates the contact structure from the semiconductor layer; and a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure includes peripheral circuitry. The system also includes a memory controller coupled to the memory device and configured to control the NAND memory string array via the peripheral circuitry. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the relevant art to make and use the disclosure.

[0009] Figure 1A Schematic diagram showing a cross-section of a 3D memory device according to some aspects of the present disclosure.

[0010] Figure 1B An overview of a 3D memory device according to some aspects of the present disclosure is shown.

[0011] Figure 1C Shown Figure 1A and 1B Side view of an example of a 3D memory device.

[0012] Figure 2 According to some aspects of the present disclosure Figure 1A and 1B Side view of an example of a 3D memory device.

[0013] Figures 3A-3N Some aspects of the present disclosure are shown for forming Figure 2 The manufacturing process of 3D memory devices in .

[0014] Figure 4A and 4B Some aspects of the present disclosure are shown for forming Figure 2 An example of a part of the manufacturing process of a 3D memory device.

[0015] Figure 5 Some aspects of the present disclosure are shown for forming Figure 2 Flowchart of a method for a 3D memory device.

[0016] Figure 6 A block diagram of an exemplary system having a memory device according to some aspects of the present disclosure is shown.

[0017] Figure 7A A diagram illustrating an exemplary memory card having a storage device according to aspects of the present disclosure is shown.

[0018] Figure 7B A diagram illustrating an exemplary solid-state drive (SSD) having a storage device according to aspects of the present disclosure is shown.

[0019] The present disclosure will be explained with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. In addition, the present disclosure may also be used in various other applications. The functions and structural features described in this disclosure may be combined, adjusted, and modified with one another and in ways not specifically shown in the accompanying drawings, so that these combinations, adjustments, and modifications are within the scope of this disclosure.

[0021] Typically, a term can be understood, at least in part, from its usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood to not necessarily be intended to express an exclusive set of factors, but rather can allow for the presence of other factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0022] It should be readily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “over” means not only “over something” or “on something,” but also includes the meaning of “over something” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

[0023] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

[0024] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a

[0025] In 3D memory devices, the peripheral circuitry and the array of memory cells of the memory device are disposed in different planes (levels, tiers) along a vertical direction, i.e., stacked one on top of another, to reduce the planar chip size of the peripheral circuitry and the total chip size of the memory device. In 3D memory devices, memory cells are formed by the intersection of NAND memory strings and word lines. The NAND memory strings are formed to extend vertically in a memory stack (e.g., conductor / dielectric layer pairs), and the source end of the NAND memory strings is in contact with a semiconductor layer that serves as part of a source contact for applying a source voltage on the NAND memory strings. The memory stack and the peripheral circuitry are typically integrated together in a 3D NAND flash memory device through bonding.

[0026] To form electrical connections in a 3D memory device (e.g., between an array of memory cells and a peripheral circuit) and / or outside of a 3D memory device (e.g., between a 3D NAND flash memory device and an external circuit), a through-silicon contact (TSC) is typically formed. To insulate the TSC from the semiconductor layer, the portion of the semiconductor layer that is in contact with the NAND memory string is typically disconnected from the portion of the semiconductor layer through which the TSC extends. An insulating portion is formed between the two portions of the semiconductor layer for insulation. At the same time, a respective insulating spacer is formed in the semiconductor layer so that each TSC is insulated from the semiconductor layer by a respective insulating spacer. The insulating spacers and the insulating portion are typically formed by patterning the semiconductor layer to form openings and filling the openings with a dielectric material. Due to the small critical dimension of these openings, deposition of the dielectric material typically includes atomic layer deposition (ALD). Due to the high cost of photolithography, etching, and deposition, such a manufacturing process can be expensive. At the same time, the small critical dimension of the openings can result in an etching process for forming the openings being undesirably complex, and precise alignment between the openings and the TSCs is challenging.

[0027] To address one or more of the problems described above, the present disclosure provides a structure and a method of manufacturing a 3D memory device in which the critical dimension of an opening for forming an insulating layer that insulates a TSC and a semiconductor layer is increased, and the etching process for forming the opening is less challenging. The cost and difficulty of insulating different portions of the semiconductor layer can be reduced. A 3D memory device having a core region and a non-array region includes a plurality of NAND memory strings in the core region and one or more TSCs in the non-array region. The semiconductor layer is in contact with a source terminal of the NAND strings in the core region. According to the present disclosure, instead of forming a respective insulating spacer to insulate each TSC from the semiconductor layer, a single insulating layer can be formed to insulate the plurality of TSCs from the semiconductor layer. The insulating layer has a lateral width that is large enough to insulate any (e.g., all) of the TSCs from the semiconductor layer. The insulating layer can be formed at any suitable location where insulation is needed and away from the source terminals of the NAND memory strings. For example, the insulating layer can be formed in the non-array region. The insulating layer is in lateral contact with the semiconductor layer and has the same thickness as the semiconductor layer. In some embodiments, the insulating layer includes a dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0028] Unlike existing patterning techniques including photolithography and etching processes, the formation of the openings in the insulating layer in the present disclosure includes a localized thermal treatment, such as a laser annealing process, and a selective etching process. A doped amorphous silicon layer is first deposited to contact the source end of the NAND memory string, and portions of the doped amorphous silicon layer are subjected to a localized thermal treatment to convert into doped polysilicon portions. The area of the treated portions of the doped amorphous silicon layer can cover any TSC to be insulated, and does not overlap with the source end of the NAND memory string. In some embodiments, a laser annealing process is performed for the conversion. The doped polysilicon portions are selectively etched away, forming openings in the un-treated doped amorphous silicon layer. The doped amorphous silicon portions are further converted into a doped polysilicon layer, and an insulating material is deposited into the openings. The insulating layer can be further patterned such that the TSCs can extend through the insulating layer.

[0029] In the fabrication process of the present disclosure, no photolithography is needed to form the openings in the insulating layer. Instead, the patterning of the doped amorphous silicon layer includes a laser annealing process and a selective etching process. The critical dimension of the doped polysilicon portions / insulating layer is desirably large such that the laser beam can be precisely controlled for annealing the desired areas of the doped amorphous silicon layer. Compared to existing patterning techniques, the difficulty and cost of the patterning can be reduced. The larger critical dimension of the insulating layer also allows the use of other deposition methods (e.g., chemical vapor deposition (CVD) and / or physical vapor deposition (PVD)) to form the insulating layer, further reducing the fabrication cost. The increased area of the insulating layer can also reduce the parasitic capacitance of the 3D memory device.

[0030] Figure 1A A schematic diagram showing a cross-section of a 3D memory device 100 is shown. Figure 1B A top view of a 3D memory device 100 is shown. The 3D memory device 100 represents an example of a bonded chip. In some embodiments, at least some of the components of the 3D memory device 100 (e.g., the memory cell array and the peripheral circuitry) are formed separately on different substrates in parallel, and then bonded to form the bonded chip (a process referred to herein as a “parallel process”).

[0031] Note that x, y, and z axes are added in the figures of the present disclosure to further illustrate the spatial relationship of the components of the semiconductor device. The substrate of the semiconductor device (e.g., 3D memory device 100) includes two lateral surfaces (e.g., top and bottom surfaces) that extend laterally in the x and y directions (lateral or width directions). The x direction is the word line direction of the 3D memory device 100, the y direction is the bit line direction of the 3D memory device 100, and the z direction is perpendicular to the x-y plane. In some embodiments, the z direction is the NAND direction in which NAND memory strings extend vertically. As used herein, when a substrate is positioned in the z direction (vertical or thickness direction) in the lowest plane of the semiconductor device, one component (e.g., layer or device) of the semiconductor device is determined to be “on,” “over,” or “under” another component (e.g., layer or device) in the z direction relative to the substrate of the semiconductor device. The same concept is applied throughout the present disclosure for describing spatial relationships.

[0032] 3D memory device 100 can include a first semiconductor structure 102 that includes an array of memory cells (also referred to herein as a “memory cell array”). In some embodiments, the memory cell array includes a NAND flash memory cell array. For ease of description, a NAND flash memory cell array can be used as an example to describe the memory cell array in the present disclosure. However, it should be understood that the memory cell array is not limited to a NAND flash memory cell array and can include any other appropriate type of memory cell array, such as a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, just to name a few examples.

[0033] The first semiconductor structure 102 can be a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings and / or a two-dimensional (2D) NAND memory cell array. The NAND memory cells can be organized into pages or fingers, which are then organized into blocks in which each NAND memory cell is coupled to a separate line called a bit line (BL). All cells in a NAND memory cell that have the same vertical position can be coupled by a control gate by a word line (WL). In some embodiments, a memory plane contains a certain number of blocks that are coupled by the same bit line. The first semiconductor structure 102 can include one or more memory planes, and the peripheral circuitry required to perform all read / program (write) / erase operations can be included in the second semiconductor structure 104.

[0034] In some embodiments, the NAND memory cell array is a 2D NAND memory cell array, each 2D NAND memory cell including a floating gate transistor. According to some embodiments, the 2D NAND memory cell array includes a plurality of 2D NAND memory strings, each 2D NAND memory string including a plurality of memory cells (similar to a NAND gate) connected in series and two selection transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (i.e., herein refers to a flat two-dimensional (2D) surface, which is different from the term "memory plane" in this disclosure). In some embodiments, the NAND memory cell array is a 3D NAND memory string array, each 3D NAND memory string extending vertically above the semiconductor layer (in 3D) through a stacked structure, such as a memory stack. Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), the 3D NAND memory string typically includes a certain number of NAND memory cells, each of which includes a floating gate transistor or a charge capture transistor.

[0035] like Figure 1A As shown, the 3D memory device 100 may further include a second semiconductor structure 104 having peripheral circuits for the memory cell array in the first semiconductor structure 102. The peripheral circuits (also known as control and sensing circuits) may include any appropriate digital, analog, and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an I / O circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the aforementioned functional circuits, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The peripheral circuits in the second semiconductor structure 104 may be implemented using complementary metal oxide semiconductor (CMOS) technology, which may be implemented using a logic process in any appropriate technology node, for example.

[0036] like Figure 1A As shown, according to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are stacked on each other in different planes. As a result, the memory cell array in the first semiconductor structure 102 and the peripheral circuits in the second semiconductor structure 104 can be stacked on each other in different planes to reduce the planar size of the 3D memory device 100 compared to a memory device in which all peripheral circuits are arranged in the same plane. Figure 1AAs shown, in some embodiments, the first semiconductor structure 102 is above the second semiconductor structure 104 and includes a pad output interconnect layer for pad output purposes. TSVs can be formed to extend in the first semiconductor structure 102 to provide electrical connections between components in the memory device 100 (e.g., peripheral circuits and / or memory cell arrays) and any external circuits.

[0037] like Figure 1A As shown, the 3D memory device 100 further includes a bonding interface 106 vertically located between the first semiconductor structure 102 and the second semiconductor structure 104. The bonding interface 106 can be an interface between two semiconductor structures formed by any suitable bonding technology (e.g., hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, eutectic bonding, to name a few examples) as described in detail below. Data transfer between the memory cell array in the first semiconductor structure 102 and the peripheral circuit in the second semiconductor structure 104 can be performed by interconnections (e.g., bonding contacts) across the bonding interface 106. Figure 1A As shown, in some embodiments, in the z-direction, the memory cell array is above the bonding interface 106 , and the peripheral circuit is below the bonding interface 106 .

[0038] As described in detail below, some of the first semiconductor structure 102 and the second semiconductor structure 104 can be fabricated separately (and in some embodiments, in parallel) by parallel processes, so that the thermal budget of fabricating one of the first semiconductor structure 102 and the second semiconductor structure 104 does not limit the process of fabricating the other of the first semiconductor structure 102 and the second semiconductor structure 104. In addition, a large number of interconnects (e.g., bonding contacts and / or inter-layer vias (ILVs) / through substrate vias (TSVs)) can be formed across the bonding interface 106 to make direct, short-distance (e.g., micrometer or sub-micrometer scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0039] Figure 1B 1 shows an overview of a memory device 100 according to some aspects of the present disclosure. Specifically, Figure 1BThe core region 108 and the non-array region 110 in the first semiconductor structure 102 in the x-y plane are shown. In some implementations, an array of memory cells is formed in the core region 108, and a TSC is formed in the non-array region 110. In some implementations, the non-array region 110 is located at a periphery of or around the core region 108. For example, the non-array region 110 can be a region away from the array of memory cells, such as a staircase region. In various implementations, other regions can be included in the non-array region 110 but are not part of the staircase region. In some implementations, the non-array region 110 and the core region 108 do not overlap with each other in the x-y plane.

[0040] Figure 1C A side view of a portion of a 3D memory device 103, which is an example of the memory device 100, is shown. The 3D memory device includes the first semiconductor structure 105 and the second semiconductor structure 107 bonded to each other at the bonding interface 109. The first semiconductor structure 105 is an example of the first semiconductor structure 102, and the second semiconductor structure 107 is an example of the second semiconductor structure 104. The first semiconductor structure 105 includes a plurality of NAND memory strings 117, a plurality of TSCs 115, a semiconductor layer 111, and a plurality of pad-out interconnects 119. Source ends of the NAND memory strings 117, which are located in the core region 108, are in contact with a first portion 111-1 of the semiconductor layer. A second portion 111-2 of the semiconductor layer is insulated / disconnected from the first portion 111-1 of the semiconductor layer by an insulating portion 113, which includes a dielectric material such as silicon oxide. The TSCs 115 can be located in the non-array region 110 and extend through the second portion 111-2 of the semiconductor layer. The pad-out interconnects 119 can be conductively connected to components in the 3D memory device 103 for the purpose of pad-out. Each TSC 115 is located in (e.g., through) a respective insulating spacer 121 in the second portion 111-2 of the semiconductor layer. The insulating spacer 121 includes the same material as the insulating portion 113, such as silicon oxide.

[0041] The insulating portion 113 and the insulating spacer 121 are formed by patterning the semiconductor layer 111 to form respective openings and filling the openings with a dielectric material. The patterning process typically includes a photolithography process followed by an etching process. The openings used to form the insulating spacer 121 are, for example, precisely aligned with the TSCs 115. Due to the small critical dimensions of the insulating portion 113 and the insulating spacer 121, an ALD is typically used to deposit the dielectric material. As a result, the manufacturing process for forming the 3D memory device 103 can be challenging and costly.

[0042] Figure 2A side view of a portion of an exemplary 3D memory device 200 in accordance with some aspects of the present disclosure is shown in the xz plane. According to some embodiments, the 3D memory device 200 may be an example of the memory device 100 and is a bonded chip including a first semiconductor structure 203 and a second semiconductor structure 207 stacked in different planes in a vertical direction (e.g., the z direction). According to some embodiments, the first semiconductor structure 203 and the second semiconductor structure 207 are bonded at a bonding interface 209 therebetween. Note that Figure 2 、 3A The components shown in 3N, 4A, and 4B are intended to illustrate relative positions and do not indicate actual electrical connections in the 3D memory device 200 .

[0043] like Figure 2 As shown, the first semiconductor structure 203 and the second semiconductor structure 207 can be bonded to each other in a face-to-face manner at a bonding interface 209. The second semiconductor structure 207 may include a substrate 202 and a device layer 204 above and in contact with the substrate 202. The substrate 202 may include silicon (e.g., single crystal silicon, c-silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable semiconductor material. In some embodiments, element 202 represents a semiconductor layer, which can be formed by thinning the substrate. In some embodiments, the substrate 202 includes single crystal silicon. In some embodiments, the device layer 204 includes peripheral circuits (details not shown in the figure). The peripheral circuits may include high voltage (HV) circuits (e.g., driver circuits) and low voltage (LV) circuits (e.g., page buffer circuits and logic circuits). In some embodiments, the peripheral circuitry includes a plurality of transistors in contact with the substrate 202 (or semiconductor layer 202, if applicable). The transistors can include any transistor disclosed herein, such as planar transistors and 3D transistors.

[0044] In some embodiments, the second semiconductor structure 207 further includes an interconnect layer 205 above the device layer 204 for transmitting electrical signals to and from peripheral circuits in the device layer 204. Figure 2As shown, the interconnect layer 205 can be vertically located between the bonding interface 209 and the device layer 204 (including the transistors of the peripheral circuitry). The interconnect layer 205 can include multiple interconnects, including lateral lines and vias. As used herein, the term "interconnect" can broadly include any appropriate type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnects can be coupled to the transistors of the peripheral circuitry in the device layer 204. The interconnect layer 205 can also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") in which lateral lines and vias can be formed. That is, the interconnect layer 205 can include lateral lines and vias in multiple ILD layers. In some embodiments, the devices in the device layer 204 are coupled to each other via the interconnects in the interconnect layer 205. The interconnects in the interconnect layer 205 can include conductive materials, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer in the interconnect layer 205 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof. In some embodiments, the interconnects in the interconnect layer 205 include W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (fewer defects, such as voids) among conductive metal materials.

[0045] like Figure 2 As shown, the second semiconductor structure 207 may further include a bonding layer 206 at the bonding interface 209 and above and in contact with the interconnect layer 205. The bonding layer 206 may include a plurality of bonding contacts 233 and a dielectric electrically isolating the bonding contacts 233. The bonding contacts 233 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. In some embodiments, the bonding contacts 233 of the bonding layer 206 include Cu. The remaining area of ​​the bonding layer 206 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contact 233 and the surrounding dielectric in the bonding layer 206 can be used for hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-metal (e.g., Cu-Cu) bonding and dielectric-dielectric (e.g., SiO2-SiO2) bonding. For example, the bonding interface can be distinguished based on the relative position (e.g., displacement) of the bonding contacts 231 and 233.

[0046] likeFigure 2 As shown, the first semiconductor structure 102 may further include a bonding layer 208 at a bonding interface 209, for example, on an opposite side of the bonding interface 209 relative to the bonding layer 206 in the second semiconductor structure 207. The bonding layer 208 may include a plurality of bonding contacts 231 and a dielectric electrically isolating the bonding contacts 231. The bonding contacts 231 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 208 may be formed of a dielectric material such as silicon oxide. The bonding contacts 231 in the bonding layer 208 and the surrounding dielectric may be used for hybrid bonding. In some embodiments, the bonding interface 209 is the location where the bonding layers 208 and 206 meet and bond. In practice, the bonding interface 209 may be a layer having a certain thickness that includes the top surface of the bonding layer 206 and the bottom surface of the bonding layer 208.

[0047] like Figure 2 As shown, the first semiconductor structure 203 may further include an interconnect layer 210 above and in contact with the bonding layer 208 for transmitting electrical signals. The interconnect layer 210 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 210 also include local interconnects, such as bitline contacts and wordline contacts. The interconnect layer 210 may also include one or more ILD layers, in which lateral lines and vias may be formed. The interconnects in the interconnect layer 210 may include conductive materials, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer in the interconnect layer 210 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0048] like Figure 2As shown, the first semiconductor structure 203 can include an array of memory cells, such as an array of NAND memory strings 217 over and in contact with the interconnect layer 210. In some embodiments, the interconnect layer 210 is vertically between the NAND memory strings 217 and the bonding interface 209. According to some embodiments, each NAND memory string 217 extends vertically through a plurality of pairs of gate conductive layers 239 and dielectric layers 240. The stacked and interleaved gate conductive layers 239 and dielectric layers 240 are also referred to herein as a stack structure, such as a memory stack 212 (conductor / dielectric layer pair). According to some embodiments, the interleaved gate conductive layers 239 and dielectric layers 240 in the memory stack 212 alternate in a vertical direction. Each gate conductive layer 239 can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The adhesive layer can include a conductive material, such as titanium nitride (TiN), which can improve adhesion between the gate electrode and the gate dielectric layer. The gate electrode of the gate conductive layer 239 can extend laterally as a word line, ending at one or more step structures of the memory stack 212. The step structures, which are part of the non-array region 110, can be in contact with a plurality of word line contacts 237 for applying a voltage on the gate conductive layer 239.

[0049] The number of pairs of gate conductive layers 239 and dielectric layers 240 in the memory stack 212 can be one of the factors that determines the number of memory cells in the array of memory cells. The gate conductive layers 239 can include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 239 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 239 includes a doped polysilicon layer. Each gate conductive layer 239 can include a control gate that surrounds a memory cell.

[0050] As Figure 2As shown, each NAND memory string 217 includes a channel structure extending vertically through the memory stack 212. In some embodiments, the channel structure includes a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a “charge trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, the blocking layer are radially arranged from the center of the pillar toward the outer surface in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The channel structure can also include a channel plug on a drain end of the NAND memory string 217. The channel plug can include polysilicon and be in contact with the semiconductor channel. In some embodiments, each NAND memory string 217 is a “charge trapping” type of NAND memory. It should be understood that the NAND memory string 217 is not limited to a “charge trapping” type of NAND memory string and can be a “floating gate” type of NAND memory string in other examples.

[0051] According to some embodiments, the NAND memory string 217 does not have any semiconductor plug on its source end. Instead, the 3D memory device 200 includes a semiconductor layer 211 above and in contact with the memory stack 212. The semiconductor layer 211 can be in contact with sidewalls of the semiconductor channel of the channel structure at the source end of each NAND memory string 217. The semiconductor layer 211 can include a semiconductor material, such as doped polysilicon. In some embodiments, the semiconductor layer 211 is doped with N-type dopants, such as phosphorus and / or arsenic. The thickness of the semiconductor layer 211 can be in a range from 100 nm to 600 nm. In some embodiments, the semiconductor layer 211 and a source contact in the slit structure (e.g., an array common source or ACS, not shown) can collectively function as a portion of a source line (not shown) coupled to the source end of the NAND memory string 217, such as for applying an erase voltage to the source end of the NAND memory string 217 during an erase operation.

[0052] The semiconductor layer 211 includes a first semiconductor layer portion 211-1 and a second semiconductor layer 211-2, which are located at the same level in the z-direction and are separated by an insulating layer 213. The insulating layer 213 may be in lateral contact with each of the first semiconductor layer portion 211-1 and the second semiconductor layer portion 211-2 and may have the same thickness as the semiconductor layer 211. The first semiconductor layer portion 211-1 and the second semiconductor layer portion 211-2 may be disconnected / insulated from each other by the insulating layer 213. In some embodiments, the insulating layer 213 is a single insulating layer including a uniform dielectric / material in the xy plane. That is, the insulating layer 213 may not be disconnected between any two contact structures 215. The first semiconductor layer portion 211-1, which is partially or entirely located in the core region 108, may be located above and in contact with the source terminal of the NAND memory string 217. The area of ​​the first portion 211-1 of the semiconductor layer can be sufficiently large, for example, greater than or equal to the total area in which all NAND memory strings 217 are formed (e.g., a sub-region of the core region 108), to contact the source terminals of all NAND memory strings 217. The orthographic projection of the insulating layer 213 in the xy plane can cover multiple (e.g., all) contact structures 215. In various embodiments, the orthographic projection of the insulating layer 213 at least partially overlaps the stepped region. In some embodiments, the orthographic projection of the insulating layer 213 does not overlap the core region 108. In various embodiments, the second portion 211-2 of the semiconductor layer may or may not be present. In some embodiments, the top surface of the insulating layer 213 is coplanar with the top surface of the semiconductor layer 211, and the bottom surface of the insulating layer 213 is coplanar with the bottom surface of the semiconductor layer 211. The insulating layer 213 may include a dielectric material such as silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the insulating layer 213 includes silicon oxide.

[0053] like Figure 2 As shown, the first semiconductor structure 203 may further include one or more contact structures 215 extending vertically in the insulating layer 213 (e.g., through the insulating layer 213). In some embodiments, the contact structures 215 couple the interconnects in the interconnect layer 210 to the pad output interconnects 219 in the pad output interconnect layer 216 to facilitate electrical connection through the first semiconductor structure 203. The contact structures 215 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some embodiments, the contact structures 215 include W. In some embodiments, each of the contact structures 215 may be a TSV having a depth (e.g., a length along the z-direction) on the order of microns or tens of microns (e.g., between 1 μm and 100 μm).

[0054] like Figure 2As shown, the contact structure 215 can be located in the non-array region 110 of the first semiconductor structure 203, or can be located away from the NAND memory strings 217, e.g., in the x-y plane. In some embodiments, the insulating layer 213 can be partially or fully located in the non-array region 110 to provide insulation of the at least one contact structure 215 from the semiconductor layer 211. In some embodiments, the insulating layer 213 is located in a staircase region of the 3D memory device 200. In some other embodiments, the insulating layer 213 is located outside the staircase region but in the non-array region 110. In some embodiments, the width of the insulating layer 213 in the x-direction and / or y-direction is large enough to enclose multiple (e.g., all) contact structures 215 in the non-array region 110, such that all contact structures 215 around in / within the insulating layer 213 are insulated from the first portion 211-1 of the semiconductor layer. The insulating layer 213 can also insulate the second portion 211-2 of the semiconductor layer (if any) from the first portion 211-1 of the semiconductor layer. In various embodiments, the insulating layer 213 can be located away from the source end of the NAND memory strings 217, and the width and / or area of the insulating layer 213 can desirably be large enough to insulate a maximum number of contact structures 215. For example, the area of the insulating layer 213 (e.g., a sub-region of the non-array region 110) can be larger than or equal to the total area where the contact structures 215 are located. In some embodiments, the insulating layer 213 is located in the non-array region 110.

[0055] As Figure 2As shown, the first semiconductor structure 203 can also include a pad output interconnect layer 216 over and in contact with the semiconductor layer 211. In some embodiments, the semiconductor layer 211 is disposed vertically in the z-direction between the pad output interconnect layer 216 and the NAND memory string 217. The pad output interconnect layer 216 can include a second insulating layer 214 over and in contact with the semiconductor layer 211 and the insulating layer 213, a plurality of contacts 241 over and in contact with the first portion of the semiconductor layer 211-1, a first contact layer 221 over and in contact with the contact structure 215, a second contact layer 223 over and in contact with the contacts 241, a third insulating layer 227 over and in contact with the first contact layer 221 and the second contact layer 223, and a plurality of pad output interconnects 219, e.g., contact pads, in the third insulating layer 227. In some embodiments, the pad output interconnects 219 that are electrically connected to the contact structure 215 are employed to drive transistors in the peripheral circuitry in the device layer 204. In some embodiments, the pad output interconnects 219 that are electrically connected to the NAND memory string 217 are employed to provide voltages for operations, e.g., erase, write, and read, of the memory cells.

[0056] The second insulating layer 214 can provide insulation between the contact structure 215 and the contact 241. The first contact layer 221 in contact with the contact structure 215 and the corresponding pad output interconnect 219 can provide an electrical connection between the contact structure 215 and the corresponding pad output interconnect 219. The second contact layer 223 in contact with the contact 241 and the corresponding pad output interconnect 219 can provide an electrical connection between the source end of the NAND memory string 217 and the corresponding pad output interconnect 219. The first contact layer 221 and the second contact layer 223 can be insulated from each other, for example, by one or more insulating portions 225. In some embodiments, the pad output interconnect 219 can carry electrical signals between the 3D memory device 200 and an external device, for example, for the purpose of pad output. In some embodiments, the second insulating layer 214, the insulating portions 225, and the third insulating layer 227 can each include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or any combination thereof. Each of the second insulating layer 214 and the third insulating layer 227 can be a single layer structure or a multi-layer structure. For example, the third insulating layer 227 can include a silicon nitride layer on top of a silicon oxide layer. The silicon oxide layer can be in contact with the first contact layer 221 and the second contact layer 223, and the silicon nitride layer can cover the silicon oxide layer. The silicon oxide layer can provide a balanced stress on the first and second contact layers and the silicon nitride layer. The silicon nitride layer can provide a desired insulation to prevent contamination, such as moisture, air, and / or chemicals. The contact structure 215, the contact 241, the first contact layer 221 and the second contact layer 223, and the pad output interconnect 219 can each include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the contact structure 215, the contact 241, and the pad output interconnect 219 can each include tungsten.

[0057] It should be noted that although the second insulating layer 214 and the insulating layer 213 can include the same material and the interface between the second insulating layer 214 and the insulating layer 213 can not be visible, e.g., indistinguishable, the second insulating layer 214 and the insulating layer 213 can be defined as two different layers in the present disclosure. For example, if the insulating layer 213 and the second insulating layer 214 include the same material, the insulating layer 213 can be a portion of the material in lateral contact with the semiconductor layer 211 (e.g., on the side of the semiconductor layer 211), and the second insulating layer 214 can be a portion of the material in vertical contact with the semiconductor layer 211 and the insulating layer 213 (e.g., on the top surface of the semiconductor layer 211 and the insulating layer 213). That is, the interface between the semiconductor layer 211 and the insulating layer 213 can extend in the z-direction, and the interface between the semiconductor layer 211 / insulating layer 213 and the second insulating layer 214 can extend in the x-y plane.

[0058] Figures 3A-3N A manufacturing process for forming a 3D memory device 200 is shown in accordance with some aspects of the present disclosure. Figure 4A and 4B A portion of another manufacturing process for forming a 3D memory device 200 is shown in accordance with some aspects of the present disclosure. Figure 5 A flowchart of a method 500 for forming a 3D memory device 200 is shown in accordance with some aspects of the present disclosure. It should be understood that the operations shown in the method 500 are not exhaustive and that other operations can also be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed concurrently, or in a different order than shown. Figure 5

[0059] Referring to Figure 5 , the method 500 begins at operation 502, where a doped amorphous silicon layer is formed over a semiconductor structure having a core region and a staircase region. Figure 3A A corresponding structure is shown.

[0060] As shown in Figure 3A , a doped amorphous silicon layer 320 is formed over a semiconductor structure 350, the doped amorphous silicon layer 320 having a core region 108 and a non-array region 110. The semiconductor structure 350 can be an example of the 3D memory device 200. As shown in Figure 3A , the semiconductor structure 350 can include a portion of a first semiconductor structure bonded with a second semiconductor structure at a bonding interface 309. The second semiconductor structure can include a substrate 302, a device layer 304, an interconnect layer 305, and a bonding layer 306. The portion of the first semiconductor structure can include a bonding layer 308, an interconnect layer 310, and an array stack 312. The array stack 312 can include a plurality of gate conductive layers 339 and a plurality of dielectric layers 340 interleaved. The array stack 312 can also include an array of NAND memory strings 317 extending in the interleaved gate conductive layers 339 and dielectric layers 340. The first semiconductor structure can also include one or more first contact portions 315-1 extending vertically and coupled to the interconnect layer 310. The first contact portions 315-1 can later form a lower portion of a TSV (e.g., the contact structure 215). The NAND memory strings 317 can be located in the core region 108, and the first contact portions 315-1 can be located in the non-array region 110. Detailed descriptions of each component can refer to the description of the 3D memory device 200 in Figure 2 , and are not repeated herein.

[0061] ​To form the first semiconductor structure, a stack structure (e.g., a memory stack including interleaved gate conductive layers and dielectric layers) is formed on a first substrate to form an array stack 312. In some embodiments, the first substrate includes a suitable base material such as silicon. To form the memory stack, in some embodiments, a dielectric stack (not shown) including interleaved sacrificial layers (not shown) and dielectric layers is formed on the first substrate. In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The interleaved sacrificial layers and dielectric layers can be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The dielectric stack can be repeatedly patterned to form a plurality of steps in the non-array region 110. The memory stack can then be formed by a gate replacement process (e.g., using a wet / dry etch selective to the dielectric layers to the sacrificial layers and filling the resulting recesses with conductive layers to replace the sacrificial layers with conductive layers). In some embodiments, each conductive layer includes a metal layer, such as a W layer. It should be appreciated that in some examples, the memory stack can also be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without using a gate replacement process. In some embodiments, a pad oxide layer including silicon oxide (e.g., a local oxidation of silicon (LOCOS) thermally grown) is formed between the memory stack and the first substrate. A plurality of contact vias extending vertically and landing on the steps can be formed to form electrical connections between the gate conductive layers 339 and the interconnect layers 310 to be formed.

[0062] The NAND memory strings 317 can be formed over the first substrate. Each NAND memory string 317 extends vertically through the dielectric stack (or memory stack, depending on the fabrication process) to contact the first substrate. In some embodiments, the fabrication process to form the NAND memory strings 317 includes forming channel holes through the dielectric stack (or memory stack) and into the first substrate using dry etching and / or wet etching (e.g., deep reactive-ion etching (DRIE)), followed by filling the channel holes with a plurality of layers (e.g., memory films (e.g., tunneling, memory, and blocking layers) and semiconductor layers) using thin film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof).

[0063] In some embodiments, the interconnect layer 310 is formed over the array of NAND memory strings 317 on the first substrate. The interconnect layer 310 can include a first plurality of interconnects in one or more ILD layers. The interconnect layer 310 can include interconnects of MEOL and / or BEOL in multiple ILD layers to electrically connect with the NAND memory strings 317. In some embodiments, the interconnect layer 310 includes multiple ILD layers and interconnects formed therein in multiple processes. For example, the interconnects in the interconnect layer 310 can include conductive material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes used to form the interconnects can also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other appropriate processes. The ILD layers can include dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The illustrated ILD layers and interconnects can be collectively referred to as the interconnect layer 310. In some embodiments, the interconnects in the interconnect layer 310 include W, which has a relatively high thermal budget in conductive metal material to withstand subsequent high temperature processes.

[0064] In some embodiments, the bonding layer 308 is formed over the interconnect layer 310. The bonding layer 308 can include a plurality of first bonding contacts 331 surrounded by dielectric. In some embodiments, a dielectric layer is deposited on a top surface of the interconnect layer 310 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The first bonding contacts 331 through the dielectric layer and to the interconnects in the interconnect layer 310 can then be formed by first patterning a contact hole through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact hole can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact hole includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0065] To form the second semiconductor structure, a device layer 304 is formed on a substrate 302 (e.g., a second substrate). The device layer 304 may include a plurality of transistors on the substrate 302. The substrate 302 may be a silicon substrate having single crystal silicon. The transistors may be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other appropriate process. In some embodiments, doped regions are formed in the substrate 302 by ion implantation and / or thermal diffusion, the doped regions being used, for example, as wells and source / drain regions of transistors. In some embodiments, isolation regions (e.g., shallow trench isolation (STI)) are also formed in the substrate 302 by wet / dry etching and thin film deposition. The transistors may be used as part or all of the peripheral circuitry for controlling the NAND storage string 317. It will be understood that the details of manufacturing the transistors may vary depending on the type of transistor and are therefore not described in detail for ease of description.

[0066] In some embodiments, an interconnect layer 305 is formed above the transistors on the substrate 302. The interconnect layer 305 may include a plurality of interconnects in one or more ILD layers. Figure 3A As shown, the interconnect layer 305 can be formed above the transistors in the device layer 304. The interconnect layer 305 can include interconnects of MEOL and / or BEOL in multiple ILD layers to electrically connect to the transistors. In some embodiments, the interconnect layer 305 includes multiple ILD layers and interconnects formed therein in multiple processes. In some embodiments, a first contact portion 315-1 can be formed in the non-array area 110, extending in the array stack 312 and coupled to the interconnects in the interconnect layer 305. The formation of the first contact portion 315-1 can include photolithography, etching, and deposition. For example, the first contact portion 315-1 and the interconnects in the interconnect layer 305 can include conductive materials deposited by one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, chemical plating, or any combination thereof). The manufacturing process for forming the interconnect can also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). The ILD layer and the interconnects may be collectively referred to as interconnect layer 305. In some embodiments, the interconnects in interconnect layer 305 include W, which has a relatively high thermal budget among conductive metal materials to withstand subsequent high temperature processes.

[0067] In some embodiments, a bonding layer 306 is formed over the interconnect layer 305. The bonding layer 306 can include a plurality of second bonding contacts 333 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on a top surface of the interconnect layer 305 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The second bonding contacts 333 through the dielectric layer and to the interconnect contacts in the interconnect layer 305 can then be formed by first patterning a contact hole through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact hole can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact hole includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0068] As shown in FIG. 3B, the first semiconductor structure (e.g., the array stack 312 and the NAND memory strings 317 formed therethrough) is flipped upside down. The downward facing bonding layer 308 is bonded to the upward facing bonding layer 306, i.e., in a face-to-face manner, thereby forming a bonding interface 309. That is, the first and second bonding contacts in the bonding layers 308 and 306 are bonded at the bonding interface 309. In some embodiments, a processing Figure 3A technique, e.g., a plasma treatment, a wet treatment, and / or a local thermal treatment, is applied to the bonding surfaces prior to bonding. As a result of the bonding, e.g., hybrid bonding, the first bonding contacts 331 and the second bonding contacts 333 on opposite sides of the bonding interface 309 can be intermixed with each other. According to some embodiments, after bonding, the first bonding contacts 331 in the bonding layer 308 and the second bonding contacts 333 in the bonding layer 306 are aligned and in contact with each other, such that the array stack 312 and the NAND memory strings 317 formed therethrough can be coupled to the transistors across the bonding interface 309 through the bonded bonding contacts. The first substrate can then be partially or completely removed to expose a source end of the NAND memory strings 317. In some embodiments, removing the first substrate includes an appropriate etching process (e.g., dry etching and / or wet etching) and / or a planarization process (e.g., chemical mechanical polishing or CMP). The bonded chip in which the first substrate is partially or completely removed can be referred to as a semiconductor structure 350.

[0069] A doped amorphous silicon layer 320 can be deposited over the semiconductor structure 350 on the sides / surfaces that expose the source ends of the NAND memory strings 317. The doped amorphous silicon layer 320 can be in contact with at least the source ends of a plurality (e.g., all) of the NAND memory strings 317 in the core region 108. In some embodiments, the doped amorphous silicon layer 320 covers and is in contact with at least one (e.g., all) of the first contact portions 315-1 in the non-array region 110. For example, the doped amorphous silicon layer 320 can cover both the core region 108 and the non-array region 110. In some embodiments, the doped amorphous silicon layer 320 is deposited using a low temperature deposition process (e.g., low temperature chemical vapor deposition (CVD)). For example, the deposition temperature can be in a range from 400 degrees Celsius to 450 degrees Celsius. The dopant, such as phosphorous and / or arsenic, can be doped using an in-situ doping process. In some embodiments, the thickness of the doped amorphous silicon layer 320 is in a range from 100 nm to 600 nm. In various embodiments, the thickness of the doped amorphous silicon layer 320 is controlled to be within a desirable range so that a subsequent localized heat treatment (e.g., a laser anneal process) can fully convert the selected regions.

[0070] The method 500 proceeds to operation 504, where a first portion of the doped amorphous silicon layer in the staircase region is converted to a doped polysilicon portion using a localized heat treatment, and a second portion of the doped amorphous silicon layer over the core region is maintained. Figure 3B The corresponding structures are shown.

[0071] As Figure 3BAs shown, a first portion 320a of the doped amorphous silicon layer can be converted to a doped polysilicon portion, while a second portion 320b of the doped amorphous silicon layer can be preserved. In some embodiments, a third portion 320c of the doped amorphous silicon layer in the non-array region 110 can also be preserved. The first portion 320a of the doped amorphous silicon layer can be over, e.g., covering, any / all of the first contact portions 315-1 to insulate the NAND memory strings 317. In some embodiments, the first portion 320a of the doped amorphous silicon layer is partially or completely located in the non-array region 110. The conversion of the doped amorphous silicon to the doped polysilicon can include a localized thermal process, e.g., a laser annealing process. The localized thermal process can be confined in the desired controlled area and does not affect other heat-sensitive structures, such as the bonding contacts 331 and 332 at the bonding interface 209 and other copper structures / interconnects. The first portion 320a of the doped amorphous silicon layer can be crystallized and form the doped polysilicon portion during the localized thermal process. In some embodiments, the temperature of the laser annealing process can be in the range of 1300 degrees Celsius to 1700 degrees Celsius. In some embodiments, the laser annealing process includes a plurality of laser pulses, each laser pulse having a pulse time of 100 ns (i.e., nanoseconds) to 300 ns.

[0072] The localized thermal process, e.g., the laser annealing process, can be controlled to be performed only on the first portion 320a of the doped amorphous silicon layer. A lateral dimension LI (e.g., in the x-direction and / or the y-direction) of the first portion 320a of the doped amorphous silicon layer can be large enough to cover at least the plurality (e.g., all) of the first contact portions 315-1. For example, the lateral dimension LI can be equal to or less than a lateral dimension of the non-array region 110 in the x-direction. In some embodiments, the lateral dimension LI can be equal to or less than a lateral dimension of the staircase region. In some embodiments, the lateral dimension LI (e.g., along the x-direction and / or the y-direction) can be equal to or greater than three times a thickness of the doped amorphous silicon layer 320a in the z-direction. In some embodiments, an area of the first portion 320a of the doped amorphous silicon layer can cover a total area of all of the first contact portions 315-1 in all lateral directions. Meanwhile, a lateral dimension L2 of the second portion 320b of the doped amorphous silicon layer can be greater than or equal to a total lateral dimension of all of the NAND memory strings 317 in the x-direction. For example, an area of the second portion 320b of the doped amorphous silicon layer can completely cover all of the NAND memory strings 317 and thus be equal to or greater than a total area of all of the NAND memory strings 317. In some embodiments, the lateral dimension L2 is equal to or greater than a lateral dimension of the core region 108.

[0073] Referring back to Figure 5 , the method 500 proceeds to operation 506, where the doped polysilicon portion is removed to form a first opening. Figure 3CThe corresponding structure is shown.

[0074] As Figure 3C shown, the doped polysilicon layer converted from the first portion 320a of the doped amorphous silicon layer can be selectively removed, thereby forming a first opening 313a in the doped amorphous silicon layer 320. The first opening 313a can expose the first contact portion 315-1, e.g., any first contact portion 315-1 covered by the doped polysilicon layer. In some embodiments, the aspect ratio (e.g., the ratio of the depth to the width) of the first opening 313a is less than or equal to 1 / 3. For example, the aspect ratio is less than or equal to 1 / 5. The small aspect ratio can allow the deposition process of the insulating material into the first opening 313a to be cheaper and easier. In some embodiments, ALD is not needed to perform the deposition. In some embodiments, the first opening 313a is a single opening. The second portion 320b of the doped amorphous silicon layer can be retained. In some embodiments, the third doped amorphous silicon layer 320c (if any) can be retained.

[0075] The doped polysilicon layer can be removed using an etchant that has a higher etch rate on doped polysilicon than on doped amorphous silicon, such that the doped polysilicon layer can be selectively etched away from the doped amorphous silicon layer 320. In some embodiments, the etchant includes ammonia.

[0076] Referring back to Figure 5 , the method 500 proceeds to operation 508, in which the remaining portion of the doped amorphous silicon layer is converted to a doped polysilicon layer using a local thermal treatment. Figure 3D The corresponding structure is shown.

[0077] As Figure 3DAs shown, the remaining second portion 320b of the doped amorphous silicon layer and any remaining third portion 320c of the doped amorphous silicon layer can be converted to a doped polysilicon layer 311 using a local thermal treatment (e.g., a laser anneal process, similar or identical to the laser anneal process in operation 504). The doped polysilicon layer 311 can be referred to as a semiconductor layer. The remaining portions of the doped amorphous silicon layer 320 can be crystallized during the local thermal treatment and form a doped polysilicon layer. The crystallization of the doped amorphous silicon can be controlled in any appropriate areas of the doped amorphous silicon layer 320 where an electrical connection is desired to be formed. In some embodiments, the first portion 320b of the doped amorphous silicon layer can be converted to a first portion 311-1 of the doped polysilicon layer, and any third portion 320c of the doped amorphous silicon layer can be converted to a second portion 311-2 of the doped polysilicon layer. In some embodiments, the temperature of the laser anneal process can be in a range of 1300 degrees Celsius to 1700 degrees Celsius. In some embodiments, the laser anneal process includes a plurality of laser pulses, each laser pulse having a pulse time of 100 ns (i.e., nanoseconds) to 300 ns. The local thermal treatment (e.g., laser anneal process) can be controlled to be performed at least on the second portion 320b of the doped amorphous silicon layer. In some embodiments, the local thermal treatment is performed only on the remaining second portion 320b of the amorphous silicon layer, and not on the third portion 320c of the amorphous silicon layer. In some embodiments, the local thermal treatment is performed only on the portion of the remaining second portion 320b of the amorphous silicon layer that is in contact with the NAND memory string 317, and not on the remaining portion of the second portion 320b of the amorphous silicon layer or the third portion 320c of the amorphous silicon layer.

[0078] Referring back to Figure 5 , the method 500 proceeds to operation 510, in which an insulating material is deposited over the polysilicon layer and in the first opening, thereby forming a first insulating layer in the first opening and a second insulating layer over the first insulating layer and the doped polysilicon layer. Figure 3E The corresponding structure is shown.

[0079] As Figure 3EAs shown, an insulating material can be deposited over the doped polysilicon layer 311 and in the first opening 313a, thereby forming a first insulating layer 313 in the first opening 313a and a second insulating layer 314 over the first insulating layer 313 and the doped polysilicon layer 311. The first insulating layer 313 can be formed by filling the first opening 313a with the insulating material and can cover any first contact portion 315-1 exposed in the first opening 313a. The first insulating layer 313a can contact the first portion 311-1 of the doped polysilicon layer and the second portion 311-2 of the doped polysilicon layer (if any). In some embodiments, if the doped polysilicon layer 311 does not include the second portion 311-2 of the doped polysilicon layer, the first insulating layer 313 can extend laterally to the outer edge of the non-array region 110. The insulating material (e.g., a dielectric material) can include silicon oxide, silicon nitride, silicon oxynitride, and / or other low-k dielectrics. The insulating material can be deposited using any suitable deposition method, such as CVD, PVD, and / or ALD. In some embodiments, the deposition of the insulating material does not include ALD.

[0080] Return Reference Figure 5 , the method 500 proceeds to operation 512 , where a plurality of second openings are formed through the first and second insulating layers in the step region, and one or more third openings are formed in the second insulating layer in the core region. Figure 3F and 3G The corresponding structure is shown.

[0081] like Figure 3F As shown, a patterned photoresist layer 352 can be formed over the second insulating layer 314 in the core region 108 and the non-array region 110. The patterned photoresist layer 352 may include one or more openings 354 (in the core region 108) for forming a contact portion connecting the first portion 311-1 of the doped polysilicon layer and the pad output interconnect, and one or more openings 356 for forming a contact portion connecting the first contact portion 315-1. The openings 354 and 356 can each be in contact with the second insulating layer 314. In some embodiments, the openings 356 can each be aligned with the corresponding first contact portion 315-1 in the z-direction. The patterned photoresist layer 352 can be formed by applying a photoresist layer over the second insulating layer 314 and performing a photolithography process to form the openings 354 and 356.

[0082] like Figure 3GAs shown, using the patterned photoresist layer 352 as an etching mask, an appropriate etching process (e.g., dry etching and / or wet etching) can be performed to form a plurality of second openings 360 that pass through the first insulating layer 313 and the second insulating layer 314 and each contact the corresponding first contact portion 315-1. In the same etching process, one or more third openings 358 are formed in the second insulating layer 314 and contact the first portion 311-1 of the doped polysilicon layer. The patterned photoresist layer 352 can then be removed, for example, using an ashing process.

[0083] In some other embodiments, the second opening and the third opening may be formed separately, for example, using different etching processes. Figure 4A and 4B An alternative fabrication process for forming the second and third openings in separate etching processes is shown. Figure 4A As shown, first, the first insulating layer 313 and the second insulating layer 314 are patterned using a first patterned photoresist layer (not shown) to form the second openings 360, wherein the first patterned photoresist layer includes openings for forming the second openings 360 but not for forming any third openings. Next, the first insulating layer 313 and the second insulating layer 314 can be etched in the non-array area 110 by a first etching process to form second openings 360 that are each aligned with the corresponding first contact portion 315-1. The first patterned photoresist layer can be removed. Then, another photoresist layer can be spin-coated onto the second insulating layer 314 and fill the second openings 360, thereby forming a photoresist portion 408 in each second opening 360. The photoresist layer can be patterned to form a second patterned photoresist layer 404, which includes openings 406 for forming the third openings in the second insulating layer 314. A second etching process can be performed using the second patterned photoresist layer 404 as an etching mask to form a third opening 358 in the second insulating layer 314. The second patterned photoresist layer 404 and the photoresist portion 408 can then be removed. In some embodiments, the first etching process and the second etching process can each include a suitable dry etch and / or wet etch. In some embodiments, removing the photoresist can include an ashing process.

[0084] Return Reference Figure 5 , the method 500 proceeds to operation 514 where a second contact portion is formed in each of the second openings, and a third contact portion is formed in each of the third openings. Figure 3H The corresponding structure is shown.

[0085] like Figure 3HAs shown, a second contact portion 315-2 is formed in each second opening 360, and a third contact portion 341 is formed in each third opening 358. The second contact portion 315-2 can each contact the corresponding first contact portion 315-1. In some embodiments, each first contact portion 315-1 and the corresponding second contact portion 315-2 can form a contact structure 315, such as a TSC. The second contact portion 315-2 and the third contact portion 341 can each include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the second contact portion 315-2 and the third contact portion 341 can be formed by depositing a conductive material layer to fill the second opening 360 and the third opening 358 and performing a recess etch (e.g., a blank etch) to remove any excess conductive material on the second insulating layer 314. In some embodiments, the depositing of the conductive material includes CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. The recess etching may include appropriate dry etching and / or wet etching.

[0086] Return Reference Figure 5 , the method 500 proceeds to operation 516 , where a first contact layer conductively connected to the second contact portion is formed, and a second contact layer conductively connected to the third contact portion is formed. Figures 3I-3K The corresponding structure is shown.

[0087] like Figure 3I As shown, the contact material layer 362 can be formed to contact the second contact portion 315-2 and the third contact portion 341. The contact material layer 362 can include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the contact material layer 362 can be deposited using CVD, PVD, ALD, electroplating, chemical plating, or a combination thereof.

[0088] like Figure 3JAs shown, a patterned photoresist layer 364 can be formed over the contact material layer 362. The patterned photoresist layer 364 can include one or more openings 366 for patterning the contact material layer 362 to disconnect a portion of the contact material layer 362 that is conductively connected to the third contact portion 341 (e.g., the NAND memory string 317) from another portion of the contact material layer 362 that is conductively connected to the contact structure 315. In some embodiments, in the xy plane, the opening 366 can be located between the third contact portion 341 and the contact structure 315 and can contact the contact material layer 362. The patterned photoresist layer 364 can be formed by spin coating the photoresist layer over the contact material layer 362 and patterning the photoresist layer using a photolithography process.

[0089] like Figure 3K As shown, a first contact layer 321 is formed that is conductively connected to the second contact portion 315-2 (or the contact structure 315), and a second contact layer 323 is formed that is conductively connected to the third contact portion 341. The first contact layer 321 can be disconnected from the second contact layer 323 by one or more openings 325 between the first contact layer 321 and the second contact layer 323. The openings 325 can be formed by etching the contact material layer 362 using a patterned photoresist layer 364 as an etching mask. In some embodiments, the etching of the contact material layer 362 includes an appropriate dry etching and / or wet etching method. The patterned photoresist layer 364 can then be removed using an ashing process.

[0090] Return Reference Figure 5 , the method 500 proceeds to operation 518 , where the first pad output interconnect is conductively connected to the first contact layer, and the second pad output interconnect is conductively connected to the second contact layer. Figures 3L-3N The corresponding structure is shown.

[0091] like Figure 3L As shown, a dielectric material can be deposited over the first contact layer 321 and the second contact layer 323 to form one or more dielectric layers. The dielectric material can fill the opening 325 to provide insulation between the first contact layer 321 and the second contact layer 323. In some embodiments, a first dielectric material is deposited in contact with the first and second contact layers 321 and filling the opening 325, thereby forming a first dielectric layer 327. A second dielectric material can be deposited over the first dielectric layer 327, thereby forming a second dielectric layer 329. In some embodiments, the first dielectric layer 327 includes silicon oxide, and the second dielectric layer 329 includes silicon nitride. The deposition of the first and second dielectric materials can each include CVD, PVD, ALD, or a combination thereof.

[0092] As shown in Figure 3M patterned photoresist layer 368 can be formed over the second dielectric layer 329. The patterned photoresist layer 368 can include one or more openings 370 for patterning the first dielectric layer 327 and the second dielectric layer 329 and forming the pad output interconnects. In some embodiments, the openings 370 can be positioned over the contact structures 315 and the third contact portions 341, respectively. The patterned photoresist layer 368 can be formed by spin-coating a photoresist layer over the second dielectric layer 329 and patterning the photoresist layer using a photolithography process. The first dielectric layer 327 and the second dielectric layer 329 can be etched using the patterned photoresist layer 368 as an etch mask to form corresponding openings (not shown) in the first dielectric layer 327 and the second dielectric layer 329. At least one of the openings can be in contact with the first contact layer 321, and at least one of the openings can be in contact with the second contact layer 323. The patterned photoresist layer 368 can be removed using an ashing process.

[0093] As shown in Figure 3N pad output interconnects 319 can be formed in the openings. At least one of the pad output interconnects 319 can be in contact with the first contact layer 321, and at least one of the pad output interconnects can be in contact with the second contact layer 323. The pad output interconnects 319 can include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the pad output interconnects 319 can be deposited using CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. In some embodiments, a recess etch (e.g., dry etch and / or wet etch) is performed after deposition to remove any excess conductive material on the second dielectric layer 329.

[0094] Figure 6 A block diagram illustrating a system 600 having a memory device in accordance with some aspects of the present disclosure is shown. The system 600 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other appropriate electronic device having a memory device therein. As Figure 6As shown, the system 600 can include a host 608 and a storage system 602 having one or more memory devices 604 and a memory controller 606. The host 608 can be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 608 can be configured to send data to or receive data from the memory devices 604.

[0095] The memory devices 604 can be any memory device disclosed herein, such as the 3D memory device 200. In some implementations, each memory device 604 includes a memory cell array, a peripheral circuit of the memory cell array. As described in detail above, the memory cell array and the peripheral circuit are stacked with each other in different planes.

[0096] According to some embodiments, a memory controller 606 is coupled to the memory device 604 and the host 608 and is configured to control the memory device 604. The memory controller 606 can manage data stored in the memory device 604 and communicate with the host 608. In some embodiments, the memory controller 606 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices (e.g., personal computers, digital cameras, mobile telephones, etc.). In some embodiments, the memory controller 606 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media-card (eMMC) used as data storage for mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 606 can be configured to control the operations of the memory device 604, such as read, erase, and program operations. In some embodiments, the memory controller 606 is configured to control the memory cell array through the first and second peripheral circuits. The memory controller 606 can also be configured to manage various functions related to data stored or to be stored in the memory device 604, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction codes (ECC) for data read from or written to the memory device 604. Any other appropriate functions, such as formatting the memory device 604, can also be performed by the memory controller 606. The memory controller 606 can communicate with external devices (e.g., the host 608) according to a particular communication protocol.For example, the memory controller 606 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, and the like.

[0097] The memory controller 606 and the one or more memory devices 604 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 6A, the memory controller 606 and a single memory device 604 can be integrated into a memory card 702. The memory card 702 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. The memory card 702 can further include a memory card connector 704 that couples the memory card 702 with a host (e.g., the host 608 in FIG. 6B). In another example as shown in FIG. 6B, the memory controller 606 and multiple memory devices 604 can be integrated into an SSD 706. The SSD 706 can also include an SSD connector 708 that couples the SSD 706 with a host (e.g., the host 608 in FIG. 6B). In some implementations, the storage capacity and / or operating speed of the SSD 706 is greater than that of the memory card 702. Figure 7A Figure 6 Figure 7B Figure 6

[0098] ​​​​According to an aspect of the present disclosure, a 3D memory device includes a first semiconductor structure and a second semiconductor bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with a source end of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure in the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

[0099] In some embodiments, the first semiconductor structure further includes a second contact structure through the insulating layer. The insulating layer laterally contacts the semiconductor layer and insulates the contact structure and the second contact structure from each other. The insulating layer insulates the contact structure and the second contact structure from the semiconductor layer.

[0100] In some embodiments, the semiconductor layer includes a first portion in a core region of the first semiconductor structure and a second portion in a non-array region of the first semiconductor structure. In some embodiments, the insulating layer is in the non-array region of the first semiconductor structure and insulates the first portion of the semiconductor layer from the second portion.

[0101] In some embodiments, the semiconductor layer is in a core region of the first semiconductor structure; and the insulating layer is in a staircase region of the first semiconductor structure.

[0102] In some embodiments, the semiconductor layer is in a core region of the first semiconductor structure; and the insulating layer is in a non-array region of the first semiconductor structure and outside of a staircase region of the first semiconductor structure.

[0103] In some embodiments, the insulating layer includes a dielectric material.

[0104] In some embodiments, the insulating layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0105] In some embodiments, an area of the insulating layer is greater than an area in which the plurality of contact structures are formed and less than or equal to the non-array region.

[0106] In some embodiments, the semiconductor layer and the insulating layer have a same thickness in a range of 100 nm to 600 nm.

[0107] In some embodiments, the semiconductor layer includes doped polysilicon.

[0108] In some embodiments, an area of the semiconductor layer is greater than or equal to an area in which all of the NAND memory strings are formed.

[0109] In some embodiments, the first semiconductor structure further includes a pad-out interconnect layer; and the second semiconductor structure further includes a substrate.

[0110] Another aspect of the present disclosure provides a 3D memory device including a first semiconductor structure having a core region and a non-array region. The first semiconductor structure includes an array of NAND memory strings in a sub-region of the core region, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in the non-array region, and a plurality of contact structures in the insulating layer and in another sub-region of the non-array region. The insulating layer electrically insulates the contact structures from the semiconductor layer. The 3D memory device further includes a second semiconductor structure bonded with the first semiconductor layer. The second semiconductor structure includes a transistor.

[0111] In some embodiments, an area of the insulating layer is equal to or greater than an area of the other sub-region and is less than or equal to an area of the non-array region; and the insulating layer insulates the contact structures from each other.

[0112] In some embodiments, an area of the semiconductor layer is equal to or greater than an area of the sub-region.

[0113] In some embodiments, the insulating layer includes a dielectric material.

[0114] In some embodiments, the insulating layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0115] In some embodiments, the semiconductor layer and the insulating layer have a same thickness in a range of 100 nm to 600 nm.

[0116] In some embodiments, the semiconductor layer includes doped polysilicon.

[0117] In some embodiments, the first semiconductor structure further includes a pad-out interconnect layer; and the second semiconductor structure further includes a substrate.

[0118] Another aspect of the present disclosure provides a method for forming a 3D memory device. The method includes bonding together a first semiconductor structure and a second semiconductor structure, the first semiconductor structure having a core region and a non-array region. The method further includes depositing a doped amorphous silicon layer over the core region and the non-array region of the first semiconductor structure, removing a first portion of the doped amorphous silicon layer in the non-array region to form an opening exposing a first contact portion of the first semiconductor structure, converting a second portion of the doped amorphous silicon layer in the core region to a doped polysilicon layer, forming an insulating layer in the opening, and forming a second contact portion in the insulating layer. The second contact portion is in contact with the first contact portion.

[0119] In some embodiments, the method further includes converting a first portion of the doped amorphous silicon layer to a doped polysilicon portion prior to converting the second portion of the doped amorphous silicon layer. Removing the first portion of the doped amorphous silicon layer includes selectively removing the doped polysilicon portion from the doped amorphous silicon layer.

[0120] In some embodiments, converting the first portion of the doped amorphous silicon layer includes performing a localized thermal treatment on the first portion of the doped amorphous silicon layer.

[0121] In some embodiments, converting the second portion of the doped amorphous silicon layer includes performing another localized treatment on the second portion of the doped amorphous silicon layer.

[0122] In some embodiments, the localized thermal treatment and the other localized thermal treatment each include a respective laser anneal process.

[0123] In some embodiments, the respective laser anneal processes have an anneal temperature in a range of 1300 degrees Celsius to 1700 degrees Celsius and include a plurality of laser pulses each having a pulse time of 100 ns to 300 ns.

[0124] In some embodiments, the etchant used to selectively etch the doped polysilicon portion includes ammonia.

[0125] In some embodiments, depositing the doped amorphous silicon layer includes a low temperature deposition process and an in-situ doping process.

[0126] In some embodiments, the doped amorphous silicon layer is doped with an N-type dopant, where the N-type dopant includes at least one of phosphorous or arsenic.

[0127] In some embodiments, the insulating layer is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof.

[0128] In some embodiments, forming the first semiconductor structure includes forming an array of NAND strings and a first contact portion portion over a substrate; and thinning the substrate to expose source ends of the NAND strings.

[0129] In some embodiments, depositing the doped amorphous silicon layer is to contact the doped amorphous silicon layer to the source ends of the NAND strings.

[0130] In some embodiments, the method further includes depositing an insulating material to fill the opening and over the doped polysilicon layer to form an insulating layer in the opening and a second insulating layer over the insulating layer. The second insulating layer is located in the core region and the non-array region.

[0131] In some embodiments, the method further includes a second opening in the insulating layer and the second insulating layer for exposing the first contact portion, a third opening in the second insulating layer for exposing the doped polysilicon layer, and a second contact portion in the second opening and a third contact portion in the third opening. The third contact portion is in contact with the doped polysilicon layer.

[0132] In some embodiments, the second opening and the third opening are formed in a same patterning process.

[0133] In some embodiments, the method further includes forming, over the second insulating layer, a first contact layer electrically connected to the second contact portion and a second contact layer electrically connected to the third contact portion. The first contact layer and the second contact layer are insulated from each other. The method can further include forming, over the first contact layer and the second contact layer, a pad output interconnect layer. The pad output interconnect layer includes respective contact structures electrically connected to the first contact layer and the second contact layer.

[0134] In some embodiments, forming the second semiconductor structure includes forming a peripheral circuit over a respective substrate. The peripheral circuit includes a plurality of transistors.

[0135] In some embodiments, the aspect ratio of the opening is less than or equal to 1 / 3.

[0136] Another aspect of the disclosure provides a system. The system includes a memory device configured to store data. The memory device includes a first semiconductor structure having an array of NAND memory strings, a semiconductor layer in contact with a source end of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, a contact structure in the insulating layer, wherein the insulating layer electrically isolates the contact structure from the semiconductor layer, and a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure includes a peripheral circuit. The system further includes a memory controller coupled to the memory device and configured to control the array of NAND memory strings through the peripheral circuit.

[0137] The foregoing description of specific implementations can readily be modified and / or adjusted to provide various applications. Accordingly, such modifications and adjustments are intended to be within the scope and spirit of the disclosed implementations. Based on the teachings and guidance provided herein, a person skilled in the art should not have difficulty applying the teachings and guidance to new and / or different applications without undue experimentation.

[0138] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: a first semiconductor structure, the first semiconductor structure comprising: an array of NAND memory strings, a semiconductor layer in contact with a source end of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer; a contact structure in the insulating layer, wherein the insulating layer electrically insulates the contact structure from the semiconductor layer; a contact in contact with the semiconductor layer, wherein the semiconductor layer is between the contact and the array of NAND memory strings; and two or more contact layers spaced apart from each other, wherein a first contact layer of the contact layers is in contact with the contact and the contact is between the semiconductor layer and the first contact layer; and a second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure comprising a transistor.

2. The 3D memory device of claim 1, wherein: the first semiconductor structure further comprises a second contact structure through the insulating layer; the insulating layer is laterally in contact with the semiconductor layer and insulates the contact structure and the second contact structure from each other; and the insulating layer insulates the contact structure and the second contact structure from the semiconductor layer.

3. The 3D memory device of claim 1 or 2, wherein: the semiconductor layer comprises a first portion in a core region of the first semiconductor structure and a second portion in a non-array region of the first semiconductor structure; and the insulating layer is in the non-array region of the first semiconductor structure and insulates the first portion of the semiconductor layer from the second portion.

4. The 3D memory device of claim 3, wherein: the semiconductor layer is in a core region of the first semiconductor structure; and the insulating layer is in a staircase region of the first semiconductor structure.

5. The 3D memory device of claim 3, wherein: the semiconductor layer is in a core region of the first semiconductor structure; and the insulating layer is in the non-array region of the first semiconductor structure and outside a staircase region of the first semiconductor structure.

6. The three-dimensional memory device of claims 1 or 2, wherein, the insulating layer comprises a dielectric material.

7. The three-dimensional memory device of claims 1 or 2, wherein, the insulating layer comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride.

8. The three-dimensional memory device of claim 3, wherein, an area of the insulating layer is greater than an area in which a plurality of contact structures are formed and less than or equal to the non-array region.

9. The three-dimensional memory device of claims 1 or 2, wherein, the semiconductor layer and the insulating layer have a same thickness in a range of 100 nm to 600 nm.

10. The three-dimensional memory device of claims 1 or 2, wherein, the semiconductor layer comprises doped polysilicon.

11. The three-dimensional memory device of claims 1 or 2, wherein, an area of the semiconductor layer is greater than or equal to an area in which all of the NAND memory strings are formed.

12. The 3D memory device of claim 1 or 2, wherein: the first semiconductor structure further comprises a pad-out interconnect layer; and the second semiconductor structure further comprises a substrate.

13. The three-dimensional memory device of claims 1 or 2, wherein, the first semiconductor structure further comprises one or more insulating layers between the contact layers spaced apart from each other.

14. The three-dimensional memory device of claims 1 or 2, wherein, The first semiconductor structure further includes a pad output interconnect, the first contact portion layer being between the pad output interconnect and the contact portion.

15. The three-dimensional memory device of claims 1 or 2, wherein, The contact portion structure is in contact with a second contact portion layer of the contact portion layers different from the first contact portion layer.

16. The three-dimensional memory device of claim 15, wherein, The first semiconductor structure further includes a second pad output interconnect, the second contact portion layer being between the second pad output interconnect and the contact portion structure.

17. A three-dimensional (3D) memory device, comprising: a first semiconductor structure having a core region and a non-array region, the first semiconductor structure including: an array of NAND memory strings in a sub-region of the core region, a semiconductor layer in contact with a source end of the array of NAND memory strings, an insulating layer in the non-array region, a plurality of contact portion structures in the insulating layer and in another sub-region of the non-array region, wherein the insulating layer electrically insulates the contact portion structures from the semiconductor layer, a contact portion in contact with the semiconductor layer, wherein the semiconductor layer is between the contact portion and the array of NAND memory strings, and two or more contact portion layers spaced apart from each other, wherein a first contact portion layer of the contact portion layers is in contact with the contact portion, and the contact portion is between the semiconductor layer and the first contact portion layer, and a second semiconductor structure bonded to the first semiconductor layer, the second semiconductor structure including a transistor.

18. The three-dimensional memory device of claim 17, wherein: an area of the insulating layer is equal to or greater than an area of the other sub-region and is less than or equal to an area of the non-array region; and the insulating layer insulates the contact portion structures from each other.

19. The three-dimensional memory device of claim 17 or 18, wherein: an area of the semiconductor layer is equal to or greater than an area of the sub-region.

20. The three-dimensional memory device of claim 17 or 18, wherein, the insulating layer includes a dielectric material.

21. The three-dimensional memory device of claim 17 or 18, wherein, the insulating layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

22. The three-dimensional memory device of claim 17 or 18, wherein, the semiconductor layer and the insulating layer have a same thickness in a range of 100 nm to 600 nm.

23. The three-dimensional memory device of claim 17 or 18, wherein, the semiconductor layer includes doped polysilicon.

24. The three-dimensional memory device of claim 17 or 18, wherein: the first semiconductor structure further includes a pad output interconnect layer; and the second semiconductor structure further includes a substrate.

25. A method for forming a three-dimensional (3D) memory device, comprising: bonding together a first semiconductor structure and a second semiconductor structure, the first semiconductor structure having a core region and a non-array region; depositing a doped amorphous silicon layer over the core region and the non-array region of the first semiconductor structure; removing a first portion of the doped amorphous silicon layer in the non-array region to form an opening exposing a first contact portion portion of the first semiconductor structure; converting a second portion of the doped amorphous silicon layer in the core region to a doped polysilicon layer; forming an insulating layer in the opening; and forming a second contact portion portion in the insulating layer, the second contact portion portion being in contact with the first contact portion portion.

26. The method of claim 25, further comprising converting the first portion of the doped amorphous silicon layer to a doped polysilicon portion prior to converting the second portion of the doped amorphous silicon layer, wherein, removing the first portion of the doped amorphous silicon layer includes: selectively removing the doped polysilicon portion from the doped amorphous silicon layer.

27. The method of claim 25, wherein, converting the first portion of the doped amorphous silicon layer includes performing a local thermal treatment on the first portion of the doped amorphous silicon layer.

28. The method of any one of claims 25-27, wherein, converting the second portion of the doped amorphous silicon layer includes performing another local thermal treatment on the second portion of the doped amorphous silicon layer.

29. The method of claim 28, wherein, the local thermal treatment and the other local thermal treatment each include a respective laser anneal process.

30. The method of claim 29, wherein, the respective laser anneal processes have an anneal temperature in a range of 1300 degrees Celsius to 1700 degrees Celsius and include a plurality of laser pulses each having a pulse time of 100 ns to 300 ns.

31. The method of claim 26 or 27, wherein, an etchant used to selectively etch the doped polysilicon portion includes ammonia.

32. The method of any one of claims 25-27, wherein, depositing the doped amorphous silicon layer includes a low temperature deposition process and an in-situ doping process.

33. The method of claim 32, wherein, the doped amorphous silicon layer is doped with an N-type dopant, wherein the N-type dopant includes at least one of phosphorous or arsenic.

34. The method of any one of claims 25-27, wherein, the insulating layer is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof.

35. The method of any one of claims 25-27, wherein, forming the first semiconductor structure includes: forming an array of NAND strings and the first contact portion over a substrate; and thinning the substrate to expose source ends of the NAND strings.

36. The method of claim 35, wherein, depositing the doped amorphous silicon layer to contact the doped amorphous silicon layer with the source ends of the NAND strings.

37. The method of any one of claims 25-27, further comprising depositing an insulating material to fill the opening and to be deposited over the doped polysilicon layer to form the insulating layer in the opening and a second insulating layer over the insulating layer, the second insulating layer being in the core region and the non-array region.

38. The method of claim 37, further comprising forming: a second opening in the insulating layer and the second insulating layer to expose the first contact portion; a third opening in the second insulating layer to expose the doped polysilicon layer; and a second contact portion in the second opening and a third contact portion in the third opening, the third contact portion being in contact with the doped polysilicon layer. the second opening and the third opening are formed in a same patterning process.

39. The method of claim 38, wherein, 40. The method of claim 38 or 39, further comprising: forming a first contact layer electrically connected to the second contact portion and a second contact layer electrically connected to the third contact portion over the second insulating layer, the first contact layer and the second contact layer being insulated from each other; and forming a pad output interconnect layer over the first contact layer and the second contact layer, wherein the pad output interconnect layer includes respective contact structures electrically connected to the first contact layer and the second contact layer. forming the second semiconductor structure includes forming a peripheral circuit including a plurality of transistors over respective substrates. an aspect ratio of the opening is less than or equal to 1 / 3.

41. The method of any one of claims 25-27, wherein, ​ 42. The method of any one of claims 25-27, wherein, ​ 43. A storage system, comprising: a storage device configured to store data, the storage device comprising: a first semiconductor structure, the first semiconductor structure comprising: an array of NAND storage strings, a semiconductor layer in contact with a source terminal of the array of NAND storage strings, an insulating layer in contact with the semiconductor layer, a contact structure in the insulating layer, wherein the insulating layer electrically insulates the contact structure from the semiconductor layer, a contact in contact with the semiconductor layer, wherein the semiconductor layer is between the contact and the array of NAND storage strings; and two or more contact layers spaced apart from each other, wherein a first contact layer of the contact layers is in contact with the contact and the contact is between the semiconductor layer and the first contact layer; and a second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure comprising a peripheral circuit; and a memory controller coupled to the storage device and configured to control the array of NAND storage strings through the peripheral circuit.

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