Method and device for inserting pseudo sequence in data modulation

Abstract

A method and apparatus for inserting a pseudo sequence during data modulation in a communication system according to a channel state and a link state, etc. are disclosed. In an embodiment, a method for data modulation by a wireless communication node of a wireless communication system includes: inserting at least one first pseudo sequence into a first data sequence in a first data block; and inserting at least one second pseudo sequence into a second data sequence in a second data block; wherein a first length of the first pseudo sequence is different from a second length of the second pseudo sequence, and wherein the second pseudo sequence includes the first pseudo sequence or is included in the first pseudo sequence.

Description

Technical Field

[0001] The present disclosure relates generally to wireless communications, and more particularly, to a method and apparatus for inserting a dummy sequence during data modulation in a communication system according to a channel state, a link state, etc. Background Art

[0002] 4G LTE (fourth generation long term evolution) adopts orthogonal frequency division multiplexing (OFDM) technology, and the resources in the time-frequency domain composed of subcarriers and OFDM symbols form the wireless resources of the LTE system in the time-frequency domain. Cyclic prefix (CP) is used in OFDM to resist multipath delay. However, because CP does not carry any useful data, the addition of CP increases the wireless resource overhead. Due to the increased demand for subcarrier spacing and the reduction in symbol length, the resource overhead problem caused by CP becomes more serious, especially when the frequency band operates in the high frequency range (e.g., ≥24.25GHz). In addition, when the frequency band operates in the high frequency range, both CP-OFDM spectrum leakage and peak-to-average ratio will increase. Summary of the invention

[0003] The example embodiments disclosed herein are intended to solve problems related to one or more problems existing in the prior art, as well as to provide additional features, which will become apparent by reference to the following detailed description when combined with the accompanying drawings. According to various embodiments, example systems, methods, devices, and computer program products are disclosed herein. However, it should be understood that these embodiments are presented by way of example and not by way of limitation, and it will be apparent to those of ordinary skill in the art who read this disclosure that various modifications may be made to the disclosed embodiments while remaining within the scope of this disclosure.

[0004] OFDM technology uses CP to solve the multipath delay problem and divides the frequency selective channel into a set of parallel flat fading channels, which simplifies the channel estimation method. DFT-s-OFDM (Discrete Fourier Transform Extended OFDM) technology is based on CP-OFDM and adds discrete Fourier transform DFT before subcarrier mapping, which solves the high PARP (peak-to-average power ratio) problem in CP-OFDM. Waveforms based on CP-OFDM are constantly used in 5G NR (fifth generation new air interface). Although CP can resist multipath delay, CP does not carry any useful data, which increases wireless resource overhead. Due to the increased demand for subcarrier spacing and the reduction in symbol length, the resource overhead problem caused by CP becomes more serious, especially when the frequency band operates in the high frequency range (e.g., ≥24.25GHz). In addition, the spectrum waveform leakage based on CP-OFDM is also relatively large. 5G NR supports the mixed use of different parameter sets (such as numerology), that is, it supports different subcarrier spacings between adjacent subbands, and therefore, specific interference occurs between adjacent subbands. Although the interference and spectrum leakage between subbands can be slightly reduced by some implementation techniques (such as using soft CP or filtering methods), a specific guard interval is still required between subbands with different subcarrier spacings. This reduces the spectrum efficiency. For high-frequency scenarios, the current IEEE 802.11ad protocol uses a single carrier (SC) technology with low PAPR. GI (guard interval) has the advantages of supporting channel estimation, time / frequency tracking, and phase noise compensation. However, the length of GI is fixed and cannot flexibly adapt to changes in the wireless channel environment, thereby reducing the spectrum efficiency. Therefore, there is a need to develop a method and an apparatus to reduce the resource overhead caused by fixed CP / GI, and can also well suppress out-of-band leakage, maintain low PAPR and high channel estimation accuracy.

[0005] In an embodiment, a method for data modulation by a wireless communication node of a wireless communication system comprises: inserting at least one first pseudo-sequence into a first data sequence in a first data block; and inserting at least one second pseudo-sequence into a second data sequence in a second data block; wherein a first length of the first pseudo-sequence is different from a second length of the second pseudo-sequence, and wherein the second pseudo-sequence includes the first pseudo-sequence or is included in the first pseudo-sequence.

[0006] In yet another embodiment, a method for data modulation by a wireless communication device of a wireless communication system comprises: receiving a first data block from a wireless communication node, wherein the first data block comprises at least one first pseudo-sequence and a first data sequence; and receiving a second data block from the wireless communication node, wherein the second data block comprises at least one second pseudo-sequence and a second data sequence; wherein a first length of the first pseudo-sequence is different from a second length of the second pseudo-sequence, and wherein the second pseudo-sequence comprises the first pseudo-sequence or is included in the first pseudo-sequence.

[0007] In another embodiment, a method for data modulation by a wireless communication device of a wireless communication system includes: inserting at least one first pseudo sequence into a first data sequence in a first data block; and inserting at least one second pseudo sequence into a second data sequence in a second data block; wherein a first length of the first pseudo sequence is different from a second length of the second pseudo sequence, and wherein the second pseudo sequence includes the first pseudo sequence or is included in the first pseudo sequence.

[0008] In another embodiment, a method for data modulation by a wireless communication node of a wireless communication system includes: receiving a first data block from a wireless communication device, wherein the first data block includes at least one first pseudo-sequence and a first data sequence; and receiving a second data block from the wireless communication device, wherein the second data block includes at least one second pseudo-sequence and a second data sequence; wherein a first length of the first pseudo-sequence is different from a second length of the second pseudo-sequence, and wherein the second pseudo-sequence includes the first pseudo-sequence or is included in the first pseudo-sequence.

[0009] In another embodiment, a computing device includes at least one processor and a memory coupled to the processor, the at least one processor configured to perform the method.

[0010] In another embodiment, a non-transitory computer-readable medium has stored thereon computer-executable instructions for performing the method. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] When read together with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that the various features are not necessarily drawn to scale. In fact, the size and geometry of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0012] Figure 1A An exemplary wireless communication network according to some embodiments of the present disclosure is shown.

[0013] Figure 1B A block diagram of an exemplary wireless communication system according to some embodiments of the present disclosure is shown.

[0014] Figure 2A method for inserting a dummy sequence during data modulation in a wireless communication system according to some embodiments of the present disclosure is shown.

[0015] Figure 3A A schematic diagram of a data block according to some embodiments of the present disclosure is shown.

[0016] Figure 3B A schematic diagram of a data block according to some embodiments of the present disclosure is shown.

[0017] Figure 3C A schematic diagram of a data block according to some embodiments of the present disclosure is shown.

[0018] Figure 3D A schematic diagram of a data block according to some embodiments of the present disclosure is shown.

[0019] Figure 3E A plurality of data blocks in two adjacent frames are shown according to some embodiments of the present disclosure.

[0020] Figure 3F A plurality of data blocks in two adjacent frames are shown according to some embodiments of the present disclosure.

[0021] Figure 4 A schematic diagram of a data modulation system for data preparation according to some embodiments of the present disclosure is shown.

[0022] Figure 5 A method for inserting a dummy sequence during data modulation in a wireless communication system according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0023] Various exemplary embodiments of the present invention are described below with reference to the accompanying drawings so that those of ordinary skill in the art can make and use the present invention. It will be apparent to those of ordinary skill in the art that, after reading this disclosure, various changes or modifications may be made to the examples described herein without departing from the scope of the present invention. Therefore, the present invention is not limited to the exemplary embodiments and applications described or illustrated herein. In addition, the specific order or hierarchy of steps in the methods disclosed herein are merely exemplary methods. Based on design preferences, the specific order or hierarchy of steps of the disclosed methods or processes may be rearranged while remaining within the scope of the present invention. Therefore, it will be understood by those of ordinary skill in the art that the methods and techniques disclosed herein present various steps or actions in a sample order, and unless otherwise expressly stated, the present invention is not limited to the specific order or hierarchy presented.

[0024] Embodiments of the present invention are described in detail with reference to the accompanying drawings. Although the same or similar components are shown in different drawings, they may be designated by the same or similar reference numerals. Detailed descriptions of constructions or processes known in the art may be omitted to avoid obscuring the subject matter of the present invention. In addition, terms are defined in consideration of their functions in embodiments of the present invention and may be changed according to the intention, usage, etc. of a user or operator. Therefore, they should be defined based on the overall content of this specification.

[0025] Figure 1A An exemplary wireless communication network 100 according to some embodiments of the present disclosure is shown. In a wireless communication system, a network-side wireless communication node or base station (BS) may be a node B, an E-utran node B (also referred to as an evolved node B, eNodeB or eNB), a micro-station, a femto-station or the like. A terminal-side node or user equipment (UE) may be a long-range communication system, such as a mobile phone, a smart phone, a personal digital assistant (PDA), a tablet computer, a laptop, or a short-range communication system, such as, for example, a wearable device, a vehicle with a vehicle communication system, and the like. The network and terminal-side communication nodes are represented by BS 102 and UE 104, respectively, which are generally referred to as "communication nodes" in all embodiments of the present disclosure hereinafter. Such communication nodes may be able to perform wireless and / or wired communications according to some embodiments of the present invention. Note that all embodiments are preferred examples only and are not intended to limit the present disclosure. Therefore, it should be understood that while remaining within the scope of the present disclosure, the system may include any desired UE and BS combination.

[0026] refer to Figure 1A , the wireless communication network 100 includes a BS 102 and UEs 104a and 104b (collectively referred to herein as UEs 104). BS 102 and UEs 104 are contained within the geographic boundaries of a cell 101. Wireless transmissions from the transmit antennas of UEs 104 to the receive antennas of BS 102 are referred to as uplink transmissions, and wireless transmissions from the transmit antennas of BS 102 to the receive antennas of UEs 104 are referred to as downlink transmissions. Although only two UEs 104 are shown, Figure 1A 101, but it should be noted that any number of UEs 104 may be included in cell 101 and is within the scope of the present invention. In some embodiments, the coverage of uplink communication 105b is greater than the coverage of uplink communication 105a, as shown by dashed circles 112 and 110, respectively. BS 102 is located at the intercept area of ​​coverage areas 110 and 112 for BS 102 to perform uplink communications with UE 104a and UE 104b in cell 101.

[0027] The direct communication channel 105 / 103 between the UE 104 and the BS 102 may be through an interface such as a Uu interface, which is also known as the Universal Mobile Telecommunications System (UMTS) air interface. The direct communication channel (side link transmission) 106 between the UEs may be through a PC5 interface, which is introduced to address high mobile speeds and high density applications such as vehicle-to-vehicle (V2V) communications. The BS 102 is connected to a core network (CN) 108 through an external interface 107 such as an Iu interface.

[0028] UE 104a and 104b obtain their synchronization timing from BS 102, which obtains its own synchronization timing from the core network 108 through Internet timing, such as a public time NTP (Network Time Protocol) server or an RNC (Radio Frequency Simulation System Network Controller) server. This is called network-based synchronization. Alternatively, BS 102 can also obtain synchronization timing from a global navigation satellite system (GNSS) (not shown) through satellite signals 106, especially for large BSs in large cells with direct line of sight to the sky, which is called satellite-based synchronization.

[0029] Figure 1B A block diagram of an exemplary wireless communication system 150 according to some embodiments of the present disclosure is shown. The system 150 may include components and elements configured to support known or conventional operating features that do not require detailed description herein. In an exemplary embodiment, the system 150 may be used in applications such as Figure 1A Data symbols are sent and received in the wireless communication environment of the wireless communication network 100 as described above.

[0030] System 150 generally includes a BS 102 and two UEs 104a and 104b, collectively referred to as UE 104 hereinafter for ease of discussion. BS 102 includes a BS transceiver module 152, a BS antenna array 154, a BS memory module 156, a BS processor module 158, and a network interface 160, each coupled to and interconnected with each other via a data communication bus 180 as needed. UE 104 includes a UE transceiver module 162, a UE antenna 164, a UE memory module 166, a UE processor module 168, and an input / output (I / O) interface 169, each coupled to and interconnected with each other via a data communication bus 190 as needed. BS 102 communicates with UE 104 via a communication channel 192, which may be any wireless channel or other medium known in the art suitable for data transmission as described herein.

[0031] As will be understood by those skilled in the art, in addition to Figure 1BIn addition to those shown in the embodiment disclosed herein, system 150 may also include any number of blocks, modules, circuits, etc. It will be appreciated by those skilled in the art that the various illustrative blocks, modules, circuits, and processing logic described in conjunction with the embodiments disclosed herein may be implemented in hardware, computer-readable software, firmware, or any actual combination thereof. In order to clearly illustrate this interchangeability and compatibility of hardware, firmware, and software, various illustrative components, blocks, modules, circuits, and steps are generally described according to their functions. Whether such functions are implemented as hardware, firmware, or software depends on specific applications and design constraints imposed on the entire system. Personnel familiar with the concepts described herein may implement such functions in a suitable manner for each specific application, but such implementation decisions should not be interpreted as limiting the scope of the present invention.

[0032] Wireless transmission from the transmit antenna of UE 104 to the receive antenna of BS 102 is referred to as an uplink transmission, and wireless transmission from the transmit antenna of BS 102 to the receive antenna of UE 104 is referred to as a downlink transmission. According to some embodiments, UE transceiver 162 may be referred to herein as an "uplink" transceiver 162, which includes an RF transmitter and receiver circuit each coupled to UE antenna 164. A duplex switch (not shown) may alternatively couple the uplink transmitter or receiver to the uplink antenna in a time duplex manner. Similarly, according to some embodiments, BS transceiver 152 may be referred to herein as a "downlink" transceiver 152, which includes an RF transmitter and receiver circuit each coupled to antenna array 154. The downlink duplex switch may alternatively couple the downlink transmitter or receiver to the downlink antenna array 154 in a time division duplex manner. The operation of the two transceivers 152 and 162 is coordinated in time so that the uplink receiver is coupled to the uplink UE antenna 164 to receive transmissions over the wireless communication channel 193 at the same time as the downlink transmitter is coupled to the downlink antenna array 154. Preferably, there is tightly synchronized timing with only a minimum guard time between changes in duplex direction. The UE transceiver 162 communicates with the BS 102 via the wireless communication channel 192 through the UE antenna 164, or communicates with other UEs via the wireless communication channel 193 through the UE antenna 164. The wireless communication channel 193 can be any wireless channel suitable for sidelink transmission of data as described above or other media known in the art.

[0033] The UE transceiver 162 and the BS transceiver 152 are configured to communicate via a wireless data communication channel 192 and cooperate with an appropriately configured RF antenna arrangement 154 / 164 that can support a specific wireless communication protocol and modulation scheme. In some embodiments, the BS transceiver 152 is configured to send a physical downlink control channel (PDCCH) and a configured slot structure related information (SFI) entry set to the UE transceiver 162. In some embodiments, the UE transceiver 162 is configured to receive a PDCCH containing at least one SFI field from the BS transceiver 152. In some exemplary embodiments, the UE transceiver 162 and the BS transceiver 152 are configured to support industry standards such as long-term evolution (LTE) and emerging 5G standards and the like. However, it should be understood that the present invention is not necessarily limited to specific standards and associated protocols in application. Instead, the UE transceiver 162 and the BS transceiver 152 can be configured to support alternative or additional wireless data communication protocols, including future standards or variations thereof.

[0034] The BS processor module 158 and the UE processor module 168 are implemented or realized using a general purpose processor, a content addressable memory, a digital signal processor, an application specific integrated circuit, a field programmable gate array, any suitable programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. In this manner, the processor may be implemented as a microprocessor, a controller, a microcontroller, or a state machine, or the like. The processor may also be implemented as a combination of computing devices, for example, a combination of a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a digital signal processor core, or any other such configuration.

[0035] Then, the UE processor module 168 detects the PHR trigger message on the UE transceiver module 162, and the UE processor module 168 is further configured to determine at least one second SFI entry set based on at least one predefined algorithm and at least one first SFI entry set received and configured by the BS 102, wherein the at least one predefined algorithm is selected based on other parameters calculated or received information. The UE processor module 168 is further configured to generate at least one second SFI entry set and monitor the PDCCH received on the UE transceiver module 162 to further receive at least one SFI field. As used herein, "SFI entry set" means an SFI table or multiple SFI entries.

[0036] In addition, the steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be directly embodied in hardware, firmware, software modules executed by processor modules 158 and 168, respectively, or any practical combination thereof. Memory modules 156 and 166 may be implemented as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. In this regard, memory modules 156 and 166 may be coupled to processor modules 158 and 168, respectively, so that processor modules 158 and 168 can read information from and write information to memory modules 156 and 166, respectively. Memory modules 156 and 166 may also be integrated into their respective processor modules 158 and 168. In some embodiments, memory modules 156 and 166 may each include a cache memory for storing temporary variables or other intermediate information during the execution of instructions executed by processor modules 158 and 168, respectively. The memory modules 156 and 166 may also each include non-volatile memory for storing instructions that are executed by the processor modules 158 and 168, respectively.

[0037] The network interface 160 generally represents the hardware, software, firmware, processing logic and / or other components of the base station 102, which enables bidirectional communication between the BS transceiver 152 and the communication nodes and other network components configured to communicate with the BS 102. For example, the network interface 160 can be configured to support Internet or WiMAX traffic. In a typical deployment, without limitation, the network interface 160 provides an 802.3 Ethernet interface so that the BS transceiver 152 can communicate with a computer network based on conventional Ethernet. In this way, the network interface 160 may include a physical interface for connecting to a computer network (e.g., a mobile switching center (MSC)). The term "configured for" or "configured to" as used herein with respect to a particular operation or function refers to a device, component, circuit, structure, machine, signal, etc. that is physically constructed, programmed, formatted and / or arranged to perform a specified operation or function. The network interface 160 may allow the BS 102 to communicate with other BSs or a core network via a wired or wireless connection.

[0038] Reference again Figure 1AAs mentioned above, BS 102 repeatedly broadcasts system information associated with BS 102 to one or more UEs (e.g., 104) to allow UE 104 to access the network within the cell 101 where BS 102 is located and generally operate normally within the cell 101. A plurality of information, such as, for example, downlink and uplink cell bandwidths, downlink and uplink configurations, configurations for random access, etc., may be included in the system information, which will be discussed in further detail below. Typically, BS 102 broadcasts a first signal carrying some primary system information (e.g., the configuration of cell 101) via a PBCH (physical broadcast channel). For clarity of illustration, such a broadcasted first signal is referred to herein as a "first broadcast signal". Note that BS 102 may subsequently broadcast one or more signals carrying some other system information via a corresponding channel (e.g., a physical downlink shared channel (PDSCH)), which is referred to herein as a "second broadcast signal", "third broadcast signal", etc.

[0039] Reference again Figure 1B In some embodiments, the primary system information carried by the first broadcast signal may be sent by BS 102 via communication channel 192 in a symbol format. According to some embodiments, the original form of the primary system information may be presented as one or more sequences of digital bits, and the one or more sequences of digital bits may be processed through multiple steps (e.g., encoding, scrambling, modulation, mapping steps, etc.), all of which may be processed by BS processor module 158 to become the first broadcast signal. Similarly, according to some embodiments, when UE 104 receives the first broadcast signal (in symbol format) using UE transceiver 162, UE processor module 168 may perform multiple steps (demapping, demodulating, decoding steps, etc.) to estimate the primary system information, such as, for example, the bit position, the number of bits of the primary system information, etc. The UE processor module 168 is also coupled to an I / O interface 169, which provides the UE 104 with the ability to connect to other devices such as a computer. The I / O interface 169 is a communication path between these accessories and the UE processor module 168.

[0040] In some embodiments, UE 104 may operate in a hybrid communication network, where the UE communicates with BS 102 and with other UEs (e.g., between 104a and 104b). As described in further detail below, UE 104 supports sidelink communications with other UEs, as well as downlink / uplink communications between BS 102 and UE 104. As discussed above, sidelink communications allow UEs 104a and 104b to establish direct communication links with each other or with other UEs from different cells without requiring BS 102 to relay data between UEs.

[0041] Figure 2 A method 200 for inserting a dummy sequence during data modulation in a wireless communication system according to some embodiments of the present disclosure is shown. It should be understood that the method may be used in Figure 2 Additional operations are provided before, during, and after the method 200, and some operations may be omitted or reordered. The communication system in the illustrated embodiment includes a BS 102 and a UE 104. In the illustrated embodiment, the UE 104 is within one of at least one service cell covered by the BS 102, i.e., the UE 104 is connected to the BS 102. In an embodiment, the BS 102 is a wireless access point or a wireless communication node. In some other embodiments, the UE 104 is a wireless station or a wireless communication device. It should be noted that any number of BSs 102 or UEs 104 may be used and is within the scope of the present invention.

[0042] Method 200 begins at operation 202, where, according to some embodiments, download (DL) data is prepared by BS 102. In some embodiments, the data preparation performed by BS 102 before transmitting the DL data to UE 104 includes at least one of the following processes: dividing the DL data into a plurality of first data sequences having a first length, inserting at least one pseudo sequence into the plurality of first data sequences, performing a discrete Fourier transform (DFT), performing subcarrier mapping in the frequency domain, inserting at least one guard subcarrier, performing an inverse fast Fourier transform (IFFT), filtering the plurality of first blocks, and performing digital-to-analog conversion on the plurality of first blocks, which are then sent to a receiving antenna of UE 104 via a transmitting antenna of BS 102. In some embodiments, the at least one pseudo sequence is inserted for at least one of the following reasons, including but not limited to: a cyclic prefix, assisted phase tracking, assisted channel estimation, and synchronization. In some embodiments, the pseudo sequence may also be named a reference sequence. The preparation performed by BS 102 in operation 202 is also performed in the following manner: Figure 4 Detailed discussion in.

[0043] The method 200 continues with operation 204, where, according to some embodiments, a plurality of first blocks are sent from the BS 102 to the UE 104. In some embodiments, each of the plurality of first blocks includes at least one of: a plurality of first data blocks, at least one reference signal block, and at least one synchronization block. In some embodiments, each of the plurality of first data blocks includes a first data sequence and a first dummy sequence.

[0044] In some embodiments, the first pseudo-sequence is selected by BS 102 from a pseudo-sequence set. In some embodiments, the pseudo-sequence set includes a plurality of pseudo-sequences. In some embodiments, the pseudo-sequence set is predetermined by the system. In some embodiments, the pseudo-sequence set includes a plurality of pseudo-sequences (i.e., a first number A of pseudo-sequences), wherein each of the plurality of pseudo-sequences includes M elements, i.e., the length M of the pseudo-sequence, wherein M is a positive integer and M is less than the length of the block, and wherein A is a positive integer. In some embodiments, each of the M elements is a complex number having a constant modulus value. In some embodiments, the pseudo-sequence set includes at least one base sequence, and the second number of pseudo-sequences (e.g., P) in the pseudo-sequence set includes at least one base sequence at the end, wherein P is a positive integer and P≤A, for example, the second pseudo-sequence 308 includes the first pseudo-sequence 306 at the end. In some embodiments, a plurality of pseudo-sequences in the pseudo-sequence set may have the same number of elements of different values. In some embodiments, each of the plurality of pseudo-sequences in the pseudo-sequence set has a sequence index number. In some other embodiments, the first pseudo sequence is cut out from one of the following: a Zadoff-Chu (ZC) sequence, a Golay complementary sequence, and a maximum length (M) sequence.

[0045] The method 200 continues with operation 206, where the plurality of first blocks are processed by the UE 104 and a channel is monitored according to some embodiments. In some embodiments, the processing of the plurality of first blocks includes at least one of: performing a DFT transform to the frequency domain, performing frequency domain equalization, transforming to the time domain using an IFFT, removing at least one reference block, and performing decoding and demodulation on the plurality of first data blocks. In some embodiments, monitoring of the channel is performed based on at least one reference block in the plurality of first blocks to obtain a channel state.

[0046] The method 200 continues with operation 208, where, according to some embodiments, a first message is sent from the UE 104 to the BS 102. In some embodiments, the first message includes a channel state determined by the UE 104 based on at least one reference block received from the BS 102. In some embodiments, the channel state includes a multipath delay. In some embodiments, the first message is sent via a physical uplink control channel (PUCCH). In some other embodiments, the first message is sent in a radio resource control (RRC) message.

[0047] The method 200 continues with operation 210, where, according to some embodiments, DL data is further prepared. In some embodiments, the second pseudo sequence is determined from the pseudo sequence set according to the channel state received in the first message. In some embodiments, the data preparation performed by the BS 102 before sending the DL data to the UE 104 includes at least one of the following processes: dividing the DL data into a plurality of second data sequences having a second length, inserting at least one pseudo sequence into the plurality of second data sequences, performing a discrete Fourier transform (DFT), performing subcarrier mapping in the frequency domain, inserting at least one guard subcarrier, performing an inverse fast Fourier transform (IFFT), filtering the plurality of second blocks, and performing digital-to-analog conversion on the plurality of second blocks, which are then sent to the receiving antenna of the UE 104 through the transmitting antenna of the BS 102. In some embodiments, each of the plurality of second blocks includes at least one of the following: a plurality of second data blocks, at least one reference block, and at least one synchronization block. In some embodiments, each of the plurality of second data blocks includes a second data sequence and a second pseudo sequence. In some other embodiments, the second pseudo sequence is truncated from one of: a Zadoff-Chu (ZC) sequence, a Golay complementary sequence, and a maximum length (M) sequence.

[0048] Method 200 continues with operation 212, where, according to some embodiments, a second message is sent from BS 102 to UE 104. In some embodiments, the second message includes: a pseudo-sequence index of a second pseudo-sequence used with the second data sequence to construct a second data block. In some other embodiments, the pseudo-sequence index of the second pseudo-sequence may be implicitly sent from BS 102 to UE 104, in which case operation 212 may be omitted.

[0049] The method 200 continues with operation 214 where a plurality of second chunks are sent from the BS 102 to the UE 104 according to some embodiments.

[0050] The method 200 continues with operation 216, where the plurality of second blocks are processed by the UE 104 and the channel is monitored according to some embodiments. In some embodiments, the processing of the plurality of second blocks includes at least one of: performing a DFT transform to the frequency domain, performing frequency domain equalization, transforming to the time domain using IFFT, removing at least one reference block, and performing decoding and demodulation on the plurality of second data blocks. In some embodiments, monitoring of the channel is performed based on at least one reference block in the plurality of second blocks to obtain a channel state.

[0051] It should be noted that there may be more than one UE 104, i.e., multiple UEs in the service cell of BS 102. In this case, time division multiplexing may be used to send DL data from BS 102 to each of the multiple UEs through different data blocks 302. Different data blocks 302 for different UEs may include at least one pseudo sequence, which is determined according to the channel state between each of the multiple UEs and BS 102, for example, different pseudo sequences are used for different UEs with different channel states. When the channel state (e.g., multipath delay) changes, BS 102 may change the pseudo sequences for different UEs.

[0052] Figure 3A A schematic diagram 300 of data blocks according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the schematic diagram 300 includes 2 data blocks, namely a first data block 302-1 and a second data block 302-2. It should be noted that in the illustrated embodiment, for the purpose of discussion, only 2 adjacent data blocks from DL or uplink (UL) data are shown, and the DL / UL data may include any number of data blocks. For example, there may be at least one first data block before the first data block 302-1, or there may be at least one second data block after the second data block 302-2. It should also be noted that the first data block 302-1 and the second data block 302-2 may also be separated by at least one other block, wherein the at least one other block may be at least one of the following: a reference block and a synchronization block, which is described below Figure 3E-3F This is discussed in further detail in .

[0053] In the illustrated embodiment, the first data block 302-1 includes a first data sequence 304-1, and the second data block includes a second data sequence 304-2. In the illustrated embodiment, the first data sequence 304-1 is longer than the second data sequence 304-2, i.e., the first data sequence 304-1 includes more data or elements than the second data sequence 304-2. In some embodiments, both the first data sequence 304-1 and the second data sequence 304-2 are smaller in size than the corresponding data blocks (e.g., 302-1 and 302-2).

[0054] In addition, the first data block 302-1 includes a first pseudo sequence 306-1, wherein the first pseudo sequence 306 is directly inserted at the end of the first data sequence 304-1. In the illustrated embodiment, the length of the first data block 302-1 is the sum of the length of the first data sequence 304-1 and the length of the first pseudo sequence 306. Similarly, the second data block 302-2 includes a second pseudo sequence 308, wherein the second pseudo sequence 308 is directly inserted at the end of the second data sequence 304-2. In the illustrated embodiment, the length of the second data block 302-2 is the sum of the length of the second data sequence 304-2 and the length of the second pseudo sequence 308. In the illustrated embodiment, the second pseudo sequence 308 is longer than the first pseudo sequence 306. In the illustrated embodiment, the second pseudo sequence 308 includes a sequence 310 and the first pseudo sequence 306. By using this method, if the two data blocks 302-1 and 302-2 are for the same UE 104, when an increased multipath delay is detected during data transmission, a longer pseudo sequence and a shorter data sequence can be dynamically constructed to increase resistance to multipath interference. By using this method, if the two data blocks 302 are from two different UEs, for example, the first data block 302-1 is from a first UE and the second data block 302-2 is from a second UE, the second UE can resist a larger multipath delay than the first UE.

[0055] In some embodiments, the first pseudo-sequence 306 and the second pseudo-sequence 308 are selected from a pseudo-sequence set according to the channel state. In some embodiments, the pseudo-sequence set is predetermined by the system. In some embodiments, the pseudo-sequence set includes a plurality of pseudo-sequences (i.e., a first number A of pseudo-sequences), wherein each of the plurality of pseudo-sequences includes M elements, i.e., the length M of the pseudo-sequence, wherein M is a positive integer and M is less than the length of the block, and wherein A is a positive integer. In some embodiments, each of the M elements is a complex number with a constant modulus value. In some embodiments, the pseudo-sequence set includes at least one base sequence, and the second number of pseudo-sequences (e.g., P) in the pseudo-sequence set includes at least one base sequence at the end, wherein P is a positive integer and P≤A, for example, the second pseudo-sequence 308 includes the first pseudo-sequence 306 at the end. In some embodiments, a plurality of pseudo-sequences in the pseudo-sequence set may have the same number of elements with different values. In some embodiments, each of the plurality of pseudo-sequences in the pseudo-sequence set has a sequence index number. In some other embodiments, the first dummy sequence 306 and the second dummy sequence 308 are truncated from one of: a Zadoff-Chu (ZC) sequence, a Golay complementary sequence, and a maximum length (M) sequence.

[0056] Figure 3BA schematic diagram 300 of data blocks according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the schematic diagram 300 includes 2 data blocks, namely a first data block 302-1 and a second data block 302-2. In some other embodiments, the first data block 302-1 and the second data block 302-2 each have a window size for FFT processing. It should be noted that in the illustrated embodiment, for the purpose of discussion, only 2 adjacent data blocks from DL or UL data are shown, and the DL / UL data may include any number of data blocks. For example, there may be at least one first data block before the first data block 302-1, or there may be at least one second data block after the second data block 302-2. It should also be noted that the first data block 302-1 and the second data block 302-2 may also be separated by at least one other block, wherein the at least one other block may be at least one of the following: a reference block and a synchronization block, which is described below Figure 3E-3F This is discussed in further detail in .

[0057] In the illustrated embodiment, the first data block 302-1 includes a first data sequence 304-1, and the second data block includes a second data sequence 304-2. In the illustrated embodiment, the first data sequence 304-1 is longer than the second data sequence 304-2, i.e., the first data sequence 304-1 includes more data or elements than the second data sequence 304-2. In some embodiments, both the first data sequence 304-1 and the second data sequence 304-2 are smaller in size than the corresponding data blocks (e.g., 302-1 and 302-2).

[0058] In addition, the first data block 302-1 includes a first pseudo sequence 306-1 and a third pseudo sequence 312, wherein the first pseudo sequence 306 is directly inserted at the end of the first data sequence 304-1, and the third pseudo sequence 312 is directly inserted at the beginning of the first data sequence 304-1. In the illustrated embodiment, the length of the first data block 302-1 is the sum of the length of the first data sequence 304-1, the length of the first pseudo sequence 306, and the length of the third pseudo sequence 312. Similarly, the second data block 302-2 includes a second pseudo sequence 308 and a third pseudo sequence, wherein the second pseudo sequence 308 is directly inserted at the end of the second data sequence 306-2, and the third pseudo sequence 312 is directly inserted at the beginning of the second data sequence 304-2. In the illustrated embodiment, the length of the second data block 302-2 is the sum of the length of the second data sequence 304-2, the length of the second pseudo sequence 308, and the length of the third pseudo sequence 312. In the illustrated embodiment, the second pseudo sequence 308 is longer than the first pseudo sequence 306. In the illustrated embodiment, second pseudo-sequence 308 includes sequence 310 and first pseudo-sequence 306 .

[0059] In some other embodiments, the third pseudo sequence 312 may also be inserted at the end of the first pseudo sequence 306 and at the end of the second pseudo sequence 308. In this case, the time window for FFT processing is defined between the beginning of the third pseudo sequence 312 and the beginning of the immediately following third pseudo sequence 312. Using this method, when an increased multipath delay is detected during data transmission, a longer pseudo sequence and a shorter data sequence may be dynamically constructed to increase resistance to multipath interference. The additional third pseudo sequence 312 may reduce interference between blocks caused by multipath delay and also reduce out-of-band leakage.

[0060] In some embodiments, the first pseudo sequence 306, the second pseudo sequence 308, and the third pseudo sequence 312 are selected from the pseudo sequence set according to the channel state. In some embodiments, the pseudo sequence set is predetermined by the system. In some embodiments, the pseudo sequence set includes a plurality of pseudo sequences (i.e., a first number A of pseudo sequences), wherein each of the plurality of pseudo sequences includes M elements, i.e., the length M of the pseudo sequence, wherein M is a positive integer and M is less than the length of the block, and wherein A is a positive integer. In some embodiments, each of the M elements is a complex number with a constant modulus value. In some embodiments, the pseudo sequence set includes at least one base sequence, and the second number of pseudo sequences (e.g., P) in the pseudo sequence set includes at least one base sequence at the end, wherein P is a positive integer and P≤A, for example, the second pseudo sequence 308 includes the first pseudo sequence 306 at the end. In some embodiments, the plurality of pseudo sequences in the pseudo sequence set may have the same number of elements with different values. In some embodiments, each of the plurality of pseudo sequences in the pseudo sequence set has a sequence index number. In some other embodiments, the first dummy sequence 306, the second dummy sequence 308, and the third dummy sequence 312 are truncated from one of: a Zadoff-Chu (ZC) sequence, a Golay complementary sequence, and a maximum length (M) sequence.

[0061] Figure 3CA schematic diagram 300 of data blocks according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the schematic diagram 300 includes 2 data blocks, namely a first data block 302-1 and a second data block 302-2. In some other embodiments, the first data block 302-1 and the second data block 302-2 each have a window size for FFT processing. It should be noted that in the illustrated embodiment, for the purpose of discussion, only 2 adjacent data blocks from DL or UL data are shown, and the DL / UL data may include any number of data blocks. For example, there may be at least one first data block before the first data block 302-1, or there may be at least one second data block after the second data block 302-2. It should also be noted that the first data block 302-1 and the second data block 302-2 may also be separated by at least one other block, wherein the at least one other block may be at least one of the following: a reference block and a synchronization block, which is described below Figure 3E-3F This is discussed in further detail in .

[0062] In the illustrated embodiment, the first data block 302-1 includes a first data sequence 304-1, and the second data block includes a second data sequence 304-2. In the illustrated embodiment, the first data sequence 304-1 is shorter than the second data sequence 304-2, i.e., the first data sequence 304-1 includes less data and elements than the second data sequence 304-2. In some embodiments, both the first data sequence 304-1 and the second data sequence 304-2 are smaller in size than the corresponding data blocks (e.g., 302-1 and 302-2).

[0063] In addition, the second data block 302-2 includes a first pseudo sequence 306 and a third pseudo sequence 312, wherein the first pseudo sequence 306 is directly inserted at the end of the second data sequence 304-2, and the third pseudo sequence 312 is directly inserted at the beginning of the second data sequence 304-2. In the illustrated embodiment, the length of the second data block 302-2 is the sum of the length of the second data sequence 304-2, the length of the first pseudo sequence 306, and the length of the third pseudo sequence 312. Similarly, the first data block 302-1 includes a second pseudo sequence 308 and a third pseudo sequence 312, wherein the second pseudo sequence 308 is directly inserted at the end of the first data sequence 304-1, and the third pseudo sequence 312 is directly inserted at the beginning of the first data sequence 304-1. In the illustrated embodiment, the length of the first data block 302-1 is the sum of the length of the first data sequence 304-1, the length of the second pseudo sequence 308, and the length of the third pseudo sequence 312. In the illustrated embodiment, the second pseudo sequence 308 is longer than the first pseudo sequence 306. In the illustrated embodiment, second pseudo-sequence 308 includes sequence 310 and first pseudo-sequence 306 .

[0064] Using this method, when reduced multipath delay is detected during data transmission, shorter dummy sequences and longer data sequences can be dynamically constructed to improve frequency efficiency. An additional third dummy sequence 312 is inserted to reduce interference between blocks caused by multipath delay and also reduce out-of-band leakage.

[0065] In some embodiments, the first pseudo sequence 306, the second pseudo sequence 308, and the third pseudo sequence 312 are selected from the pseudo sequence set according to the channel state. In some embodiments, the pseudo sequence set is predetermined by the system. In some embodiments, the pseudo sequence set includes a plurality of pseudo sequences (i.e., a first number A of pseudo sequences), wherein each of the plurality of pseudo sequences includes M elements, i.e., the length M of the pseudo sequence, wherein M is a positive integer and M is less than the length of the block, and wherein A is a positive integer. In some embodiments, each of the M elements is a complex number with a constant modulus value. In some embodiments, the pseudo sequence set includes at least one base sequence, and the second number of pseudo sequences (e.g., P) in the pseudo sequence set includes at least one base sequence at the end, wherein P is a positive integer and P≤A, for example, the second pseudo sequence 308 includes the first pseudo sequence 306 at the end. In some embodiments, the plurality of pseudo sequences in the pseudo sequence set may have the same number of elements with different values. In some embodiments, each of the plurality of pseudo sequences in the pseudo sequence set has a sequence index number. In some other embodiments, the first dummy sequence 306, the second dummy sequence 308, and the third dummy sequence 312 are truncated from one of: a Zadoff-Chu (ZC) sequence, a Golay complementary sequence, and a maximum length (M) sequence.

[0066] Figure 3D A schematic diagram 300 of data blocks according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the schematic diagram 300 includes 2 data blocks, namely a first data block 302-1 and a second data block 302-2. In some other embodiments, the first data block 302-1 and the second data block 302-2 each have a window size for FFT processing. It should be noted that in the illustrated embodiment, for the purpose of discussion, only 2 adjacent data blocks from DL or UL data are shown, and the DL / UL data may include any number of data blocks. For example, there may be at least one first data block before the first data block 302-1, or there may be at least one second data block after the second data block 302-2. It should also be noted that the first data block 302-1 and the second data block 302-2 may also be separated by at least one other block, wherein the at least one other block may be at least one of the following: a reference block and a synchronization block, which is described below Figure 3E-3F This is discussed in further detail in .

[0067] In the illustrated embodiment, the first data block 302-1 includes a first data sequence 304-1, and the second data block includes a second data sequence 304-2. In the illustrated embodiment, the first data sequence 304-1 is shorter than the second data sequence 304-2, i.e., the first data sequence 304-1 includes less data and elements than the second data sequence 304-2. In some embodiments, both the first data sequence 304-1 and the second data sequence 304-2 are smaller in size than the corresponding data blocks (e.g., 302-1 and 302-2).

[0068] In addition, the first data block 302-1 includes a first pseudo sequence 306 and a third pseudo sequence 312, wherein the first pseudo sequence 306 is directly inserted at the end of the first data sequence 304-1, and the third pseudo sequence 312 is directly inserted at the end of the first pseudo sequence 306. In the illustrated embodiment, the length of the first data block 302-1 is the sum of the length of the first data sequence 304-1, the length of the first pseudo sequence 306, and the length of the third pseudo sequence 312. Similarly, the second data block 302-2 includes a second pseudo sequence 308 and a third pseudo sequence 312, wherein the second pseudo sequence 308 is directly inserted at the end of the second data sequence 306-2, and the third pseudo sequence 312 is directly inserted at the end of the second pseudo sequence 308. In the illustrated embodiment, the length of the second data block 302-2 is the sum of the length of the second data sequence 304-2, the length of the second pseudo sequence 308, and the length of the third pseudo sequence 312. In the illustrated embodiment, the second pseudo sequence 308 is longer than the first pseudo sequence 306. In the illustrated embodiment, second pseudo-sequence 308 includes sequence 310 and first pseudo-sequence 306 .

[0069] Using this method, when increased multipath delay is detected during data transmission, longer pseudo sequences and shorter data sequences can be dynamically constructed to improve resistance to multipath interference. An additional third pseudo sequence 312 is inserted to reduce interference between blocks caused by multipath delay and also reduce out-of-band leakage.

[0070] In some embodiments, the first pseudo sequence 306, the second pseudo sequence 308, and the third pseudo sequence 312 are selected from the pseudo sequence set according to the channel state. In some embodiments, the pseudo sequence set is predetermined by the system. In some embodiments, the pseudo sequence set includes a plurality of pseudo sequences (i.e., a first number A of pseudo sequences), wherein each of the plurality of pseudo sequences includes M elements, i.e., the length M of the pseudo sequence, wherein M is a positive integer and M is less than the length of the block, and wherein A is a positive integer. In some embodiments, each of the M elements is a complex number with a constant modulus value. In some embodiments, the pseudo sequence set includes at least one base sequence, and the second number of pseudo sequences (e.g., P) in the pseudo sequence set includes at least one base sequence at the end, wherein P is a positive integer and P≤A, for example, the second pseudo sequence 308 includes the first pseudo sequence 306 at the end. In some embodiments, the plurality of pseudo sequences in the pseudo sequence set may have the same number of elements with different values. In some embodiments, each of the plurality of pseudo sequences in the pseudo sequence set has a sequence index number. In some other embodiments, the first dummy sequence 306, the second dummy sequence 308, and the third dummy sequence 312 are truncated from one of: a Zadoff-Chu (ZC) sequence, a Golay complementary sequence, and a maximum length (M) sequence.

[0071] Figure 3E A schematic diagram 300 of multiple data blocks in two adjacent frames 320 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the schematic diagram 300 includes 2 frames, namely a first frame 320-1 and a second frame 320-2. In the illustrated embodiment, the first frame 320-1 includes 6 first data blocks, namely 302-1a, 302-1b, 302-1c, 302-1d, 302-1e, and 302-1f; and the second frame 320-2 includes 6 second data blocks, namely 302-2a, 302-2b, 302-2c, 302-2d, 302-2e, and 302-2f. In the illustrated embodiment, the 6 first data blocks 302-1 in the first frame 320-1 are directly coupled to each other in series; and the 6 second data blocks 302-2 in the second frame 320-2 are also directly coupled to each other in series.

[0072] In addition, each of the six first data blocks 302-1 in the first frame 320-1 includes a first data sequence and a first dummy sequence, wherein the first dummy sequence is inserted at the end of the first data sequence in the first data block, such as Figure 3A In the illustrated embodiment, each of the six second data blocks 302-2 in the second frame 320-2 includes a second data sequence and a second dummy sequence, wherein the second dummy sequence is inserted at the end of the second data sequence in the second data block, as shown in FIG. Figure 3BIn the illustrated embodiment, the first frame 320-1 and the second frame 320-2 include reference blocks 322-1 and 322-2 respectively before the first first data block 302-1a and the first second data block 302-2a. Therefore, the sixth first data block 302-1f and the first second data block 302-2a are separated by the second reference block 322-2. In some embodiments, even if a change in the channel state, such as a reduced multipath delay, is detected within the first frame 320-1, a change in the pseudo sequence can be implemented in the next frame, such as the second frame 320-2.

[0073] Figure 3F A schematic diagram 300 of multiple data blocks in two adjacent frames 320 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the schematic diagram 300 includes 2 frames, namely a first frame 320-1 and a second frame 320-2. In the illustrated embodiment, the first frame 320-1 includes 4 first data blocks, namely 302-1a, 302-1b, 302-1c, and 302-1d, and 2 second data blocks 302-2a and 302-2b; and the second frame 320-2 includes 6 second data blocks, namely 302-2c, 302-2d, 302-2e, 302-2f, 302-2g, and 302-2h. In the illustrated embodiment, the 4 first data blocks 302-1 and the 2 second data blocks 302-2 in the first frame 320-1 are directly coupled to each other in series; and the 6 second data blocks 302-2 in the second frame 320-2 are also directly coupled to each other in series.

[0074] In addition, each of the four first data blocks 302-1 in the first frame 320-1 includes a first data sequence and a first dummy sequence, wherein the first dummy sequence is inserted at the end of the first data sequence in the first data block, such as Figure 3A In the illustrated embodiment, each of the two second data blocks 302-2 in the first frame 320-2 includes a second data sequence and a second dummy sequence, wherein the second dummy sequence is inserted at the end of the second data sequence in the second data block, as shown in FIG. Figure 3B Similarly, each of the six second data blocks 302-2 in the second frame 320-2 includes a second data sequence and a second pseudo sequence, wherein the second pseudo sequence is inserted at the end of the second data sequence in the second data block, as shown in FIG. Figure 3BIn the illustrated embodiment, the first frame 320-1 and the second frame 320-2 each include reference blocks 322-1 and 322-2 before the first first data block 302-1a and the third second data block 302-2c, respectively. In some embodiments, when a change in channel status, such as a reduced multipath delay, is detected within the first frame 320-1, a change in the pseudo sequence may be implemented in the same frame (e.g., the first frame 320-2 after the fourth first data block 302-1d).

[0075] Figure 4 A schematic diagram of a data modulation system 400 for data preparation according to some embodiments of the present disclosure is shown. In some embodiments, the data modulation system 400 includes a discrete Fourier transform (DFT) unit 402, a subcarrier mapping unit 404, an inverse fast Fourier transform (IFFT) unit 406, a real and imaginary part splitting unit 408, a first pulse shaping and digital-to-analog conversion unit 410, a first mixing module 414-1, a second mixing module 414-2, and an adding module 414-3. In the illustrated embodiment, the DFT unit 402 receives the first pseudo sequence 306 at an input 426, receives the sequence 310 at an input 424, receives the data sequence (e.g., the first data sequence 304-1 or the second data sequence 304-2) at an input 422, and receives the third pseudo sequence 312 at an input 420. In some embodiments, the DFT unit 402 includes M inputs, where M is the length of a data block (e.g., the first data block 302-1 or the second data block 302-2). In some embodiments, the IFFT unit 406 includes N inputs, where N is an integer and N is greater than M due to oversampling at the subcarrier mapping unit 404 .

[0076] In the illustrated embodiment, the second data block 302-2 in the time domain, including the third pseudo sequence 312, the second data sequence 304-2, the sequence 310, and the first pseudo sequence 306, is provided at the input of the real and imaginary part splitting unit 408. In the illustrated embodiment, the real part 430 of the output of the real and imaginary part splitting unit 408 is then provided at the first mixing module 414-1 to form a radio frequency signal with the input 434. Similarly, the imaginary part 432 of the output of the real and imaginary part splitting unit 408 is then provided at the second mixing module 414-2 to form a radio frequency signal with the input 436. In the illustrated embodiment, the outputs of both the mixing module 414-1 and the mixing module 414-2 are then provided to the input of the adding module 414-3 to provide an output 438.

[0077] Figure 5 A method 500 for inserting a dummy sequence during data modulation in a wireless communication system according to some embodiments of the present disclosure is shown. It should be understood that the method may be performed in Figure 5Additional operations are provided before, during, and after the method 500, and some operations may be omitted or reordered. The communication system in the illustrated embodiment includes a BS 102 and a UE 104. In the illustrated embodiment, the UE 104 is within one of at least one service cell covered by the BS 102, i.e., the UE 104 is connected to the BS 102. In some embodiments, the BS 102 is a wireless access point or a wireless communication node. In some other embodiments, the UE 104 is a wireless station or a wireless communication device. It should be noted that any number of BSs 102 or UEs 104 may be used and is within the scope of the present invention.

[0078] The method 500 begins at operation 502, where uplink (UL) data is prepared by the UE 104 according to some embodiments. In some embodiments, the data preparation performed by the UE 104 before transmitting the UL data to the BS 102 includes at least one of the following processes: dividing the UL data into a plurality of first data sequences having a first length, inserting at least one dummy sequence into the plurality of first data sequences, performing a discrete Fourier transform (DFT), performing subcarrier mapping in the frequency domain, inserting at least one guard subcarrier, performing an inverse fast Fourier transform (IFFT), filtering the plurality of first blocks, and performing digital-to-analog conversion on the plurality of first blocks, which are then sent to the receiving antennas of the BS 102 via the transmitting antennas of the UE 104. In some embodiments, the at least one dummy sequence is inserted for at least one of the following reasons, including but not limited to: a cyclic prefix, assisted phase tracking, assisted channel estimation, and synchronization. The preparation performed by the UE 104 is also performed at least one of the following processes: dividing the UL data into a plurality of first data sequences having a first length, inserting at least one dummy sequence into the plurality of first data sequences, performing a discrete Fourier transform (DFT), performing subcarrier mapping in the frequency domain, inserting at least one guard subcarrier, performing an inverse fast Fourier transform (IFFT), filtering the plurality of first blocks, and performing digital-to-analog conversion on the plurality of first blocks, which are then sent to the receiving antennas of the BS 102 via the transmitting antennas of the UE 104. In some embodiments, the at least one dummy sequence is inserted for at least one of the following reasons, including but not limited to: a cyclic prefix, assisted phase tracking, assisted channel estimation, and synchronization. Figure 4 Discussed in detail in .

[0079] The method 500 continues with operation 504, where, according to some embodiments, a plurality of first blocks are sent from the UE 104 to the BS 102. In some embodiments, each of the plurality of first blocks includes at least one of: a plurality of first data blocks, at least one reference signal block, and at least one synchronization block. In some embodiments, each of the plurality of first data blocks includes a first data sequence and a first dummy sequence.

[0080] In some embodiments, the first pseudo-sequence is selected by UE 104 from a pseudo-sequence set. In some embodiments, the pseudo-sequence set includes a plurality of pseudo-sequences. In some embodiments, the pseudo-sequence set is predetermined by the system. In some embodiments, each of the plurality of pseudo-sequences includes M elements, i.e., the length M of the pseudo-sequence, wherein M is a positive integer and M is less than the length of the block. In some embodiments, each of the M elements is a complex number with a constant modulus value. In some embodiments, the pseudo-sequence set includes at least one base sequence, and each of the pseudo-sequences in the pseudo-sequence set includes at least one base sequence, i.e., each of the plurality of pseudo-sequences is a combination of at least one base sequence. In some embodiments, at least one base sequence has the same number of elements. In some embodiments, each of the plurality of pseudo-sequences in the pseudo-sequence set has a sequence index number. In some other embodiments, the first pseudo-sequence is intercepted from one of the following: a Zadoff-Chu (ZC) sequence, a Gray complementary sequence, and a maximum length (M) sequence.

[0081] The method 500 continues with operation 506, where the plurality of first blocks are processed by the BS 102 and a channel is monitored according to some embodiments. In some embodiments, the processing of the plurality of first blocks includes at least one of: performing a DFT transform to the frequency domain, performing frequency domain equalization, transforming to the time domain using an IFFT, removing at least one reference block, and performing decoding and demodulation on the plurality of first data blocks. In some embodiments, monitoring of the channel is performed based on at least one reference block in the plurality of first blocks to obtain a channel state.

[0082] The method 500 continues with operation 508, where, in accordance with some embodiments, a first message is sent from the BS 102 to the UE 104. In some embodiments, the first message includes: a pseudo-sequence index of a second pseudo-sequence in the set of pseudo-sequences determined by the BS 102 based on at least one reference block received from the UE 104. In some embodiments, the first message is sent via a physical downlink control channel (PDCCH). In some other embodiments, the first message is sent in a radio resource control (RRC) message.

[0083] The method 500 continues with operation 510, where, according to some embodiments, UL data is further prepared by the UE 104. In some embodiments, the second pseudo sequence is determined according to the pseudo sequence index received in the first message. In some embodiments, the data preparation performed by the UE 104 before transmitting the UL data to the UE 104 includes at least one of the following processes: dividing the DL data into a plurality of second data sequences having a second length, inserting at least one pseudo sequence into the plurality of second data sequences, performing a discrete Fourier transform (DFT), performing subcarrier mapping in the frequency domain, inserting at least one guard subcarrier, performing an inverse fast Fourier transform (IFFT), filtering the plurality of second blocks, and performing digital-to-analog conversion on the plurality of second blocks, which are then sent to the receiving antenna of the BS 102 through the transmitting antenna of the UE 104. In some embodiments, each of the plurality of second blocks includes at least one of the following: a plurality of second data blocks, at least one reference block, and at least one synchronization block. In some embodiments, each of the plurality of second data blocks includes a second data sequence and a second pseudo sequence.

[0084] The method 500 continues with operation 512 where a plurality of second chunks are sent from the UE 104 to the BS 102 in accordance with some embodiments.

[0085] The method 500 continues with operation 514, where the plurality of second blocks are processed by the BS 102 and the channel is monitored according to some embodiments. In some embodiments, the processing of the plurality of second blocks includes at least one of: performing a DFT transform to the frequency domain, performing frequency domain equalization, transforming to the time domain using IFFT, removing at least one reference block, and performing decoding and demodulation on the plurality of second data blocks. In some embodiments, monitoring of the channel is performed based on at least one reference block in the plurality of second blocks to obtain a channel state.

[0086] It should be noted that there may be more than one UE 104, i.e., multiple UEs in the service cell of BS 102. In this case, frequency division multiplexing may be used to send UL data from each of the multiple UEs to BS 102 through different data blocks 302. Different data blocks 302 for different UEs may include at least one pseudo sequence, which is determined according to the channel state between each of the multiple UEs and BS 102, for example, different pseudo sequences are used for different UEs with different channel states. When the channel state (e.g., multipath delay) changes, BS 102 may change the pseudo sequence for different UEs.

[0087] Although various embodiments of the present invention have been described above, it should be understood that they are presented only by way of example and not by way of limitation. Similarly, various figures may depict example architectures or configurations, which are provided to enable those of ordinary skill in the art to understand the exemplary features and functions of the present invention. However, it will be understood by these personnel that the present invention is not limited to the example architectures or configurations shown, but may be implemented using a variety of alternative architectures and configurations. In addition, as will be understood by those of ordinary skill in the art, one or more features of an embodiment may be combined with one or more features of another embodiment described herein. Therefore, the breadth and scope of the present disclosure should not be limited by any of the exemplary embodiments described above.

[0088] It should also be understood that any reference to an element herein using names such as "first," "second," etc. does not generally limit the number or order of those elements. Rather, these names may be used herein as a convenient means of distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not mean that only two elements may be employed, or that the first element must be located before the second element in some manner.

[0089] In addition, those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols referenced in the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0090] It will be further understood by those of ordinary skill in the art that any of the various illustrative logical blocks, modules, processors, devices, circuits, methods, and functions described in conjunction with the aspects disclosed herein may be implemented by electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two that may be designed using source code coding or some other technique), various forms of program or design code in conjunction with instructions (which, for convenience, may be referred to herein as "software" or "software modules"), or a combination of the two. In order to clearly illustrate this interchangeability of hardware, firmware, and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware, firmware, or software, or a combination of these techniques, depends on the specific application and the design constraints imposed on the overall system. A skilled technician may implement the described functionality in various ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0091] In addition, it will be understood by those of ordinary skill in the art that the various illustrative logic blocks, modules, devices, components, and circuits described herein may be implemented within or performed by an integrated circuit (IC) that includes a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, or any combination thereof. The logic blocks, modules, and circuits may further include antennas and / or transceivers to communicate with various components within a network or within a device. The general purpose processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors combined with a DSP core, or a combination of any other suitable configurations to perform the functions described herein.

[0092] If implemented in software, the function can be stored as one or more instructions or codes on a computer-readable medium. Therefore, the steps of the method or algorithm disclosed herein can be implemented as software stored on a computer-readable medium. Computer-readable media include both computer storage media and communication media, and communication media include any media that can enable a computer program or code to be transferred from one place to another. The storage medium can be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include: RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage device, or any other medium that can be used to store the desired program code in the form of instructions or data structures and can be accessed by a computer.

[0093] In this document, the term "module" as used herein refers to software, firmware, hardware, and any combination of these elements for performing the associated functions described herein. In addition, for the purpose of discussion, various modules are described as discrete modules; however, it will be apparent to those of ordinary skill in the art that two or more modules can be combined to form a single module that performs the associated functions according to embodiments of the present invention.

[0094] In addition, memory or other storage devices and communication components can be used in embodiments of the present invention. It will be understood that, for the sake of clarity, the above description has described embodiments of the present invention with reference to different functional units and processors. However, it will be apparent that any appropriate functional distribution between different functional units, processing logic elements or domains can be used without departing from the present invention. For example, the functionality shown as being performed by a separate processing logic element or controller can be performed by the same processing logic element or controller. Therefore, reference to a specific functional unit is only a reference to an appropriate device for providing the described functionality, rather than an indication of a strict logical or physical structure or organization.

[0095] Various modifications to the embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the scope of this disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments shown herein, but should be given the widest scope consistent with the novel features and principles disclosed herein, as set forth in the following claims.

Claims

1. A method for performing data modulation by a wireless communication node of a wireless communication system, comprising: inserting at least one first dummy sequence into a first data sequence in a first data block; and inserting at least one second dummy sequence into a second data sequence in a second data block; wherein a first length of the first pseudo-sequence is different from a second length of the second pseudo-sequence, and wherein the second pseudo-sequence includes the first pseudo-sequence or is included in the first pseudo-sequence, The third length of the first data block is equal to the fourth length of the second data block. Wherein, when the second pseudo sequence includes the first pseudo sequence, the first pseudo sequence is configured at the end of the second pseudo sequence, and when the second pseudo sequence is included in the first pseudo sequence, the second pseudo sequence is configured at the end of the first pseudo sequence.

2. The method according to claim 1, wherein: The at least one first dummy sequence and the at least one second dummy sequence are selected from a dummy sequence set, wherein the dummy sequence set includes a plurality of dummy sequences.

3. The method according to claim 2, wherein: The pseudo sequence set is predetermined by the wireless communication system.

4. The method according to claim 2, wherein: Each of the plurality of pseudo-sequences includes M elements, wherein each of the M elements is a complex number having a constant modulus value.

5. The method according to claim 2, wherein: Each of the plurality of pseudo sequences in the pseudo sequence set is one of: intercepted from a Zadoff-Chu (ZC) sequence, intercepted from a Gray complementary sequence, intercepted from a maximum length (M) sequence, and modulated by Pi / 2 binary phase shift keying BPSK modulation.

6. The method of claim 1, wherein the first data block is one of: adjacent to the second data block, and separated from the second data block by at least one of a reference signal block and a synchronization signal block.

7. The method according to claim 1, wherein: The first data block is arranged in a first subframe, and the second data block is arranged in a second subframe.

8. The method according to claim 1, further comprising: Before inserting the at least one second dummy sequence, receiving a first message from a wireless communication device; determining the at least one second pseudo sequence according to the first message; and After inserting at least one second dummy sequence, performing a data modulation process; and sending information of the at least one second pseudo sequence to a wireless communication device, wherein the first message includes information on a link status, wherein the first message is received in one of: a physical uplink control channel PUCCH and a radio resource control RRC message, and wherein the data modulation process includes at least one of: discrete Fourier transform DFT, subcarrier mapping, inverse fast Fourier transform IFFT, real and imaginary part splitting, pulse shaping, digital-to-analog conversion, and signal mixing.

9. A method for performing data modulation by a wireless communication device of a wireless communication system, comprising: receiving a first data block from a wireless communication node, wherein the first data block comprises at least a first dummy sequence and a first data sequence; and receiving a second data block from the wireless communication node, wherein the second data block comprises at least a second dummy sequence and a second data sequence; wherein a first length of the first pseudo-sequence is different from a second length of the second pseudo-sequence, and wherein the second pseudo-sequence includes the first pseudo-sequence or is included in the first pseudo-sequence, The third length of the first data block is equal to the fourth length of the second data block. Wherein, when the second pseudo sequence includes the first pseudo sequence, the first pseudo sequence is configured at the end of the second pseudo sequence, and when the second pseudo sequence is included in the first pseudo sequence, the second pseudo sequence is configured at the end of the first pseudo sequence.

10. The method according to claim 9, wherein: The at least one first dummy sequence and the at least one second dummy sequence are selected from a dummy sequence set, wherein the dummy sequence set includes a plurality of dummy sequences.

11. The method according to claim 10, wherein: The pseudo sequence set is predetermined by the wireless communication system.

12. The method according to claim 10, wherein: Each of the plurality of pseudo-sequences includes M elements, wherein each of the M elements is a complex number having a constant modulus value.

13. The method according to claim 10, wherein: Each of the plurality of pseudo sequences in the pseudo sequence set is one of: intercepted from a Zadoff-Chu (ZC) sequence, intercepted from a Gray complementary sequence, intercepted from a maximum length (M) sequence, and modulated by Pi / 2 binary phase shift keying BPSK modulation.

14. The method of claim 9, wherein the first data block is one of: adjacent to the second data block, and separated from the second data block by at least one of a reference signal block and a synchronization signal block.

15. The method according to claim 9, wherein: The first data block is arranged in a first subframe, and the second data block is arranged in a second subframe.

16. The method according to claim 9, further comprising: After receiving the first data block, sending a first message to the wireless communication node; and receiving information of the at least one second pseudo sequence from the wireless communication node before receiving the second data block, The first message includes information about a link state, wherein the first message is sent in one of: a physical uplink control channel PUCCH and a radio resource control RRC message, and wherein the information about the link state is used by the wireless communication node to determine the at least one second pseudo sequence.

17. A method for performing data modulation by a wireless communication device of a wireless communication system, comprising: inserting at least one first dummy sequence into a first data sequence in a first data block; and inserting at least one second dummy sequence into a second data sequence in a second data block; wherein a first length of the first pseudo-sequence is different from a second length of the second pseudo-sequence, and wherein the second pseudo-sequence includes the first pseudo-sequence or is included in the first pseudo-sequence, The third length of the first data block is equal to the fourth length of the second data block. Wherein, when the second pseudo sequence includes the first pseudo sequence, the first pseudo sequence is configured at the end of the second pseudo sequence, and when the second pseudo sequence is included in the first pseudo sequence, the second pseudo sequence is configured at the end of the first pseudo sequence.

18. The method according to claim 17, wherein: The at least one first dummy sequence and the at least one second dummy sequence are selected from a dummy sequence set, wherein the dummy sequence set includes a plurality of dummy sequences.

19. The method according to claim 18, wherein: The pseudo sequence set is predetermined by the wireless communication system.

20. The method according to claim 18, wherein: Each of the plurality of pseudo-sequences includes M elements, wherein each of the M elements is a complex number having a constant modulus value.

21. The method according to claim 18, wherein: Each of the plurality of pseudo sequences in the pseudo sequence set is one of: intercepted from a Zadoff-Chu (ZC) sequence, intercepted from a Gray complementary sequence, intercepted from a maximum length (M) sequence, and modulated by Pi / 2 binary phase shift keying BPSK modulation.

22. The method of claim 17, wherein the first data block is one of: adjacent to the second data block and separated from the second data block by at least one of a reference signal block and a synchronization signal block.

23. The method according to claim 17, wherein: The first data block is arranged in a first subframe, and the second data block is arranged in a second subframe.

24. The method of claim 17, further comprising: receiving a first message from a wireless communication node before inserting the at least one second dummy sequence; and After inserting at least one second dummy sequence, performing a data modulation process, wherein the first message includes information of the at least one second pseudo-sequence, wherein the at least one second pseudo-sequence is determined by the wireless communication node according to the link status, and wherein the first message is received in one of the following: a physical downlink control channel PDCCH and a radio resource control RRC message; wherein the data modulation process includes at least one of the following: discrete Fourier transform DFT, subcarrier mapping, inverse fast Fourier transform IFFT, real and imaginary part splitting, pulse shaping, digital-to-analog conversion and signal mixing.

25. A method for data modulation by a wireless communication node of a wireless communication system, comprising: receiving a first data block from a wireless communication device, wherein the first data block includes at least a first dummy sequence and a first data sequence; and receiving a second data block from a wireless communication device, wherein the second data block includes at least a second dummy sequence and a second data sequence; wherein a first length of the first pseudo-sequence is different from a second length of the second pseudo-sequence, and wherein the second pseudo-sequence includes the first pseudo-sequence or is included in the first pseudo-sequence, The third length of the first data block is equal to the fourth length of the second data block. Wherein, when the second pseudo sequence includes the first pseudo sequence, the first pseudo sequence is configured at the end of the second pseudo sequence, and when the second pseudo sequence is included in the first pseudo sequence, the second pseudo sequence is configured at the end of the first pseudo sequence.

26. The method according to claim 25, wherein: The at least one first dummy sequence and the at least one second dummy sequence are selected from a dummy sequence set, wherein the dummy sequence set includes a plurality of dummy sequences.

27. The method according to claim 26, wherein: The pseudo sequence set is predetermined by the wireless communication system.

28. The method according to claim 26, wherein: Each of the plurality of pseudo-sequences includes M elements, wherein each of the M elements is a complex number having a constant modulus value.

29. The method according to claim 26, wherein: Each of the plurality of pseudo sequences in the pseudo sequence set is one of: intercepted from a Zadoff-Chu (ZC) sequence, intercepted from a Gray complementary sequence, intercepted from a maximum length (M) sequence, and modulated by Pi / 2 binary phase shift keying BPSK modulation.

30. The method of claim 25, wherein the first data block is one of: adjacent to the second data block and separated from the second data block by at least one of a reference signal block and a synchronization signal block.

31. The method of claim 25, wherein: The first data block is arranged in a first subframe, and the second data block is arranged in a second subframe.

32. The method of claim 25, further comprising: After receiving the first data block, determining the second pseudo sequence; and Sending a first message to the wireless communication node; wherein the at least one second pseudo-sequence is determined according to a link state, wherein the first message comprises information of the at least one second pseudo-sequence, and wherein the first message is sent in one of: a physical downlink control channel PDCCH and a radio resource control RRC message.

33. A computing device comprising at least one processor and a memory coupled to the processor, the at least one processor being configured to perform the method according to any one of claims 1 to 32.

34. A non-transitory computer-readable medium having computer-executable instructions stored thereon, which when executed by a processor implement the method according to any one of claims 1 to 32.

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