Computer system and data processing method

Abstract

In one embodiment, a computer system comprises: a payload subsystem comprising: an interface to connect with, transfer data to and receive write transactions from a respective device, a classifier to classify received write transactions as payload data and control data, a payload cache to store classified payload data; a processing unit (PU) subsystem comprising: a local PU cache to store classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system; and processing core circuitry configured to execute software program instructions to perform control and packet processing in response to control data stored in the local PU cache.

Description

[0001] Relevant application information

[0002] This application is a continuation-in-part of U.S. Patent Application S / N 16 / 907,347, filed June 22, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to computer systems, and more particularly, but not exclusively, to data caching. Background Technology

[0004] Network interface controllers (NICs) are typically Fast Peripheral Component Interconnect (PCIe) cards that are inserted into servers or storage enclosures to enable connectivity to Ethernet. SmartNICs offer functionality beyond simple connectivity and implement network traffic processing on the NIC itself, which would otherwise be performed by the central processing unit (CPU) in the case of a basic NIC.

[0005] U.S. Patent Publication 2015 / 0271244 by Bloch et al. describes a network interface device including a host interface and a network interface. The host interface is configured to connect to a host processor, and the network interface is configured to transmit and receive packets over a network. It includes multiple different physical ports configured to connect to the network. Processing circuitry is configured to receive data packets from the network via one of the physical ports and, in response to a destination identifier in the packet, determine whether to deliver the payload of the data packet to the host processor via the host interface or to forward the packet to the network via another physical port.

[0006] U.S. Patent 8,051,212 to Kagan et al. describes a network interface adapter comprising: an outgoing packet generator adapted to generate an outgoing request packet for delivery to a remote responder in response to a request submitted by a host processor; and a network output port coupled to transmit the outgoing request packet over the network to the remote responder. A network input port receives an incoming response packet from the remote responder, and an incoming request packet sent by the remote requester, in response to the outgoing request packet sent to the remote responder. An incoming packet processor receives and processes the incoming response packet and the incoming request packet, and causes the outgoing packet generator to generate an outgoing response packet, in addition to the outgoing request packet, for transmission to the remote requester in response to the incoming request packet. Summary of the Invention

[0007] According to embodiments of the present disclosure, a computer system is provided, comprising: a payload subsystem including: an interface configured to connect to a corresponding device, transmit data to the corresponding device, and receive write transactions from the corresponding device; a classifier configured to classify the received write transactions into payload data and control data; and a payload cache configured to store the classified payload data; and a processing unit (PU) subsystem including: a local PU cache for storing the classified control data, wherein the payload cache and the local PU cache are different physical caches in corresponding different physical locations within the computer system; and a processing core circuit configured to execute software program instructions to perform control and packet processing in response to the control data stored in the local PU cache.

[0008] According to further embodiments of this disclosure, the processing core circuitry is configured to manage the transmission of classified payload data from a first device in the device to a second device in the device via an interface and a payload cache.

[0009] Furthermore, according to embodiments of this disclosure, the first device includes an external storage device directly connected to one of the interfaces, and the second device includes a network node connected to one of the interfaces via a network.

[0010] Additionally, according to embodiments of this disclosure, the first device includes a first network node connected to one of the interfaces via a network, and the second device includes a second network node connected to one of the interfaces via a network.

[0011] Furthermore, according to embodiments of this disclosure, the processing core circuitry is configured to manage the transmission of categorized payload data from the first device to the second device via an interface and a payload cache, without requiring software access to the payload cache.

[0012] According to further embodiments of this disclosure, the processing core circuitry is configured to manage the transmission of classified payload data from the first device to the second device via an interface and a payload cache, without requiring software to store any classified payload data in a local PU cache.

[0013] According to a further embodiment of the present disclosure, the processing core circuit is configured to generate a buffer descriptor for a corresponding free memory location in the payload cache, provide the buffer descriptor to the interface, and the interface is configured to transmit payload data from the first device to the second device via the payload cache in response to the provided buffer descriptor.

[0014] In addition, according to embodiments of this disclosure, the processing core circuitry is configured to manage at least one queue in response to a buffer descriptor, and the interface is configured to transmit payload data from a first device to a second device via a payload cache in response to at least one queue.

[0015] Furthermore, according to embodiments of this disclosure, the payload cache is physically located closer to the interface than the processing core circuitry, and the local PU cache is physically located closer to the processing core circuitry than the interface.

[0016] Further according to embodiments of this disclosure, the classifier is configured to classify received write transactions into payload data and control data in response to one or more of the following: data type, packet descriptor data, packet header data, data size, redirection label data, or address data.

[0017] According to a further embodiment of the present disclosure, the system includes: a memory configured to store data across multiple memory locations, a processing core circuit configured to cache cache lines read from the memory at corresponding memory locations into a local PU cache; an interconnect configured to manage read and write operations of the memory and the local PU cache, maintain local cache location data of cache lines of the cache according to the corresponding memory location of the cache lines of the cache, and maintain memory consistency, and wherein a classifier is configured to classify received write transactions into payload data and control data in response to at least some of the local cache location data and the corresponding memory location of the write transaction.

[0018] Additionally, according to embodiments of this disclosure, the payload subsystem further includes at least one hardware accelerator configured to perform any one or more of the following: calculate a checksum from payload data stored in a payload cache, perform a redundancy check from payload data stored in a payload cache, compress at least some payload data stored in a payload cache, or encrypt at least some payload data stored in a payload cache.

[0019] According to another embodiment of this disclosure, a method is also provided, comprising: receiving a write transaction from a connected device; classifying the received write transaction into payload data and control data; storing the classified payload data in a payload cache; storing the classified control data in a local processing unit (PU) cache, wherein the payload cache and the local PU cache are different physical caches in corresponding different physical locations in a computer system; and executing software program instructions to perform control and packet processing in response to the control data stored in the local PU cache.

[0020] Furthermore, according to embodiments of this disclosure, executing software program instructions includes managing the transmission of categorized payload data from a first device in the device to a second device in the device via a payload cache.

[0021] According to further embodiments of this disclosure, the software program manages the transmission of categorized payload data from the first device to the second device via a payload cache without accessing the payload cache.

[0022] Furthermore, according to embodiments of this disclosure, the software program manages the transmission of categorized payload data from the first device to the second device via a payload cache, without storing any categorized payload data in a local PU cache.

[0023] Additionally, according to embodiments of this disclosure, the method includes: generating a buffer descriptor for a corresponding free memory location in the payload cache; and, in response to the buffer descriptor, transferring payload data from a first device to a second device via the payload cache.

[0024] Furthermore, according to embodiments of this disclosure, the method includes: managing at least one queue in response to a buffer descriptor; and transmitting payload data from a first device to a second device via a payload cache in response to at least one queue.

[0025] Further according to embodiments of this disclosure, the classification includes classifying received write transactions into payload data and control data in response to one or more of the following: data type, packet descriptor data, packet header data, data size, control tag data, or address data.

[0026] Furthermore, according to embodiments of this disclosure, the classification includes: classifying received write transactions into payload data and control data in response to: local cache location data maintained in a directory, which is maintained to provide memory consistency, and the corresponding memory location of the write transaction.

[0027] Additionally, according to an embodiment of this disclosure 20, the method includes performing any one or more of the following: calculating a checksum from payload data stored in a payload cache, performing a redundancy check from payload data stored in a payload cache, compressing at least some payload data stored in a payload cache, or encrypting at least some payload data stored in a payload cache. Attached Figure Description

[0028] The invention will be understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0029] Figure 1 This is a block diagram of a computer system constructed and operated according to an embodiment of the present invention;

[0030] Figure 2 Is included Figure 1 A flowchart of the steps in the data management method within the system;

[0031] Figure 3 Is included Figure 1 A flowchart of the steps in the method for fulfilling a data request in the system;

[0032] Figure 4 Is included Figure 1 A flowchart of the steps in the method of transmitting payload data in the system;

[0033] Figure 5 Is included Figure 1 A flowchart of the steps in a queue-based method for fulfilling data requests in a system; and

[0034] Figure 6 Is included Figure 1 The flowchart shows the steps in a queue-based method for transmitting payload data in a system. Detailed Implementation

[0035] SmartNICs, storage controllers, or other interfaces can process incoming packets and later forward modified packets to destinations such as host processors, network nodes, or external solid-state drives (SSDs). For example, some (or a portion of) the packets can be processed by hardware accelerators or general-purpose processors.

[0036] As another example, a device connected to a server via a network can request content stored on an external disk that is directly connected to the server via a Fast Peripheral Component Interconnect (PCIe) interface. Data can be retrieved from the external disk, optionally processed by a hardware accelerator, and then written to system memory (e.g., Dynamic Random Access Memory (DRAM)). Once in memory, a "store and forward" process managed by the server's central processing unit (CPU) activates the server's network interface controller (NIC) to send the data over the network to the remote device.

[0037] Packet processing can include each packet process, involving access to packet descriptors and packet headers, as well as a software-maintained context database, where most of the packet payload is not accessed. This processing is typically performed using the CPU.

[0038] Alternatively, payload data processing, such as checking data integrity, data compression, and data encryption, can typically be performed using dedicated hardware accelerators.

[0039] Since each packet processing is sensitive to memory access latency and involves accessing a limited portion of the packet, it is advantageous to cache data as close to the CPU as possible. For payload data processing, caching the payload data on the die is beneficial to avoid external memory bandwidth. Within the die, placing the payload close to hardware accelerators and input / output (I / O) interfaces to reduce on-chip interconnect bandwidth is beneficial. Understanding cache capacity is crucial for properly tuning system performance in both packet processing and payload data processing scenarios.

[0040] One solution is to use a local cache near the CPU and share a larger system cache between the CPU and peripheral devices such as accelerators and / or I / O interfaces.

[0041] The above solutions suffer from various problems. First, the shared cache location is not optimal for access by the CPU and peripheral devices. This can lead to excessively high average read latency, which in turn has a severe negative impact on CPU performance. It may also require high-bandwidth interconnects to transfer payload data between I / O interfaces and optional accelerators. Second, because the CPU performs other tasks besides data transfers between I / O interfaces, software running on the CPU may evict payload data from the shared cache to memory (e.g., DRAM), further degrading the performance of the transfer process. Third, it is difficult to analyze the shared cache capacity allocation between software and hardware to properly tune system performance.

[0042] Embodiments of the present invention address the aforementioned problems by splitting the cache of data written from external devices via the I / O interface into payload data and control data. The payload data is stored in a payload cache 20, which is typically physically closer to the I / O interface and accelerator, while the control data is stored in a local CPU cache, which is typically physically closer to the CPU. In the disclosed embodiments, a shared cache for storing both payload and control data is not required. In some embodiments, the CPU and local CPU cache can be replaced by any suitable processing unit (PU) and local PU cache, such as a graphics processing unit (GPU) and GPU cache.

[0043] As used in the specification and claims, the term "payload data" is defined as data received from an external device via an I / O interface and transmitted to another external device via an I / O interface without being read for use by the CPU.

[0044] As used in the specification and claims, the term "control data" is defined as data received from an external device via an I / O interface and required to be read for use by the CPU.

[0045] In some implementations, a classifier categorizes write transactions received from the respective external device into payload data and control data. The classifier can use any suitable method to identify payload data and control data. In some implementations, the classifier categorizes received write transactions into payload data and control data based on one or more of the following: data type, packet descriptor data, packet header data, data size, redirection tag data, or address data. In some implementations, data provided by a memory consistency catalog can be used to classify the data.

[0046] Embodiments of the present invention reduce latency and the interconnect bandwidth requirements associated with the use of a shared cache, and prevent CPU processes unrelated to payload data transfer from evicting payload data from memory. For example, if the local CPU cache overflows, the overflow will go to memory without interfering with the payload data, and vice versa for the payload. Processing performance is improved because the CPU experiences shorter read latency. Software running on the CPU can tailor its data structures and behavior to its dedicated local CPU cache. The size of the payload cache can be determined based on line speed and known peripheral latency without considering unexpected software behavior. Providing the payload cache near the I / O interface and(one or more) accelerators frees up routing resources near the CPU used for processing. In addition, the bandwidth behavior of the I / O interface and(one or more) accelerators is easy to analyze, allowing for optimization of interconnect design in the I / O interface and(one or more) accelerator areas. Similarly, the location of the payload cache and the CPU local cache allows for reduced interconnects and lower interconnect complexity.

[0047] System Description

[0048] Documents incorporated herein by reference shall be considered part of this application, and only the definitions in this specification shall apply unless any term defined in those incorporated documents conflicts with the explicit or implicit definitions in this specification.

[0049] Now to Figure 1 For reference, Figure 1 This is a block diagram of a computer system 10 constructed and operated according to an embodiment of the present invention. Also... Figure 2 For reference, Figure 2 Is included Figure 1 The flowchart 50 shows the steps in the data management method of System 10.

[0050] Computer system 10 includes a payload subsystem 12, a central processing unit (CPU) subsystem 14, memory 16, a directory 18, and an interconnect 20. The payload subsystem 12 includes multiple interfaces 22, a classifier 24, a payload cache 26, and optionally one or more accelerators 28. The CPU subsystem 14 includes processing core circuitry 30 and a local CPU cache 32. The processing core circuitry 30 may include one or more processing cores 34. The local CPU cache 32 may include one or more caches 36. The payload subsystem 12, CPU subsystem 14, interconnect 20, directory 18, and memory 16 can be implemented on a single die or on two or more dies.

[0051] In some implementations, CPU subsystem 14 may be implemented as any suitable processing unit (PU) subsystem, such as a graphics processing unit (GPU) subsystem including one or more graphics processing cores, and any suitable local PU cache, such as a local GPU cache.

[0052] External device 38-1 is connected to computer system 10 via interface 22-1, and external device 38-2 is connected to computer system 10 via interface 22-2. Computer system 10 may include more than two interfaces 22 connected to more than two corresponding external devices 38.

[0053] External device 38 may include any suitable external device, such as an external storage device (e.g., a fast non-volatile memory (NVMe) SSD) or a network node.

[0054] In some embodiments, external device 38-1 includes an external storage device directly connected to interface 22-1 (e.g., via cable without a network), and external device 38-2 includes a network node connected to interface 22-2 via network 40. In these embodiments, interface 22-1 may include any suitable interface, such as a PCIe interface, and interface 22-2 may include a NIC.

[0055] In some embodiments, external device 38-1 includes a network node connected to interface 22-1 via network 40 (e.g., via network cable, Wi-Fi, or Bluetooth), and external device 38-2 includes another network node connected to interface 22-2 via network 40 or via another network (e.g., via network cable, Wi-Fi, or Bluetooth). In these embodiments, each interface 22-1, 22-2 includes a NIC.

[0056] In some implementations, external devices 38-1 and 38-2 can be directly connected to computer system 10 via interface 22.

[0057] Memory 16 (e.g., DRAM or any suitable RAM) is configured to store data across multiple memory locations. Interconnect 20 is configured to: manage read and write operations of memory 16, local CPU cache 32, and payload cache 26; maintain local cache location data in directory 18 of cache lines according to the corresponding memory location of the cache lines; and maintain the consistency of memory 16 according to a suitable memory coherence protocol.

[0058] Payload cache 26 and local CPU cache 32 are different physical caches in corresponding physical locations within computer system 10. Payload cache 26 is generally physically located closer to interface 22 than processing core circuitry 30. Local CPU cache 36 is generally physically located closer to processing core circuitry 30 than interface 22. As used in the specification and claims, the term A being physically closer to B than C is defined herein as meaning that a connection between A and B is faster and / or cheaper than a connection between A and C.

[0059] Interface 22 is configured to connect (directly, for example, via cable without a network, and / or indirectly via a network) to a corresponding external device 38. Interface 22 is configured to transmit data with the corresponding device 38, for example, transmitting data from external device 38-1 to external device 38-2. Interface 22 is configured to receive (box 52) write transactions from the corresponding device 38. Write transactions may include packets or data elements, where any packet or data element includes payload data and / or control data. For example, a data element may include a header portion as control data and a payload portion as payload data. A data element may include a header portion and a payload portion, both classified as control data, such as a data transmission request, notification, or acknowledgment. A data element may include only payload data.

[0060] Classifier 24 is configured to receive write transactions from interface 22 and classify the received write transactions (box 54) into payload data and control data. The control data may include control structures and packet headers. In some implementations, the functionality of classifier 24 may be incorporated into each interface 22.

[0061] Classification can be performed using any suitable method and standard. For example, an interface such as a NIC can have a detailed understanding of the data type being written, the packet descriptor, and the packet header. This information can be used to determine whether a write transaction (e.g., a received packet) is payload data or control data, or which parts of the write transaction are payload data or control data. For example, the packet descriptor and packet header can be classified as control data, while the packet payload portion can be classified as payload data. As another example, an interface device such as a PCIe interface can use heuristics to estimate whether a write transaction is control data or payload data. For example, a small transaction can imply that the control structure should be stored in the local CPU cache 32, while a large transaction can be stored in the payload cache 26. A PCIe "direction tag" from an external device can be used to encode whether a write transaction is control data or payload data. The indication of whether the data is payload data or control data can be encoded by the software device driver in the address used in the write transaction (e.g., in the most significant bit of that address).

[0062] Therefore, in some implementations, classifier 24 is configured to classify received write transactions into payload data and control data in response to one or more of the following: data type; packet descriptor data; packet header data; data size; redirection label data; or address data.

[0063] In some implementations, classifier 24 is configured to classify received write transactions into payload data and control data in response to local cache location data (stored in directory 18) and the corresponding memory location of the write transaction. For example, if a write transaction is associated with a specific memory location in memory 16, directory 18 can be searched to find the cache location associated with that memory location to determine whether data from that memory location is cached in payload cache 26 or local CPU cache 32. The result of the search then provides an indication of whether the received write transaction should be classified as payload data or control data.

[0064] In practice, some or all of the functions of classifier 24 may be combined in a single physical component, or alternatively, implemented using multiple physical components. These physical components may include hardwired or programmable devices, or a combination of both. In some implementations, at least some functions of classifier 24 may be executed by a programmable processor under the control of suitable software. For example, the software may be downloaded to the device electronically via a network. Alternatively or additionally, the software may be stored in a tangible, non-transitory computer-readable storage medium, such as optical, magnetic, or electronic memory.

[0065] Payload cache 26 is configured to store (box 56) categorized payload data transported from interface 22-1 to interface 22-2. Payload data is written from interface 22-1 to payload cache 26.

[0066] The local CPU cache 32 is configured to store (box 58) categorized control data and other data used by the software being executed. The local CPU cache 32 may include multiple cache levels per core 34, per core cluster, or shared among all cores 34.

[0067] The processing core circuit 30 is configured to execute software program instructions to: perform control and packet processing in response to control data stored in the local CPU cache 32 (and optionally in response to data stored in any other location); cache cache lines read from memory 16 at the appropriate memory locations into the local CPU cache 36; and manage the transfer of classified payload data from external device 38-1 to external device 38-2 via interface 22 and payload cache 26 (box 60).

[0068] In some implementations, the software running on the processing core circuitry 30 is configured to manage the transfer of categorized payload data from device 38-1 to device 38-2 via interface 22 and payload cache 26 without requiring the software to access payload cache 26 (e.g., read from or write to it).

[0069] In some implementations, the software running on the processing core circuitry 30 is configured to manage the transfer of classified payload data from device 38-1 to device 38-2 via interface 22 and payload cache 26, without requiring the software to store any classified payload data in the local CPU cache 32.

[0070] In practice, some or all of the functions of the processing core circuitry 30 may be combined in a single physical component, or alternatively, implemented using multiple physical components. In some embodiments, at least some functions of the processing core circuitry 30 may be executed by a programmable processor under the control of suitable software. For example, the software may be downloaded to the device electronically via a network. Alternatively or additionally, the software may be stored in a tangible, non-transitory computer-readable storage medium, such as optical, magnetic, or electronic memory.

[0071] One or more accelerators 28 are configured to perform any one or more of the following: calculate a checksum from the payload data stored in the payload cache 26; perform a redundancy check from the payload data stored in the payload cache 26; compress at least some of the payload data stored in the payload cache 26; or encrypt at least some of the payload data stored in the payload cache 26.

[0072] Data requests and data transfers can be handled using any suitable method. (Reference) Figure 3 and Figure 4 The description outlines a method for handling data requests. (See references.) Figure 5 and Figure 6 The description describes another method.

[0073] Now to Figure 3 For reference, Figure 3 Is included Figure 1 The flowchart 70 shows the steps in the method for fulfilling a data request in System 10. Also, [the flowchart is missing here]. Figure 1 For reference.

[0074] Interface 22-2 is configured to receive (box 72) data transfer requests from external device 38-2. The requested data is stored in external device 38-1. The data transfer request is classified as control data by classifier 24 and transmitted to local CPU cache 32 for processing by the software of processing core circuitry 30. In some embodiments, the control data is stored in any suitable location in local CPU cache 32 (e.g., any free cache line). Processing core circuitry 30 is configured to generate (box 74) one or more buffer descriptors indicating one or more free memory locations in payload cache 26. Processing core circuitry 30 is configured to provide (box 76) the buffer descriptors(s) to interface 22. Processing core circuitry 30 may provide the buffer descriptors to interface 22 via write and read requests to external device 38, as referenced. Figure 4 More detailed description. Interface 22 is configured to transfer payload data (provided by device 38-1) from device 38-1 to device 38-2 via payload cache 26 in response to one or more provided buffer descriptors (box 78). As part of the data transfer request, interface 22 uses buffer descriptors to write data to and read data from payload cache 26, as will be described in reference to... Figure 4 For a more detailed description, steps in boxes 76 and 78 (arrow 80) can be repeated while fulfilling the data transfer request, as shown in the reference. Figure 4More detailed description. As space in payload cache 26 becomes available, more buffer descriptors can be generated (arrow 82). These buffer descriptors may need to be processed by interface 22 to provide cache locations in payload cache 26. Once all requested data has been transferred from external device 38-1, external device 38-1 can be configured to send an end-of-data notification to processing core circuitry 30, which is received by interface 22-1 (box 84) and transferred to the local CPU cache 32.

[0075] Now to Figure 4 For reference, Figure 4 Including Figure 1 The flowchart 90 shows the steps in the method for transmitting payload data in System 10. Also, regarding... Figure 1 For reference.

[0076] Processing core circuitry 30 is configured to provide (block 92) a buffer descriptor for a free memory location in payload cache 26 to interface 22-1. Processing core circuitry 30 can also send a request to external device 38-1 to transfer a block of payload to interface 22-1. In some embodiments, processing core circuitry 30 can send a request to external device 38-1 to transfer all requested data to interface 22-1, and allow interface 22-1 to control data transfer from external device 38-1 to interface 22-1. Interface 22-1 is configured to write (block 94) payload data received from external device 38-1 to payload cache 26 in response to the buffer descriptor provided by processing core circuitry 30. Interface 22-1 or external device 38-1 is configured to provide acknowledgment of the write to processing core circuitry 30 (block 96). This acknowledgment is classified as control data and transferred to local CPU cache 32 for reception (block 98) and processing by processing core circuitry 30. In response to a write confirmation, processing core circuitry 30 is configured to provide (box 100) the same buffer descriptor to interface 22-2 (e.g., a transmit interface) and / or external device 38-2. Processing core circuitry 30 can also send a request to external device 38-2 based on the buffer descriptor to read payload data from interface 22-2. In response to the read request, external device 38-2 can be configured to read data from interface 22-2 based on the provided buffer descriptor. In some embodiments, processing core circuitry 30 can send a request to external device 38-2 to transfer all payload from interface 22-2, allowing interface 22-2 to control data transfer from payload cache 26 to external device 22-2 based on one or more buffer descriptors provided by processing core circuitry 30. Interface 22-2 is configured to read payload data from payload cache 26 (box 102) in response to the provided buffer descriptor. Once a read is successfully performed, interface 22-2 or external device 38-2 is configured to provide (box 104) an acknowledgment of the read. Processing core circuitry 30 is configured to receive (box 106) the read acknowledgment, and the buffer descriptor can be reused since it now points to a free (or unused) memory location. Steps in boxes 92-106 can be repeated until all payloads for the requested data have been transferred from external device 38-1 to external device 38-2.

[0077] As mentioned above, one or more accelerators 28 can perform operations on the payload data stored in the payload cache 26. Therefore, between the steps of blocks 98 and 100, the processing core circuitry 30 can send a processing request to one or more accelerators 28 to process the payload data stored in the payload cache 26. Once one or more accelerators 28 have completed their processing, they send an acknowledgment to the processing core circuitry 30.

[0078] It should be noted that the above process can be performed in parallel for two or more free memory locations associated with the corresponding buffer descriptor.

[0079] Now to Figure 5 For reference, Figure 5 Including Figure 1 The flowchart 200 shows the steps in the queue-based method for fulfilling data requests in System 10. Also, Figure 1 For reference.

[0080] The core processing circuit 30 is configured to manage at least one queue in response to a buffer descriptor, as described in the following reference. Figure 6 For a more detailed description, interface 22 is configured to transmit payload data from external device 38-1 to external device 38-2 via payload cache 26 in response to one or more queues, as described below. Figure 6 More detailed description. One or more queues may be stored in memory 16 (and cached in local CPU cache 32 and local cache of interface 22 (not shown) respectively when used by processing core circuitry 30 and interface 22) or in a shared cache shared by processing core circuitry 30, interface 22, and one or more accelerators 28. One or more queues may include buffer descriptors, work queue elements (WQEs), or work descriptors based on buffer descriptors or any suitable data.

[0081] Interface 22-2 is configured to receive (box 202) data transfer requests from external device 38-2. The requested data is stored in external device 38-1. The data transfer request is classified as control data by classifier 24 and transmitted to local CPU cache 32 for processing by software of processing core circuitry 30. Processing core circuitry 30 is configured to generate (box 204) one or more buffer descriptors indicating one or more free memory locations and one or more queues in payload cache 26. Processing core circuitry 30 is configured to provide (box 206) (one or more) buffer descriptors to interface 22 via one or more queues (e.g., in the receive queue of interface 22-1 and the send queue of interface 22-2). Additional completion queues can also be generated and managed for read and write acknowledgments. Interface 22 is configured to transfer payload data (provided by device 38-1) from device 38-1 to device 38-2 via payload cache 26 in response to (one or more) buffer descriptors provided in the queues (box 208). As part of a data transfer request, interface 22 uses a buffer descriptor to write data to and read data from payload cache 26, as referenced. Figure 6For a more detailed description, steps 206 and 208 can be repeated while fulfilling the data transfer request, as shown in the reference. Figure 6 In more detail. As space in payload cache 26 becomes available, more buffer descriptors can be generated and added to the queue. These buffer descriptors may need to be processed by interface 22 to provide cache locations in payload cache 26. Once all data has been transferred from external device 38-1, external device 38-1 can be configured to send an end-of-data notification to processing core circuitry 30, which is received by interface 22-1 (box 210) and transferred to the local CPU cache 32.

[0082] Now to Figure 6 For reference, Figure 6 Including Figure 1 Flowchart 220 shows the steps in the method for transmitting payload data based on queues in System 10. Also, Figure 1 For reference.

[0083] Processing core circuitry 30 is configured to provide a buffer descriptor (box 222) in the receive queue for a free memory location in payload cache 26, which is periodically read by interface 22-1. Processing core circuitry 30 can also send a request to external device 38-1 to transfer a block of payload to interface 22-1. In some embodiments, processing core circuitry 30 can send a request to external device 38-1 to transfer all requested data to interface 22-1, and allow interface 22-1 to control data transfer from external device 38-1 to interface 22-1. In response to reading the receive queue, interface 22-1 is configured to write (box 224) payload data received from external device 38-1 to payload cache 26 in response to a buffer descriptor provided by processing core circuitry 30 in the receive queue. Interface 22-1 is configured to provide acknowledgments of the write (refer to the buffer descriptor) via a write completion queue (box 226), which is periodically read by processing core circuitry 30. In response to a write acknowledgment, processing core circuitry 30 is configured to provide (box 228) the same buffer descriptor in the transmit queue, which is periodically read by interface 22-2 (e.g., the transmit interface). In response to reading the transmit queue, interface 22-2 is configured to read payload data (box 230) from payload cache 26 in response to the buffer descriptor provided in the transmit queue. Processing core circuitry 30 can also send a request to external device 38-2 based on the buffer descriptor to read payload data from interface 22-2. In response to this read request, external device 38-2 can be configured to read data from interface 22-2 based on the provided buffer descriptor. In some embodiments, processing core circuitry 30 can send a request to external device 38-2 to transmit all payloads from interface 22-2, allowing interface 22-2 to control data transfer from payload cache 26 to external device 38-2 based on one or more buffer descriptors provided by the transmit queue in processing core circuitry 30. Once a read is successfully performed, interface 22-2 is configured to provide (box 232) an acknowledgment of the read (refer to the buffer descriptor) in the read completion queue, which is periodically read by the processing core circuitry 30. In response to the read acknowledgment, the processing core circuitry 30 is configured to reuse (box 234) the buffer location, as the buffer descriptor now points to a free memory location. The steps of boxes 222-234 can be repeated until all payloads for the requested data have been transferred from external device 38-1 to external device 38-2.

[0084] As mentioned above, one or more accelerators 28 can perform operations on the payload data stored in the payload cache 26. Therefore, between the steps of blocks 226 and 228, the processing core circuitry 30 can send processing requests to one or more accelerators 28 via a processing queue (reference buffer descriptor) to process the payload data stored in the payload cache 26. Once one or more accelerators 28 have completed their processing, they write an acknowledgment to the processing completion queue, which is periodically read by the processing core circuitry 30.

[0085] It should be noted that the above process can be performed in parallel for two or more free memory locations associated with the corresponding buffer descriptor, such that any one of the queues may include one, two or more buffer descriptors depending on the processing stage for each memory location in the payload cache 26.

[0086] For clarity, the various features of the invention described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, for brevity, the various features of the invention described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

[0087] The above embodiments have been illustrated by examples, and the present invention is not limited to the content specifically shown and described above. Rather, the scope of the present invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications that would occur to those skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Claims

1. A computer system comprising: a payload subsystem comprising: interfaces configured to connect with respective external devices; transfer data with the respective external devices; and receive write transactions from the respective external devices; a classifier configured to classify the received write transactions as payload data and control data; and a payload cache configured to store the classified payload data; and a processing unit subsystem comprising: a local processing unit cache configured to store the classified control data, wherein the payload cache and the local processing unit cache are different physical caches in respective different physical locations in the computer system; and processing core circuitry configured to execute software program instructions to perform control and packet processing in response to the control data stored in the local processing unit cache, wherein the control data is read for use by the processing core circuitry and the payload data is transferred to an external device without being read by the processing core circuitry.

2. The system of claim 1, wherein the processing core circuitry is configured to manage transfer of the classified payload data from a first one of the external devices to a second one of the external devices via the interfaces and the payload cache.

3. The system of claim 2, wherein: the first device comprises an external storage device directly connected to one of the interfaces; and the second device comprises a network node connected to one of the interfaces via a network.

4. The system of claim 2, wherein: the first device comprises a first network node connected to one of the interfaces via a network; and the second device comprises a second network node connected to one of the interfaces via the network.

5. The system of claim 2, wherein the processing core circuitry is configured to manage transfer of the classified payload data from the first device to the second device via the interfaces and the payload cache without the software program instructions accessing the payload cache.

6. The system of claim 5, wherein the processing core circuitry is configured to manage transfer of the classified payload data from the first device to the second device via the interfaces and the payload cache without the software program instructions storing any of the classified payload data in the local processing unit cache.

7. The system of claim 6, wherein: the processing core circuitry is configured to: generate a buffer descriptor for a respective free memory location in the payload cache; and provide the buffer descriptor to the interfaces; and the interfaces are configured to transfer the payload data from the first device to the second device via the payload cache in response to the provided buffer descriptor. ​ 8. The system of claim 7, wherein the processing core circuit is configured to manage at least one queue responsive to the buffer descriptor, the interface is configured to transfer the payload data from the first device to the second device via the payload cache responsive to the at least one queue.

9. The system of claim 1, wherein the payload cache is physically located closer to the interface than the processing core circuit, and the local processing unit cache is physically located closer to the processing core circuit than the interface.

10. The system of claim 1, wherein the classifier is configured to classify the received write transaction as payload data and control data responsive to one or more of: a data type; a packet descriptor data; a packet header data; a data size; a steering tag data; or an address data.

11. The system of claim 1, further comprising: a memory configured to store data across a plurality of memory locations, the processing core circuit configured to cache cache lines read from the memory at respective memory locations into the local processing unit cache; an interconnect configured to: manage read and write operations of the memory and the local processing unit cache; maintain local cache location data for cache lines of the cache according to respective memory locations of the cache lines; and maintain coherency of the memory, and wherein the classifier is configured to classify the received write transaction as payload data and control data responsive to at least some of the local cache location data and respective memory locations of the write transaction.

12. The system of claim 1, wherein the payload subsystem further comprises at least one hardware accelerator configured to perform any one or more of: compute a checksum from the payload data stored in the payload cache; perform a redundancy check from the payload data stored in the payload cache; compress at least some payload data stored in the payload cache; or encrypt at least some payload data stored in the payload cache.

13. A data processing method comprising: receiving a write transaction from a connected external device; classifying the received write transaction as payload data and control data; storing the classified payload data in a payload cache; storing the classified control data in a local processing unit cache, wherein the payload cache and the local processing unit cache are different physical caches on respective different physical locations in a computer system; and a processing core circuit executing software program instructions to perform control and packet processing responsive to the control data stored in the local processing unit cache, wherein the control data is read for use by the processing core circuit, and the payload data is transferred to an external device without being read by the processing core circuit.

14. The method of claim 13, wherein said executing software program instructions comprises: managing transfer of the categorized payload data from a first device of the external devices to a second device of the external devices via the payload cache.

15. The method of claim 14, wherein the software program instructions manage transfer of the categorized payload data from the first device to the second device via the payload cache without accessing the payload cache.

16. The method of claim 15, wherein the software program instructions manage transfer of the categorized payload data from the first device to the second device via the payload cache without storing any of the categorized payload data in the local processing unit cache.

17. The method of claim 16, further comprising: generating a buffer descriptor of a respective free memory location in the payload cache; and transferring the payload data from the first device to the second device via the payload cache in response to the buffer descriptor.

18. The method of claim 17, further comprising: managing at least one queue in response to the buffer descriptor; and transferring the payload data from the first device to the second device via the payload cache in response to the at least one queue.

19. The method of claim 13, wherein the classifying comprises: classifying the received write transaction as payload data and control data in response to one or more of: a data type; a packet descriptor data; a packet header data; a data size; a steering tag data; or an address data.

20. The method of claim 13, wherein the classifying comprises: classifying the received write transaction as payload data and control data in response to: local cache location data maintained in a directory, the directory being maintained to provide memory coherency; and a respective memory location of the write transaction.

21. The method of claim 13, further comprising performing any one or more of: calculating a checksum from the payload data stored in the payload cache; performing a redundancy check from the payload data stored in the payload cache; compressing at least some payload data stored in the payload cache; or encrypting at least some payload data stored in the payload cache.

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