Resistive memory device and reliability improvement method thereof

Abstract

The present invention provides a resistive memory device and a reliability improvement method thereof. The reliability improvement method includes: performing a formation operation on a plurality of memory cells; reading the formed memory cells to obtain a plurality of formed currents respectively; setting a reference current according to a statistical value in the formed current; performing a setting operation on the memory cells; calculating a ratio of the set current to the reference current of each memory cell, and judging the physical state of each memory cell according to the ratio; and determining whether to perform a repair operation on each memory cell according to the physical state of each memory cell.

Description

Technical Field

[0001] The present invention relates to a resistive memory device and a reliability improvement method thereof, and more particularly to a reliability improvement method for data retention of a resistive memory device. Background Art

[0002] With the advancement of electronic technology, providing high-reliability data storage capabilities has become a necessary function of modern electronic devices. In resistive memory, when reading data from a memory cell, a reference current is often used to compare the read current of the memory cell to obtain the data stored in the memory cell.

[0003] Since the reference current is usually set to a fixed current, the read current that can be provided by the memory cell after being set or reset must have a certain uniformity, otherwise, the read operation performed on the memory cell may easily read wrong data. Figure 1 In the relationship diagram of the setting conditions and the current distribution after setting of the resistive memory cell, in the pre-baking state 110, corresponding to the three different setting states S1-S3, the read current distribution of the memory cell has a relatively high uniformity and can be evenly distributed in the range of about 20-32 micro amperes. However, in the post-baking state 120, the read current distribution of the memory cells corresponding to the three different setting states S1-S3 has a variation, wherein the read current distribution of the memory cells corresponding to the setting states S1 and S2 is seriously divergent. This greatly increases the possibility of errors in the read operation. Summary of the invention

[0004] The present invention is directed to a resistive memory device and a reliability improvement method thereof, which can effectively improve the data reliability of the storage unit thereof.

[0005] According to an embodiment of the present invention, a reliability improvement method includes: performing a formation action on a plurality of memory cells; reading the formed memory cells to obtain a plurality of post-formation currents respectively; setting a reference current according to statistical values ​​of the plurality of post-formation currents; performing a setting action on the memory cells; calculating a ratio of the post-setting current to the reference current of each memory cell, and determining a physical state of each memory cell according to the ratio; and determining whether to perform a repair action on each memory cell according to the physical state of each memory cell.

[0006] According to an embodiment of the present invention, a resistive memory device includes a memory cell array, a sense amplifier, and a controller. The memory cell array has a plurality of memory cells. The sense amplifier is coupled to the memory cell array. The controller is coupled to the sense amplifier to perform the above reliability improvement method.

[0007] Based on the above, the physical state of each memory cell in the resistive memory device is determined according to the ratio of the current after setting to the maximum value of the current after formation, and subsequent repair actions are performed according to the physical state of each memory cell, which can effectively improve the reliability of the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0009] Figure 1 A diagram showing the relationship between the setting conditions of a resistive memory cell and the current distribution after setting;

[0010] Figure 2 A distribution diagram of read current of a resistive memory cell corresponding to different conditions;

[0011] Figure 3 A flow chart of a reliability improvement method according to an embodiment of the present invention is presented;

[0012] Figure 4 A schematic diagram of an implementation method of a reliability improvement method according to an embodiment of the present invention is shown;

[0013] Figure 5 A schematic diagram of another implementation of the reliability improvement method according to an embodiment of the present invention is shown;

[0014] Figure 6 A schematic diagram of a memory device according to an embodiment of the present invention is shown.

[0015] Description of Figure Numbers

[0016] 110, 210: state before baking;

[0017] 120, 220: state after baking;

[0018] 600: memory device;

[0019] 610: storage cell array;

[0020] 620: controller;

[0021] 630: sense amplifier;

[0022] 641: address latch;

[0023] 642: X decoder;

[0024] 643: Y decoder;

[0025] 651: input data latch;

[0026] 652: output data latch;

[0027] 660: Input and output buffer;

[0028] 670, 680: logic circuits;

[0029] 690: voltage generator;

[0030] 6100: bias voltage lookup table;

[0031] S681, S682: steps;

[0032] ADDS: address signal;

[0033] CMDS: command signal;

[0034] If: current after formation;

[0035] IOS: input and output signals;

[0036] Is: current after setting;

[0037] S1~S3: setting state;

[0038] S310~S360, S410~S494, S510~S594: reliability improvement steps. DETAILED DESCRIPTION

[0039] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0040] Please refer to Figure 2 , Figure 2 is a resistive memory cell, corresponding to the distribution diagram of the read current of the memory cell under different conditions. Figure 2 In the figure, the horizontal axis represents the ratio of the post-setting current Is after the setting operation is performed on the memory cell to the post-forming current If after the forming operation is performed on the memory cell. The vertical axis represents the distribution of the read current of the memory cell (in microamperes). Figure 2 In the state before baking 210, corresponding to each condition (different ratio Is / If), the distribution of the read current of the memory cell can have a relatively high uniformity. However, in the state after baking 220, corresponding to a relatively high ratio (Is / If>=1.4), the distribution of the read current of the memory cell can have a relatively high uniformity. It can be known that the physical characteristics of the memory cell can be determined based on the ratio of the setting current Is and the forming current If, and can be used as a basis for repairing the memory cell.

[0041] Please refer to the following Figure 3 , Figure 3 The flowchart of the reliability improvement method of the embodiment of the present invention is shown. The reliability improvement method is applicable to resistive memory. Figure 3 In step S310, a forming action is performed on a plurality of memory cells in the memory. Here, the initialization action performed on the resistive memory cell is called a forming action. In the forming action, a bias voltage must be applied to the memory cell, and when the electric field exceeds a critical value, a quasi-collapse phenomenon will occur in the dielectric layer of the resistive memory cell, causing the dielectric layer to change from a high-resistance insulating state to a state where the resistance value can be converted. After the forming action is completed, the resistance value of the dielectric layer of the memory cell can be effectively lowered or increased by a setting action or a reset action in the subsequent process, and the effect of data storage is produced.

[0042] In step S320, the formed memory cells are read and a plurality of formed currents are obtained. Then, in step S330, a reference current is generated based on the plurality of formed currents. In one embodiment, the reference current may be generated based on the statistical values ​​(e.g., maximum value, average value, median value, etc.) of the plurality of formed currents. In other embodiments, the reference current may be generated based on the average value, median value, etc. of the plurality of formed currents. Generally, the reference current may be equal to the maximum value of the formed currents.

[0043] In step S340, a setting operation is performed on the memory cell, and in step S350, a reading operation is performed on each memory cell after the setting operation is completed to obtain multiple post-setting currents of the memory cell, and the ratio of the post-setting current to the reference current generated in step S330 is calculated, and then the physical state of each corresponding memory cell is determined according to each ratio. Then in step S360, a corresponding repair operation is performed according to the physical state of each memory cell.

[0044] Please note that, basically, performing a set operation on the formed memory cell can further reduce the resistance value of the memory cell. That is, under normal conditions, the ratio of the set current to the reference current is greater than 1. In addition, according to Figure 2 It can be seen from the figure that the physical state of the memory cell can be known based on the ratio of the set current to the reference current. For example, when the ratio Is / If<1.4 (i.e., the set current is less than 1.4*reference current), the read current distribution of the memory cell after baking tends to diverge; and when the ratio Is / If>=1.4, the read current distribution uniformity of the memory cell after baking is relatively concentrated. Figure 2 In the embodiment of the present invention, multiple reference values ​​can be set as a basis for determining the physical state of the storage unit.

[0045] For example, in the embodiment of the present invention, a first reference value, a second reference value, and a third reference value may be set, wherein 1<first reference value<second reference value<third reference value. In step S350, when the ratio of the set current corresponding to the storage unit to the reference current is between 1 and the first reference value, the storage unit is a bad storage unit, and therefore, in step S360, a spare storage unit may be used to repair the storage unit, or the data stored in the storage unit may be recorded, and an error correction code operation may be performed to repair the storage unit, or the storage unit may be set to fail.

[0046] When the ratio of the set current to the reference current corresponding to the storage unit is between the first reference value and the second reference value, the storage unit is a dangerous storage unit, so an additional small reset pulse insertion (SIRP) action can be performed on this storage unit in step S360 to repair this storage unit and improve the ratio of the set current to the reference current. It is particularly mentioned here that the so-called SIRP action is to appropriately insert a reset pulse with a relatively small voltage value (relative to the voltage value of the set pulse / formed pulse) after applying a set pulse (or forming a pulse) to this storage unit, and then re-apply the set pulse (or forming a pulse). This can effectively reduce the resistance value of such storage units and increase their set current (or formed current).

[0047] When the ratio of the set current corresponding to the memory cell to the reference current is between the second reference value and the third reference value, the memory cell can be directly determined to be a safe memory cell without performing a repair operation.

[0048] When the ratio of the set current to the reference current corresponding to the memory cell is greater than the third reference value, the memory cell is also a safe memory cell and no repair action is required. However, since the ratio is greater than the third reference value, it means that the resistance of this memory cell is pushed to a lower range when performing the set action. Therefore, when performing the reset action on this memory cell in the subsequent steps, it may be necessary to strengthen the reset action (for example, perform the reset with higher energy), so this memory cell can be recorded as a memory cell that needs to be strengthened reset.

[0049] Incidentally, the physical state of each storage unit can be completed by setting a plurality of corresponding marking values. For example, corresponding to four possible physical states, each storage unit can have a corresponding two-bit marking value. When performing a set, reset or read operation on each storage unit, a corresponding repair operation can be performed according to the marking value corresponding to each storage unit to improve data reliability.

[0050] Please refer to the following Figure 4 , Figure 4A schematic diagram of an implementation method of a reliability improvement method according to an embodiment of the present invention is shown. In step S410, a forming operation is performed on all memory cells in a memory array. Next, in step S420, it is determined whether the formed current of the memory cell that has completed the forming operation is greater than a target value. If the determination result is yes, step S440 is performed. If the determination result is no, step S430 is performed.

[0051] The above target value is used to determine whether the memory cell has successfully completed the formation operation. When the formation operation of the memory cell is not completed, an additional SIRP operation can be performed through step S430 to further reduce the resistance value of the memory cell.

[0052] In step S440, the statistical values ​​(such as maximum value, average value, median, etc.) of the post-formation current corresponding to all memory cells are obtained, and the reference current IR is set according to the statistical values ​​(step S450). Then, a resistor-capacitor circuit can be adjusted through step S460, and the resistor-capacitor circuit can be in a state that can provide the reference current IR. In detail, the resistor-capacitor circuit can receive a fixed bias voltage and generate a current according to the provided resistance value. Among them, when the reference current IR is set, the embodiment of the present invention can adjust the resistance value provided by the resistor-capacitor circuit by means of trimming, and make the current provided by the resistor-capacitor circuit exactly equal to the reference current IR.

[0053] Of course, the adjustment mechanism of the resistance value of the above-mentioned resistor and capacitor circuit can also be completed in a digital manner. In this way, the current generated by the resistor and capacitor circuit may have an inevitable error with the reference current IR. In practice. The current generated by the resistor and capacitor circuit only needs to be substantially equal to the reference current IR, and does not need to be exactly the same. In an embodiment of the present invention, the current generated by the resistor and capacitor circuit can be slightly greater than the reference current IR.

[0054] In addition, the above-mentioned resistor and capacitor circuit can be additionally disposed outside the memory cell array, or a memory cell in the memory cell array can be selected to implement it.

[0055] Next, in step S470, a setting operation is performed on the memory cell, and the setting current I of the memory cell is read. When the setting current I<1.2*reference current IR (step S481), step S491 is executed to mark the memory cell as a bad memory cell, and a repair action such as replacement with a spare memory cell or error correction is required, or the memory cell is set as a failure; when 1.2*reference current IR≤setting current I<1.4*reference current IR (step S482), step S492 is executed to mark the memory cell as a dangerous memory cell, and a repair action of an additional SIRP action is required; when 1.4*reference current IR≤setting current I<2*reference current IR (step S483), step S493 is executed to mark the memory cell as a safe memory cell; and when 2*reference current IR≤setting current I (step S484), step S494 is executed to record the memory cell as an over-set memory cell.

[0056] Please refer to Figure 5 , Figure 5 A schematic diagram showing another implementation of the reliability improvement method of an embodiment of the present invention. In this embodiment, the action details of steps S510 to S530 and steps S550 to S570 are the same as those of the aforementioned implementation, and will not be described in detail herein. It is worth noting that in step S540, this implementation only judges the post-formation current of some memory cells in the memory cell array, and thereby obtains the statistical value of the post-formation current. In this implementation, one selected memory cell in each memory cell row can be selected from a plurality of memory cell rows in the memory cell array to calculate the statistical value of the post-formation current. Furthermore, each selected memory cell corresponds to a plurality of different memory columns in the memory cell array.

[0057] In simple terms, multiple memory cells in the memory cell array can be selected as selected memory cells according to the diagonal layout position. Of course, the embodiment of the present invention is not limited thereto.

[0058] In this embodiment, since not all memory cells are selected to perform the reference current setting operation, the ratio between the set current I and the reference current IR is set more strictly in steps S581 to S584. Among them, step S581 determines whether the set current I is less than 1.4*reference current IR; step S582 determines whether the set current I is greater than or equal to 1.4*reference current IR and less than 1.6*reference current IR; step S583 determines whether the set current I is greater than or equal to 1.6*reference current IR and less than 2.3*reference current IR; step S584 determines whether the set current I is greater than or equal to 2.3*reference current IR. Steps S591 to S594 respectively correspond to the judgment results of steps S581 to S584 to perform the recording operation of the physical state of the memory cell. The details of steps S581 to S584 are similar to steps S491 to S494, and are not repeated here.

[0059] Of course, the above Figure 4 , Figure 5 In the embodiment, the ratio between the set current I and the reference current IR can be adjusted according to the actual electrical characteristics of the resistive memory.

[0060] Incidentally, regarding Figure 4 , Figure 5 In the implementation manner, the reference value can be set by a plurality of resistor and capacitor circuits. Figure 4 For example, a first resistor-capacitor circuit can be used to generate a current of 1.2*reference current IR; a second resistor-capacitor circuit can be used to generate a current of 1.4*reference current IR; and a third resistor-capacitor circuit can be used to generate a current of 2*reference current IR. After the reference current IR is set, these resistor-capacitor circuits can adjust the magnitude of the generated current by trimming. Of course, the first resistor-capacitor circuit to the third resistor-capacitor circuit can be circuits disposed outside the memory cell array, or can be multiple memory cells in the memory cell array.

[0061] Please refer to Figure 6 , Figure 6A schematic diagram of a memory device according to an embodiment of the present invention is shown. The memory device 600 includes a memory cell array 610, a controller 620, a sense amplifier 630, an address latch 641, an X decoder 642, a Y decoder 643, an input data latch 651, an output data latch 652, an input / output buffer 660, logic circuits 670, 680, a voltage generator 690, and a bias lookup table 6100. The memory cell array 610 has a plurality of memory cells, and in this embodiment, the memory cells are resistive memory cells. The memory cell array 610 has a Y gate 611 to control the input of the address signal in the Y direction. The memory cell array 610 is also coupled to the X decoder 642 and the Y decoder 643 to receive the decoded address information in the X and Y directions respectively. The X decoder 642 and the Y decoder 643 are coupled to the address latch 641, wherein the address latch 641 is used to store the address information ADDS. In addition, the logic circuit 670 is used to control whether the address latch 641, the X decoder 642, and the Y decoder 643 are enabled, and determine whether the memory cell array 610 can be accessed.

[0062] The memory cell array 610 is further coupled to a sense amplifier 630. The sense amplifier 630 is used to sense the read current of the memory cell and obtain output data. The input data latch 651 and the output data latch 652 latch the write data and output data of the memory cell respectively. The input-output buffer 660 temporarily stores the write data and output data and is used to receive or provide an input-output signal IOS.

[0063] It is worth noting that the controller 620 can receive the post-formation current of the memory cell sensed by the sense amplifier 630 through the logic circuit 680, and calculate the statistical value of the post-formation current (such as the maximum value, average value, median, etc.) to set the reference current. In this embodiment, for example, the reference current is set with the maximum value of the post-formation current. The controller 620 has an adjustment signal generator 621. The adjustment signal generator 621 can generate an adjustment signal based on the statistical value of the post-formation current. The logic circuit 680 is used to perform steps S681 and S682. The logic circuit 680 receives the above-mentioned adjustment signal, and performs the generation action of the adjustment value of the formation voltage and the setting voltage according to the adjustment signal in step S681. The logic circuit 680 can adjust the resistor-capacitor circuit (not shown) according to the above-mentioned adjustment value to generate a reference current. The logic circuit 680 also determines in step S682 whether the reference current generated by the resistor-capacitor circuit is not less than the statistical value of the post-formation current, and completes the reference current setting action accordingly.

[0064] When performing the comparison operation of the set current, based on the reference current IR1 set according to the formed current statistics (e.g., the maximum value), the controller 620 can make the multiple resistor-capacitor circuits generate multiple reference currents IRAx respectively according to multiple reference values. The reference current IRAx can be provided to the sense amplifier 630 at the same time to compare with the set current of the memory cell, and determine whether the set current of the memory cell is in one of the multiple intervals formed by the set multiple reference currents IRAx, and thereby determine the physical state of the memory cell.

[0065] In addition, the controller 620 is coupled to the bias voltage lookup table 6100 and enables the bias voltage lookup table 6100 to provide a bias voltage setting value to enable the voltage generator 690 to generate a corresponding reset voltage or a setting voltage.

[0066] The controller 620 further receives the command signal CMDS to execute each access operation related to the memory cell array 610 .

[0067] The controller 620 of the embodiment of the present invention may be a processor with computing capabilities. Alternatively, the controller 620 may be a hardware circuit designed by a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art, and implemented by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC).

[0068] In summary, the present invention calculates the ratio of the current after setting to the maximum value of the current after forming of the memory cell, and determines the physical state of each memory cell according to the ratio. In this way, subsequent repair actions can be performed according to the physical state of each memory cell, which can effectively improve the reliability of the memory cell.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A reliability improvement method, applicable to a resistive memory device, characterized in that: include: performing a forming action on a plurality of storage units; Reading the plurality of formed memory cells to obtain a plurality of formed currents respectively; Setting a reference current according to the statistical values ​​of the plurality of formed currents; Providing a resistor and capacitor circuit, and recording the reference current by adjusting the impedance value provided by the resistor and capacitor circuit; performing a setting operation on the plurality of storage units; Calculating a ratio of a set current of each of the memory cells to the reference current, and determining a physical state of each of the memory cells according to the ratio; as well as Whether to perform a repair operation on each of the storage units is determined according to the physical state of each of the storage units.

2. The reliability improvement method according to claim 1, characterized in that: The steps of calculating the ratio of the set current to the reference current of each memory cell and determining the physical state of each memory cell according to the ratio include: A plurality of different reference values ​​are set, and the ratio is compared with the plurality of reference values ​​to obtain the physical state of each of the memory cells.

3. The reliability improvement method according to claim 2, characterized in that: The step of determining whether to perform the repair operation on each of the storage units according to the physical state of each of the storage units comprises: When the ratio is less than a first reference value, each of the corresponding storage cells is set to a first state, and a replacement action is performed on each of the storage cells or an error correction code action is performed on the data stored in each of the storage cells to repair each of the storage cells, or each of the storage cells is set to fail; When the ratio is greater than or equal to the first reference value and less than a second reference value, each of the corresponding storage units is set to a second state, and a small reset pulse insertion operation is performed for each of the corresponding storage units to repair each of the storage units; When the ratio is greater than or equal to the second reference value and less than a third reference value, each of the corresponding memory cells is set to a third state without performing a repair operation on each of the memory cells; and When the ratio is greater than the third reference value, each of the corresponding memory cells is set to the fourth state, and no repair operation is performed on each of the memory cells. When performing a reset operation on each of the memory cells, an enhanced reset operation is used. The first reference value<the second reference value<the third reference value.

4. The reliability improvement method according to claim 2, characterized in that: The method also includes selecting all memory cells in a memory cell array as the plurality of memory cells. The reliability improvement method according to claim 4 , wherein the plurality of reference values ​​are 1, 1.2, 1.4 and 2 respectively.

6. The reliability improvement method according to claim 2, characterized in that: Also includes: In a plurality of memory cell rows of a memory cell array, a selected memory cell in each of the memory cell rows is selected to obtain each of the memory cells, The plurality of storage cells respectively correspond to different storage columns in the storage cell array.

7. The reliability improvement method according to claim 6, characterized in that: The multiple reference values ​​are respectively 1, 1.4, 1.6 and 2.

3.

8. The reliability improvement method according to claim 1, characterized in that: Also includes: A first reference storage unit is provided to record the reference current.

9. The reliability improvement method according to claim 7, further comprising: A plurality of second reference storage units are provided to respectively record a plurality of products generated by the reference current and a plurality of reference values.

10. A resistive memory device, characterized in that: include: A memory cell array having a plurality of memory cells; a sense amplifier coupled to the memory cell array; A controller, coupled to the sense amplifier, configured to: performing a forming operation on the plurality of storage units; enabling the sense amplifier to read the plurality of formed memory cells to obtain a plurality of formed currents respectively; Setting a first reference current according to a statistical value of the plurality of formed currents; performing a setting operation on the plurality of storage units; The sense amplifier calculates a ratio of a set current of each memory cell to the first reference current, and the controller determines a physical state of each memory cell according to the ratio; as well as Determining whether to perform a repair operation on each of the storage units according to the physical state of each of the storage units; as well as a reference current generator coupled to the controller and the sense amplifier, The controller provides an adjustment signal according to the statistical values ​​of the multiple formed currents, so that the reference current generator provides the first reference current according to the adjustment signal, and the reference current generator is a resistor-capacitor circuit.

11. The resistive memory device according to claim 10, wherein: The reference current generator further generates a plurality of second reference currents according to the first reference current and a plurality of reference values, and the sense amplifier compares the set current of each of the memory cells with the plurality of second reference currents to determine the physical state of each of the memory cells.

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