Logic circuits and semiconductor devices

Abstract

The logic circuit includes: a thin-film transistor having a channel formation region formed using an oxide semiconductor; and a capacitor with terminals, one of which is brought into a floating state by turning off the thin-film transistor. The oxide semiconductor has a 5×10 19 (atoms / cm) 3 The thin-film transistor (TFT) uses a hydrogen concentration of 100% or less, and thus acts essentially as an insulator in the absence of an electric field. Therefore, the cutoff current of the TFT can be reduced, thereby suppressing leakage of charge stored in the capacitor through the TFT. Correspondingly, malfunctions in the logic circuit can be prevented. Furthermore, the reduction in the cutoff current of the TFT reduces excess current flowing in the logic circuit, resulting in lower power consumption of the logic circuit.

Description

[0001] This application is a divisional application of the following invention patent application:

[0002] Invention title: Logic circuit and semiconductor device; Application date: September 24, 2010; Application number: 201811233695.2. Technical Field

[0003] One aspect of the present invention relates to a logic circuit comprising a field-effect transistor formed using an oxide semiconductor. Furthermore, another aspect of the present invention relates to a semiconductor device comprising a logic circuit.

[0004] Note that in this specification, semiconductor device refers to all devices that can operate by using semiconductor characteristics, and electro-optical devices, semiconductor circuits and electronic devices are all included in the scope of semiconductor device. Background Technology

[0005] The technique of forming thin-film transistors (TFTs) by using a thin semiconductor film formed on a substrate with an insulating surface is gaining more attention. TFTs are used in display devices, exemplified by LCD televisions. Silicon-based semiconductor materials are considered suitable for thin semiconductor films in TFTs. Besides silicon-based semiconductor materials, oxide semiconductors are also gaining attention.

[0006] Zinc oxide and materials containing zinc oxide as a component are known as oxide semiconductor materials. Furthermore, materials using electron carrier densities less than 102 are disclosed. 18 / cm 3 Thin-film transistors formed from amorphous oxide (oxide semiconductor) (Patent Documents 1 to 3).

[0007] [References]

[0008] [Patent Literature]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2006-165527

[0010] [Patent Document 2] Japanese Patent Application Publication No. 2006-165528

[0011] [Patent Document 3] Japanese Patent Application Publication No. 2006-165529 Summary of the Invention

[0012] However, differences in stoichiometry between oxide semiconductors and oxide semiconductors occur during thin film formation. For example, the conductivity of oxide semiconductors changes due to oxygen excess or oxygen deficiency. Furthermore, hydrogen entering the oxide semiconductor thin film during formation forms oxygen (O)-hydrogen (H) bonds and acts as an electron donor, contributing to variations in conductivity. Additionally, since OH bonds are polar molecules, they also contribute to variations in the characteristics of active devices such as thin-film transistors fabricated using oxide semiconductors.

[0013] Even when it has less than 10 18 / cm 3 When the electron carrier density is such that, the oxide semiconductor is essentially an n-type oxide semiconductor. Therefore, approximately 10-1 of the thin-film transistor disclosed in the patent literature is obtained. 3 The low on-to-off ratio of thin-film transistors is attributed to their large off-state current.

[0014] The on-to-off ratio is a measure of the characteristics of a switch. Circuits containing thin-film transistors with low on-to-off ratios become unstable. Furthermore, current flows excessively due to the large off-state current, thus increasing power consumption.

[0015] In view of the above problems, one object of an embodiment of the present invention is to suppress faults in logic circuits including thin-film transistors formed using oxide semiconductors.

[0016] Furthermore, one objective of an embodiment of the present invention is to reduce the power consumption of logic circuits including thin-film transistors formed using oxide semiconductors.

[0017] According to one embodiment of the invention, the logic circuit includes a thin-film transistor having a channel formation region formed using an oxide semiconductor, wherein the oxide semiconductor is made intrinsic or substantially intrinsic by removing impurities (e.g., hydrogen and water) that have the potential to act as electron donors (or donors), and the oxide semiconductor has a larger bandgap than silicon semiconductor.

[0018] Specifically, the logic circuit includes a thin-film transistor having a channel formation region formed using oxide semiconductor, wherein the hydrogen concentration is set to 5 × 10⁻⁶. 19 / cm 3 Or smaller, preferably 5×10 18 / cm 3 Or smaller, more preferably 5×10 17 / cm 3 Or even smaller to remove hydrogen or OH bonds contained in the oxide semiconductor, and the carrier density is set to 5 × 10⁻⁶. 14 / cm3 Or smaller, preferably 5×10 12 / cm 3 Or smaller.

[0019] The bandgap of the oxide semiconductor is set to 2 eV or greater, preferably 2.5 eV or greater, more preferably 3 eV or greater, in order to minimize the impurities (e.g., hydrogen) that form donors. Furthermore, the carrier density of the oxide semiconductor is set to 1 × 10⁻⁶. 14 / cm 3 Or smaller, preferably 1×10 12 / cm 3 Or smaller.

[0020] This purified oxide semiconductor is used for the channel formation region of thin-film transistors. Accordingly, even with a channel width of 10 mm, a drain voltage of 1 V and 10 V and a gate voltage in the range of -5 V to -20 V are achieved, resulting in a voltage of 1 × 10⁻⁶. -13 [A] or smaller drain current.

[0021] In other words, one embodiment of the present invention is a logic circuit comprising: a thin-film transistor; and a capacitor having terminals, one of which is electrically connected to a node that enters a floating state by turning off the thin-film transistor. The channel formation region of the thin-film transistor uses a hydrogen concentration of 5 × 10⁻⁶. 19 (atoms / cm) 3 It is formed from oxide semiconductors.

[0022] Note that in this specification, concentration is measured by secondary ion mass spectrometry (hereinafter referred to as SIMS). However, there are no specific limitations when describing other measurement methods.

[0023] In addition, semiconductor devices including logic circuits are also an embodiment of the present invention.

[0024] According to one embodiment of the present invention, the logic circuit includes: a thin-film transistor having a channel formation region formed using an oxide semiconductor; and a capacitor having terminals, wherein one of the terminals is brought into a floating state by turning off the thin-film transistor. The oxide semiconductor is an oxide semiconductor with a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5 × 10⁻⁶. 19 (atoms / cm) 3The oxide semiconductor, or even smaller, acts as an insulator or near-insulator semiconductor when no electric field is present (a near-insulator semiconductor is essentially an insulator). Therefore, the cutoff current of the thin-film transistor can be reduced. Consequently, leakage of charge stored in the capacitor through the thin-film transistor can be suppressed. Therefore, logic circuit failures can be prevented. Furthermore, the period during which one terminal of the capacitor can be in a floating state can be extended. In other words, the number of times data is rewritten to the capacitor (also known as a refresh) can be reduced.

[0025] Furthermore, by reducing the cutoff current of the thin-film transistor, the excessive current flowing in the logic circuit can be reduced. Therefore, the power consumption of the logic circuit can be reduced. Attached Figure Description

[0026] Figure 1A and Figure 1C This is a circuit diagram showing an example of an inverter, and Figure 1B and Figure 1D This is a timing diagram showing an example of a phase inverter.

[0027] Figures 2A to 2D This is a circuit diagram showing an example of an inverter.

[0028] Figure 3A This is a circuit diagram showing an example of a shift register, and Figure 3B This is a timing diagram showing an example of a shift register.

[0029] Figure 4A This is a circuit diagram showing an example of a shift register, and Figure 4B This is a timing diagram showing an example of a shift register.

[0030] Figure 5A This is a plan view showing an example of a thin-film transistor, and Figure 5B This is a cross-sectional view showing an example of a thin-film transistor.

[0031] Figures 6A to 6E This is a cross-sectional view illustrating an example of a method for manufacturing thin-film transistors.

[0032] Figure 7A This is a plan view showing an example of a thin-film transistor, and Figure 7B This is a cross-sectional view showing an example of a thin-film transistor.

[0033] Figures 8A to 8E This is a cross-sectional view illustrating an example of a method for manufacturing thin-film transistors.

[0034] Figure 9A and Figure 9B This is a cross-sectional view showing an example of a thin-film transistor.

[0035] Figures 10A to 10E This is a cross-sectional view illustrating an example of a method for manufacturing thin-film transistors.

[0036] Figures 11A to 11E This is a cross-sectional view illustrating an example of a method for manufacturing thin-film transistors.

[0037] Figures 12A to 12D This is a cross-sectional view illustrating an example of a method for manufacturing thin-film transistors.

[0038] Figures 13A to 13D This is a cross-sectional view illustrating an example of a method for manufacturing thin-film transistors.

[0039] Figure 14 This is a cross-sectional view showing an example of a thin-film transistor.

[0040] Figure 15A and Figure 15C This is a plan view showing an example of a semiconductor device, and Figure 15B This is a cross-sectional view showing any of the examples of semiconductor devices.

[0041] Figure 16 This is a simplified diagram illustrating an example of a pixel equivalent circuit for a semiconductor device.

[0042] Figures 17A to 17C This is a cross-sectional view showing an example of a semiconductor device.

[0043] Figure 18A This is a plan view showing an example of a semiconductor device, and Figure 18B This is a cross-sectional view showing an example of a semiconductor device.

[0044] Figure 19 This is a cross-sectional view showing an example of a semiconductor device.

[0045] Figure 20A and Figure 20B An example of a semiconductor device is shown.

[0046] Figure 21A and Figure 21B An example of a semiconductor device is shown.

[0047] Figure 22 An example of a semiconductor device is shown.

[0048] Figure 23 An example of a semiconductor device is shown.

[0049] Figure 24 This illustrates a portion of the band structure between the source and drain of a MOS transistor formed using oxide semiconductor.

[0050] Figure 25 This shows where a positive voltage is applied to Figure 24 The state of the drain side.

[0051] Figure 26A and Figure 26B This is the energy band diagram of a MOS transistor structure formed using oxide semiconductor, where a positive gate voltage is applied ( Figure 26A Or apply a negative gate voltage ( Figure 26B ).

[0052] Figure 27 This shows a portion of the band structure between the source and drain of a silicon MOS transistor.

[0053] Figure 28 This is a graph showing the initial characteristics of an example thin-film transistor.

[0054] Figure 29A and Figure 29B This is a top view of a component used for evaluation, serving as an example of a thin-film transistor.

[0055] Figure 30A and Figure 30B This is a graph showing the Vg-Id characteristics of a device used for evaluation, which is an example of a thin-film transistor. Detailed Implementation

[0056] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be limited to the description of the following embodiments.

[0057] Note that because the source and drain terminals of a transistor vary depending on the transistor's structure, operating conditions, etc., it is difficult to define which one is the source terminal or the drain terminal. Therefore, in this specification, for the sake of distinction, one of the source and drain terminals will be referred to as the first terminal, and the other as the second terminal.

[0058] Note that, for the sake of brevity, the size and thickness of the layers or regions of the structures shown in the accompanying drawings, etc., in some cases have been enlarged. Therefore, the embodiments of the present invention are not limited to such proportions. Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components; these terms do not numerically limit the components.

[0059] (Example 1)

[0060] In this embodiment, an example of a logic circuit is described. Specifically, refer to... Figures 1A to 1D as well as Figures 2A to 2DExamples of inverters, including thin-film transistors having channel formation regions formed using oxide semiconductors, are described below.

[0061] Figure 1A This is a circuit diagram illustrating an example of the inverter in this embodiment. Figure 1A The inverter shown includes thin-film transistors 11 to 14 and a capacitor 15. Here, thin-film transistor 11 is a depletion-mode transistor, while thin-film transistors 12 to 14 are enhancement-mode transistors. Note that in this specification, an n-channel transistor with a positive threshold voltage is called an enhancement-mode transistor, while an n-channel transistor with a negative threshold voltage is called a depletion-mode transistor.

[0062] The first terminal of the thin-film transistor 11 is electrically connected to a high power supply potential (V) DD The wiring (hereinafter referred to as high power potential line).

[0063] The gate terminal of the thin-film transistor 12 is electrically connected to a wiring for providing an input signal (IN) (hereinafter referred to as an input signal line), and the first terminal of the thin-film transistor 12 is electrically connected to the gate terminal and the second terminal of the thin-film transistor 11.

[0064] The gate terminal of thin-film transistor 13 is electrically connected to wiring for providing a pulse signal (PS) (hereinafter referred to as a pulse signal line), the first terminal of thin-film transistor 13 is electrically connected to the second terminal of thin-film transistor 12, and the second terminal of thin-film transistor 13 is electrically connected to wiring for providing a low power supply potential (V). SS (Hereinafter referred to as low power potential line) wiring.

[0065] The gate terminal of the thin-film transistor 14 is electrically connected to the pulse signal line, the first terminal of the thin-film transistor 14 is electrically connected to the gate terminal and the second terminal of the thin-film transistor 11 and the first terminal of the thin-film transistor 12, and the second terminal of the thin-film transistor 14 is electrically connected to the wiring for outputting the output signal (hereinafter, this wiring is also referred to as the output signal line).

[0066] One terminal of capacitor 15 is electrically connected to the second terminal of thin-film transistor 14 and the output signal line, and the other terminal of capacitor 15 is electrically connected to the low power supply potential line.

[0067] Note that the thin-film transistor 11 is a depletion-type transistor, where the first terminal is electrically connected to a high power supply potential line and the gate terminal is electrically connected to the second terminal. That is, the thin-film transistor 11 remains in the on state at all times. In other words, the thin-film transistor 11 functions as a resistor.

[0068] Furthermore, in this specification, the high power supply potential (V) DD ) and low power supply potential (V SS It can be any potential, as long as it is a high supply potential (V). DD ) higher than the low power supply potential (V SS For example, ground potential, 0V, etc., can be used as low power supply potentials (V). SS ), while a given positive potential can be used as a high power supply potential (V). DD ).

[0069] Next, refer to Figure 1B To describe using timing diagrams Figure 1A The operation of the circuit shown. Note that it is shown... Figure 1B The point where the gate terminal and the second terminal of the thin-film transistor 11, the first terminal of the thin-film transistor 12, and the first terminal of the thin-film transistor 14 are electrically connected to each other is called node A.

[0070] During period T1, the potentials of the input signal (IN) and the pulse signal (PS) increase to a high level. Therefore, thin-film transistors 12 to 14 are turned on. Consequently, node A and one terminal of the capacitor are electrically connected to the low power supply potential line; that is, the potential of node A and the output signal (OUT) of the inverter decrease to a low level. No charge is stored in capacitor 15.

[0071] During period T2, the potential of the pulse signal (PS) drops to a low level. Therefore, thin-film transistors 13 and 14 are turned off. When thin-film transistor 13 is turned off, the potential of node A increases to a high level. When thin-film transistor 14 is turned off, one terminal of capacitor 15 is brought into a floating state. Therefore, the output signal (OUT) of the inverter remains at a low level.

[0072] During period T3, the potential of the input signal (IN) decreases to a low level, while the potential of the pulse signal (PS) increases to a high level. Therefore, thin-film transistor 12 is turned off, while thin-film transistors 13 and 14 are turned on. Consequently, node A and one terminal of capacitor 15 are electrically connected to the high power supply potential line via thin-film transistor 11; that is, the potential of node A and the output signal (OUT) of the inverter increase to a high level. Positive charge is stored in one terminal of capacitor 15.

[0073] In each of the plurality of thin-film transistors included in the inverter of this embodiment, the channel formation region is formed using an oxide semiconductor. The oxide semiconductor is an oxide semiconductor with a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5 × 10⁻⁶. 19 (atoms / cm) 3The oxide semiconductor, or smaller, acts as an insulator or near-insulator semiconductor when no electric field is present (a near-insulator semiconductor is essentially an insulator). Therefore, the off-state current of a thin-film transistor having a channel formation region formed using an oxide semiconductor can be reduced. Thus, charge leakage through the thin-film transistor can be suppressed.

[0074] For example, by using the channel formation region formed by oxide semiconductor in the thin-film transistor 14, the level of potential change during the period when one terminal of capacitor 15 is in a floating state (i.e., period T2), such as the increase of potential during period T2, can be suppressed. Therefore, inverter malfunction can be prevented. Furthermore, the period during which one terminal of capacitor 15 is in a floating state can be made longer. In other words, the number of times data is rewritten to capacitor 15 (also known as refresh) can be reduced.

[0075] Furthermore, the use of an oxide semiconductor-formed channel region in the thin-film transistor 13 reduces the through-current flowing from the high power supply line to the low power supply line during the period when the input signal (IN) is at a high level and the pulse signal (PS) is at a low level (i.e., period T2). Therefore, the power consumption of the inverter can be reduced.

[0076] Note that the inverter in this embodiment is not limited to... Figure 1A The inverter shown below. Refer to the following... Figure 1C To describe and Figure 1A Examples of different inverters are shown.

[0077] Figure 1C The inverter shown includes thin-film transistors 21 to 24 and a capacitor 25. Here, thin-film transistor 21 is a depletion-type transistor, while thin-film transistors 22 to 24 are enhancement-type transistors.

[0078] The first terminal of the thin-film transistor 21 is electrically connected to a high power supply potential line.

[0079] The gate terminal of the thin-film transistor 22 is electrically connected to the pulse signal line, and the first terminal of the thin-film transistor 22 is electrically connected to the gate terminal and the second terminal of the thin-film transistor 21.

[0080] The gate terminal of the thin-film transistor 23 is electrically connected to the input signal line, the first terminal of the thin-film transistor 23 is electrically connected to the second terminal of the thin-film transistor 22, and the second terminal of the thin-film transistor 23 is electrically connected to the low power supply potential line.

[0081] The gate terminal of the thin-film transistor 24 is electrically connected to the pulse signal line, the first terminal of the thin-film transistor 24 is electrically connected to the second terminal of the thin-film transistor 22 and the first terminal of the thin-film transistor 23, and the second terminal of the thin-film transistor 24 is electrically connected to the output signal line.

[0082] One terminal of capacitor 25 is electrically connected to the second terminal of thin-film transistor 24 and the output signal line, and the other terminal of capacitor 25 is electrically connected to the low power supply potential line.

[0083] In short, Figure 1C The inverter shown is one in which a thin-film transistor 22 is used instead of... Figure 1A The circuit of thin-film transistor 13 in the middle.

[0084] Next, refer to Figure 1D To describe using timing diagrams Figure 1C The operation of the circuit shown. Note that it is shown... Figure 1B Meanwhile, the node where the second terminal of thin film transistor 22, the first terminal of thin film transistor 23, and the first terminal of thin film transistor 24 are electrically connected to each other is considered to be node B.

[0085] During period T4, the potentials of the input signal (IN) and the pulse signal (PS) increase to a high level. Therefore, thin-film transistors 22 to 24 are turned on. Consequently, node B and one terminal of capacitor 25 are electrically connected to a low power supply potential line; that is, the potential of node B and the output signal (OUT) of the inverter decrease to a low level. No charge is stored in capacitor 25.

[0086] During period T5, the potential of the pulse signal (PS) drops to a low level. Therefore, thin-film transistors 22 and 24 are turned off. When thin-film transistor 24 is turned off, one terminal of capacitor 25 is brought into a floating state. Therefore, the output signal (OUT) of the inverter remains low. Note that the potential of node B is low.

[0087] During period T6, the potential of the input signal (IN) decreases to a low level, while the potential of the pulse signal (PS) increases to a high level. Therefore, thin-film transistor 23 is turned off, while thin-film transistors 22 and 24 are turned on. Consequently, node B and one terminal of capacitor 25 are electrically connected to the high power supply potential line via thin-film transistor 21; that is, the potential of node B and the output signal (OUT) of the inverter increase to a high level. Positive charge accumulates in one terminal of capacitor 25.

[0088] exist Figure 1C In each of the multiple thin-film transistors included in the inverter shown, the channel formation region is formed using an oxide semiconductor. The oxide semiconductor is an oxide semiconductor with a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5 × 10⁻⁶.19 (atoms / cm) 3 The oxide semiconductor, or smaller, acts as an insulator or near-insulator semiconductor when no electric field is present (a near-insulator semiconductor is essentially an insulator). Therefore, the off-state current of a thin-film transistor having a channel formation region formed using an oxide semiconductor can be reduced. Thus, charge leakage through the thin-film transistor can be suppressed.

[0089] For example, by using the channel formation region formed by the thin-film transistor 24 with oxide semiconductor, the level of potential change during the period when one terminal of capacitor 25 is in a floating state can be suppressed. Therefore, inverter failure can be prevented. In addition, the period during which node B is in a floating state can be longer. In other words, the number of times data is rewritten to capacitor 25 (also known as refresh) can be reduced.

[0090] Furthermore, the use of an oxide semiconductor-formed channel region in the thin-film transistor 22 reduces the through current flowing from the high power supply line to the low power supply line during the period when the input signal (IN) is at a high level and the pulse signal (PS) is at a low level (i.e., period T5). Therefore, the power consumption of the inverter can be reduced.

[0091] While depletion-mode transistors are used in thin-film transistors that are electrically connected to the high power supply potential line in an inverter, enhancement-mode transistors can be used in thin-film transistors. Figure 2A It replaces the thin-film transistor 31, which is used as an enhancement transistor. Figure 1A The circuit diagram shown illustrates the thin-film transistor 11 included in the inverter. Similarly, Figure 2B It replaces the thin-film transistor 41, which is used as an enhancement transistor. Figure 1C The circuit diagram shown includes the thin-film transistor 21 contained in the inverter. Note that the gate terminal and first terminal of each of the thin-film transistors 31 and 41 are electrically connected to a high power supply potential line.

[0092] Although capacitors are included in each inverter, each inverter can be operated without capacitors. Figure 2C Showing from Figure 2A The circuit diagram shown is for removing capacitor 15 in the inverter. Similarly, Figure 2D Showing from Figure 2B The circuit diagram shown is for removing capacitor 25 in the inverter.

[0093] This embodiment can be implemented by combining it appropriately with any other embodiment.

[0094] (Example 2)

[0095] In this embodiment, an example of a logic circuit is described. Specifically, refer to... Figure 3A and Figure 3B as well as Figure 4A and Figure 4B Examples of shift registers that include the inverters in Embodiment 1 are described below.

[0096] The shift register in this embodiment includes: multiple pulse output circuits; wiring for providing a first clock signal (CK1), electrically connected to an odd-numbered pulse output circuit (hereinafter referred to as a first clock signal line) of the multiple pulse output circuits; and wiring for providing a second clock signal (CK2), electrically connected to an even-numbered pulse output circuit (hereinafter referred to as a second clock signal line) of the multiple pulse output circuits. Furthermore, the input terminals of each pulse output circuit are electrically connected to wiring for providing a start pulse signal (SP) (hereinafter referred to as a start pulse line) or the output terminals of the preceding pulse output circuit.

[0097] Reference Figure 3A This is a specific example illustrating the circuit configuration of a pulse output circuit. Note that pulse output circuits 110, 120, and 130 are as follows: Figure 3A As shown.

[0098] The pulse output circuit 110 includes thin-film transistors 101 to 104 and a capacitor 105. Here, thin-film transistor 101 is a depletion-type transistor, while thin-film transistors 102 to 104 are enhancement-type transistors.

[0099] The first terminal of the thin-film transistor 101 is electrically connected to a high power supply potential line.

[0100] The gate terminal of the thin-film transistor 102 is electrically connected to the start-up pulse line, and the first terminal of the thin-film transistor 102 is electrically connected to the gate terminal and the second terminal of the thin-film transistor 101.

[0101] The gate terminal of the thin-film transistor 103 is electrically connected to the clock signal line, the first terminal of the thin-film transistor 103 is electrically connected to the second terminal of the thin-film transistor 102, and the second terminal of the thin-film transistor 103 is electrically connected to the low power supply potential line.

[0102] The gate terminal of the thin-film transistor 104 is electrically connected to the first clock signal line, and the first terminal of the thin-film transistor 104 is electrically connected to the gate terminal and the second terminal of the thin-film transistor 101 and the first terminal of the thin-film transistor 102.

[0103] One terminal of capacitor 105 is electrically connected to the second terminal of thin-film transistor 104, and the other terminal of capacitor 105 is electrically connected to a low power supply potential line.

[0104] In other words, Figure 3AThe pulse output circuit 110 shown uses Figure 1A The inverter shown is used to form the phase inverter.

[0105] Note that "input terminal of pulse output circuit 110" refers to the terminal that receives the input start pulse signal (SP) or the output signal of the preceding pulse output circuit, while "output terminal of pulse output circuit 110" refers to the terminal that outputs a signal from it to the pulse input terminal of the following stage. That is, here, the gate terminal of thin-film transistor 102 is electrically connected to the input terminal of the pulse output circuit, and the second terminal of thin-film transistor 104 and one terminal of capacitor 105 are electrically connected to the output terminal. Unless otherwise specified, the gate terminal of thin-film transistor 102 can be referred to as the input terminal of the pulse output circuit, and the second terminal of thin-film transistor 104 and one terminal of capacitor 105 can be referred to as the output terminal of the pulse output circuit.

[0106] The specific circuit configuration of pulse output circuit 120 is similar to that of pulse output circuit 110; therefore, reference is made to that description here. Note that the difference between pulse output circuit 120 and pulse output circuit 110 is that the input terminals of pulse output circuit 120 are electrically connected to the output terminals of pulse output circuit 110, and the second clock signal (CK2) is input to the terminal corresponding to the terminal in pulse output circuit 110 to which the first clock signal (CK1) is input.

[0107] The circuit configuration of the pulse output circuits following pulse output circuit 120 is similar to that of pulse output circuits 110 and 120. Therefore, reference is made to that description here. Furthermore, as described above, the odd-numbered pulse output circuits are electrically connected to the first clock signal line, while the even-numbered pulse output circuits are electrically connected to the second clock signal line.

[0108] Next, refer to Figure 3B To describe using timing diagrams Figure 3A The circuit shown operates. Note that, for convenience, Figure 3A In this circuit, specific nodes are represented by C to G, and the changes in the potential of each node are used to describe... Figure 3B The timing diagram.

[0109] During period t1, the potential of the startup pulse signal (SP) increases to a high level. Therefore, thin-film transistor 102 turns on. Thin-film transistor 101 is a depletion-type transistor in which its gate terminal is electrically connected to the second terminal. That is, thin-film transistor 101 remains in the on state during any period. In other words, thin-film transistor 101 functions as a resistor.

[0110] During period t2, the potential of the start-up pulse signal (SP) remains at a high level. Therefore, the thin-film transistor 102 remains in the on state.

[0111] During period t3, the potential of the first clock signal (CK1) increases to a high level. Therefore, thin-film transistors 103 and 104 are turned on. Furthermore, the potential of the startup pulse signal (SP) remains high. Therefore, thin-film transistor 102 remains in the on state. Consequently, nodes C and D are electrically connected to the low power supply potential line; that is, the potential of nodes C and D decreases to a low level.

[0112] During period t4, the potential of the first clock signal (CK1) drops to a low level. Therefore, thin-film transistors 103 and 104 are turned off. Consequently, node C is electrically connected to the high power supply potential line via thin-film transistor 101, and node D enters a floating state. That is, the potential of node C increases to a high level, while the potential of node D remains at a low level.

[0113] During period t5, the potential of the start pulse signal (SP) decreases to a low level. Therefore, thin-film transistor 102 is turned off. Furthermore, the potential of the second clock signal (CK2) increases to a high level. Therefore, thin-film transistors 113 and 114 are turned on. Thus, node F is electrically connected to the high power supply potential line through thin-film transistor 111; that is, the potential of node F increases to a high level. Therefore, thin-film transistor 122 is turned on.

[0114] During period t6, the potential of the second clock signal (CK2) drops to a low level. Therefore, thin-film transistors 113 and 114 are turned off. This causes node F to enter a floating state; that is, the potentials of nodes E and F remain at a high level.

[0115] During period t7, the potential of the first clock signal (CK1) increases to a high level. Therefore, thin-film transistors 103, 104, 123, and 124 are turned on. When thin-film transistor 104 is turned on, node D is electrically connected to the high power supply potential line through thin-film transistor 101; that is, the potential of node D increases to a high level. Therefore, thin-film transistor 112 is turned on. The potential of node F remains high; therefore, thin-film transistor 122 remains on. Therefore, node G is electrically connected to the low power supply potential line; that is, the potential of node G decreases to a low level.

[0116] During period t8, the potential of the first clock signal (CK1) drops to a low level. Therefore, thin-film transistors 103, 104, 123, and 124 are turned off. When thin-film transistor 104 is turned off, node C is electrically connected to the high power supply potential line through thin-film transistor 101, causing node D to enter a floating state. Therefore, nodes C and D remain at a high level. When thin-film transistor 123 is turned off, node G is electrically connected to the high power supply potential line through thin-film transistor 121; that is, the potential of node G increases to a high level.

[0117] During period t9, the potential of the second clock signal (CK2) increases to a high level. Therefore, thin-film transistors 113 and 114 are turned on. The potential of node D remains high, keeping thin-film transistor 112 in the on state. Therefore, nodes E and F are electrically connected to the low power supply potential line; that is, the potential of nodes E and F decreases to a low level. Therefore, thin-film transistor 122 is turned off. Furthermore, the potential of the startup pulse (SP) increases to a high level again. Note that the operation accompanying the increase of the startup pulse (SP) potential in the period following this period is the same as the operation in the period following period t1. Therefore, refer to this description here.

[0118] During period t10, the potential of the second clock signal (CK2) drops to a low level. Therefore, thin-film transistors 113 and 114 are turned off. This causes node F to enter a floating state; that is, the potential of node F remains at a low level. Furthermore, node E is electrically connected to the high power supply potential line via thin-film transistor 111; that is, the potential of node E increases to a high level.

[0119] For operations within the period after period t10, the above operations are repeated. Therefore, refer to this description here.

[0120] Note that capacitors (e.g., capacitors 105, 115, and 125) included in the pulse output circuits are configured to maintain the output signals of each pulse output circuit.

[0121] In each of the plurality of thin-film transistors included in the shift register of this embodiment, the channel formation region is formed using an oxide semiconductor. The oxide semiconductor is an oxide semiconductor with a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5 × 10⁻⁶. 19 (atoms / cm) 3 The oxide semiconductor, or smaller, acts as an insulator or near-insulator semiconductor when no electric field is present (a near-insulator semiconductor is essentially an insulator). Therefore, the off-state current of a thin-film transistor having a channel formation region formed using an oxide semiconductor can be reduced. Thus, charge leakage through the thin-film transistor can be suppressed.

[0122] For example, by using the channel formation region formed by the thin-film transistor 104 with oxide semiconductor, the level of potential change of node D during the period when node D is in a floating state (e.g., period t4 to t6), such as the increase of potential during period t4 to t6, can be suppressed. Therefore, shift register malfunctions can be prevented. Furthermore, the period during which node D is in a floating state can be longer. In other words, the number of times data is rewritten to capacitor 105 (also known as refresh) can be reduced.

[0123] Furthermore, the use of an oxide semiconductor-formed channel region in the thin-film transistor 103 can reduce the through current flowing from the high power supply line to the low power supply line during periods when the potential of the startup pulse (SP) is high and the potential of the first clock signal (CK1) is low (e.g., periods t1, t2, and t4). Therefore, the power consumption of the shift register can be reduced.

[0124] Note that the shift register in this embodiment is not limited to Figure 3A The shift register shown. (Refer to...) Figure 4A and Figure 4B To describe and Figure 3A and Figure 3B Examples of different shift registers are shown.

[0125] Figure 4A The shift register shown includes pulse output circuits 210, 220, and 230. Pulse output circuit 210 includes thin-film transistors 201 to 204 and a capacitor 205. Here, thin-film transistor 201 is a depletion-mode transistor, while thin-film transistors 202 to 204 are enhancement-mode transistors.

[0126] The first terminal of the thin-film transistor 201 is electrically connected to a high power supply potential line.

[0127] The gate terminal of the thin-film transistor 202 is electrically connected to the first clock signal line, and the first terminal of the thin-film transistor 202 is electrically connected to the gate terminal and the second terminal of the thin-film transistor 201.

[0128] The gate terminal of the thin-film transistor 203 is electrically connected to the start-up pulse line, the first terminal of the thin-film transistor 203 is electrically connected to the second terminal of the thin-film transistor 202, and the second terminal of the thin-film transistor 203 is electrically connected to the low power supply potential line.

[0129] The gate terminal of the thin-film transistor 204 is electrically connected to the first clock signal line, and the first terminal of the thin-film transistor 204 is electrically connected to the second terminal of the thin-film transistor 202 and the first terminal of the thin-film transistor 203.

[0130] One terminal of capacitor 205 is electrically connected to the second terminal of thin-film transistor 204, and the other terminal of capacitor 205 is electrically connected to a low power supply potential line.

[0131] In short, Figure 4A The pulse output circuit 210 shown uses a thin-film transistor 202 instead of a thin-film transistor 202. Figure 3A The pulse output circuit 110 shown includes the thin-film transistor 103.

[0132] Figure 4B It is shown Figure 4A The timing diagram shows the operation of the circuit. Note that, for simplicity, Figure 4A Specific nodes of the circuit are represented by H to L, and the potential changes of each node are referenced to describe the reference. Figure 4B The timing diagram.

[0133] During period t11, the potential of the start-up pulse signal (SP) increases to a high level. Therefore, thin-film transistor 203 turns on. Consequently, node H is electrically connected to the low power supply potential line; that is, the potential of node H decreases to a low level.

[0134] During period t12, the potential of the start pulse signal (SP) remains high. That is, the potential of node H remains low.

[0135] During period t13, the potential of the first clock signal (CK1) increases to a high level. Therefore, thin-film transistors 202 and 204 are turned on. Furthermore, the potential of the start-up pulse signal (SP) remains high, keeping thin-film transistor 203 in the on state. Therefore, node I is electrically connected to the low power supply potential line; that is, the potential of node I decreases to a low level.

[0136] During period t14, the potential of the first clock signal (CK1) drops to a low level. Therefore, thin-film transistors 202 and 204 are turned off. This causes node I to enter a floating state, keeping its potential at a low level.

[0137] During period t15, the potential of the start pulse signal (SP) decreases to a low level. Therefore, thin-film transistor 203 is turned off. This causes node H to enter a floating state, keeping its potential at a low level. Furthermore, the potential of the second clock signal (CK2) increases to a high level. Therefore, thin-film transistors 212 and 214 are turned on. Therefore, nodes J and K are electrically connected to the high power supply potential line through thin-film transistor 211; that is, the potential of nodes J and K increases to a high level. Therefore, thin-film transistor 223 is turned on. Therefore, node L is electrically connected to the low power supply potential line; that is, the potential of node L decreases to a low level.

[0138] During period t16, the potential of the second clock signal (CK2) drops to a low level. Therefore, thin-film transistors 212 and 214 are turned off, causing nodes J and K to enter a floating state. Consequently, the potentials of nodes J and K remain high, while the potential of node L remains low.

[0139] During period t17, the potential of the first clock signal (CK1) increases to a high level. Therefore, thin-film transistors 202, 204, 222, and 224 are turned on. When thin-film transistors 202 and 204 are turned on, nodes H and I are electrically connected to the high power supply potential line through thin-film transistor 201; that is, the potential of nodes H and I increases to a high level. Therefore, thin-film transistor 213 is turned on. Therefore, node J is electrically connected to the low power supply potential line; that is, the potential of node J decreases to a low level.

[0140] During period t18, the potential of the first clock signal (CK1) drops to a low level. Therefore, thin-film transistors 202, 204, 222, and 224 are turned off. When thin-film transistors 202 and 204 are turned off, nodes H and I enter a floating state. Therefore, the potentials of nodes H and I remain at a high level.

[0141] During period t19, the potential of the second clock signal (CK2) increases to a high level. Therefore, thin-film transistors 212 and 214 are turned on. Furthermore, the potential of node I remains high, causing thin-film transistor 213 to remain on. Therefore, nodes J and K are electrically connected to the low power supply potential line; that is, the potential of node J remains low, and the potential of node K decreases to a low level. Therefore, thin-film transistor 223 is turned off. Therefore, node L is electrically connected to the low power supply potential line; that is, the potential of node L remains low. Furthermore, the potential of the startup pulse (SP) increases to a high level again. Note that the operation accompanying the increase of the startup pulse (SP) potential in the periods following this period is the same as the operation in the periods following period t11. Therefore, this description is referred to here.

[0142] During period t20, the potential of the second clock signal (CK2) drops to a low level. Therefore, thin-film transistors 212 and 214 are turned off. This causes nodes J and K to enter a floating state. Consequently, the potentials of nodes J and K remain at a low level.

[0143] For operations within the period after period t20, the above operations are repeated. Therefore, refer to this description here.

[0144] Note that capacitors (e.g., capacitors 205, 215, and 225) included in the pulse output circuits are configured to maintain the output signals of each pulse output circuit.

[0145] exist Figure 4AIn each of the multiple thin-film transistors included in the shift register shown, the channel formation region is formed using an oxide semiconductor. The oxide semiconductor is an oxide semiconductor with a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5 × 10⁻⁶. 19 (atoms / cm) 3 The oxide semiconductor, or smaller, acts as an insulator or near-insulator semiconductor when no electric field is present (a near-insulator semiconductor is essentially an insulator). Therefore, the off-state current of a thin-film transistor having a channel formation region formed using an oxide semiconductor can be reduced. Thus, charge leakage through the thin-film transistor can be suppressed.

[0146] For example, by using the channel formation region formed by oxide semiconductor in the thin-film transistor 204, the potential level changes during the period when node I is in a floating state (e.g., periods t11, t12, t14 to t16 and t18 to t20), such as potential drops during periods t11, t12, t19, t20, etc., can be suppressed. Therefore, shift register malfunctions can be prevented. Furthermore, the period during which node I is in a floating state can be longer. In other words, the number of times data is rewritten to capacitor 205 (also known as refresh) can be reduced.

[0147] Furthermore, the use of an oxide semiconductor-formed channel region in the thin-film transistor 202 can reduce the shoot-through current flowing from the high power supply line to the low power supply line during periods when the startup pulse (SP) is at a high level and the first clock signal (CK1) is at a low level (e.g., periods t11, t12, t14 to t16, and t18 to t20). Therefore, the power consumption of the shift register can be reduced.

[0148] While depletion-mode transistors are used in thin-film transistors electrically connected to the high power supply potential lines in the aforementioned shift registers, enhancement-mode transistors can alternatively be used in thin-film transistors. That is, Figure 2A and Figure 2B The inverter shown can be used in the pulse output circuit of this embodiment.

[0149] Although capacitors are included in the pulse output circuitry of each shift register, each shift register can operate without capacitors. That is, Figure 2C and Figure 2D The inverter shown can be used in the pulse output circuit of this embodiment.

[0150] This embodiment can be implemented by appropriately combining it with any other embodiment.

[0151] (Example 3)

[0152] In this embodiment, an example of a thin-film transistor included in the logic circuit of Embodiment 1 or Embodiment 2 is described.

[0153] Reference Figure 5A and Figure 5B as well as Figures 6A to 6E This describes one embodiment of a thin-film transistor and a method for manufacturing the thin-film transistor of this embodiment.

[0154] Figure 5A and Figure 5B Examples of planar and cross-sectional structures of thin-film transistors are shown. Figure 5A and Figure 5B The thin-film transistor 410 shown is one of the top-gate thin-film transistors.

[0155] Figure 5A This is a plan view of a thin-film transistor 410 with a top-gate structure, and Figure 5B It is along Figure 5A The cross-sectional view taken by line C1-C2 in the diagram.

[0156] The thin-film transistor 410 includes an insulating layer 407, an oxide semiconductor layer 412, a source or drain electrode layer 415a, a source or drain electrode layer 415b, a gate insulating layer 402, and a gate electrode layer 411 on a substrate 400 having an insulating surface. Wiring layers 414a and 414b are configured to contact and be electrically connected to the source or drain electrode layers 415a and 415b, respectively.

[0157] Although the description uses a single-gate thin-film transistor as thin-film transistor 410, a multi-gate thin-film transistor including multiple channel formation regions can be formed as needed.

[0158] The following reference Figures 6A to 6E This describes the process of fabricating a thin-film transistor 410 on a substrate 400.

[0159] There are no specific limitations on the substrate that can be used as the substrate 400 with an insulating surface, as long as it has at least heat resistance to withstand subsequent heat treatments. Glass substrates formed from barium borosilicate glass, aluminum borosilicate glass, etc., can be used.

[0160] When subsequent heat treatments are performed at high temperatures, a substrate with a strain point of 730°C or higher is preferably used as a glass substrate. Materials used as glass substrates include, for example, aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass. Note that by including barium oxide (BaO) and boron oxide (B2O3) such that the amount of BaO is greater than that of B2O3, the glass substrate is heat-resistant and has greater practical applications. Therefore, it is preferable to use a glass substrate containing BaO and B2O3 such that the amount of BaO is greater than that of B2O3.

[0161] Note that, instead of the glass substrate described above, a substrate formed of an insulator such as a ceramic substrate, quartz substrate, or sapphire substrate can be used as the substrate. Alternatively, crystallized glass can be used. And alternatively, a plastic substrate can be used appropriately.

[0162] First, an insulating layer 407, serving as a base film, is formed on a substrate 400 having an insulating surface. As the insulating layer 407 in contact with the oxide semiconductor layer, an oxide insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer is preferably used. Although plasma methods, sputtering methods, etc., can be used to form the insulating layer 407, sputtering is preferred to form the insulating layer 407 so that hydrogen is contained in the insulating layer 407 as little as possible.

[0163] In this embodiment, a silicon oxide layer serving as the insulating layer 407 is formed using a sputtering method. The substrate 400 is transferred to a processing chamber, and a sputtering gas, from which hydrogen and moisture have been removed and which contains high-purity oxygen, is introduced, thereby forming the silicon oxide layer 407 as the insulating layer on the substrate 400 using a silicon semiconductor target. The substrate 400 may be at room temperature or may be heated.

[0164] For example, an RF sputtering method is used to form a silicon oxide layer under the following conditions: a quartz (preferably synthetic quartz) is used as the target; the substrate temperature is 108°C; the distance between the substrate and the target (TS distance) is 60 mm; the pressure is 0.4 Pa; the power of the high-frequency power supply is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (the oxygen to argon flow ratio is 1:1 (each flow rate is 25 sccm)). The thickness of the silicon oxide layer is 100 nm. Note that instead of quartz (preferably synthetic quartz), a silicon target can be used as the target in forming the silicon oxide layer. Oxygen or a mixture of oxygen and argon is used as the sputtering gas.

[0165] In this case, the insulating layer 407 is preferably formed while removing any remaining moisture in the processing chamber. This serves to prevent hydrogen, hydroxyl groups, and moisture from being contained within the insulating layer 407.

[0166] To remove residual moisture in the processing chamber, an entrapment vacuum pump is preferably used. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferred. Furthermore, the evacuation unit can be a turbopump equipped with a cold trap. In a deposition chamber using a cryogenic pump for evacuation, hydrogen atoms, hydrogen-containing compounds, such as water (H₂O), are expelled, thereby reducing the impurity concentration of the insulating layer 407 formed in the deposition chamber.

[0167] Preferably, a high-purity gas from which impurities such as hydrogen, water, hydroxyl or hydrides have been removed to a concentration expressed in ppm or ppb is used as the sputtering gas used when forming the insulating layer 407.

[0168] Examples of sputtering methods include: RF sputtering methods, where a high-frequency power supply is used as the sputtering power source; DC sputtering methods, where a DC power supply is used; and pulsed DC sputtering methods, where a bias voltage is applied in a pulsed manner. RF sputtering methods are primarily used for forming insulating films, while DC sputtering methods are primarily used for forming metal films.

[0169] In addition, there are multi-source sputtering devices, which can accommodate multiple targets of different materials. With multi-source sputtering devices, films of different materials can be formed in a stacked manner within the same chamber, or multiple materials can be simultaneously deposited within the same chamber for film formation.

[0170] Additionally, there is a sputtering apparatus equipped with an internal magnet system for magnetron sputtering methods, and a sputtering apparatus for ECR sputtering methods in which plasma generated by employing microwaves is used without the use of glow discharge.

[0171] In addition, as a deposition method using sputtering, there are reactive sputtering methods, in which the target material and the sputtering gas components react chemically with each other during deposition to form their compound thin films, and there are bias sputtering methods, in which a voltage is also applied to the substrate during deposition.

[0172] Furthermore, the insulating layer 407 may have a layered structure, wherein, for example, nitride insulating layers such as silicon nitride layers, silicon oxynitride layers, aluminum nitride layers or aluminum oxynitride layers and oxide insulating layers are stacked from the substrate 400 side in this order.

[0173] For example, a sputtering gas from which hydrogen and moisture are removed and which contains high-purity nitrogen is introduced, and a silicon target is used, thereby forming a silicon nitride layer between the silicon oxide layer and the substrate. In this case, it is preferable to form a silicon nitride layer while removing any remaining moisture in the processing chamber, similar to the silicon oxide layer.

[0174] In the case of forming a silicon nitride layer, the substrate can be heated during film formation.

[0175] When the stack of silicon nitride and silicon oxide layers is configured as insulating layer 407, the silicon nitride and silicon oxide layers can be formed in the same processing chamber using a common silicon target. After first introducing a nitrogen-containing sputtering gas, the silicon nitride layer is formed using a silicon target installed in the processing chamber. Then, the sputtering gas is switched to an oxygen-containing sputtering gas, and the same silicon target is used to form the silicon oxide layer. Since the silicon nitride and silicon oxide layers can be formed sequentially without exposure to air, impurities such as hydrogen and moisture can be prevented from adsorbing onto the surface of the silicon nitride layer.

[0176] Then, an oxide semiconductor film is formed on the gate insulating layer 407 with a thickness of 2 nm to 200 nm (including both ends).

[0177] Furthermore, in order to contain as little hydrogen, hydroxyl, and moisture as possible in the oxide semiconductor layer, it is preferable to preheat the substrate 400 on which the insulating layer 407 is formed as a pretreatment for film formation in the preheating chamber of the sputtering apparatus, so as to eliminate and remove impurities such as hydrogen and moisture adsorbed onto the substrate 400. Note that a cryogenic pump is preferred as an exhaust unit provided in the preheating chamber. Note that this preheating treatment can be omitted. In addition, this preheating can be similarly performed on the substrate 400 on which the gate insulating layer 402 has not yet been formed, as well as on the substrate 400 on which layers up to the source or drain electrode layer 415a and the source or drain electrode layer 415b have been formed.

[0178] Note that before forming the oxide semiconductor layer using sputtering, dust adhering to the surface of the insulating layer 407 is preferably removed by reverse sputtering, in which argon gas is introduced and plasma is generated. Reverse sputtering refers to a method in which a high-frequency power supply is used to apply voltage to the substrate side in an argon atmosphere without applying voltage to the target side, thereby generating plasma to modify the substrate surface. Note that nitrogen, helium, oxygen, etc., can be used instead of an argon atmosphere.

[0179] The oxide semiconductor layer is formed using a sputtering method. The oxide semiconductor layer can be formed using In-Ga-Zn-O based oxide semiconductor layers, In-Sn-Zn-O based oxide semiconductor layers, In-Al-Zn-O based oxide semiconductor layers, Sn-Ga-Zn-O based oxide semiconductor layers, Al-Ga-Zn-O based oxide semiconductor layers, Sn-Al-Zn-O based oxide semiconductor layers, In-Zn-O based oxide semiconductor layers, Sn-Zn-O based oxide semiconductor layers, Al-Zn-O based oxide semiconductor layers, In-O based oxide semiconductor layers, Sn-O based oxide semiconductor layers, or Zn-O based oxide semiconductor layers. In this embodiment, the oxide semiconductor layer is formed using a sputtering method with the aid of an In-Ga-Zn-O based metal oxide target. Furthermore, the oxide semiconductor layer can be formed using a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically argon) and oxygen. When using a sputtering method, a target containing 2 wt% to 10 wt% (including both ends) of SiO2 can be used for film formation.

[0180] Preferably, a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups or hydrides have been removed to a concentration expressed in ppm or ppb is used as the sputtering gas for forming the oxide semiconductor layer.

[0181] As a target for forming an oxide semiconductor layer using a sputtering method, a metal oxide target containing zinc oxide as its main component can be used. Another example of a metal oxide target is a metal oxide target containing In, Ga, and Zn (in a composition ratio of In₂O₃:Ga₂O₃:ZnO = 1:1:1 [mol], In:Ga:Zn = 1:1:0.5 [atoms]). Alternatively, a metal oxide target containing In, Ga, and Zn can be used (in a composition ratio of In:Ga:Zn = 1:1:1 or 1:1:2 [atoms]). The volume of the portion excluding the area occupied by the spacers, etc., relative to the total volume of the formed metal oxide target (also known as the fill factor of the metal oxide target) is 90% to 100% (including both ends), preferably 95% to 99.9% (including both ends). A dense oxide semiconductor layer is formed by means of a metal oxide target with a high fill factor.

[0182] The substrate is held in a processing chamber under reduced pressure. Sputtering gas, from which hydrogen and moisture have been removed, is introduced into the processing chamber where residual moisture has been removed. An oxide semiconductor layer is formed on the substrate 400 using a metal oxide as a target. To remove residual moisture in the processing chamber, a gas-trap vacuum pump is preferably used. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump is preferably used. Furthermore, the exhaust unit can be a turbopump with a cold trap. In the deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, hydrogen-containing compounds such as water (H2O) (more preferably, compounds containing carbon atoms), etc., are exhausted, thereby reducing the impurity concentration of the oxide semiconductor layer formed in the deposition chamber. The substrate can be heated during the formation of the oxide semiconductor layer.

[0183] An example of deposition conditions is as follows: substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the DC power supply is 0.5 kW, and the atmosphere is an atmosphere containing oxygen and argon (oxygen to argon flow rate ratio of 15 sccm:30 sccm). A pulsed DC power supply is preferred because it reduces the amount of powdery material (also known as particles or dust) generated during film formation, and the film thickness can be uniform. The thickness of the oxide semiconductor layer is preferably from 5 nm to 30 nm (inclusive). Note that the appropriate thickness depends on the oxide semiconductor material used, and the thickness can be selected according to the material.

[0184] Then, in the first photolithography process, the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 412 (see...). Figure 6A The resist mask used to form the island-shaped oxide semiconductor layer 412 can be formed using an inkjet printing method. When the resist mask is formed using an inkjet printing method, no photomask is used; therefore, manufacturing costs can be reduced.

[0185] Note that the etching of the oxide semiconductor layer can be dry etching, wet etching, or both.

[0186] As the etching gas for dry etching, a chlorine-containing gas (chlorine-based gas, such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4) or carbon tetrachloride (CCl4)) is preferably used.

[0187] Alternatively, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3)) can be used; hydrogen bromide (HBr); oxygen (O2); any of these gases to which a rare gas such as helium (He) or argon (Ar) has been added; and so on.

[0188] As a dry etching method, parallel plate RIE (reactive ion etching) or ICP (inductively coupled plasma) etching can be used. In order to etch the film into the desired shape, the etching conditions (such as the electric charge applied to the coil-shaped electrode, the electric charge applied to the substrate-side electrode, and the temperature of the substrate-side electrode) are appropriately adjusted.

[0189] As an etchant for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid can be used. Alternatively, ITO07N (manufactured by KANTO CHEMICAL CO.,INC.) can be used.

[0190] In wet etching, the etchant is removed along with the etched material through cleaning. The waste liquid containing the etchant and the etched material can be purified, and the material can be reused. When materials such as indium contained in oxide semiconductor layers are collected from the waste liquid after etching and reused, resources can be used efficiently and costs can be reduced.

[0191] Etching conditions (such as etchant, etching time, and temperature) are appropriately adjusted according to the material so that the oxide semiconductor layer can be etched into the desired shape.

[0192] In this embodiment, a wet etching method is used, with a mixed solution of phosphoric acid, acetic acid and nitric acid as the etchant, to process the oxide semiconductor layer into an island-shaped oxide semiconductor layer 412.

[0193] In this embodiment, the oxide semiconductor layer 412 undergoes a first heat treatment. The temperature of the first heat treatment is higher than or equal to 400°C and lower than or equal to 750°C, preferably higher than or equal to 400°C and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer is heat-treated at 450°C for 1 hour in a nitrogen atmosphere, without being exposed to air, thus preventing water and hydrogen from entering the oxide semiconductor layer; thereby obtaining the oxide semiconductor layer. Through the first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer 412 can be performed.

[0194] Equipment used for heat treatment is not limited to electric furnaces, but can be any equipment equipped with heat conduction or thermal radiation from heating elements such as resistance heating elements to heat the object to be treated. For example, RTA (Rapid Thermal Annealing) equipment such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) equipment can be used. LRTA equipment is used to heat the object to be treated by radiation of light (electromagnetic waves) emitted from bulbs such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps. GRTA equipment is used for heat treatment using high-temperature gases. As the gas, inert gases such as nitrogen or rare gases such as argon are used, which hardly react with the object to be treated during heat treatment.

[0195] For example, as a first heat treatment, GRTA can be performed as follows: The substrate is transferred and placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then transferred and removed from the heated inert gas. GRTA achieves high-temperature heat treatment in a short time.

[0196] Note that in the first heat treatment, it is preferable that water, hydrogen, etc., are not contained in nitrogen or rare gases such as helium, neon, or argon. Alternatively, it is preferable that the nitrogen or rare gases such as helium, neon, or argon introduced into the equipment for heat treatment have a purity of 6N (99.9999%) or higher, or more preferably 7N (99.99999%) or higher (that is, the impurity concentration is set to 1 ppm or lower, preferably 0.1 ppm or lower).

[0197] Furthermore, the oxide semiconductor layer can be crystallized into a microcrystalline film or a polycrystalline film depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 412. For example, the oxide semiconductor layer can be crystallized to become a microcrystalline oxide semiconductor layer with a crystallinity of 90% or more, or 80% or more. Additionally, depending on the conditions of the first heat treatment and the material of the oxide semiconductor layer 412, the oxide semiconductor layer can become an amorphous oxide semiconductor layer without containing crystalline components. The oxide semiconductor layer can be an oxide semiconductor layer in which microcrystalline portions (particle size greater than or equal to 1 mm and less than or equal to 20 nm, typically greater than or equal to 2 nm and less than or equal to 4 nm) are mixed into the amorphous oxide semiconductor layer.

[0198] Alternatively, a first heat treatment may be performed on the oxide semiconductor layer that has not yet been processed into an island-shaped oxide semiconductor layer 412. In this case, after the first heat treatment, the substrate is removed from the heating device and a photolithography process is performed.

[0199] The heat treatment that has the effect of dehydration or dehydrogenation on the oxide semiconductor layer can be performed at any of the following times: after the formation of the oxide semiconductor layer; after the formation of the source electrode layer and the drain electrode layer on the oxide semiconductor layer 412; and after the formation of the gate insulating layer on the source electrode layer and the drain electrode layer.

[0200] Subsequently, a conductive layer is formed on the insulating layer 407 and the oxide semiconductor layer 412. The conductive layer can be formed by, for example, sputtering or vacuum evaporation. Materials for the conductive layer include elements selected from Al, Cr, Cu, Ta, Ti, Mo, or W, alloys containing any of the aforementioned elements, etc. Furthermore, one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium can be used. The conductive layer can have a single-layer structure or a layered structure of two or more layers. For example, a single-layer structure containing an aluminum layer of silicon, a two-layer structure in which a titanium layer is stacked on top of an aluminum layer, a three-layer structure in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order shown, etc. Alternatively, layers, alloy layers, or nitride layers composed of one or more elements selected from the following elements can be used: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

[0201] A second photolithography process is performed. A resist mask is formed on the conductive film, and selective etching is performed to form source or drain electrode layers 415a and 415b. The resist mask is then removed (see [link to photolithography process]). Figure 6B Note that the source and drain electrode layers preferably have a tapered shape, as this improves the coverage of the gate insulating layer stacked on top of them.

[0202] In this embodiment, the titanium layer is formed to a thickness of 150 nm using a sputtering method and is used for the source or drain electrode layer 415a and the source or drain electrode layer 415b.

[0203] Note that the materials and etching conditions are properly adjusted so that the oxide semiconductor layer 412 is not removed and the insulating layer 407 beneath the oxide semiconductor layer 412 is not exposed when etching the conductive layer.

[0204] In this embodiment, the Ti layer is used as a conductive film, the In-Ga-Zn-O based oxide semiconductor is used as the oxide semiconductor layer 412, and the ammonia-hydrogen peroxide solution (a mixture of ammonia, water and hydrogen peroxide solution) is used as an etchant.

[0205] Note that in the second photolithography process, only a portion of the oxide semiconductor layer 412 is etched, thereby forming an oxide semiconductor layer with grooves (recessed portions). The resist mask used to form the source or drain electrode layers 415a and 415b can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, manufacturing costs can be reduced.

[0206] Ultraviolet light, a KrF laser beam, or an ArF laser beam is used for exposure to form the resist mask during the second photolithography process. The channel length L of the thin-film transistor to be formed depends on the spacing between the bottoms of the source and drain electrode layers adjacent to each other on the oxide semiconductor layer 412. Note that when exposure is performed with a channel length L less than 25 nm, far-ultraviolet light with extremely short wavelengths of several nanometers to tens of nanometers is used for exposure to form the resist mask during the second photolithography process. Exposure using far-ultraviolet light produces high resolution and a large focal depth. Accordingly, the channel length L of the thin-film transistor to be formed can be set from 10 nm to 1000 nm (including both ends). Therefore, the operating speed of the circuit can be increased, and the off-state current can be significantly reduced, enabling low power consumption.

[0207] Subsequently, a gate insulating layer 402 is formed over the insulating layer 407, the oxide semiconductor layer 412, the source or drain electrode layer 415a, and the source or drain electrode layer 415b (see [link]). Figure 6C ).

[0208] A gate insulating layer 402 with a single-layer or multi-layer structure comprising a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, and an aluminum oxide layer can be formed using plasma CVD methods, sputtering methods, etc. Note that the gate insulating layer 402 is preferably formed by sputtering, such that the gate insulating layer 402 contains as little hydrogen as possible. When the silicon oxide layer is formed by sputtering, a silicon target or a quartz target is used as the target, and oxygen or a mixture of oxygen and argon is used as the sputtering gas.

[0209] The gate insulating layer 402 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked from the source or drain electrode layer 415a and the source or drain electrode layer 415b. For example, a silicon oxide layer (SiO2) with a thickness of 5 nm to 300 nm (including both ends) is formed as the first gate insulating layer. x (x>0)), and a silicon nitride (SiN) layer with a thickness of 50nm to 200nm (including both ends) is stacked on top of the first gate insulating layer as the second gate insulating layer. y(y>0)); Therefore, a gate insulating layer with a thickness of 100nm can be formed. In this embodiment, the silicon oxide layer is formed to a thickness of 100nm by RF sputtering under the following conditions: pressure of 0.4Pa; power of the high-frequency power supply of 1.5kW; and atmosphere containing oxygen and argon (oxygen to argon flow ratio of 1:1 (each flow rate of 25sccm)).

[0210] Then, a third photolithography process is performed. A resist mask is formed, and selective etching is performed to remove portions of the gate insulating layer 402, thereby forming openings 421a and 421b that respectively reach the source or drain electrode layers 415a and 415b (see [link to image]). Figure 6D ).

[0211] Then, after forming a conductive layer over the gate insulating layer 402 and over the openings 421a and 421b, the gate electrode layer 411 and wiring layers 414a and 414b are formed in the fourth photolithography process. Note that the resist mask can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, manufacturing costs can be reduced.

[0212] Furthermore, it is possible to form a gate electrode layer 411 and wiring layers 414a and 414b having a single-layer or layered structure using any of the metallic materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium and scandium, as well as an alloy material containing any of these materials as the main component.

[0213] As a two-layer structure for each of the gate electrode layer 411 and wiring layers 414a and 414b, for example, a two-layer structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer structure in which a molybdenum layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, are preferred. As a three-layer structure, a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are preferred. Note that the gate electrode layer can be formed using a light-transmitting conductive layer. A light-transmitting conductive oxide can be given as an example of a light-transmitting conductive layer.

[0214] In this embodiment, the titanium layer is formed to a thickness of 150 nm using a sputtering method and is used for the gate electrode layer 411 and wiring layers 414a and 414b.

[0215] Subsequently, a second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at 200°C to 400°C (including both ends), for example from 250°C to 350°C (including both ends)). In this embodiment, the second heat treatment is performed in a nitrogen atmosphere at 250°C for 1 hour. The second heat treatment may be performed after a protective layer or a planarized insulating layer is formed on the thin-film transistor 410.

[0216] Furthermore, heat treatment can be performed in air at 100°C to 200°C (inclusive) for 1 to 30 hours (inclusive). This heat treatment can be performed at a fixed heating temperature. Alternatively, the following temperature variation can be repeated multiple times: the heating temperature is increased from room temperature to 100°C to 200°C (inclusive), and then decreased to room temperature. Furthermore, this heat treatment can be performed under reduced pressure. Under reduced pressure, the heating time can be shortened.

[0217] Through the above steps, a thin-film transistor 410 can be formed, including an oxide semiconductor layer 412 in which the concentration of hydrogen, moisture, hydroxyl groups, or hydrides is reduced (see [link]). Figure 6E The thin-film transistor 410 can be used as a thin-film transistor included in the logic circuit of Embodiment 1 or Embodiment 2.

[0218] A protective insulating layer or a planarizing insulating layer for planarization may be disposed on the thin-film transistor 410. For example, a protective insulating layer having any single-layer or layered structure using a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, and an aluminum oxide layer may be formed.

[0219] Although not shown, heat-resistant organic materials such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used to form a planar insulating layer. Besides these organic materials, low-dielectric-constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc., can also be used. Note that a planar insulating layer can be formed by stacking multiple insulating layers formed using any of these materials.

[0220] Note that siloxane resins correspond to Si-O-Si bonded resins formed using siloxane materials as starting materials. Siloxane resins may include organic groups (e.g., alkyl or aryl) or fluorine groups as substituents. Furthermore, the organic groups may include fluorine groups.

[0221] There are no specific restrictions on the method for forming a planar insulating layer, and depending on the material, the following methods or approaches can be used: such as sputtering, SOG, spin coating, dip coating, spraying, or droplet emission methods (e.g., inkjet, screen printing, or offset printing), or tools such as doctor blades, roller coaters, curtain coaters, or blade coating machines.

[0222] By removing residual moisture from the reaction atmosphere as described above during the formation of the oxide semiconductor layer, the concentration of hydrogen and hydrides in the oxide semiconductor layer can be reduced. Consequently, the oxide semiconductor layer can be stabilized.

[0223] The logic circuits in Embodiments 1 and 2, which include the thin-film transistors described above, are capable of having stable electrical characteristics and high reliability.

[0224] This embodiment can be implemented by appropriately combining it with other embodiments.

[0225] (Example 4)

[0226] In this embodiment, another example of the thin-film transistors included in the logic circuit of Embodiment 1 or Embodiment 2 is described. The same parts as in Embodiment 3, parts having similar functions to those in Embodiment 3, and steps similar to those in Embodiment 3 can be handled as in Embodiment 3, and repeated descriptions are omitted. Furthermore, detailed descriptions of the same parts are also omitted.

[0227] Reference Figure 7A and Figure 7B as well as Figures 8A to 8E This describes one embodiment of a thin-film transistor and a method for manufacturing the thin-film transistor of this embodiment.

[0228] Figure 7A and Figure 7B Examples of planar and cross-sectional structures of thin-film transistors are shown. Figure 7A and Figure 7B The thin-film transistor 460 shown is one of the top-gate thin-film transistors.

[0229] Figure 7A This is a plan view of a thin-film transistor 460 with a top-gate structure, and Figure 7B It is along Figure 7A The cross-sectional view taken by line D1-D2 in the diagram.

[0230] The thin-film transistor 460 includes an insulating layer 457, source or drain electrode layers 465a (465a1 and 465a2), an oxide semiconductor layer 462, a source or drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, and a gate electrode layer 461 (461a and 461b) on a substrate 450 having an insulating surface. The source or drain electrode layers 465a (465a1 and 465a2) are electrically connected to the wiring layer 464 through the wiring layer 468. Although not shown, the source or drain electrode layer 465b is electrically connected to the wiring layer through an opening formed in the gate insulating layer 452.

[0231] The following reference Figures 8A to 8E This describes the process of fabricating a thin-film transistor 460 on a substrate 450.

[0232] First, an insulating layer 457, which serves as a base film, is formed on a substrate 450 having an insulating surface.

[0233] In this embodiment, a silicon oxide layer serving as the insulating layer 457 is formed using a sputtering method. The substrate 450 is transferred to a processing chamber, and a sputtering gas, from which hydrogen and moisture have been removed and which contains high-purity oxygen, is introduced, thereby forming the silicon oxide layer 457 as the insulating layer on the substrate 450 using a silicon target or quartz (preferably synthetic quartz). Oxygen or a mixture of oxygen and argon is used as the sputtering gas.

[0234] For example, a silicon oxide layer is formed using RF sputtering under the following conditions: the sputtering gas purity is 6N; quartz (preferably synthetic quartz) is used; the substrate temperature is 108°C; the distance between the substrate and the target (TS distance) is 60 mm; the pressure is 0.4 Pa; the power of the high-frequency power supply is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (oxygen to argon flow ratio of 1:1 (each flow rate 25 sccm)). The thickness of the silicon oxide layer is 100 nm. Note that instead of quartz (preferably synthetic quartz), a silicon target can be used as the target for forming the silicon oxide layer.

[0235] In this case, the insulating layer 457 is preferably formed while removing residual moisture from the processing chamber. This is to prevent hydrogen, hydroxyl groups, and moisture from being contained in the insulating layer 457. In a deposition chamber using a cryogenic pump for venting, hydrogen atoms, compounds containing hydrogen atoms, such as water (H2O), etc., are discharged, thereby reducing the impurity concentration of the insulating layer 457 formed in the deposition chamber.

[0236] Preferably, a high-purity gas from which impurities such as hydrogen, water, hydroxyl or hydrides have been removed to a concentration expressed in ppm or ppb is used as the sputtering gas used when forming the insulating layer 457.

[0237] Furthermore, the insulating layer 457 may have a layered structure, wherein, for example, nitride insulating layers such as silicon nitride layers, silicon oxynitride layers, aluminum nitride layers or aluminum oxynitride layers and oxide insulating layers are stacked from the substrate 450 side in this order.

[0238] For example, a sputtering gas from which hydrogen and moisture are removed and which contains high-purity nitrogen is introduced, and a silicon target is used, thereby forming a silicon nitride layer between the silicon oxide layer and the substrate. In this case, it is preferable to form a silicon nitride layer while removing residual moisture in the processing chamber, similar to the silicon oxide layer.

[0239] Subsequently, a conductive layer is formed over the insulating layer 457, and a first photolithography process is performed. A resist mask is formed over the conductive layer, and selective etching is performed to form source or drain electrode layers 465a1 and 465a2. The resist mask is then removed (see [link to photolithography]). Figure 8AIn cross-section, the source or drain electrode layers 465a1 and 465a2 appear to be separated; however, the source or drain electrode layers 465a1 and 465a2 are continuous layers. Note that the source and drain electrode layers preferably have a tapered shape, as this improves the coverage of the gate insulating layer stacked on top of them.

[0240] The materials used as source or drain electrode layers 465a1 and 465a2 include elements selected from Al, Cr, Cu, Ta, Ti, Mo, or W, alloys containing any of the aforementioned elements, etc. Additionally, one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium can be used. The conductive layer can have a single-layer structure or a layered structure of two or more layers. For example, a single-layer structure containing an aluminum layer of silicon, a two-layer structure in which a titanium layer is stacked on top of an aluminum layer, a three-layer structure in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order shown, etc. Alternatively, layers, alloy layers, or nitride layers composed of combinations of one or more elements selected from the following elements can be used: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

[0241] In this embodiment, the titanium layer is formed to a thickness of 150 nm using a sputtering method and is used for the source or drain electrode layers 465a1 and 465a2.

[0242] Then, an oxide semiconductor layer is formed on the gate insulating layer 457 and the source or drain electrode layers 465a1 and 465a2 with a thickness of 2 nm to 200 nm (including both ends).

[0243] Then, an oxide semiconductor layer is formed, and in the second photolithography process, the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 462 (see...). Figure 8B In this embodiment, an oxide semiconductor layer is formed using a sputtering method with the aid of an In-Ga-Zn-O based metal oxide target.

[0244] The substrate is held in a processing chamber under reduced pressure. Sputtering gas, from which hydrogen and moisture have been removed, is introduced into the processing chamber where residual moisture has been removed. An oxide semiconductor layer is deposited on the substrate 450 using a metal oxide as a target. To remove residual moisture in the processing chamber, a gas-trap vacuum pump is preferably used. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump is preferably used. Furthermore, the exhaust unit can be a turbopump with a cold trap. In the deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably, compounds containing carbon atoms), etc., are exhausted, thereby reducing the impurity concentration of the oxide semiconductor layer formed in the deposition chamber. The substrate can be heated during the formation of the oxide semiconductor layer.

[0245] Preferably, a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups or hydrides have been removed to a concentration expressed in ppm or ppb is used as the sputtering gas for forming the oxide semiconductor layer.

[0246] An example of deposition conditions is as follows: substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the DC power supply is 0.5 kW, and the atmosphere is an atmosphere containing oxygen and argon (oxygen to argon flow rate ratio of 15 sccm:30 sccm). A pulsed DC power supply is preferred because it reduces the amount of powdery material (also known as particles or dust) generated during film formation, and the film thickness can be uniform. The thickness of the oxide semiconductor layer is preferably from 5 nm to 30 nm (inclusive). Note that the appropriate thickness depends on the oxide semiconductor material used, and the thickness can be selected according to the material.

[0247] In this embodiment, a wet etching method is used, with a mixed solution of phosphoric acid, acetic acid and nitric acid as the etchant, to process the oxide semiconductor layer into an island-shaped oxide semiconductor layer 462.

[0248] Subsequently, the oxide semiconductor layer 462 undergoes a first heat treatment. The temperature of the first heat treatment is higher than or equal to 400°C and lower than or equal to 750°C, preferably higher than or equal to 400°C and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer is heat-treated at 450°C for 1 hour in a nitrogen atmosphere, without being exposed to air, thus preventing water and hydrogen from entering the oxide semiconductor layer; thereby obtaining the oxide semiconductor layer. Through the first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer 462 can be performed.

[0249] The equipment used for heat treatment is not limited to an electric furnace, but can be any device equipped with heat conduction or thermal radiation from a heating element such as a resistance heating element to heat the object to be treated. For example, RTA (Rapid Thermal Annealing) equipment such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) equipment can be used. For example, as a first heat treatment, GRTA can be performed as follows: The substrate is transferred and placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then transferred and removed from the heated inert gas. GRTA achieves high-temperature heat treatment in a short time.

[0250] Note that in the first heat treatment, it is preferable that water, hydrogen, etc., are not contained in nitrogen or rare gases such as helium, neon, or argon. Alternatively, it is preferable that the nitrogen or rare gases such as helium, neon, or argon introduced into the equipment for heat treatment have a purity of 6N (99.9999%) or higher, or more preferably 7N (99.99999%) or higher (that is, the impurity concentration is set to 1 ppm or lower, preferably 0.1 ppm or lower).

[0251] Furthermore, the oxide semiconductor layer can be crystallized into a microcrystalline layer or a polycrystalline layer depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer.

[0252] Alternatively, the first heat treatment of the oxide semiconductor layer can be performed on an oxide semiconductor layer that has not yet been processed into an island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device, and a photolithography process is performed.

[0253] The heat treatment that has the effect of dehydration or dehydrogenation on the oxide semiconductor layer can be performed at any of the following times: after the formation of the oxide semiconductor layer; after the formation of the source electrode layer and the drain electrode layer on the oxide semiconductor layer; and after the formation of the gate insulating layer on the source electrode layer and the drain electrode layer.

[0254] Subsequently, a conductive layer is formed over the insulating layer 457 and the oxide semiconductor layer 462, and a third photolithography process is performed. A resist mask is formed over the conductive layer, and selective etching is performed to form a source or drain electrode layer 465b and a wiring layer 468. Then, the resist mask is removed (see...). Figure 8C The source or drain electrode layer 465b and the wiring layer 468 can be formed using similar materials and steps as the source or drain electrode layers 465a1 and 465a2.

[0255] In this embodiment, a titanium layer of 150 nm thickness is formed by sputtering and is used for the source or drain electrode layer 465b and the wiring layer 468. In this embodiment, the same titanium layer is used for both source or drain electrode layers 465a1 and 465a2, as well as source or drain electrode layer 465b, such that the etch selectivity of source or drain electrode layers 465a1 and 465a2 is the same as or substantially the same as that of source or drain electrode layer 465b. Therefore, the wiring layer 468 is disposed over a portion of the source or drain electrode layer 465a2 that is not covered by the oxide semiconductor layer 462, to prevent source or drain electrode layers 465a1 and 465a2 from being etched when the source or drain electrode layer 465b is etched. In cases where a different material providing a high selectivity ratio between source or drain electrode layer 465b and source or drain electrode layers 465a1 and 465a2 is used in the etching step, the wiring layer 468 protecting the source or drain electrode layer 465a2 during etching is not necessarily provided.

[0256] Note that the materials and etching conditions were appropriately adjusted so that the oxide semiconductor layer 462 was not removed during the etching of the conductive layer.

[0257] In this embodiment, the Ti layer is used as a conductive film, the In-Ga-Zn-O based oxide semiconductor is used as oxide semiconductor layer 462, and the ammonia-hydrogen peroxide solution (a mixture of ammonia, water and hydrogen peroxide solution) is used as an etchant.

[0258] Note that during the third photolithography process, a portion of the oxide semiconductor layer 462 is etched, thereby forming an oxide semiconductor layer with grooves (recessed portions). The resist mask used to form the source or drain electrode layer 465b and the wiring layer 468 can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, manufacturing costs can be reduced.

[0259] Subsequently, a gate insulating layer 452 is formed on an insulating layer 457, an oxide semiconductor layer 462, source or drain electrode layers 465a1 and 465a2, a source or drain electrode layer 465b, and a wiring layer 468.

[0260] A gate insulating layer 452 with a single-layer or layered structure comprising a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, and an aluminum oxide layer can be formed using plasma CVD methods, sputtering methods, etc. Note that the gate insulating layer 452 is preferably formed by sputtering, such that the gate insulating layer 452 contains as little hydrogen as possible. When the silicon oxide film is formed by sputtering, a silicon target or a quartz target is used as the target, and a mixture of oxygen and argon gas is used as the sputtering target.

[0261] The gate insulating layer 452 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked from the source or drain electrode layers 465a1 and 465a2 and the source or drain electrode layer 465b. In this embodiment, the silicon oxide layer is formed to a thickness of 100 nm using an RF sputtering method under the following conditions: a pressure of 0.4 Pa; a high-frequency power supply of 1.5 kW; and an atmosphere containing oxygen and argon (oxygen to argon flow rate ratio of 1:1 (each flow rate of 25 sccm)).

[0262] Subsequently, a fourth photolithography process is performed. A resist mask is formed, and selective etching is performed to remove a portion of the gate insulating layer 452, thereby forming an opening 423 leading to the wiring layer 468 (see [link]). Figure 8D Although not shown, an opening leading to the source or drain electrode layer 465b may be formed when the opening 423 is formed. In this embodiment, the opening leading to the source or drain electrode layer 465b is formed after further stacking of interlayer insulating layers, and a wiring layer for electrical connection is formed in the opening.

[0263] Then, after forming a conductive layer on the gate insulating layer 452 and in the opening 423, the gate electrode layer 461 (461a and 461b) and the wiring layer 464 are formed in the fifth photolithography process. Note that the resist mask can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, the manufacturing cost can be reduced.

[0264] Furthermore, it is possible to form a gate electrode layer 461 (461a and 461b) and a wiring layer 464 having a single-layer or layered structure using any of the metallic materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium and scandium, as well as an alloy material containing any of these materials as the main components.

[0265] In this embodiment, the titanium layer is formed to a thickness of 150 nm using a sputtering method and is used for the gate electrode layer 461 (461a and 461b) and the wiring layer 464.

[0266] Subsequently, a second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at 200°C to 400°C (including both ends), for example from 250°C to 350°C (including both ends)). In this embodiment, the second heat treatment is performed in a nitrogen atmosphere at 250°C for 1 hour. The second heat treatment may be performed after a protective layer or a planarized insulating layer is formed on the thin-film transistor 460.

[0267] Furthermore, heat treatment can be performed in air at 100°C to 200°C (inclusive) for 1 to 30 hours (inclusive). This heat treatment can be performed at a fixed heating temperature. Alternatively, the following temperature variation can be repeated multiple times: the heating temperature is increased from room temperature to 100°C to 200°C (inclusive), and then decreased to room temperature. Furthermore, this heat treatment can be performed under reduced pressure. Under reduced pressure, the heating time can be shortened.

[0268] Through the above steps, a thin-film transistor 460 can be formed, including an oxide semiconductor layer 462 in which the concentration of hydrogen, moisture, hydroxyl groups, or hydrides is reduced (see above). Figure 8E ).

[0269] A protective insulating layer or a planarizing insulating layer for planarization may be disposed on the thin-film transistor 460. Although not shown, an opening leading to the source or drain electrode layer 465b may be formed. In this embodiment, an opening leading to the source or drain electrode layer 465b is formed in the gate insulating layer 452, the protective insulating layer, and the planarization layer, and a wiring layer for electrical connections to the source or drain electrode layer 465b is formed in the opening.

[0270] By removing residual moisture from the reaction atmosphere as described above during the formation of the oxide semiconductor film, the concentration of hydrogen and hydrides in the oxide semiconductor film can be reduced. Consequently, the oxide semiconductor film can be stabilized.

[0271] The logic circuits in Embodiments 1 and 2, which include the thin-film transistors described above, are capable of having stable electrical characteristics and high reliability.

[0272] This embodiment can be implemented by appropriately combining it with other embodiments.

[0273] (Example 5)

[0274] In this embodiment, another example of the thin-film transistor included in the logic circuit of Embodiment 1 or Embodiment 2 is described. The same parts as in Embodiment 3 or Embodiment 4, parts having similar functions to those in Embodiment 3 or Embodiment 4, and steps similar to those in Embodiment 3 or Embodiment 4 can be handled as in Embodiment 3 or Embodiment 4, and repeated descriptions are omitted. Furthermore, detailed descriptions of the same parts are also omitted.

[0275] Reference Figure 9A and Figure 9B The thin-film transistor of this embodiment will be described below.

[0276] Figure 9A and Figure 9B An example of a cross-sectional structure of a thin-film transistor is shown. Figure 9A and Figure 9B Thin-film transistors 425 and 426 are thin-film transistors in which the oxide semiconductor layer is sandwiched between the conductive layer and the gate electrode layer.

[0277] In addition, Figure 9A and Figure 9B In this process, a silicon substrate is used as the substrate, and thin-film transistors 425 and 426 are disposed on an insulating layer 422 formed on the silicon substrate 420.

[0278] Figure 9A In this process, a conductive layer 427 is formed on a silicon substrate 420 between insulating layers 422 and 407, such that it overlaps at least with the entire oxide semiconductor layer 412.

[0279] Notice, Figure 9B An example is shown in which the conductive layer between insulating layer 422 and insulating layer 407 is processed by etching, just like conductive layer 424, and overlaps with a portion of oxide semiconductor layer 412, which includes at least the channel formation region.

[0280] Conductive layers 427 and 424 can each be formed using a metallic material capable of withstanding the temperature of the heat treatment to be performed in a subsequent step: elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), alloy films containing any combination of these elements, nitrides containing any of the aforementioned elements as components, etc. Furthermore, conductive layers 427 and 424 can each have a monolayer or layered structure, and for example, a monolayer of tungsten or a stack of tungsten nitride and tungsten layers can be used.

[0281] The potentials of conductive layers 427 and 424 may be the same as or different from the potential of the gate electrode layer 411 of thin-film transistors 425 and 426. Conductive layers 427 and 424 can also be used as second gate electrode layers. The potentials of conductive layers 427 and 424 can be fixed potentials, such as GND or 0V.

[0282] The electrical characteristics of thin-film transistors 425 and 426 can be controlled by conductive layers 427 and 424.

[0283] This embodiment can be implemented by appropriately combining it with other embodiments.

[0284] (Example 6)

[0285] In this embodiment, an example of a thin-film transistor included in the logic circuit of Embodiment 1 or Embodiment 2 is described.

[0286] Reference Figures 10A to 10E This describes one embodiment of a thin-film transistor and a method for manufacturing the thin-film transistor of this embodiment.

[0287] Figure 10E An example of a cross-sectional structure of a thin-film transistor is shown. Figure 10E The thin-film transistor 390 shown is one of the bottom-gate thin-film transistors, and is also known as an inverted staggered thin-film transistor.

[0288] Although a single-gate thin-film transistor as thin-film transistor 390 is used for the description, a multi-gate thin-film transistor including multiple channel formation regions can be formed as needed.

[0289] The following reference Figures 10A to 10E This describes the process of fabricating a thin-film transistor 390 on a substrate 394.

[0290] First, after forming a conductive layer on a substrate 394 with an insulating surface, a gate electrode layer 391 is formed in a first photolithography process. The gate electrode layer preferably has a tapered shape because the coverage of the gate insulating layer stacked on it can be improved. Note that the resist mask can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, manufacturing costs can be reduced.

[0291] There are no specific limitations on the substrate that can be used as the substrate 394 with an insulating surface, as long as it has at least heat resistance to withstand subsequent heat treatment. Glass substrates formed from barium borosilicate glass, aluminum borosilicate glass, etc., can be used.

[0292] When subsequent heat treatments are performed at high temperatures, a substrate with a strain point of 730°C or higher is preferably used as a glass substrate. Materials used as glass substrates include, for example, aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass. Note that, generally, glass substrates containing a greater amount of barium oxide (BaO) than boron oxide (B₂O₃) are heat-resistant and have wider practical applications. Therefore, glass substrates containing a greater amount of BaO than B₂O₃ are preferred.

[0293] Note that, instead of the aforementioned glass substrate, a substrate formed from an insulator such as a ceramic substrate, quartz substrate, or sapphire substrate can be used as substrate 394. Alternatively, a crystallized glass substrate, etc., can be used. Also alternatively, a plastic substrate, etc., can be used appropriately.

[0294] An insulating layer, serving as a base layer, may be disposed between the substrate 394 and the gate electrode layer 391. The base layer has the function of preventing the diffusion of impurity elements from the substrate 394, and can be formed into a single-layer structure or a layered structure using any of the following: silicon nitride layer, silicon oxide layer, silicon oxynitride layer, and silicon oxynitride layer.

[0295] Furthermore, it is possible to form a gate electrode layer 391 with a single-layer or layered structure using any of the metallic materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, as well as an alloy material containing any of these materials as the main component.

[0296] As a two-layer structure for the gate electrode layer 391, for example, a two-layer structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer structure in which a molybdenum layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked, are preferred. As a three-layer structure, a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are preferred. Note that the gate electrode layer can be formed using a light-transmitting conductive layer. A light-transmitting conductive oxide can be given as an example of a light-transmitting conductive layer.

[0297] Then, a gate insulating layer 397 is formed on the gate electrode layer 391.

[0298] A gate insulating layer 397 with a single-layer or multi-layer structure comprising a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, and an aluminum oxide layer can be formed using plasma CVD methods, sputtering methods, etc. Note that the gate insulating layer 397 is preferably formed by sputtering, such that the gate insulating layer 397 contains as little hydrogen as possible. When the silicon oxide layer is formed by sputtering, a silicon target or a quartz target is used as the target, and oxygen or a mixture of oxygen and argon is used as the sputtering gas.

[0299] The gate insulating layer 397 may have a structure in which a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 391 side. For example, a silicon nitride layer (SiN) with a thickness of 50 nm to 200 nm (including both ends) as the first gate insulating layer is formed using a sputtering method. y (y>0)), and a silicon oxide layer (SiO) with a thickness of 5nm to 300nm (including both ends) is stacked on top of the first gate insulating layer as the second gate insulating layer. x (x>0)); Therefore, a gate insulating layer with a thickness of 100nm can be formed.

[0300] Furthermore, in order to minimize the presence of hydrogen, hydroxyl groups, and moisture in the gate insulating layer 397 and oxide semiconductor layer 393 to be formed later, it is preferable that the substrate 394 on which the gate electrode layer 391 is formed, or the substrate 394 on which the layer up to the gate insulating layer 397 is formed, is preheated in the preheating chamber of the sputtering apparatus as a pretreatment for film formation, so as to eliminate and remove impurities such as hydrogen and moisture adsorbed on the substrate 394. The temperature used for preheating is 100°C to 400°C (inclusive), preferably 150°C to 300°C (inclusive). Note that a cryogenic pump is preferred as an exhaust unit provided in the preheating chamber. Note that this preheating treatment can be omitted. In addition, this preheating can be similarly performed on the substrate 394 on which the oxide insulating layer 396 has not yet been formed, and on the substrate 394 on which the layer up to the source electrode layer 395a and the drain electrode layer 395b is formed.

[0301] Then, the oxide semiconductor layer 393 is formed on the gate insulating layer 397 with a thickness of 2 nm to 200 nm (including both ends) (see [link]). Figure 10A ).

[0302] Note that before the oxide semiconductor layer 393 is formed by sputtering, dust adhering to the surface of the gate insulating layer 397 is preferably removed by reverse sputtering, in which argon gas is introduced and plasma is generated. Reverse sputtering refers to a method in which voltage is applied to the substrate side in an argon atmosphere instead of the target side, using an RF power supply to modify the surface. Note that nitrogen, helium, oxygen, etc., can be used instead of argon atmosphere.

[0303] The oxide semiconductor layer 393 is formed using a sputtering method. The oxide semiconductor layer 393 can be formed using an In-Ga-Zn-O based oxide semiconductor layer, an In-Sn-Zn-O based oxide semiconductor layer, an In-Al-Zn-O based oxide semiconductor layer, a Sn-Ga-Zn-O based oxide semiconductor layer, an Al-Ga-Zn-O based oxide semiconductor layer, a Sn-Al-Zn-O based oxide semiconductor layer, an In-Zn-O based oxide semiconductor layer, a Sn-Zn-O based oxide semiconductor layer, an Al-Zn-O based oxide semiconductor layer, an In-O based oxide semiconductor layer, a Sn-O based oxide semiconductor layer, or a Zn-O based oxide semiconductor layer. In this embodiment, the oxide semiconductor layer 393 is formed using a sputtering method with the aid of an In-Ga-Zn-O based metal oxide target. Furthermore, the oxide semiconductor layer 393 can be formed using a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically argon) and oxygen. When using a sputtering method, a target containing 2 wt% to 10 wt% (including both ends) of SiO2 can be used for film formation.

[0304] As a target for forming the oxide semiconductor layer 393 using a sputtering method, a metal oxide target containing zinc oxide as its main component can be used. As another example of a metal oxide target, an oxide film containing In, Ga, and Zn can be used to form the target (in a composition ratio of In₂O₃:Ga₂O₃:ZnO = 1:1:1 [mol], In:Ga:Zn = 1:1:0.5 [atoms]). Alternatively, a metal oxide target containing In, Ga, and Zn can be used (in a composition ratio of In:Ga:Zn = 1:1:1 or 1:1:2 [atoms]). The fill rate of the metal oxide target is 90% to 100% (including both ends), preferably 95% to 99.9% (including both ends). A dense oxide semiconductor layer is formed by means of a metal oxide target with a high fill rate.

[0305] The substrate is held in a processing chamber under reduced pressure and heated to room temperature or below 400°C. Then, a sputtering gas, in which hydrogen and moisture have been removed, is introduced into the processing chamber to remove residual moisture, and an oxide semiconductor film 393 is formed on the substrate 394 using a metal oxide as a target. To remove residual moisture in the processing chamber, a gas-tight vacuum pump is preferably used. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferably used. Furthermore, the exhaust unit can be a turbopump with a cold trap. In the deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, hydrogen-containing compounds such as water (H2O) (more preferably, compounds containing carbon atoms), etc., are exhausted, thereby reducing the impurity concentration of the oxide semiconductor film formed in the deposition chamber. By performing deposition via sputtering while removing residual moisture in the processing chamber using a cryogenic pump, the substrate temperature when forming the oxide semiconductor layer 393 can be above or equal to room temperature and below 400°C.

[0306] An example of deposition conditions is as follows: the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the DC power supply is 0.5 kW, and the atmosphere is an oxygen atmosphere (oxygen flow rate of 100%). Preferably, a pulsed DC power supply is used because it reduces the powdery material generated during film formation, and the film thickness can be uniform. The thickness of the oxide semiconductor layer is preferably 5 nm to 30 nm (inclusive). Note that the appropriate thickness depends on the oxide semiconductor material used, and the thickness can be selected according to the material.

[0307] Examples of sputtering methods include: RF sputtering methods, where a high-frequency power supply is used as the sputtering power source; DC sputtering methods, where a DC power supply is used; and pulsed DC sputtering methods, where a bias voltage is applied in a pulsed manner. RF sputtering methods are primarily used for forming insulating films, while DC sputtering methods are primarily used for forming metal films.

[0308] In addition, there are multi-source sputtering devices, which can accommodate multiple targets of different materials. With multi-source sputtering devices, films of different materials can be formed in a stacked manner within the same chamber, or multiple materials can be simultaneously deposited within the same chamber to form films.

[0309] Additionally, there is a sputtering apparatus equipped with an internal magnet system for magnetron sputtering methods, and a sputtering apparatus for ECR sputtering methods in which plasma generated by employing microwaves is used without the use of glow discharge.

[0310] In addition, as a deposition method using sputtering, there are reactive sputtering methods, in which the target material and sputtering gas components chemically react with each other during deposition to form their compound thin film, and there are bias sputtering methods, in which a voltage is also applied to the substrate during deposition.

[0311] Then, in the second photolithography process, the oxide semiconductor layer 393 is processed into an island-shaped oxide semiconductor layer 399 (see...). Figure 10B The resist mask used to form the island oxide semiconductor layer 399 can be formed using an inkjet printing method. When the resist mask is formed using an inkjet printing method, no photomask is used; therefore, manufacturing costs can be reduced.

[0312] If a contact hole is formed in the gate insulating layer 397, this step can be performed when forming the oxide semiconductor layer 399.

[0313] Note that the etching of the oxide semiconductor layer 393 can be dry etching, wet etching, or both.

[0314] As the etching gas for dry etching, a chlorine-containing gas (chlorine-based gas, such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4) or carbon tetrachloride (CCl4)) is preferably used.

[0315] Alternatively, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3)) can be used; hydrogen bromide (HBr); oxygen (O2); any of these gases to which a rare gas such as helium (He) or argon (Ar) has been added; and so on.

[0316] As a dry etching method, parallel plate RIE (reactive ion etching) or ICP (inductively coupled plasma) etching can be used. In order to etch the layer into the desired shape, the etching conditions (such as the electric charge applied to the coil-shaped electrode, the electric charge applied to the substrate-side electrode, and the temperature of the substrate-side electrode) are appropriately adjusted.

[0317] As an etchant for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid can be used. Alternatively, ITO07N (manufactured by KANTO CHEMICAL CO.,INC.) can be used.

[0318] In wet etching, the etchant is removed along with the etched material through cleaning. The waste liquid containing the etchant and etched material can be purified, and the material can be reused. When materials such as indium contained in the oxide semiconductor layer are collected from the waste liquid after etching and reused, resources can be used efficiently and costs can be reduced.

[0319] Etching conditions (such as etchant, etching time, and temperature) are appropriately adjusted according to the material so that the oxide semiconductor layer can be etched into the desired shape.

[0320] Note that it is preferable to perform reverse sputtering before forming the conductive layer in the next step, so as to remove resist residues and the like from the surfaces of the oxide semiconductor layer 399 and the gate insulating layer 397.

[0321] Subsequently, a conductive layer is formed on the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive layer can be formed by sputtering or vacuum evaporation. Materials for the conductive layer include elements selected from Al, Cr, Cu, Ta, Ti, Mo, or W, alloy layers containing any combination of these elements, etc. Furthermore, one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium can be used. The metallic conductive layer can have a single-layer structure or a layered structure of two or more layers. For example, a single-layer structure containing an aluminum film of silicon, a two-layer structure in which a titanium layer is stacked on top of an aluminum layer, a three-layer structure in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order shown, etc. Alternatively, layers, alloy layers, or nitride layers containing one or more elements selected from the following elements can be used: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

[0322] The third photolithography process is performed. A resist mask is formed on the conductive layer, and selective etching is performed to form the source electrode layer 395a and the drain electrode layer 395b. Then, the resist mask is removed (see...). Figure 10C ).

[0323] Ultraviolet light, a KrF laser beam, or an ArF laser beam is used for exposure to form the resist mask during the third photolithography process. The channel length L of the thin-film transistor to be formed depends on the spacing between the bottoms of the source and drain electrode layers adjacent to each other on the oxide semiconductor layer 399. Note that when exposure is performed with a channel length L less than 25 nm, extremely short wavelength far-ultraviolet light, ranging from several nanometers to tens of nanometers, is used for exposure to form the resist mask during the third photolithography process. Exposure using far-ultraviolet light produces high resolution and a large depth of focus. Accordingly, the channel length L of the thin-film transistor to be formed can be set from 10 nm to 1000 nm (including both ends). Therefore, the operating speed of the circuit can be increased, and the off-state current is significantly reduced, enabling low power consumption.

[0324] Note that the materials and etching conditions were appropriately adjusted so that the oxide semiconductor layer 399 was not removed during the etching of the conductive layer.

[0325] In this embodiment, the Ti layer is used as a metal conductive film, the In-Ga-Zn-O based oxide semiconductor is used as the oxide semiconductor layer 399, and the ammonia-hydrogen peroxide solution (a mixture of ammonia, water and hydrogen peroxide solution) is used as an etchant.

[0326] Note that during the third photolithography process, only a portion of the oxide semiconductor layer 399 is etched, thereby forming an oxide semiconductor layer with grooves (recessed portions). The resist mask used to form the source electrode layer 395a and the drain electrode layer 395b can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, manufacturing costs can be reduced.

[0327] To reduce the number of photomasks and steps in photolithography, etching steps can be performed using a resist mask formed by a multi-tone mask, which serves as an exposure mask through which light passes, thus allowing for multiple intensities. Since the resist mask formed using a multi-tone mask has multiple thicknesses and can be further shaped by etching, it can be used to set different patterns in multiple etching steps. Therefore, a resist mask corresponding to at least two different patterns can be formed using a single multi-tone mask. Consequently, the number of exposure masks can be reduced, and the number of corresponding photolithography steps can also be reduced, thereby simplifying the process.

[0328] Water adsorbed on the surface of exposed portions of an oxide semiconductor layer can be removed by plasma treatment using gases such as N2O, N2, or Ar. Alternatively, plasma treatment can be performed using a mixture of oxygen and argon.

[0329] When plasma processing is performed, an oxide insulating layer 396 is formed without exposure to air as an oxide insulating layer that serves as a protective insulating film and is in contact with a portion of the oxide semiconductor layer 396 (see [link]). Figure 10D In this embodiment, an oxide insulating layer 396 is formed in the region where the oxide semiconductor layer 399 does not overlap with the source electrode layer 395a and the drain electrode layer 395b, and is in contact with the oxide semiconductor layer 399.

[0330] In this embodiment, a substrate 394 on which layers up to the island-shaped oxide semiconductor layer 399, the source electrode layer 395a, and the drain electrode layer 395b are formed is heated to room temperature or below 100°C, a sputtering gas containing high-purity hydrogen and having removed hydrogen and moisture is introduced, and a silicon target is used, thereby forming a defective silicon oxide layer as an oxide insulating layer 396.

[0331] For example, the silicon oxide layer is formed using a pulsed DC sputtering method, wherein the sputtering gas purity is 6N, a boron-doped silicon target (resistivity 0.01 Ω·cm) is used, the substrate-target distance (TS) is 89 mm, the pressure is 0.4 Pa, the DC power supply is 6 kW, and the atmosphere is an oxygen atmosphere (oxygen flow rate 100%). The thickness of the silicon oxide layer is 300 nm. Note that instead of a silicon target, quartz (preferably synthetic quartz) can be used as the target in forming the silicon oxide layer. As the sputtering gas, oxygen or a mixture of oxygen and argon is used.

[0332] In this case, the oxide insulating layer 396 is preferably formed while removing residual moisture from the processing chamber. This serves to prevent hydrogen, hydroxyl groups, and moisture from being contained within the oxide semiconductor layer 399 and the oxide insulating layer 396.

[0333] To remove residual moisture in the processing chamber, a gas trapping vacuum pump is preferably used. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump is preferred. Furthermore, the exhaust unit can be a turbopump with a cold trap. In a deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, compounds containing hydrogen atoms, such as water (H2O), are expelled, thereby reducing the impurity concentration of the oxide insulating layer 396 formed in the deposition chamber.

[0334] Note that as an oxide insulating layer 396, silicon oxynitride layers, aluminum oxide layers, aluminum oxynitride layers, etc., can be used to replace silicon oxide layers.

[0335] Furthermore, the heat treatment can be performed at temperatures ranging from 100°C to 400°C, while the oxide insulating layer 396 and the oxide semiconductor layer 399 are in contact with each other. Since the oxide insulating layer 396 in this embodiment has multiple defects, this heat treatment allows impurities such as hydrogen, moisture, hydroxyl groups, or hydrides contained in the oxide semiconductor layer 399 to diffuse into the oxide insulating layer 396, thereby further reducing the impurities in the oxide semiconductor layer 399.

[0336] Through the above steps, a thin-film transistor 390 can be formed, including an oxide semiconductor layer 392 in which the concentration of hydrogen, moisture, hydroxyl groups, or hydrides is reduced (see above). Figure 10E ).

[0337] By removing residual moisture from the reaction atmosphere as described above during the formation of the oxide semiconductor layer, the concentration of hydrogen and hydrides in the oxide semiconductor layer can be reduced. Consequently, the oxide semiconductor layer can be stabilized.

[0338] A protective insulating layer may be disposed on the oxide insulating layer. In this embodiment, the protective insulating layer 398 is formed on the oxide insulating layer 396. As the protective insulating layer 398, a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, an aluminum oxynitride layer, etc., are used.

[0339] A substrate 394, on which the layer up to the oxide insulating layer 396 is formed, is heated to a temperature of 100°C to 400°C. A sputtering gas containing high-purity nitrogen, having been dehydrogenated and moisture removed, is introduced, and a silicon semiconductor target is used, thereby forming a silicon nitride layer as a protective insulating layer 398. In this case, the protective insulating layer 398 is preferably formed while removing any remaining moisture in the processing chamber, similar to the oxide insulating layer 396.

[0340] When forming the protective insulating layer 398, the substrate 394 is heated to 100°C to 400°C during the formation of the protective insulating layer 398, thereby allowing hydrogen or moisture contained in the oxide semiconductor layer to diffuse into the oxide insulating layer. In this case, heat treatment is not necessarily performed after forming the oxide insulating layer 396.

[0341] When a silicon oxide layer is formed as an oxide insulating layer 396 and a silicon nitride layer is stacked thereon as a protective insulating layer 398, the silicon oxide layer and the silicon nitride layer can be formed in the same processing chamber using a common silicon target. After first introducing an oxygen-containing sputtering gas, the silicon oxide layer is formed using a silicon target installed in the processing chamber. Then, the sputtering gas is switched to a nitrogen-containing sputtering gas, and the same silicon target is used to form the silicon nitride layer. Since the silicon oxide layer and the silicon nitride layer can be formed sequentially without exposure to air, it is possible to prevent impurities such as hydrogen and moisture from adsorbing onto the surface of the silicon oxide layer. In this case, after forming the silicon oxide layer as an oxide insulating layer 396 and stacking the silicon nitride layer thereon as a protective insulating layer 398, it is preferable to perform a heat treatment (at a temperature of 100°C to 400°C) to diffuse hydrogen or moisture contained in the oxide semiconductor layer into the oxide insulating layer.

[0342] After the protective insulating layer is formed, a heat treatment can be performed in air at 100°C to 200°C (including both ends) for 1 to 30 hours (including both ends). This heat treatment can be performed at a fixed heating temperature. Alternatively, the following temperature variation can be repeated multiple times: the heating temperature is increased from room temperature to 100°C to 200°C (including both ends), and then decreased to room temperature. Furthermore, this heat treatment can be performed at a reduced pressure before forming the oxide insulating layer. Under reduced pressure, the heating time can be shortened. With this heat treatment, the thin-film transistor is constantly turned off. Therefore, the reliability of the thin-film transistor can be improved.

[0343] Residual moisture in the reaction atmosphere is removed during the formation of the oxide semiconductor layer, which includes the channel formation region above the gate insulating layer, thereby reducing the concentration of hydrogen and hydrides in the oxide semiconductor layer.

[0344] The above steps can be used to manufacture substrates (on which transistors are formed) for liquid crystal display panels, electroluminescent display panels, and display devices using electronic ink. Since these steps can be performed at temperatures of 400°C or lower, they can also be applied to manufacturing processes using glass substrates with a thickness of 1 mm or less and sides greater than 1 mm. Furthermore, because all of the above steps can be performed at processing temperatures of 400°C or lower, display panels can be manufactured without consuming a large amount of energy.

[0345] The logic circuits in Embodiments 1 and 2, which include the thin-film transistors described above, are capable of having stable electrical characteristics and high reliability.

[0346] This embodiment can be implemented by appropriately combining it with other embodiments.

[0347] (Example 7)

[0348] In this embodiment, an example of a thin-film transistor included in the logic circuit of Embodiment 1 or Embodiment 2 is described.

[0349] Reference Figures 11A to 11E This describes one embodiment of a thin-film transistor and a method for manufacturing the thin-film transistor of this embodiment.

[0350] Figures 11A to 11E An example of a cross-sectional structure of a thin-film transistor is shown. Figure 11D The thin-film transistor 310 shown is one of the bottom-gate thin-film transistors, and is also known as an anti-interlaced thin-film transistor.

[0351] Although the description uses a single-gate thin-film transistor as thin-film transistor 310, a multi-gate thin-film transistor including multiple channel formation regions can be formed as needed.

[0352] The following reference Figures 11A to 11E This describes the process of fabricating a thin-film transistor 310 on a substrate 300.

[0353] First, after forming a conductive layer on a substrate 300 with an insulating surface, a gate electrode layer 311 is formed in the first photolithography process. Note that the resist mask can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, manufacturing costs can be reduced.

[0354] There are no specific limitations on the substrate that can be used as the substrate 300 with an insulating surface, as long as it has sufficient heat resistance to withstand subsequent heat treatments. Glass substrates formed from barium borosilicate glass, aluminum borosilicate glass, etc., can be used.

[0355] When subsequent heat treatments are performed at high temperatures, a substrate with a strain point of 730°C or higher is preferably used as a glass substrate. Materials used as the glass substrate include, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass. Note that by containing a greater amount of barium oxide (BaO) than boron oxide (B₂O₃), the glass substrate is heat-resistant and has greater practical applications. Therefore, a glass substrate containing a greater amount of BaO than B₂O₃ is preferred.

[0356] Note that, instead of the glass substrate described above, a substrate formed of an insulator such as a ceramic substrate, quartz substrate, or sapphire substrate can be used as the substrate. Alternatively, a crystallized glass substrate, etc., can be used.

[0357] An insulating layer, used as a substrate layer, may be disposed between the substrate 300 and the gate electrode layer 311. The substrate layer has the function of preventing the diffusion of impurity elements from the substrate 300, and can be formed into a single-layer structure or a layered structure using any of the following: silicon nitride layer, silicon oxide layer, silicon oxynitride layer, and silicon oxynitride layer.

[0358] Furthermore, it is possible to form a gate electrode layer 311 with a single-layer or layered structure having any of the metallic materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium and scandium, as well as an alloy material containing any of these materials as the main component.

[0359] As a two-layer structure for the gate electrode layer 311, for example, a two-layer structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer structure in which a molybdenum layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked, are preferred. As a three-layer structure, a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are preferred.

[0360] Then, a gate insulating layer 302 is formed on the gate electrode layer 311.

[0361] A gate insulating layer 302 with a single-layer or layered structure using silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, and aluminum oxide layers can be formed using plasma CVD, sputtering, or similar methods. For example, a silicon oxynitride layer can be formed using SiH4, oxygen, and nitrogen as deposition gases via plasma CVD. For instance, the gate insulating layer 302 may have a thickness of 100 nm to 500 nm (including both ends), and in the case of a layered structure, a second gate insulating layer with a thickness of 5 nm to 300 nm (including both ends) may be stacked on top of a first gate insulating layer with a thickness of 50 nm to 200 nm (including both ends).

[0362] In this embodiment, a silicon oxynitride layer with a thickness of less than or equal to 100 nm is formed as a gate insulating layer 302 using a plasma CVD method.

[0363] Then, the oxide semiconductor layer 330 is formed on the gate insulating layer 302 with a thickness of 2nm to 200nm (including both ends).

[0364] Note that, prior to the formation of the oxide semiconductor layer 330 using a sputtering method, dust adhering to the surface of the gate insulating layer 302 is preferably removed by reverse sputtering, in which argon gas is introduced and plasma is generated. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc., can be used.

[0365] The oxide semiconductor layer 330 is formed using an In-Ga-Zn-O based oxide semiconductor layer, an In-Sn-Zn-O based oxide semiconductor layer, an In-Al-Zn-O based oxide semiconductor layer, a Sn-Ga-Zn-O based oxide semiconductor layer, an Al-Ga-Zn-O based oxide semiconductor layer, a Sn-Al-Zn-O based oxide semiconductor layer, an In-Zn-O based oxide semiconductor layer, a Sn-Zn-O based oxide semiconductor layer, an Al-Zn-O based oxide semiconductor layer, an In-O based oxide semiconductor layer, a Sn-O based oxide semiconductor layer, or a Zn-O based oxide semiconductor layer. In this embodiment, the oxide semiconductor layer 330 is formed using a sputtering method with the aid of an In-Ga-Zn-O based oxide semiconductor target. Figure 11A The cross-sectional view corresponds to this stage. Furthermore, an oxide semiconductor layer 330 can be formed using a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically argon) and oxygen. When using a sputtering method, a target containing 2 wt% to 10 wt% (including both ends) of SiO2 can be used for film formation.

[0366] As a target for forming the oxide semiconductor layer 330 using a sputtering method, a metal oxide target containing zinc oxide as its main component can be used. Another example of a metal oxide target is a metal oxide target containing In, Ga, and Zn (in a composition ratio of In₂O₃:Ga₂O₃:ZnO = 1:1:1 [mol], In:Ga:Zn = 1:1:0.5 [atoms]). Alternatively, a metal oxide target containing In, Ga, and Zn can be used (in a composition ratio of In:Ga:Zn = 1:1:1 or 1:1:2 [atoms]). The fill rate of the metal oxide target is 90% to 100% (including both ends), preferably 95% to 99.9% (including both ends). A dense oxide semiconductor layer is formed by means of a metal oxide target with a high fill rate.

[0367] Preferably, a high-purity gas from which impurities such as hydrogen, water, hydroxyl or hydrides have been removed to a concentration expressed in ppm or ppb is used as the sputtering gas for forming the oxide semiconductor layer 330.

[0368] The substrate is held in a processing chamber under reduced pressure, and the substrate temperature is set to 100°C to 600°C, preferably 200°C to 400°C. Film formation is performed simultaneously with heating the substrate, thereby reducing the concentration of impurities in the oxide semiconductor layer formed. Furthermore, damage caused by sputtering is reduced. Then, a sputtering gas, in which hydrogen and moisture have been removed, is introduced into the processing chamber where residual moisture has been removed, and the oxide semiconductor film 330 is formed on the substrate 300 using a metal oxide as a target. To remove residual moisture in the processing chamber, a gas-trapping vacuum pump is preferably used. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump is preferably used. Furthermore, the exhaust unit can be a turbopump with a cold trap. In the deposition chamber where a cryogenic pump is used for exhaust, hydrogen atoms, hydrogen-containing compounds such as water (H2O) (more preferably, compounds containing carbon atoms), etc., are exhausted, thereby reducing the impurity concentration of the oxide semiconductor layer formed in the deposition chamber.

[0369] An example of deposition conditions is as follows: the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the DC power supply is 0.5 kW, and the atmosphere is an oxygen atmosphere (oxygen flow rate of 100%). Preferably, a pulsed DC power supply is used because it reduces the powdery material generated during film formation, and the film thickness can be uniform. The thickness of the oxide semiconductor layer is preferably 5 nm to 30 nm (inclusive). Note that the appropriate thickness depends on the oxide semiconductor material used, and the thickness can be selected according to the material.

[0370] Then, in the second photolithography process, the oxide semiconductor layer 330 is processed into an island-shaped oxide semiconductor layer. The resist mask used to form the island-shaped oxide semiconductor layer can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, manufacturing costs can be reduced.

[0371] Subsequently, the oxide semiconductor layer undergoes a first heat treatment. This first heat treatment allows for dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment is higher than or equal to 400°C and lower than or equal to 750°C, preferably higher than or equal to 400°C and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is heat-treated at 450°C for 1 hour in a nitrogen atmosphere, without being exposed to air, thus preventing water and hydrogen from entering the oxide semiconductor layer; thus, oxide semiconductor layer 331 (see...) is obtained. Figure 11B ).

[0372] Equipment used for heat treatment is not limited to electric furnaces, but can be any equipment equipped with heat conduction or thermal radiation from heating elements such as resistance heating elements to heat the object to be treated. For example, RTA (Rapid Thermal Annealing) equipment such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) equipment can be used. LRTA equipment is used to heat the object to be treated by radiation of light (electromagnetic waves) emitted from bulbs such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps. GRTA equipment is used for heat treatment using high-temperature gases. The gas used is an inert gas such as nitrogen or a rare gas such as argon that will not react with the object to be treated.

[0373] For example, as a first heat treatment, GRTA can be performed as follows: The substrate is transferred and placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then transferred and removed from the heated inert gas. GRTA achieves high-temperature heat treatment in a short time.

[0374] Note that in the first heat treatment, it is preferable that water, hydrogen, etc., are not contained in nitrogen or rare gases such as helium, neon, or argon. Alternatively, it is preferable that the nitrogen or rare gases such as helium, neon, or argon introduced into the equipment for heat treatment have a purity of 6N (99.9999%) or higher, or more preferably 7N (99.99999%) or higher (that is, the impurity concentration is set to 1 ppm or lower, preferably 0.1 ppm or lower).

[0375] Furthermore, the oxide semiconductor layer can be crystallized into a microcrystalline layer or a polycrystalline layer depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer. For example, the oxide semiconductor layer can be crystallized to become a microcrystalline oxide semiconductor layer with a crystallinity of 90% or more, or 80% or more. Additionally, depending on the conditions of the first heat treatment and the material of the oxide semiconductor layer, the oxide semiconductor layer can become an amorphous oxide semiconductor layer without containing crystalline components. The oxide semiconductor layer can be an oxide semiconductor layer in which microcrystalline portions (particle size greater than or equal to 1 mm and less than or equal to 20 nm, typically greater than or equal to 2 nm and less than or equal to 4 nm) are mixed into an amorphous oxide semiconductor layer.

[0376] Alternatively, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor layer 330 that has not yet been processed into an island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device and a photolithography process is performed.

[0377] The heat treatment that has the effect of dehydration or dehydrogenation on the oxide semiconductor layer can be performed at any of the following times: after the formation of the oxide semiconductor layer; after the formation of the source electrode layer and the drain electrode layer on the oxide semiconductor layer; and after the formation of the protective insulating layer on the source electrode layer and the drain electrode layer.

[0378] When a contact hole is formed in the gate insulating layer 302, this step can be performed before or after the dehydration or dehydrogenation of the oxide semiconductor layer.

[0379] Note that etching of oxide semiconductor films is not limited to wet etching, but can also be dry etching.

[0380] Etching conditions (such as etchant, etching time, and temperature) are appropriately adjusted according to the material so that the material can be etched into the desired shape.

[0381] Subsequently, a conductive layer is formed on the gate insulating layer 302 and the oxide semiconductor layer 331. The conductive layer can be formed by sputtering or vacuum evaporation. Materials for the conductive layer include elements selected from Al, Cr, Cu, Ta, Ti, Mo, or W, alloy layers containing any combination of these elements, etc. Furthermore, one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium can be used. The conductive film can have a single-layer structure or a layered structure of two or more layers. For example, a single-layer structure containing an aluminum layer of silicon, a two-layer structure in which a titanium layer is stacked on top of an aluminum layer, a three-layer structure in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order shown, etc. Alternatively, layers, alloy layers, or nitride layers containing one or more elements selected from the following elements can be used: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

[0382] If heat treatment is performed after the formation of the conductive layer, it is preferable that the conductive layer has sufficient heat resistance to withstand the heat treatment.

[0383] The third photolithography process is performed. A resist mask is formed on the conductive layer, and selective etching is performed to form the source electrode layer 315a and the drain electrode layer 315b. Then, the resist mask is removed (see...). Figure 11C ).

[0384] Ultraviolet light, a KrF laser beam, or an ArF laser beam is used for exposure to form the resist mask during the third photolithography process. The channel length L of the thin-film transistor to be formed depends on the spacing between the bottoms of the source and drain electrode layers adjacent to each other on the oxide semiconductor layer 331. Note that when exposure is performed with a channel length L less than 25 nm, extremely short wavelength far-ultraviolet light, ranging from several nanometers to tens of nanometers, is used for exposure to form the resist mask during the third photolithography process. Exposure using far-ultraviolet light produces high resolution and a large depth of focus. Accordingly, the channel length L of the thin-film transistor to be formed can be set from 10 nm to 1000 nm (including both ends). Therefore, the operating speed of the circuit can be increased, and the off-state current is significantly reduced, enabling low power consumption.

[0385] Note that the materials and etching conditions were appropriately adjusted so that the oxide semiconductor layer 331 was not removed during the etching of the conductive layer.

[0386] In this embodiment, the Ti layer is used as a conductive layer, the In-Ga-Zn-O based oxide semiconductor is used as oxide semiconductor layer 331, and the ammonia peroxide solution (a mixture of ammonia, water and hydrogen peroxide solution) is used as an etchant.

[0387] Note that in the third photolithography process, only a portion of the oxide semiconductor layer 331 is etched, thereby forming an oxide semiconductor layer with grooves (recessed portions). The resist mask used to form the source electrode layer 315a and the drain electrode layer 315b can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, manufacturing costs can be reduced.

[0388] Furthermore, an oxide conductive layer can be formed between the oxide semiconductor layer and the source and drain electrode layers. The oxide conductive layer and the metal layer used to form the source and drain electrode layers can be formed sequentially. The oxide conductive layer can serve as both the source and drain regions.

[0389] When the oxide conductive layer is disposed as the source and drain regions between the oxide semiconductor layer and the source and drain electrode layers, the source and drain regions can have low resistance, and the transistor can operate at high speed.

[0390] To reduce the number of photomasks and steps in photolithography, etching steps can be performed using a resist mask formed by a multi-tone mask that serves as an exposure mask through which light passes, thus allowing for multiple intensities. Since the resist mask formed using the multi-tone mask has multiple thicknesses and can be further shaped by etching, it can be used to set different patterns in multiple etching steps. Therefore, a resist mask corresponding to at least two different patterns can be formed using a single multi-tone mask. Consequently, the number of exposure masks can be reduced, and the number of corresponding photolithography steps can also be reduced, thereby simplifying the process.

[0391] Subsequently, a plasma treatment using a gas such as N2O, N2, or Ar is performed. This plasma treatment removes water adsorbed onto the surface of exposed portions of the oxide semiconductor layer. Alternatively, the plasma treatment can be performed using a mixture of oxygen and argon.

[0392] After plasma treatment, an oxide insulating layer 316 is formed without exposure to air, serving as a protective insulating layer and contacting a portion of the oxide semiconductor layer.

[0393] The oxide insulating layer 316 can be appropriately formed to a thickness greater than or equal to 1 nm using methods such as sputtering, which prevents impurities such as water or hydrogen from entering the oxide insulating layer 316. When hydrogen is contained in the oxide insulating layer 316, hydrogen can either enter the oxide semiconductor layer or extract oxygen from the oxide semiconductor layer, thereby making the back channel of the oxide semiconductor layer n-type (with lower resistance) and thus forming a parasitic channel. Therefore, it is important to employ a formation method in which hydrogen is not used, so as to form an oxide insulating layer 316 containing as little hydrogen as possible.

[0394] In this embodiment, the silicon oxide layer is formed as an oxide insulating layer 316 with a thickness of 200 nm using a sputtering method. The substrate temperature during film formation can be higher than or equal to room temperature and lower than or equal to 300°C, and in this embodiment it is 100°C. The silicon oxide layer can be formed using a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas (typically argon) and oxygen. Furthermore, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used to form the silicon oxide layer using a sputtering method in an atmosphere containing oxygen and nitrogen. The target should not contain substances such as moisture, hydrogen ions, and OH-. - An inorganic insulating layer, typically a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer, is formed in an oxygen-deficient region and is therefore n-type, i.e. has low resistance, to form an oxide insulating layer 316 in contact with the oxide semiconductor layer. This layer is formed to prevent such impurities from entering from the outside.

[0395] In this case, the oxide insulating layer 316 is preferably formed while removing residual moisture from the processing chamber. This serves to prevent hydrogen, hydroxyl groups, and moisture from being contained within the oxide semiconductor layer 331 and the oxide insulating layer 316.

[0396] To remove residual moisture in the processing chamber, a gas trapping vacuum pump is preferably used. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferably used. Furthermore, the exhaust unit can be a turbopump with a cold trap. In a deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, compounds containing hydrogen atoms, such as water (H2O), are expelled, thereby reducing the impurity concentration of the oxide insulating layer 316 formed in the deposition chamber.

[0397] Preferably, a high-purity gas, with impurities such as hydrogen, water, hydroxyl groups, or hydrides removed to a concentration expressed in ppm or ppb, is used as the sputtering gas for forming the oxide insulating layer 316.

[0398] Subsequently, a second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at 200°C to 400°C (including both ends), for example from 250°C to 350°C (including both ends)). For example, the second heat treatment is performed in a nitrogen atmosphere at 250°C for 1 hour. During the second heat treatment, heat is applied while a portion of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 316.

[0399] Through the above steps, when the formed oxide semiconductor layer undergoes heat treatment for dehydration or dehydrogenation, the oxide semiconductor layer has a low resistance, i.e., it becomes n-type. Then, an oxide insulating layer is formed to contact the oxide semiconductor layer. Accordingly, a portion of the oxide semiconductor layer is selectively in an oxygen-excess state. Therefore, the channel formation region 313 overlapping with the gate electrode layer 311 becomes i-type. At this time, a high-resistance source region 314a, which has a carrier concentration at least higher than that of the channel formation region 313 and overlaps with the source electrode layer 315a, and a high-resistance drain region 314b, which has a carrier concentration at least higher than that of the channel formation region 313 and overlaps with the drain electrode layer 315b, are formed in a self-aligned manner. Through the above steps, a thin-film transistor 310 is formed (see...). Figure 11D ).

[0400] Furthermore, heat treatment can be performed in air at 100°C to 200°C (inclusive) for 1 to 30 hours (inclusive). In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment can be performed at a fixed heating temperature. Alternatively, the following temperature variation can be repeated multiple times: the heating temperature is increased from room temperature to 100°C to 200°C (inclusive), and then decreased to room temperature. Furthermore, this heat treatment can be performed at a reduced pressure before forming the oxide insulating layer. Under reduced pressure, the heating time can be shortened. Through this heat treatment, hydrogen is introduced from the oxide semiconductor layer into the oxide insulating layer; therefore, the thin-film transistor can be kept off. Thus, the reliability of the thin-film transistor can be improved. When a silicon oxide layer with multiple defects is used as the oxide insulating layer, this heat treatment allows impurities such as hydrogen, moisture, hydroxyl groups, or hydrides contained in the oxide semiconductor layer to diffuse into the oxide insulating layer, further reducing impurities in the oxide semiconductor layer.

[0401] Note that by forming a high-resistance drain region 314b (and a high-resistance source region 314a) in the oxide semiconductor layer overlapping with the drain electrode layer 315b (and the source electrode layer 315a), the reliability of the thin-film transistor can be improved. Specifically, by forming the high-resistance drain region 314b, a structure in which the conductivity of the drain electrode layer 315b, the high-resistance drain region 314b, and the channel formation region 313 gradually changes can be obtained. Therefore, in the thin-film transistor connected to a high power supply potential V, the reliability of the thin-film transistor can be improved. DD When the drain electrode layer 315b of the wiring is in operation, the high-resistance drain region acts as a buffer, and even if a high voltage is applied between the gate electrode layer 311 and the drain electrode layer 315b, no local high electric field is applied; therefore, the withstand voltage of the thin-film transistor can be increased.

[0402] Furthermore, when the thickness of the oxide semiconductor layer is 15 nm or less, a high-resistance source region or a high-resistance drain region is formed in the oxide semiconductor layer along the entire thickness direction. When the thickness of the oxide semiconductor layer is 30 nm or more and 50 nm or less, in a portion of the oxide semiconductor layer, i.e., in the region where the oxide semiconductor layer contacts and is near the source electrode layer or drain electrode layer, the resistance is reduced, and a high-resistance source region or a high-resistance drain region is formed, while enabling the region of the oxide semiconductor layer near the gate insulating film to be type I.

[0403] A protective insulating layer can also be formed on the oxide insulating layer 316. For example, the silicon nitride layer can be formed using an RF sputtering method. RF sputtering is preferred as a method for forming the protective insulating layer due to its high yield. The sputtering method is free of substances such as moisture, hydrogen ions, and OH groups. -An inorganic insulating layer is formed to remove impurities such as silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride, and to prevent them from entering from the outside. For example, a silicon nitride layer, aluminum nitride layer, silicon oxynitride layer, aluminum oxynitride layer, etc., are used. In this embodiment, a silicon nitride layer is used to form the protective insulating layer 303 (see [link to documentation]). Figure 11E ).

[0404] In this embodiment, a substrate 300 on which the layer up to the oxide insulating layer 316 is formed is heated to a temperature of 100°C to 400°C, a sputtering gas containing high-purity nitrogen and free of hydrogen and moisture is introduced, and a silicon target is used, thereby forming a silicon nitride layer as a protective insulating layer 303. In this case, it is preferable to form the protective insulating layer 303 while removing any remaining moisture in the processing chamber, similar to the oxide insulating layer 316.

[0405] Although not shown, a planarization insulating layer for planarization may be disposed on the protective insulating layer 303.

[0406] The logic circuits in Embodiments 1 and 2, which include the thin-film transistors described above, are capable of having stable electrical characteristics and high reliability.

[0407] This embodiment can be implemented by appropriately combining it with other embodiments.

[0408] (Example 8)

[0409] In this embodiment, an example of a thin-film transistor included in the logic circuit of Embodiment 1 or Embodiment 2 is described.

[0410] Reference Figures 12A to 12D This describes one embodiment of a thin-film transistor and a method for manufacturing the thin-film transistor of this embodiment.

[0411] Figure 12D An example of a cross-sectional structure of a thin-film transistor is shown. Figure 12D The thin-film transistor 360 shown is one of the bottom-gate thin-film transistors, also known as a channel-protected thin-film transistor (also known as a channel-blocking thin-film transistor) and an anti-interlaced thin-film transistor.

[0412] Although a single-gate thin-film transistor as thin-film transistor 360 is used for the description, a multi-gate thin-film transistor including multiple channel formation regions can be formed as needed.

[0413] The following reference Figures 12A to 12D This describes the process of fabricating a thin-film transistor 360 on a substrate 320.

[0414] First, after forming a conductive layer on a substrate 320 with an insulating surface, a gate electrode layer 361 is formed in the first photolithography process. Note that the resist mask can be formed using an inkjet method. When the resist mask is formed using an inkjet method, no photomask is used; therefore, manufacturing costs can be reduced.

[0415] Furthermore, it is possible to form a gate electrode layer 361 with a single-layer or layered structure using any of the metallic materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, as well as an alloy material containing any of these materials as the main component.

[0416] Then, a gate insulating layer 322 is formed on the gate electrode layer 361.

[0417] In this embodiment, a silicon oxynitride layer with a thickness of less than or equal to 100 nm is formed as a gate insulating layer 322 using a plasma CVD method.

[0418] Then, an oxide semiconductor layer is formed on the gate insulating layer 322 at a size of 2 nm to 200 nm (including both ends), and is processed into an island-shaped oxide semiconductor layer during a second photolithography process. In this embodiment, the oxide semiconductor layer is formed using a sputtering method with the aid of an In-Ga-Zn-O based metal oxide target.

[0419] In this case, the oxide semiconductor layer is preferably formed while removing any remaining moisture from the processing chamber. This is to prevent hydrogen, hydroxyl groups, and moisture from being contained within the oxide semiconductor layer.

[0420] To remove residual moisture in the processing chamber, a gas trap vacuum pump is preferably used. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferred. Furthermore, the exhaust unit can be a turbopump with a cold trap. In a deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, hydrogen-containing compounds, such as water (H₂O), are expelled, thereby reducing the impurity concentration of the oxide semiconductor layer formed in the deposition chamber.

[0421] Preferably, a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups or hydrides have been removed to a concentration expressed in ppm or ppb is used as the sputtering gas for forming the oxide semiconductor layer.

[0422] Subsequently, the oxide semiconductor layer undergoes dehydration or dehydrogenation. The temperature of the first heat treatment for dehydration or dehydrogenation is higher than or equal to 400°C and lower than or equal to 750°C, preferably higher than or equal to 400°C and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer is heat-treated at 450°C for 1 hour in a nitrogen atmosphere, without being exposed to air, thus preventing water and hydrogen from entering the oxide semiconductor layer; thus, oxide semiconductor layer 332 is obtained (see...). Figure 12A ).

[0423] Subsequently, a plasma treatment using a gas such as N2O, N2, or Ar is performed. This plasma treatment removes water adsorbed onto the surface of exposed portions of the oxide semiconductor layer. Alternatively, the plasma treatment can be performed using a mixture of oxygen and argon.

[0424] Subsequently, after forming an oxide insulating layer over the gate insulating layer 322 and the oxide semiconductor layer 332, a resist mask is formed during the third photolithography process. Selective etching is performed to form the oxide insulating layer 366. Then, the resist mask is removed.

[0425] In this embodiment, the silicon oxide layer is formed as an oxide insulating layer 366 with a thickness of 200 nm using a sputtering method. The substrate temperature during film formation can be higher than or equal to room temperature and lower than or equal to 300°C, and in this embodiment it is 100°C. The silicon oxide layer can be formed using a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas (typically argon) and oxygen. Furthermore, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used to form the silicon oxide layer using a sputtering method in an atmosphere containing oxygen and nitrogen.

[0426] In this case, the oxide insulating layer 366 is preferably formed while removing residual moisture from the processing chamber. This serves to prevent hydrogen, hydroxyl groups, and moisture from being contained within the oxide semiconductor layer 332 and the oxide insulating layer 366.

[0427] To remove residual moisture in the processing chamber, a gas trapping vacuum pump is preferably used. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferred. Furthermore, the exhaust unit can be a turbopump with a cold trap. In a deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, compounds containing hydrogen atoms, such as water (H2O), are expelled, thereby reducing the impurity concentration of the oxide insulating layer 366 formed in the deposition chamber.

[0428] Preferably, a high-purity gas, with impurities such as hydrogen, water, hydroxyl groups, or hydrides removed to a concentration expressed in ppm or ppb, is used as the sputtering gas for forming the oxide insulating layer 366.

[0429] Subsequently, a second heat treatment can be performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at 200°C to 400°C (including both ends), for example from 250°C to 350°C (including both ends)). For example, the second heat treatment is performed in a nitrogen atmosphere at 250°C for 1 hour. During the second heat treatment, heat is applied while a portion of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 366.

[0430] In this embodiment, heat treatment is also performed on the oxide semiconductor layer 332, on which the oxide insulating layer 366 is disposed and thus exposes a portion of the oxide semiconductor layer 332, in a nitrogen atmosphere, an inert gas atmosphere, or under reduced pressure. By performing heat treatment in a nitrogen atmosphere, an inert gas atmosphere, or under reduced pressure, the resistance of the region of the oxide semiconductor layer 332 that is not covered by the oxide insulating layer 366 and is thus exposed can be increased. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

[0431] By heat-treating the oxide semiconductor layer 332, on which the oxide insulating layer 366 is disposed, in a nitrogen atmosphere, the resistance of the exposed area of ​​the oxide semiconductor layer 332 is reduced. Therefore, regions with different resistances are formed (in...) Figure 12B The oxide semiconductor layer 362 (represented by shaded and white areas) is shown in the image.

[0432] Subsequently, after forming conductive layers over the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366, a resist mask is formed during the fourth photolithography process. Selective etching is performed to form the source electrode layer 365a and the drain electrode layer 365b. Then, the resist mask is removed (see...). Figure 12C ).

[0433] The materials used for the source electrode layer 365a and the drain electrode layer 365b include elements selected from Al, Cr, Cu, Ta, Ti, Mo, or W, alloy layers containing any combination of these elements, and so on. The metallic conductive layer may have a single-layer structure or a layered structure of two or more layers.

[0434] Through the above steps, the oxide semiconductor layer becomes oxygen-deficient, and correspondingly, when the formed oxide semiconductor layer undergoes heat treatment for dehydration or dehydrogenation, its resistance is reduced, i.e., it becomes n-type. Then, an oxide insulating layer is formed to contact the oxide semiconductor layer. Accordingly, a portion of the oxide semiconductor layer is selectively in an oxygen-excess state. Therefore, the channel formation region 363 overlapping with the gate electrode layer 361 becomes i-type. At this time, a high-resistance source region 364a, having a carrier concentration at least higher than that of the channel formation region 363 and overlapping with the source electrode layer 365a, and a high-resistance drain region 364b, having a carrier concentration at least higher than that of the channel formation region 363 and overlapping with the drain electrode layer 365b, are formed in a self-adjusting manner. Through the above steps, a thin-film transistor 360 is formed.

[0435] Furthermore, heat treatment can be performed in air at 100°C to 200°C (including both ends) for 1 to 30 hours (including both ends). In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment can be performed at a fixed heating temperature. Alternatively, the following temperature variation can be repeated multiple times: the heating temperature is increased from room temperature to a temperature of 100°C to 200°C (including both ends), and then decreased to room temperature. Furthermore, this heat treatment can be performed at a reduced pressure before forming the oxide insulating layer. Under reduced pressure, the heating time can be shortened. Through this heat treatment, hydrogen is introduced from the oxide semiconductor layer into the oxide insulating layer; therefore, the thin-film transistor can be kept off. Thus, the reliability of the thin-film transistor can be improved.

[0436] Note that by forming a high-resistance drain region 364b (and a high-resistance source region 364a) in the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a), the reliability of the thin-film transistor can be improved. Specifically, by forming the high-resistance drain region 364b, a structure in which the conductivity of the drain electrode layer 365b, the high-resistance drain region 364b, and the channel formation region 363 gradually changes can be obtained. Therefore, in the thin-film transistor connected to a high power supply potential V, the reliability of the thin-film transistor can be improved. DD When the drain electrode layer 365b of the wiring is in operation, the high-resistance drain region acts as a buffer, and even if a high voltage is applied between the gate electrode layer 361 and the drain electrode layer 365b, no local high electric field is applied; therefore, the withstand voltage of the thin-film transistor can be increased.

[0437] A protective insulating layer 323 is formed over the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride layer (see [link to documentation]). Figure 12D ).

[0438] Note that the oxide insulating layer may also be formed on the source electrode layer 365a, the drain electrode layer 365b and the oxide insulating layer 366, and the protective insulating layer 323 may be stacked on the oxide insulating layer.

[0439] The logic circuits in Embodiments 1 and 2, which include the thin-film transistors described above, are capable of having stable electrical characteristics and high reliability.

[0440] This embodiment can be implemented by appropriately combining it with other embodiments.

[0441] (Example 9)

[0442] In this embodiment, an example of a thin-film transistor included in the logic circuit of Embodiment 1 or Embodiment 2 is described.

[0443] Reference Figures 13A to 13D This describes one embodiment of a thin-film transistor and a method for manufacturing the thin-film transistor of this embodiment.

[0444] Although used as Figure 13D The thin-film transistor 350 is described as a single-gate thin-film transistor, but a multi-gate thin-film transistor including multiple channel formation regions can be formed as needed.

[0445] The following reference Figures 13A to 13D This describes the process of fabricating a thin-film transistor 350 on a substrate 340.

[0446] First, after forming a conductive layer on a substrate 340 having an insulating surface, a gate electrode layer 351 is formed in a first photolithography process. In this embodiment, a tungsten layer is formed as the gate electrode layer 351 with a thickness of 150 nm.

[0447] Then, a gate insulating layer 342 is formed on the gate electrode layer 351. In this embodiment, a silicon oxynitride layer is formed as the gate insulating layer 342 using a plasma CVD method to a thickness of less than or equal to 100 nm.

[0448] Subsequently, after forming a conductive layer over the gate insulating layer 342, a resist mask is formed during the second photolithography process. Selective etching is performed to form the source electrode layer 355a and the drain electrode layer 355b. Then, the resist mask is removed (see...). Figure 13A ).

[0449] Then, an oxide semiconductor layer 345 is formed (see Figure 13B In this embodiment, an oxide semiconductor layer 345 is formed using a sputtering method with the aid of an In-Ga-Zn-O based metal oxide target. During a third photolithography process, the oxide semiconductor layer 345 is processed into an island-shaped oxide semiconductor layer.

[0450] In this case, the oxide semiconductor layer 345 is preferably formed while removing any remaining moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor layer 345.

[0451] To remove residual moisture in the processing chamber, a gas trap vacuum pump is preferably used. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferably used. Furthermore, the exhaust unit can be a turbopump with a cold trap. In a deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, compounds containing hydrogen atoms, such as water (H2O), are expelled, thereby reducing the impurity concentration of the oxide semiconductor layer 345 formed in the deposition chamber.

[0452] Preferably, a high-purity gas from which impurities such as hydrogen, water, hydroxyl or hydrides have been removed to a concentration expressed in ppm or ppb is used as the sputtering gas for forming the oxide semiconductor layer 345.

[0453] Subsequently, the oxide semiconductor layer undergoes dehydration or dehydrogenation. The temperature of the first heat treatment for dehydration or dehydrogenation is higher than or equal to 400°C and lower than or equal to 750°C, preferably higher than or equal to 400°C and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer is heat-treated at 450°C for 1 hour in a nitrogen atmosphere, without being exposed to air, thus preventing water and hydrogen from entering the oxide semiconductor layer; thereby obtaining oxide semiconductor layer 346 (see Figure 13C ).

[0454] As a first heat treatment, GRTA can be performed as follows: The substrate is transferred and placed in an inert gas heated to a high temperature of 650°C to 700°C for several minutes, then transferred and removed from the heated inert gas. GRTA achieves high-temperature heat treatment in a short time.

[0455] An oxide insulating layer 356 is formed to serve as a protective insulating layer and to contact the oxide semiconductor layer 346.

[0456] The oxide insulating layer 356 can be appropriately formed to a thickness greater than or equal to 1 nm using methods such as sputtering, which prevents impurities such as water or hydrogen from entering the oxide insulating layer 356. When hydrogen is contained in the oxide insulating layer 356, hydrogen can either enter the oxide semiconductor layer or extract oxygen from the oxide semiconductor layer, thereby making the back channel of the oxide semiconductor layer have a lower resistance (becoming n-type), and thus a parasitic channel can be formed. Therefore, it is important to employ a formation method in which hydrogen is not used, so as to form an oxide insulating layer 356 containing as little hydrogen as possible.

[0457] In this embodiment, the silicon oxide layer is formed as an oxide insulating layer 356 with a thickness of 200 nm using a sputtering method. The substrate temperature during film formation can be higher than or equal to room temperature and lower than or equal to 300°C, and in this embodiment it is 100°C. The silicon oxide layer can be formed using a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas (typically argon) and oxygen. Furthermore, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used to form the silicon oxide layer using a sputtering method in an atmosphere containing oxygen and nitrogen. The target should not contain substances such as moisture, hydrogen ions, and OH-. - An inorganic insulating layer, typically a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer, is formed in a region that is in an oxygen-deficient state and therefore has low resistance, and is formed as an oxide insulating layer 356 in contact with the oxide semiconductor layer.

[0458] In this case, the oxide insulating layer 356 is preferably formed while removing residual moisture from the processing chamber. This serves to prevent hydrogen, hydroxyl groups, and moisture from being contained within the oxide semiconductor layer 346 and the oxide insulating layer 356.

[0459] To remove residual moisture in the processing chamber, a gas trapping vacuum pump is preferably used. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferably used. Furthermore, the exhaust unit can be a turbopump with a cold trap. In a deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, compounds containing hydrogen atoms, such as water (H2O), are expelled, thereby reducing the impurity concentration of the oxide insulating layer 356 formed in the deposition chamber.

[0460] Preferably, a high-purity gas, with impurities such as hydrogen, water, hydroxyl groups, or hydrides removed to a concentration expressed in ppm or ppb, is used as the sputtering gas for forming the oxide insulating layer 356.

[0461] Subsequently, a second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at 200°C to 400°C (including both ends), for example from 250°C to 350°C (including both ends)). For example, the second heat treatment is performed in a nitrogen atmosphere at 250°C for 1 hour. During the second heat treatment, heat is applied while a portion of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 356.

[0462] Through the above steps, the oxide semiconductor layer, which is in an oxygen-deficient state and therefore has low resistance, is brought into an oxygen-excess state through dehydration or dehydrogenation. Thus, an i-type oxide semiconductor layer 352 with high resistance is formed. Through the above steps, a thin-film transistor 350 is formed.

[0463] Furthermore, heat treatment can be performed in air at 100°C to 200°C (inclusive) for 1 to 30 hours (inclusive). In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment can be performed at a fixed heating temperature. Alternatively, the following temperature variation can be repeated multiple times: the heating temperature is increased from room temperature to a temperature of 100°C to 200°C (inclusive), and then decreased to room temperature. Furthermore, this heat treatment can be performed under reduced pressure. Under reduced pressure, the heating time can be shortened. Through this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; therefore, the thin-film transistor can be kept off. Thus, the reliability of the semiconductor device can be improved.

[0464] The protective insulating layer 343 may also be formed on the oxide insulating layer 356. For example, the silicon nitride layer is formed using an RF sputtering method. In this embodiment, the protective insulating layer 343 is formed using a silicon nitride layer as the protective insulating layer (see [link]). Figure 13D ).

[0465] Note that the planarization insulation layer for planarization can be disposed on the protective insulation layer 343.

[0466] The logic circuits in Embodiments 1 and 2, which include the thin-film transistors described above, are capable of having stable electrical characteristics and high reliability.

[0467] This embodiment can be implemented by appropriately combining it with other embodiments.

[0468] (Example 10)

[0469] In this embodiment, an example of a thin-film transistor included in the logic circuit of Embodiment 1 or Embodiment 2 is described.

[0470] In this embodiment, reference will be made to Figure 14 This describes an example where the fabrication process of a thin-film transistor differs from that in Example 7. Because... Figure 14 Apart from certain steps and Figures 11A to 11E Since they are the same, common reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted.

[0471] First, a gate electrode layer 381 is formed on a substrate 370, and a first gate insulating layer 372a and a second gate insulating layer 372b are stacked thereon according to Embodiment 7. In this embodiment, the gate insulating layer has a two-layer structure, wherein a nitride insulating layer and an oxide insulating layer are used as the first gate insulating layer 372a and the second gate insulating layer 372b, respectively.

[0472] As an oxide insulating layer, silicon oxide layer, silicon oxynitride layer, aluminum oxide layer, aluminum oxynitride layer, etc. can be used. As a nitride insulating layer, silicon nitride layer, silicon oxynitride layer, aluminum nitride layer, aluminum oxynitride layer, etc. can be used.

[0473] In this embodiment, the gate insulating layer may have a structure in which a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 381 side. A silicon nitride layer (SiN) with a thickness of 50 nm to 200 nm (including both ends) (50 nm in this embodiment) is formed as the first gate insulating layer 372a using a sputtering method. y (y>0)), and a silicon oxide layer (SiO) with a thickness of 5nm to 300nm (including both ends) (100nm in this embodiment) is stacked on the first gate insulating layer 372a as the second gate insulating layer 372b. x (x>0)); therefore, a gate insulating layer is formed.

[0474] Subsequently, during photolithography, an oxide semiconductor layer is formed and then processed into an island-shaped oxide semiconductor layer. In this embodiment, the oxide semiconductor layer is formed using a sputtering method with the aid of an In-Ga-Zn-O based metal oxide target.

[0475] In this case, the oxide semiconductor layer is preferably formed while removing any remaining moisture from the processing chamber. This is to prevent hydrogen, hydroxyl groups, and moisture from being contained within the oxide semiconductor layer.

[0476] To remove residual moisture in the processing chamber, a gas trap vacuum pump is preferably used. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferred. Furthermore, the exhaust unit can be a turbopump with a cold trap. In a deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, hydrogen-containing compounds, such as water (H₂O), are expelled, thereby reducing the impurity concentration of the oxide semiconductor layer formed in the deposition chamber.

[0477] Preferably, a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups or hydrides have been removed to a concentration expressed in ppm or ppb is used as the sputtering gas for forming the oxide semiconductor layer.

[0478] Subsequently, the oxide semiconductor layer undergoes dehydration or dehydrogenation. The temperature of the first heat treatment for dehydration or dehydrogenation is higher than or equal to 400°C and lower than or equal to 750°C, preferably higher than or equal to 425°C. Note that at temperatures of 425°C or higher, the heat treatment time can be 1 hour or less, while at temperatures below 425°C, the heat treatment time is greater than 1 hour. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer is heat-treated in a nitrogen atmosphere, without being exposed to air, thus preventing water and hydrogen from entering the oxide semiconductor layer. In this way, the oxide semiconductor layer is obtained. Subsequently, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) is introduced into the same electric furnace, and cooling is performed. Preferably, water, hydrogen, etc., are not contained in the oxygen gas or N2O gas. Alternatively, the purity of the oxygen or N2O gas introduced into the heat treatment equipment is preferably 6N (99.9999%) or higher, more preferably 7N (99.99999%) or higher (i.e., the impurity concentration of the oxygen or N2O gas is preferably 1 ppm or lower, more preferably 0.1 ppm or lower).

[0479] Note that heat treatment equipment is not limited to electric furnaces, but can include, for example, RTA (Rapid Thermal Annealing) equipment such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) equipment. LRTA equipment is used to heat the object to be treated by radiation of light (electromagnetic waves) emitted from bulbs such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps. LRTA equipment may be equipped not only with bulbs but also with devices for heating the object to be treated by heat conduction or thermal radiation from heaters such as resistance heaters. GRTA is a method for performing heat treatment using high-temperature gases. The gas used is an inert gas such as nitrogen or a rare gas such as argon that will not react with the object to be treated during heat treatment. Alternatively, heat treatment can be performed at 600°C to 750°C for several minutes using the RTA method.

[0480] Furthermore, after the first heat treatment for dehydration or dehydrogenation, heat treatment can be performed in an oxygen gas atmosphere or an N2O gas atmosphere at a temperature of 200°C to 400°C (inclusive), preferably from 200°C to 300°C (inclusive).

[0481] The first thermal treatment of the oxide semiconductor layer can be performed before the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In this case, after the first thermal treatment, the substrate is removed from the heating device and a photolithography step is performed.

[0482] Through the above process, the entire region of the oxide semiconductor layer is in an oxygen-excess state; therefore, the oxide semiconductor layer has a high resistance, that is, the oxide semiconductor layer becomes type I. Accordingly, an oxide semiconductor layer 382 whose entire region is type I is obtained.

[0483] Subsequently, a conductive layer is formed on the oxide semiconductor layer 382. A resist mask is formed during photolithography. Etching is selectively performed, thereby forming the source electrode layer 385a and the drain electrode layer 385b. Then, the oxide insulating layer 386 is formed using a sputtering method.

[0484] In this case, the oxide insulating layer 386 is preferably formed while removing residual moisture from the processing chamber. This serves to prevent hydrogen, hydroxyl groups, and moisture from being contained within the oxide semiconductor layer 382 and the oxide insulating layer 386.

[0485] To remove residual moisture in the processing chamber, a gas trapping vacuum pump is preferably used. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferably used. Furthermore, the exhaust unit can be a turbopump with a cold trap. In a deposition chamber using a cryogenic pump for exhaust, hydrogen atoms, compounds containing hydrogen atoms, such as water (H2O), are expelled, thereby reducing the impurity concentration of the oxide insulating layer 386 formed in the deposition chamber.

[0486] Preferably, a high-purity gas, with impurities such as hydrogen, water, hydroxyl groups, or hydrides removed to a concentration expressed in ppm or ppb, is used as the sputtering gas for forming the oxide insulating layer 386.

[0487] Through the above steps, a thin-film transistor 380 can be formed.

[0488] Subsequently, in order to reduce changes in the electrical characteristics of the thin-film transistor, heat treatment (preferably at 150°C or higher and below 350°C) may be performed in an inert gas atmosphere or a nitrogen atmosphere. For example, heat treatment may be performed for 1 hour at 250°C in a nitrogen atmosphere.

[0489] Furthermore, heat treatment can be performed in air at 100°C to 200°C (inclusive) for 1 to 30 hours (inclusive). In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment can be performed at a fixed heating temperature. Alternatively, the following temperature variation can be repeated multiple times: the heating temperature is increased from room temperature to 100°C to 200°C (inclusive), and then decreased to room temperature. Under reduced pressure, the heating time can be shortened. Through this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; therefore, the thin-film transistor can be kept off. Thus, the reliability of the thin-film transistor can be improved.

[0490] The protective insulating layer 373 may be formed on the oxide insulating layer 386. In this embodiment, the protective insulating layer 373 is formed to a thickness of 100 nm using a sputtering method with the aid of a silicon nitride layer.

[0491] The protective insulating layer 373 and the first gate insulating layer 372a formed using nitride insulating layers do not contain impurities such as moisture, hydrogen, hydrides and hydroxides, and have the effect of preventing them from entering from the outside.

[0492] Therefore, during the manufacturing process after the formation of the protective insulating layer 373, it is possible to prevent impurities such as moisture from entering from the outside. Furthermore, even after the device, such as a semiconductor device, is completed, it is possible to prevent impurities such as moisture from entering from the outside for a long period of time; thus, long-term reliability of the device can be achieved.

[0493] In addition, a portion of the insulating layer between the protective insulating layer 373 formed using the nitride insulating layer and the first gate insulating layer 372a can be removed, so that the protective insulating layer 373 and the first gate insulating layer 372a are in contact with each other.

[0494] Accordingly, impurities such as moisture, hydrogen, hydrides and hydroxides in the oxide semiconductor layer are reduced as much as possible and their entry is prevented, so that the concentration of impurities in the oxide semiconductor layer can be kept low.

[0495] Although not shown, a planarization insulation layer for planarization may be disposed on the protective insulation layer 373.

[0496] The logic circuits in Embodiments 1 and 2, which include the thin-film transistors described above, are capable of having stable electrical characteristics and high reliability.

[0497] This embodiment can be implemented by appropriately combining it with other embodiments.

[0498] (Example 11)

[0499] In this embodiment, examples of semiconductor devices including the logic circuits of Embodiment 1 or Embodiment 2 are described. Specifically, refer to... Figures 15A to 15C To describe the appearance and cross-section of the liquid crystal display panel, in each liquid crystal display panel, the driver circuit includes the logic circuit in Embodiment 1 or Embodiment 2. Figure 15A and Figure 15C This is a plan view of the panel. In each panel, thin-film transistors 4010 and 4011 and liquid crystal element 4013 are sealed between the first substrate 4001 and the second substrate 4006 using sealant 4005. Figure 15B It is along Figure 15A Or a cross-sectional view taken by the MN section of 15C.

[0500] The sealant 4005 is configured to surround the pixel portion 4002 and the scan line driver circuit 4004 disposed on the first substrate 4001. A second substrate 4006 is disposed on the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004, together with the liquid crystal layer 4008, are sealed by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003, formed using a single-crystal semiconductor film or a polycrystalline semiconductor film prepared on a separately fabricated substrate, is mounted in a region different from the area surrounded by the sealant 4005 on the first substrate 4001.

[0501] Note that there are no specific restrictions on the connection method for separately formed driver circuits, and COG method, wire bonding method, TAB method, etc. can be used. Figure 15A An example of signal line driver circuit 4003 being mounted using the COG method is shown. Figure 15C An example is shown in which the signal line driver circuit 4003 is mounted using the TAB method.

[0502] The pixel portion 4002 and scan line driver circuit 4004, disposed on the first substrate 4001, include multiple thin-film transistors. As an example, Figure 15B The image shows a thin-film transistor 4010 included in pixel portion 4002 and a thin-film transistor 4011 included in scan line driver circuit 4004. Insulating layers 4041, 4042 and 4021 are disposed on thin-film transistors 4010 and 4011.

[0503] Any of the thin-film transistors of Examples 3 to 10 can be suitably used as thin-film transistors 4010 and 4011, and they can be formed using similar steps and materials as those of the thin-film transistors of Examples 3 to 10. Hydrogen or water is reduced in the oxide semiconductor layer of thin-film transistors 4010 and 4011. Therefore, thin-film transistors 4010 and 4011 are highly reliable thin-film transistors. In this embodiment, thin-film transistors 4010 and 4011 are n-channel thin-film transistors.

[0504] A conductive layer 4040 is disposed on a portion of an insulating layer 4021 that overlaps with the channel formation region of the oxide semiconductor layer in the thin-film transistor 4011. The conductive layer 4040 is disposed at the location overlapping the channel formation region of the oxide semiconductor layer, thereby reducing the amount of change in the threshold voltage of the thin-film transistor 4011 before and after BT testing. The potential of the conductive layer 4040 may be the same as or different from the potential of the gate electrode layer of the thin-film transistor 4011. The conductive layer 4040 can also serve as a second gate electrode layer. Furthermore, the potential of the conductive layer 4040 can be GND, 0V, or the conductive layer 4040 can be in a floating state. Note that a conductive layer 4040 is not necessarily required.

[0505] The pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the source or drain electrode layer of the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. A portion of the pixel electrode layer 4030, counter electrode layer 4031, and liquid crystal layer 4008 overlaps with each other, corresponding to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and counter electrode layer 4031 are respectively provided with insulating layers 4032 and 4033 serving as alignment films, and the liquid crystal layer 4008 is sandwiched between the electrode layers through the insulating layers 4032 and 4033.

[0506] Note that the light-transmitting substrate can be used as the first substrate 4001 and the second substrate 4006; it can be made of glass, ceramic, or plastic. The plastic can be a glass fiber reinforced plastic (FRP) sheet, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film.

[0507] Reference numeral 4035 denotes a columnar spacer obtained by selectively etching an insulating film, and the columnar spacer is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Alternatively, a spherical spacer may be used as spacer 4035. The counter electrode layer 4031 is electrically connected to a common potential line formed on the substrate in which the thin-film transistor 4010 is formed. The counter electrode layer 4031 and the common potential line can be electrically connected to each other using a common connection portion via conductive particles disposed between a pair of substrates. Note that the conductive particles are contained in a sealant 4005.

[0508] Alternatively, a blue-phase liquid crystal can be used that does not require an alignment film. The blue phase is one of the liquid crystal phases that forms just before the cholesteric phase becomes isotropic as the temperature of the cholesteric liquid crystal increases. Since the blue phase forms only within a narrow temperature range, a liquid crystal composition containing 5 wt% or more of a chiral reagent is used in the liquid crystal layer 4008 to improve the temperature range. The liquid crystal composition including the blue-phase liquid crystal and the chiral reagent has a short response time of 1 microsecond or less and is optically isotropic; therefore, alignment processing is not necessary, and viewing angle dependence is low. Furthermore, since no alignment film is required and no rubbing process is needed, electrostatic breakdown caused by rubbing can be prevented, and defects and damage to the liquid crystal display device can be reduced during manufacturing. Therefore, the yield of the liquid crystal display device can be improved. Specifically, thin-film transistors formed using oxide semiconductor layers have the potential for their electrical characteristics to fluctuate significantly and deviate from the design range due to electrostatic effects. Therefore, it is more efficient to use blue-phase liquid crystal materials in liquid crystal display devices that include thin-film transistors formed using oxide semiconductor layers.

[0509] Note that, in addition to transmissive liquid crystal display devices, this embodiment can also be applied to transmissive-reflective liquid crystal display devices.

[0510] Although in the example of the liquid crystal display device, the polarizer is disposed on the outer surface of the substrate (viewer side), and the color layer and electrode layer for the display element are sequentially disposed on the inner surface of the substrate, the polarizer may also be disposed on the inner surface of the substrate. The stacked structure of the polarizer and color layer is not limited to the structure in this embodiment, but can be appropriately configured depending on the materials of the polarizer and color layer and the conditions of the manufacturing process. Furthermore, a light-shielding film serving as a black matrix may be disposed in a portion other than the display area.

[0511] Above thin-film transistors 4011 and 4010, an insulating layer 4041 is formed in contact with an oxide semiconductor layer. The insulating layer 4041 can be formed using materials and methods similar to those used for the oxide insulating layer described in any of the embodiments. Here, as the insulating layer 4041, the silicon oxide layer is formed by a sputtering method. Furthermore, a protective insulating layer 4042 is formed on and in contact with the insulating layer 4041. For example, the protective insulating layer 4042 can be formed using a silicon nitride layer. To reduce the surface roughness caused by the thin-film transistors, an insulating layer 4021 is formed as a planarizing insulating layer.

[0512] An insulating layer 4021 is formed as a planar insulating layer. As the insulating layer 4021, heat-resistant organic materials such as polyimide, acrylic acid, benzocyclobutene, polyamide, or epoxy resin can be used. Besides these organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc., can also be used. Note that the insulating layer 4021 can be formed by stacking multiple insulating layers formed from these materials.

[0513] There are no specific limitations on the method used to form the insulating layer 4021. Depending on the material, the insulating layer 4021 can be formed by methods such as sputtering, SOG, spin coating, dip coating, spraying, or micro-droplet emission methods (e.g., inkjet printing, screen printing, or offset printing), or by tools (equipment) such as doctor blades, roller coaters, curtain coaters, or blade coaters. The baking step of the insulating layer 4021 also acts as annealing for the semiconductor layer, thereby enabling the efficient fabrication of semiconductor devices.

[0514] The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using light-transmitting conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO) which is indium oxide mixed with zinc oxide, conductive materials (SiO2) which are indium oxide mixed with silicon oxide, organoindium, organotin, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, etc. Furthermore, when light transmission is not required or reflectivity is required in a reflective liquid crystal display device, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using one or more materials selected from metals such as tungsten (W), molybdenum (Mo), zirconium, hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), alloys of these metals, and nitrides of these metals.

[0515] The conductive component, comprising a conductive polymer (also known as a conductive element), can be used in the pixel electrode layer 4030 and the counter electrode layer 4031. The pixel electrode formed using the conductive component preferably has a surface resistivity of less than or equal to 10,000 ohms per square and a transmittance of greater than or equal to 70% at a wavelength of 550 nm. Furthermore, the resistivity of the conductive polymer contained in the conductive composition is preferably less than or equal to 0.1 Ω·cm.

[0516] As conductive polymers, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, copolymers of two or more of them, etc., can be provided.

[0517] In addition, various signals and potentials are provided from FPC 4018 to separately formed signal line driver circuit 4003, scan line driver circuit 4004, or pixel section 4002.

[0518] Terminal electrode 4015 is formed using the same conductive film as the pixel electrode layer 4030 included in liquid crystal element 4013, and terminal electrode 4016 is formed using the same conductive film as the source and drain electrode layers of thin film transistors 4010 and 4011.

[0519] The terminal electrode 4015 is electrically connected to the terminal contained in the FPC 4018 via an anisotropic conductive film 4019.

[0520] Notice, Figures 15A to 15C Examples are shown in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, the invention is not limited to this structure. The scan line driver circuit may be formed separately and then mounted, or only a portion of the signal line driver circuit or a portion of the scan line driver circuit may be formed separately and then mounted.

[0521] Appropriately incorporate a black matrix (light-shielding layer), optical components such as polarizing elements (optical substrates), retardation elements, or anti-reflection elements. For example, circular polarization can be achieved by using a polarizing substrate and a retardation substrate. Additionally, backlights, sidelights, etc., can be used as light sources.

[0522] In an active-matrix liquid crystal display device, a display pattern is formed on the screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between a selected pixel electrode and a corresponding counter electrode, thus optically modulating the liquid crystal layer disposed between the pixel electrode and the counter electrode. This optical modulation is perceived by an observer as a display pattern.

[0523] The problem with liquid crystal displays (LCDs) is that image sticking occurs or the moving image becomes blurred when displaying moving images because the liquid crystal molecules themselves have a low response speed. As a technique to improve the moving image characteristics of LCDs, there is a so-called black-insertion driving technique that displays a complete black image every other frame.

[0524] Alternatively, a driving method called dual-frame-rate driving can be used, wherein the vertical synchronization frequency is 1.5 times or more, preferably 2 times or more, of the normal vertical synchronization frequency, thereby improving the response speed.

[0525] Furthermore, as a technique for improving the moving image characteristics of liquid crystal display devices, another driving technique exists in which a surface light source comprising multiple LED (light-emitting diode) light sources or multiple EL light sources is used as a backlight, and each light source included in the surface light source is driven individually to perform intermittent illumination during a frame period. Three or more types of LEDs can be used as the surface light source, or white LEDs can be used. Because multiple LEDs can be controlled individually, the timing of the LED light emission can be synchronized with the timing of the optical modulation switching the liquid crystal layer. In this driving technique, portions of the LEDs can be turned off. Therefore, especially when displaying images where the proportion of black areas in one of the screens is high, the liquid crystal display device can be driven with low power consumption.

[0526] When combined with any of these driving technologies, liquid crystal display devices can have better display characteristics, such as motion picture characteristics, than conventional liquid crystal display devices.

[0527] Since thin-film transistors are easily damaged by static electricity, etc., the protection circuit is preferably disposed on the same substrate as the pixel portion and the driving circuit portion. The protection circuit is preferably formed using a nonlinear element including an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scan line input terminal and the signal line input terminal. In this embodiment, multiple protection circuits are provided so that the pixel transistor, etc., is not damaged when surge voltages caused by static electricity, etc., are applied to the scan lines, signal lines, and capacitor bus lines. Accordingly, the protection circuit has a structure for releasing charge to the common wiring when a surge voltage is applied to the protection circuit. The protection circuit includes a nonlinear element disposed in parallel with the scan lines. Each nonlinear element includes a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, the nonlinear element can be formed using the same steps as the thin-film transistor in the pixel portion. For example, characteristics similar to those of a diode can be achieved by connecting the gate terminal to the drain terminal.

[0528] In addition, for liquid crystal display modules, it is possible to use twisted nematic (TN) mode, coplanar conversion (IPS) mode, edge field conversion (FFS) mode, axially symmetric orientation microcell (ASM) mode, optically compensated birefringence (OCB) mode, ferroelectric liquid crystal (FLC) mode, antiferroelectric liquid crystal (AFLC) mode, etc.

[0529] There are no specific limitations on the semiconductor devices disclosed in this specification, and the scope includes liquid crystal display devices such as TN liquid crystal, OCB liquid crystal, STN liquid crystal, VA liquid crystal, ECB liquid crystal, GH liquid crystal, polymer diffused liquid crystal, and disc liquid crystal. Specifically, a typical black liquid crystal panel, such as a transmissive liquid crystal display device, utilizing a vertical alignment (VA) mode is preferred. Some examples of vertical alignment modes are given. For example, MVA (multi-domain vertical alignment), PVA (patterned vertical alignment), and ASV modes can be used.

[0530] Furthermore, this embodiment can also be applied to VA liquid crystal display devices. A VA liquid crystal display device has a form in which the orientation of liquid crystal molecules in a liquid crystal display panel is controlled. In a VA liquid crystal display device, the liquid crystal molecules are oriented vertically relative to the panel surface when no voltage is applied. Furthermore, a method called multi-domain or multi-domain design can be used to divide pixels into certain regions (sub-pixels) and oriented liquid crystal molecules in different directions within their respective regions.

[0531] This embodiment can be implemented by appropriately combining it with any other embodiment.

[0532] (Example 12)

[0533] In this embodiment, examples of semiconductor devices including the logic circuits of Embodiment 1 or Embodiment 2 are described. Specifically, examples of manufacturing active matrix light-emitting display devices are described, in which the driver circuitry includes the logic circuits of Embodiment 1 or Embodiment 2. Note that in this embodiment, examples of light-emitting display devices including light-emitting elements utilizing electroluminescence will be described.

[0534] Electroluminescent elements are classified according to whether the light-emitting material is an organic or inorganic compound. Generally speaking, the former are called organic EL elements, and the latter are called inorganic EL elements.

[0535] In organic EL devices, by applying a voltage to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, and an electric current flows. The charge carriers (electrons and holes) then recombine, thereby emitting light. Due to this mechanism, this light-emitting element is called an electroluminescent (EMF) device.

[0536] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structure. Dispersed inorganic EL devices have a light-emitting layer in which particles of the light-emitting material are dispersed in a binder, and their light emission mechanism utilizes donor-acceptor recombination type light emission using donor and acceptor energy levels. Thin-film inorganic EL devices have a structure in which the light-emitting layer is sandwiched between dielectric layers, and their light emission mechanism utilizes localized type light emission using inner-shell electron transitions of metal ions, where the dielectric layer is sandwiched between electrodes. Note that an example of an organic EL device as a light-emitting element is described here.

[0537] Figure 16 This example of a semiconductor device illustrates an example of a pixel structure to which digital timegrayscale driving can be applied.

[0538] This describes the structure and operation of pixels to which digital temporal grayscale driving is applicable. Here, a pixel includes two n-channel transistors, each of which includes an oxide semiconductor layer as a channel formation region.

[0539] Pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor 6403. The gate of the switching transistor 6401 is connected to a scan line 6406, a first electrode (one of the source and drain electrodes) of the switching transistor 6401 is connected to a signal line 6405, and a second electrode (the other of the source and drain electrodes) of the switching transistor 6401 is connected to the gate of the driving transistor 6402. The gate of the driving transistor 6402 is connected to a power line 6407 via the capacitor 6403, the first electrode of the driving transistor 6402 is connected to the power line 6407, and the second electrode of the driving transistor 6402 is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to a common electrode. The common electrode is electrically connected to a common potential line 6408 disposed on the same substrate as the common electrode.

[0540] The second electrode (common electrode) of the light-emitting element 6404 is set to a low power supply potential. Note that the low power supply potential is a potential that satisfies the condition that the low power supply potential is less than the high power supply potential, with reference to the high power supply potential set to the power supply line 6407. Examples of low power supply potentials include GND and 0V. The potential difference between the high and low power supply potentials is applied to the light-emitting element 6404, supplying current to it and causing it to emit light. Here, to make the light-emitting element 6404 emit light, each potential is set such that the potential difference between the high and low power supply potentials is greater than the forward voltage drop of the light-emitting element 6404.

[0541] When the gate capacitance of the driving transistor 6402 is used as a replacement for the capacitor 6403, the capacitor 6403 can be omitted. The gate capacitance of the driving transistor 6402 can be formed between the channel formation region and the gate electrode.

[0542] Here, using the voltage-input voltage driving method, a video signal that enables the driving transistor 6402 to be fully turned on or off is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. Because the driving transistor 6402 operates in the linear region, a voltage higher than the power supply line voltage 6407 is applied to the gate of the driving transistor 6402. Note that this voltage is greater than or equal to (power supply line voltage + V0 of the driving transistor 6402). th The voltage is applied to signal line 6405.

[0543] Furthermore, when using analog grayscale driving instead of digital time-ratio grayscale driving, it is possible to use analog grayscale driving by inputting signals in different ways. Figure 16 Same pixel structure.

[0544] When using the analog grayscale method, the forward voltage of the light-emitting element 6404 plus the V of the driving transistor 6402 is greater than or equal to the forward voltage of the light-emitting element 6404. th A voltage is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 represents the voltage at which the desired brightness is obtained. By inputting a video signal to enable the driving transistor 6402 to operate in the saturation region, current can be supplied to the light-emitting element 6404. In order for the driving transistor 6402 to operate in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. When using an analog video signal, it is possible to feed current to the light-emitting element 6404 according to the video signal and perform analog grayscale driving.

[0545] Notice, Figure 16 The pixel structure shown is not limited to this. For example, switches, resistors, capacitors, transistors, logic circuits, etc., can be added. Figure 16 The pixels shown.

[0546] The following will refer to Figures 17A to 17C This describes the structure of the light-emitting element. Here, we will use an n-channel driven TFT as an example to describe the cross-sectional structure of a pixel. As an example, it is used for... Figure 17A , Figure 17B and Figure 17C The driving TFTs 7011, 7021 and 7001 of the semiconductor devices shown can be manufactured in a manner similar to the thin-film transistors described in any of the embodiments, and are each thin-film transistors including an oxide semiconductor layer.

[0547] To extract light emission from the light-emitting element, at least one of the anode and cathode must be transparent. Thin-film transistors and light-emitting elements are formed on a substrate. The light-emitting element can have: a top-emitting structure, where light emission is extracted through a surface opposite the substrate; a bottom-emitting structure, where light emission is extracted through a surface on the substrate side; or a dual-emitting structure, where light emission is extracted through both the surface opposite the substrate and a surface on the substrate side. Pixel structures can be adapted to light-emitting elements having any of these light-emitting structures.

[0548] Next, refer to Figure 17A To describe a light-emitting element with a bottom-emitting structure.

[0549] Figure 17A This is a cross-sectional view of a pixel when the driving TFT is of type n and light is emitted from the light-emitting element 7012 to the first electrode 7013 side. Figure 17A In the light-emitting element 7012, a first electrode layer 7013 is formed on a light-transmitting conductive layer 7017 electrically connected to the drain electrode layer of the driving TFT 7011, and an EL layer 7014 and a second electrode layer 7015 are stacked on the first electrode layer 7013 in the order shown.

[0550] As the light-transmitting conductive layer 7017, light-transmitting conductive layers such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, and indium tin oxide with added silicon oxide can be used.

[0551] Various materials can be used for the first electrode 7013 of the light-emitting element. For example, when the first electrode 7013 is used as a cathode, the first electrode 7013 is preferably formed using materials with low work function, such as alkali metals like Li or Cs, alkaline earth metals like Mg, Ca or Sr, alloys containing any of these metals (e.g., MG:Ag, Al:Li), or rare earth metals like Yb or Er. Figure 17A In this process, the first electrode 7013 is approximately shaped to achieve a thickness (preferably about 5 nm to 30 nm) for transmitting light. For example, an aluminum layer with a thickness of 20 nm is used for the first electrode 7013.

[0552] Note that the transparent conductive layer 7017 and the first electrode 7013 can be formed by stacking a transparent conductive layer and an aluminum layer and then performing selective etching. In this case, it is preferable that the etching can be performed using the same mask.

[0553] Furthermore, the periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is formed using an organic resin film such as polyimide, acrylic acid, polyamide, or epoxy resin, an inorganic insulating film, or an organopolysiloxane. Particularly preferred is that the partition wall 7019 is formed using a photosensitive resin material so that it has an opening on the first electrode 7013, and the sidewalls of the opening are formed as slopes with continuous curvature. When a photosensitive resin material is used for the partition wall 7019, the step of forming a resist mask can be omitted.

[0554] An EL layer 7014, formed over the first electrode 7013 and the spacer 7019, is acceptable, including at least a light-emitting layer. Furthermore, the EL layer 7014 can be formed as a single layer or a multilayer structure. When the EL layer 7014 is formed using multiple layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the first electrode 7013, which serves as the cathode, in the order shown. Note that not all of these layers are required, except for the light-emitting layer.

[0555] The stacking order is not limited to the order described above. The first electrode 7013 can be used as the anode, and the hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer can be stacked on the first electrode layer 7013 in the order shown. However, considering power consumption, it is preferable that the first electrode 7013 is used as the cathode, and the electron injection layer, electron transport layer, light-emitting layer, hole transport layer, and hole injection layer are stacked on the first electrode 7013 in the order shown, because compared with using the first electrode 7013 as the anode, it is more effective to prevent the voltage increase of the driver circuit section and reduce power consumption.

[0556] Furthermore, any of various materials can be used for the second electrode 7015 formed on the EL layer 7014. For example, when the second electrode 7015 is used as an anode, materials with high work functions such as ZrN, Ti, W, Ni, Pt, Cr, etc., or transparent conductive materials such as ITO, IZO, or ZnO are preferred. Additionally, a shielding film 7016, such as a light-blocking metal or a light-reflecting metal, is disposed on the second electrode 7015. In this embodiment, an ITO film is used as the second electrode 7015, and a Ti layer is used as the shielding film 7016.

[0557] The light-emitting element 7012 corresponds to the region where the EL layer 7014, including the light-emitting layer, is sandwiched between the first electrode 7013 and the second electrode 7015. Figure 17A In the case of the element structure shown, the light emitted from the light-emitting element 7012 is emitted to the side of the first electrode 7013, as indicated by the arrow.

[0558] Note that in Figure 17AIn the example shown, the transparent conductive layer serves as the gate electrode layer, and the light-emitting thin film serves as the source and drain electrode layers. Light emitted from the light-emitting element 7012 passes through the color filter layer 7033 and is able to exit through the substrate.

[0559] The color filter layer 7033 is formed by a microdroplet emission method such as inkjet or printing, or by an etching method using photolithography.

[0560] The color filter layer 7033 is covered by a cover layer 7034, and also by a protective insulating layer 7035. Note that although the cover layer 7034 has a small thickness, it is similar to... Figure 17A As shown, however, the cover layer 7034 has the function of planarizing the roughness caused by the color filter layer 7033.

[0561] The contact holes formed in the planar insulating layers 7036, 7032 and 7031 and reaching the drain electrode layer are provided in the portion overlapping with the partition wall 7019.

[0562] Reference Figure 17B To describe a light-emitting element with a dual light-emitting structure.

[0563] Figure 17B In the light-emitting element 7022, a first electrode layer 7023 is formed on a light-emitting conductive layer 7027 electrically connected to a drain electrode layer of the driving TFT 7021, and an EL layer 7024 and a second electrode 7025 are stacked on the first electrode 7023 in the order shown.

[0564] As the light-transmitting conductive layer 7027, light-transmitting conductive layers such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, and indium tin oxide with added silicon oxide can be used.

[0565] Various materials can be used for the first electrode 7023. For example, when the first electrode 7023 is used as a cathode, it is preferably formed using materials with low work functions, such as alkali metals like Li or Cs, alkaline earth metals like Mg, Ca or Sr, alloys containing any of these metals (e.g., MG:Ag, Al:Li), or rare earth metals like Yb or Er. In this embodiment, the first electrode 7023 is used as a cathode, and the first electrode 7023 is approximately formed such that the thickness of the transmitted light is such that it is approximately 5 nm to 30 nm. For example, an aluminum film with a thickness of 20 nm is used as the cathode.

[0566] Note that the transparent conductive layer 7027 and the first electrode 7023 can be formed by stacking a transparent conductive layer and an aluminum layer and then performing selective etching. In this case, it is preferable that the etching can be performed using the same mask.

[0567] Furthermore, the periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is formed using an organic resin film such as polyimide, acrylic acid, polyamide, or epoxy resin, an inorganic insulating film, or an organopolysiloxane. Particularly preferred is that the partition wall 7029 is formed using a photosensitive resin material to have an opening on the first electrode 7023, such that the sidewalls of the opening are formed as slopes with continuous curvature. When a photosensitive resin material is used for the partition wall 7029, the step of forming a resist mask can be omitted.

[0568] An EL layer 7024, formed over the first electrode 7023 and the spacer 7029, including a light-emitting layer, is acceptable. Furthermore, the EL layer 7024 can be formed as a single layer or a multilayer structure. When the EL layer 7024 is formed using multiple layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the first electrode 7023, which serves as the cathode, in the order shown. Note that not all of these layers are required, except for the light-emitting layer.

[0569] The stacking order is not limited to the order described above. The first electrode 7023 can be used as the anode, and the hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer can be stacked on the first electrode layer 7023 in the order shown. However, considering power consumption, it is preferable that the first electrode 7023 is used as the cathode, and the electron injection layer, electron transport layer, light-emitting layer, hole transport layer, and hole injection layer are stacked on the cathode in the order shown, because power consumption can be reduced more effectively compared to using the first electrode 7023 as the anode.

[0570] Furthermore, various materials can be used for the second electrode 7025 formed on the EL layer 7024. For example, when the second electrode layer 7025 is used as the anode, materials with high work function, such as transparent conductive materials like ITO, IZO, or ZnO, are preferred. In this embodiment, the second electrode 7025 is formed using an ITO layer comprising silicon oxide and is used as the anode.

[0571] The light-emitting element 7022 corresponds to the region where the EL layer 7024, including the light-emitting layer, is sandwiched between the first electrode 7023 and the second electrode 7025. Figure 17B In the case of the element structure shown, light emitted from the light-emitting element 7022 is emitted to the second electrode 7025 side and the first electrode 7023 side, as indicated by the arrows.

[0572] Note that in Figure 17B In the example shown, the light-transmitting conductive layer serves as the gate electrode layer, and the light-emitting thin film serves as the source and drain electrode layers. Light emitted from the light-emitting element 7022 to the side of the first electrode 7023 passes through the color filter layer 7043 and is able to be emitted through the substrate.

[0573] The color filter layer 7043 is formed by a microdroplet emission method such as inkjet or printing, or by an etching method using photolithography.

[0574] The color filter layer 7043 is covered by a cover layer 7044 and also by a protective insulating layer 7045.

[0575] The contact holes formed in the planar insulating layers 7046, 7042 and 7041 and reaching the drain electrode layer are provided in the portion overlapping with the partition wall 7029.

[0576] Note that when full-color display is achieved by using light-emitting elements with dual light-emitting structures on both display surfaces, the light emitted from the second electrode 7025 side does not pass through the color filter layer 7043; therefore, it is preferable that a sealing substrate with a color filter layer may also be disposed on the second electrode 7025.

[0577] Next, refer to Figure 17C To describe a light-emitting element with a top-emitting structure.

[0578] Figure 17C This is a cross-sectional view of a pixel when the driving TFT 7001 is of type n and the light emitted from the light-emitting element 7002 passes through the second electrode 7005. Figure 17C In this configuration, the drain electrode layer of the driving TFT 7001 and the first electrode 7003 are in contact with each other, and the driving TFT 7001 and the first electrode 7003 of the light-emitting element 7002 are electrically connected to each other. The EL layer 7004 and the second electrode 7005 are stacked on the first electrode 7003 in the order shown.

[0579] Furthermore, various materials can be used for the first electrode 7003. For example, when the first electrode 7003 is used as a cathode, it is preferable to use materials with low work functions, such as alkali metals like Li or Cs, alkaline earth metals like Mg, Ca or Sr, alloys containing any of these metals (e.g., MG:Ag, Al:Li), or rare earth metals like Yb or Er, to form the first electrode 7003.

[0580] Furthermore, the periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is formed using an organic resin film such as polyimide, acrylic acid, polyamide, or epoxy resin, an inorganic insulating film, or an organopolysiloxane. Particularly preferred is that the partition wall 7009 is formed using a photosensitive resin material to have an opening on the first electrode 7003, such that the sidewalls of the opening are formed as slopes with continuous curvature. When a photosensitive resin material is used for the partition wall 7009, the step of forming a resist mask can be omitted.

[0581] An EL layer 7004, formed over the first electrode 7003 and the partition 7009, is acceptable, including at least a light-emitting layer. Furthermore, the EL layer 7004 can be formed as a single layer or a multilayer structure. When the EL layer 7004 is formed using multiple layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the first electrode 7003, which serves as the cathode, in the order shown. Note that not all of these layers are required, except for the light-emitting layer.

[0582] The stacking order is not limited to the above order, but the hole injection layer, hole transport layer, light emission layer, electron transport layer and electron injection layer can be stacked on the first electrode 7003 used as the anode in the order shown.

[0583] Figure 17C In the process, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer are stacked in the order shown on a stacked film in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order shown, and an MG:Ag alloy thin film is formed thereon.

[0584] However, when the driving TFT 7001 is n-type, it is preferable that the electron injection layer, electron transport layer, light-emitting layer, hole transport layer and hole injection layer are stacked on the first electrode 7003 in the order shown, because compared with the case of using layers stacked in the above order, it is possible to more effectively prevent the increase of voltage in the driver circuit and reduce power consumption.

[0585] The second electrode 7005 is formed using a light-transmitting conductive material. For example, a light-transmitting conductive layer can be used, such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, or indium tin oxide with added silicon oxide.

[0586] The light-emitting element 7002 corresponds to the region where the EL layer 7004, including the light-emitting layer, is sandwiched between the first electrode 7003 and the second electrode 7005. Figure 17C In the case of the pixel shown, light emitted from the light-emitting element 7002 is emitted to the side of the second electrode 7005, as indicated by the arrow.

[0587] Figure 17C In this embodiment, the drain electrode layer of the driving TFT 7001 is electrically connected to the first electrode 7003 through contact holes formed in the silicon oxide layer 7051, the protective insulating layer 7052, the planarizing insulating layer 7056, the planarizing insulating layer 7053, and the insulating layer 7055. The planarizing insulating layers 7036, 7046, 7053, and 7056 can be formed using resin materials such as polyimide, acrylic acid, benzocyclobutene, polyamide, or epoxy resin. Besides these resin materials, low dielectric constant materials (low-k materials), siloxane resins, phosphosilicate glass (PSG), borosilicate glass (BPSG), etc., may also be used. Note that the planarizing insulating layers 7036, 7046, 7053, and 7056 can be formed by stacking multiple insulating layers formed using these materials. Depending on the material, planar insulating layers 7036, 7046, 7053, and 7056 can be formed using methods such as sputtering, SOG, spin coating, dip coating, spraying, or droplet emission methods (e.g., inkjet, screen printing, or offset printing) or tools (equipment) such as doctor blades, roller coaters, curtain coaters, or doctor blade coaters.

[0588] A partition 7009 is provided to insulate the first electrode 7003 from the first electrodes of adjacent pixels. The partition 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy resin, an inorganic insulating film, or an organopolysiloxane. Particularly preferred is that the partition 7009 is formed using a photosensitive resin material to have an opening above the first electrode 7003, such that the sidewalls of the opening are formed as slopes with continuous curvature. When a photosensitive resin material is used for the partition 7009, the step of forming a resist mask can be omitted.

[0589] exist Figure 17C In the structure shown, for full-color display, the light-emitting element 7002, one of the adjacent light-emitting elements, and the other of the adjacent light-emitting elements are, for example, a green light-emitting element, a red light-emitting element, and a blue light-emitting element, respectively. Alternatively, in addition to the three light-emitting elements, a light-emitting display device capable of full-color display can be manufactured using four light-emitting elements, including a white light-emitting element.

[0590] exist Figure 17C In the structure, a light-emitting display device capable of full-color display can be manufactured as follows: all the plurality of light-emitting elements are white light-emitting elements, and a sealing substrate having a color filter or the like is disposed on the light-emitting element 7002. A monochromatic material, such as white, is formed and combined with a color filter or color conversion layer, thereby enabling full-color display.

[0591] Any of the thin-film transistors of the embodiments can be suitably used as driving TFTs 7001, 7011, and 7021 for semiconductor devices, and they can be formed using similar steps and materials to the TFTs of the embodiments. Hydrogen or water is reduced in the oxide semiconductor layer of the driving TFTs 7001, 7011, and 7021. Therefore, the driving TFTs 7001, 7011, and 7021 are highly reliable thin-film transistors.

[0592] Needless to say, it can also display monochromatic light. For example, a lighting system can be formed by emitting white light, or a background color emitting device can be formed by emitting monochromatic light.

[0593] If necessary, an optical film, such as a polarizing film including a circular polarizer, can be provided.

[0594] Note that although organic EL elements are described here as light-emitting elements, inorganic EL elements can also be configured as light-emitting elements.

[0595] Note that the example described is of a thin-film transistor (driving TFT) that controls the driving of the light-emitting element being electrically connected to the light-emitting element; however, a structure in which a TFT for current control is connected between the driving TFT and the light-emitting element may also be used.

[0596] Figure 18A and Figure 18B This shows the appearance and cross-section of a light-emitting display panel (also known as a light-emitting panel). Figure 18A It is a plan view of a panel in which thin-film transistors and light-emitting elements formed on a first substrate are sealed with a sealant between the first and second substrates. Figure 18B It is along Figure 18A The cross-sectional view intercepted by line HI.

[0597] The sealant 4505 is configured to surround the pixel portions 4502, signal line driver circuits 4503a and 4503b, and scan line driver circuits 4504a and 4504b disposed on the first substrate 4501. Additionally, a second substrate 4506 is disposed on the pixel portions 4502, signal line driver circuits 4503a and 4503b, and scan line driver circuits 4504a and 4504b. Accordingly, the pixel portions 4502, signal line driver circuits 4503a and 4503b, and scan line driver circuits 4504a and 4504b, together with the filler 4507, are sealed by the first substrate 4501, the sealant 4505, and the second substrate 4506. Preferably, in this manner, the panel is encapsulated (sealed) with a protective film (e.g., a laminated film or a UV-curable resin film) or a covering material with high airtightness and minimal degassing, so that the panel is not exposed to external air.

[0598] The pixel portion 4502, signal line driver circuits 4503a and 4503b, and scan line driver circuits 4504a and 4504b, formed on the first substrate 4501, each include a plurality of thin-film transistors. The thin-film transistor 4510 in the pixel portion 4502 and the thin-film transistor 4509 in the signal line driver circuit 4503a... Figure 18B The example is shown below.

[0599] Any of the thin-film transistors of the embodiments can be suitably used as thin-film transistors 4509 and 4510, and they can be formed using similar steps and materials to those of the thin-film transistors of the embodiments. Hydrogen or water is reduced in the oxide semiconductor layer of thin-film transistors 4509 and 4510. Therefore, thin-film transistors 4509 and 4510 are extremely reliable thin-film transistors.

[0600] A conductive layer is disposed on the portion overlapping the channel formation region of the oxide semiconductor layer in thin-film transistor 4509. In this embodiment, thin-film transistors 4509 and 4510 are n-channel thin-film transistors.

[0601] A conductive layer 4540 is disposed on a portion of a silicon oxide layer 4542 that overlaps with the channel formation region of the oxide semiconductor layer in the thin-film transistor 4509. The conductive layer 4540 is disposed at the location overlapping the channel formation region of the oxide semiconductor layer, thereby reducing the amount of change in the threshold voltage of the thin-film transistor 4509 before and after BT testing. The potential of the conductive layer 4540 may be the same as or different from the potential of the gate electrode layer in the thin-film transistor 4509. The conductive layer 4540 can also serve as a second gate electrode layer. Alternatively, the potential of the conductive layer 4540 may be GND, 0V, or the conductive layer 4540 may be in a floating state.

[0602] Furthermore, the silicon oxide layer 4542 is formed as an oxide semiconductor layer covering the thin-film transistor 4510. The source or drain electrode layer of the thin-film transistor 4510 is electrically connected to the wiring layer 4550 through an opening formed in the silicon oxide layer 4542 and the insulating layer 4551 formed on the thin-film transistor. The wiring layer 4550 is formed to contact the first electrode 4517, and the thin-film transistor 4510 is electrically connected to the first electrode 4517 through the wiring layer 4550.

[0603] A color filter layer 4545 is formed on an insulating layer 4551 such that it overlaps with the light-emitting area of ​​a light-emitting element 4511.

[0604] In addition, in order to reduce the surface roughness of the color filter layer 4545, the color filter layer 4545 is covered with a cover layer 4543, which serves as a planarizing insulating film.

[0605] An insulating layer 4544 is formed on top of a cover layer 4543. For example, a silicon nitride layer may be formed as the insulating layer 4544 by a sputtering method.

[0606] Reference numeral 4511 denotes a light-emitting element. The first electrode 4517, which is a pixel electrode included in the light-emitting element 4511, is electrically connected to the source or drain electrode layer of the thin-film transistor 4510 via a wiring layer 4550. Note that the light-emitting element 4511 has a stacked structure of the first electrode 4517, the electroluminescent layer 4512, and the second electrode 4513, and there are no specific limitations on this structure. The structure of the light-emitting element 4511 can be appropriately changed according to the direction of light extraction from the light-emitting element 4511, etc.

[0607] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organopolysiloxane. Particularly preferred is that the partition 4520 is formed using a photosensitive material so as to have an opening above the first electrode 4517, such that the sidewalls of the opening are formed as inclined surfaces with continuous curvature.

[0608] The electroluminescent layer 4512 can be formed as a single-layer structure or a stacked structure.

[0609] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc., from entering the light-emitting element 4511, a protective layer can be formed on the second electrode layer 4513 and the spacer 4520. As a protective layer, a silicon nitride layer, a silicon oxynitride layer, a DLC layer, etc., can be formed.

[0610] In addition, various signals and potentials are provided from FPCs 4518a and 4518b to signal line driver circuits 4503a and 4503b, scan line driver circuits 4504a and 4504b, or pixel section 4502.

[0611] The connection terminal electrode 4515 is formed using the same conductive layer as the first electrode 4517 included in the light-emitting element 4511, and the terminal electrode 4516 is formed using the same conductive layer as the source and drain electrode layers included in the thin-film transistor 4509.

[0612] The terminal electrode 4515 is electrically connected to the terminal contained in the FPC4518a through the anisotropic conductive layer 4519.

[0613] The second substrate located in the direction from which light is extracted from the light-emitting element 4511 should be light-transmitting. In this case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used for the second substrate 4506.

[0614] As filler 4507, UV-curable resins or thermosetting resins and inert gases such as nitrogen or argon can be used. For example, PVC (polyvinyl chloride), acrylic acid, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen is used as a filler.

[0615] Additionally, when necessary, optical films such as polarizers, circular polarizers (including elliptical polarizers), or delay films (quarter-wave or half-wave plates) can be appropriately applied to the light-emitting surface of the light-emitting element. Furthermore, polarizers or circular polarizers can be provided with anti-reflective films. For example, anti-glare treatment can be performed, through which reflected light can be diffused through the protrusions and depressions of the surface to reduce glare.

[0616] Sealants can be formed using screen printing, inkjet equipment, or dispensing appratus. Materials typically used as sealants include visible light-curing resins, ultraviolet-curing resins, or thermosetting resins. Additionally, fillers may be included.

[0617] As signal line driver circuits 4503a and 4503b and scan line driver circuits 4504a and 4504b, driver circuits formed on separately prepared substrates using single-crystal semiconductor films or polycrystalline semiconductor films can be used and mounted. Alternatively, only the signal line driver circuit or a portion thereof, or only the scan line driver circuit or a portion thereof, can be formed and mounted separately. This embodiment is not limited to... Figure 18A and Figure 18B The structure shown.

[0618] Through the above process, it is possible to manufacture a highly reliable light-emitting display device (display panel) that is a semiconductor device.

[0619] This embodiment can be implemented by appropriately combining it with any other embodiment.

[0620] (Example 13)

[0621] In this embodiment, examples of semiconductor devices including the logic circuits of Embodiment 1 or Embodiment 2 are described. Specifically, examples of electronic paper in which the driver circuitry includes the logic circuits of Embodiment 1 or Embodiment 2 are described.

[0622] Figure 19This is a cross-sectional view showing an active matrix electronic paper. Any of the thin-film transistors of the embodiments can be suitably used as thin-film transistor 581 for electronic paper and can be formed using similar steps and materials as the thin-film transistors of the embodiments. In this embodiment, for example, the thin-film transistor described in Embodiment 6 is used as thin-film transistor 581. Hydrogen or water is reduced in the oxide semiconductor layer of thin-film transistor 581. Therefore, thin-film transistor 581 is a highly reliable thin-film transistor.

[0623] Figure 19 Electronic paper is an example of a display device using a torsion sphere display system. A torsion sphere display system refers to a system in which spherical particles, each colored black and white, are disposed between a first electrode layer and a second electrode layer, which serve as electrode layers for display elements, and a potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles, thereby enabling display.

[0624] The thin-film transistor 581 formed on the substrate 580 has a bottom gate structure, wherein the source and drain electrode layers are electrically connected to the first electrode layer 587 through openings formed in the silicon oxide layer 583, the protective insulating layer 584 and the insulating layer 585.

[0625] Spherical particles are disposed between the first electrode layer 587 and the second electrode layer 588. Each spherical particle includes a black region 590a and a white region 590b, and a cavity 594 filled with liquid surrounding the black region 590a and the white region 590b. The periphery of the spherical particles is filled with a filler 595 such as resin (see [link to documentation]). Figure 19 In this embodiment, the first electrode layer 587 corresponds to the pixel electrode, while the second electrode layer 588 disposed on the substrate 596 corresponds to the common electrode.

[0626] Furthermore, electrophoretic elements can be used instead of torsion spheres. Microcapsules with diameters of approximately 10 μm to 200 μm are used, encapsulating transparent liquid crystal, positively or negatively charged white microparticles, and black microparticles with a charge of the opposite polarity to the white microparticles. Within these microcapsules, positioned between a first electrode layer and a second electrode layer, when an electric field is applied by the first and second electrode layers, the white and black microparticles move in opposite directions, enabling the display of white or black. Display elements using this principle are called electrophoretic display elements and are generally referred to as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, thus eliminating the need for auxiliary light, resulting in lower power consumption, and allowing the display portion to be identified in dim lighting conditions. Additionally, the previously displayed image can be retained even when no power is supplied to the display portion. Consequently, the displayed image can be stored even when the semiconductor device with display functionality (which can be simply called a display device or a semiconductor device equipped with a display device) is located away from the electromagnetic wave source.

[0627] The electronic paper in this embodiment is a reflective display device, wherein the display is performed by controlling the voltage applied to the torsion ball using a driver circuit.

[0628] This embodiment can be implemented by appropriately combining it with any other embodiment.

[0629] (Example 14)

[0630] In this embodiment, examples of semiconductor devices that include the logic circuits of Embodiment 1 or Embodiment 2 are described. Specifically, examples of electronic devices (including arcade machines within this scope) in which the driver circuitry includes the logic circuits of Embodiment 1 or Embodiment 2 are described. Examples of electronic devices include television sets (also known as televisions or television receivers), monitors of computers, digital cameras or digital video cameras, digital photo frames, mobile phones (also known as mobile phone devices), portable game consoles, portable information terminals, audio playback devices, large arcade machines such as pinball machines, and so on.

[0631] Figure 20A An example of a mobile phone is shown. The mobile phone 1600 is equipped with a display 1602 integrated into a housing 1601, operation buttons 16043a and 1603b, an external connection port 1604, a speaker 1605, a microphone 1606, etc.

[0632] Touching with fingers, etc. Figure 20A When the display portion 1602 of the mobile phone 1600 is displayed, data can be input into the mobile phone 1600. Furthermore, operations such as making phone calls and composing emails can be performed by touching the display portion 1602 with a finger.

[0633] The display unit 1602 has three main screen modes. The first mode is a display mode primarily used for displaying images. The second mode is an input mode primarily used for inputting data such as text. The third mode is a combination of display and input modes.

[0634] For example, when making a phone call or writing an email, the display section 1602 is selected in a text input mode primarily for entering text, enabling the input of text displayed on the screen. In this case, it is preferable to display a keyboard or numeric keys in almost all areas of the screen of the display section 1602.

[0635] When a detection device, including a sensor for detecting tilt such as a gyroscope or accelerometer, is installed inside the mobile phone 1600, the display of the screen of the display section 1602 can be automatically switched by determining the orientation of the mobile phone 1600 (whether the mobile phone 1600 is horizontal or vertical for landscape mode or portrait mode).

[0636] The screen mode is switched by touching the display section 1602 or the operation buttons 1603a and 1603b on the operating housing 1601. Alternatively, the screen mode can be switched according to the type of image displayed on the display section 1602. For example, when the signal of the image displayed on the display section is moving image data, the screen mode switches to display mode. When the signal is text data, the screen mode switches to input mode.

[0637] Furthermore, in input mode, when a signal detected by the optical sensor in display section 1602 is detected while no input is performed via touch display section 1602 for a certain period of time, the screen mode can be controlled to switch from input mode to display mode.

[0638] The display portion 1602 can be used as an image sensor. For example, images of palm prints, fingerprints, etc., can be captured by touching the display portion 1602 with the palm or fingers, thereby enabling personal authentication. Furthermore, by equipping the display portion with a backlight or a sensing light source that emits near-infrared light, images of finger veins, palm veins, etc., can be captured.

[0639] Any of the semiconductor devices described in the embodiments can be applied to the display portion 1602. For example, the plurality of transistors described in the embodiments can be configured as switching elements in pixels.

[0640] Figure 20B An example of a mobile phone is also shown. The example is as follows: Figure 20B The portable information terminal shown can have multiple functions. For example, in addition to telephone functionality, this portable information terminal can also process various data segments by combining with a computer.

[0641] Figure 20B The portable information terminal shown has a housing 1800 and a housing 1801. Housing 1801 includes a display panel 1802, a speaker 1803, a microphone 1804, a pointer device 1806, a camera lens 1807, an external connection terminal 1808, etc. Housing 1800 includes a keyboard 1810, an external memory slot 1811, etc. Furthermore, an antenna is integrated into housing 1801.

[0642] The display panel 1802 is equipped with a touchscreen. Multiple operation buttons 1805, displayed as images, are located on... Figure 20B The middle part is represented by a dashed line.

[0643] In addition to the above structure, it can also be combined with contactless IC chips, small memory devices, etc.

[0644] In the display panel 1802, the display orientation is appropriately changed according to the application mode. Furthermore, the portable information terminal is equipped with a camera lens 1807 on the same surface as the display panel 1802, and therefore it can be used as a videophone. The speaker 1803 and microphone 1804 can be used for videophone calls, recording, sound playback, and voice calls. Additionally, in situations such as... Figure 20B The shells 1800 and 1801, in their unfolded state as shown, can slide and overlap each other; therefore, the size of the portable information terminal can be reduced, making it suitable for carrying.

[0645] The external connection terminal 1808 can be connected to an AC adapter and various types of cables such as USB cables, enabling charging and data communication with a personal computer. Additionally, a storage medium can be inserted into the external memory slot 1811, allowing for the storage and transfer of large amounts of data.

[0646] In addition to the functions mentioned above, it can also provide infrared communication and television reception functions.

[0647] Figure 21A An example of a television set is shown. In the television set 9600, the display portion 9603 is integrated into the housing 9601. The display portion 9603 is capable of displaying images. Here, the housing 9601 is supported by a bracket 9605.

[0648] The television 9600 can be operated using the operation switch on the housing 9601 or a separate remote control 9610. Channels can be switched and volume controlled using the operation buttons 9609 on the remote control 9610, thereby controlling the image displayed on the display unit 9603. Furthermore, the remote control 9610 may be equipped with a display unit 9607 for displaying data output from the remote control 9610.

[0649] Note that the 9600 television set is equipped with a receiver, modem, etc. Using the receiver, it can receive general television broadcasts. Furthermore, when the display device is connected to a communication network via a modem, either wired or wirelessly, it can perform one-way (from transmitter to receiver) or two-way (between transmitter and receiver or between receivers) information communication.

[0650] In the display section 9603, the plurality of transistors described in any of the embodiments can be configured as switching elements for pixels.

[0651] Figure 21BAn example of a digital photo frame is shown. For example, in digital photo frame 9700, a display portion 9703 is integrated into the housing 9701. The display portion 9703 is capable of displaying various images. For example, the display portion 9703 can display data of images taken using a digital camera, etc., and functions as a typical photo frame.

[0652] In the display section 9703, the plurality of transistors described in any of the embodiments can be configured as switching elements for pixels.

[0653] Note that the digital photo frame 9700 is equipped with an operating section, external connection terminals (USB terminal, terminals for connecting to various cables such as USB cables, etc.), a recording medium insertion section, etc. Although these components can be mounted on the same surface as the display section, for aesthetic reasons, it is preferable to mount them on the side surface or the back. For example, by inserting a memory device storing image data taken with a digital camera into the recording medium insertion section of the digital photo frame and loading that data, the image can be displayed on the display section 9703.

[0654] The Digital Photo Frame 9700 can be configured to wirelessly transmit and receive data. Through wireless communication, it can load the desired image data for display.

[0655] Figure 22 It is a portable game console, consisting of two housings, housing 9881 and housing 9891. Housings 9881 and 9891 are connected to a connecting part 9893, allowing the portable game console to be opened or folded. Display parts 9882 and 9883 are respectively integrated into housings 9881 and 9891.

[0656] In the display section 9883, the plurality of transistors described in any of the embodiments can be configured as switching elements for pixels.

[0657] in addition, Figure 22 The portable game console shown is equipped with a speaker section 9884, a recording medium insertion section 9886, an LED light 9890, input components (operation buttons 9885, connection terminals 9887, sensors 9888 (capable of measuring force, displacement, position, velocity, acceleration, angular velocity, revolutions, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electricity, radiation rays, flow rate, humidity, gradient, vibration, odor, or infrared radiation) and a microphone 9889), etc. Needless to say, the structure of the portable game console is not limited to the above description, but can employ other structures equipped with at least one thin-film transistor disclosed in this specification. The portable game console may appropriately include additional accessories. Figure 22The portable game console shown has the function of reading programs or data stored in a recording medium and displaying them on the display section, as well as the function of sharing data with another portable game console via wireless communication. Note that... Figure 22 The portable game console shown is not limited to this function; rather, it can have a variety of functions.

[0658] As described above, the logic circuit in Embodiment 1 or Embodiment 2 can be applied to the display panel of various electronic devices, and thus can provide electronic devices with high reliability.

[0659] (Example 15)

[0660] In this embodiment, examples of semiconductor devices including the logic circuitry of Embodiment 1 or Embodiment 2 are described. Specifically, electronic paper in which the driver circuitry includes the logic circuitry of Embodiment 1 or Embodiment 2 can be used in electronic devices across all fields, as long as they display information. For example, electronic paper can be applied to e-book (e-book) readers, posters, advertisements in vehicles such as trains, and displays for various cards such as credit cards. An example of such an electronic device is... Figure 23 As shown.

[0661] Figure 23 An example of an e-book reader is shown. For example, e-book reader 2700 includes two housings, housing 2701 and housing 2703. Housings 2701 and housing 2703 are coupled to hinge 2711, allowing e-book reader 2700 to be opened and closed using hinge 2711 as an axis. This structure allows e-book reader 2700 to be operated like a paper book.

[0662] Display portions 2705 and 2707 are respectively integrated into housings 2701 and 2703. Display portions 2705 and 2707 can display one image or different images. In the case where display portions 2705 and 2707 display different images, for example, the display portion on the right... Figure 23 The display portion 2705 in the middle can display text, while the display portion on the left ( Figure 23 The display section 2707 in the middle can display graphics.

[0663] Figure 23An example is shown in which the housing 2701 is equipped with operating components. For example, the housing 2701 is equipped with a power switch 2721, operation buttons 2723, a speaker 2725, etc. Page turning is possible via the operation buttons 2723. Note that a keyboard, pointer device, etc., may also be provided on the surface of the housing on which the display portion is located. Furthermore, external connection terminals (headphone terminals, USB terminals, terminals that can connect to various cables such as AC adapters and USB cables, etc.), recording media insertion portions, etc., may be provided on the back or side surface of the housing. In addition, the e-book reader 2700 may have an electronic dictionary function.

[0664] The e-book reader 2700 may be configured to wirelessly transmit and receive data. Through wireless communication, it is expected that book data, etc., can be purchased and downloaded from an e-book server.

[0665] This embodiment can be implemented by appropriately combining it with any other embodiment.

[0666] (Example 16)

[0667] According to one embodiment of the invention, impurities in an oxide semiconductor that act as carrier suppliers (donors or acceptors) are reduced to extremely low levels, thereby forming an intrinsic or substantially intrinsic oxide semiconductor, which is then used in a thin-film transistor.

[0668] Figure 24 This is the band structure of a portion of the transistor between the source and drain. For highly purified oxide semiconductors, the Fermi level is ideally located in the middle of the band gap.

[0669] In this case, at the bonding surface, if the equation φ is satisfied... m =χ, then the Fermi level of the metal electrode is the same as the conduction band level of the oxide semiconductor, where φ m χ is the work function, and x is the electron affinity of the oxide semiconductor. An ohmic contact is provided when the right side of the equation is greater than the left side. Assume the oxide semiconductor has a band gap of 3.15 eV and an electron affinity of 4.3 eV, and is in its intrinsic state (carrier density: approximately 1 × 10⁻⁶). -7 / cm 3 The source and drain electrodes are formed using titanium (Ti) with a work function of 4.3 eV. Under these conditions, the Schottky barrier relative to electrons is not as... Figure 24 As shown, it is formed.

[0670] Figure 25This illustrates the state in which a positive voltage is applied to the drain side of a transistor formed using oxide semiconductors. Because oxide semiconductors have a wide bandgap, the intrinsic carrier density of highly purified oxide semiconductors, which are intrinsic or substantially intrinsic, is zero or close to zero. However, when a voltage is applied between the source and drain, carriers (electrons) can be injected from the source side and flow into the drain side.

[0671] Figure 26A This is the energy band diagram of a MOS transistor formed using an oxide semiconductor to which a positive gate voltage is applied. In this case, almost no thermally excited carriers are present in the highly purified oxide semiconductor. Therefore, no carriers accumulate even near the gate insulating film. However, as Figure 25 As shown, the transport of charge carriers (electrons) injected from the source side is possible.

[0672] Figure 26B This is the energy band diagram of a MOS transistor formed using an oxide semiconductor to which a negative gate voltage is applied. Oxide semiconductors contain almost no majority carriers (holes); therefore, no carriers accumulate even near the gate insulating film. This indicates a small off-state current.

[0673] Figure 27 This is the energy band diagram of a transistor formed using silicon semiconductors. For silicon semiconductors, the band gap is 1.12 eV, and the intrinsic carrier density is 1.45 × 10⁻⁶. 10 / cm 3 (300K). Thermally excited carriers are not negligible even at room temperature. Therefore, the cutoff-state current changes drastically with temperature.

[0674] In this way, not only by using only oxide semiconductors with wide bandgap in the transistor, but also by reducing impurities that act as donors, such as hydrogen, the carrier density is thus set to 1 × 10⁻⁶. 14 / cm 3 Or smaller, preferably 1×10 12 / cm 3 Or even smaller, capable of removing thermally excited carriers at the actual operating temperature, allowing the transistor to operate solely with carriers injected from the source side. Accordingly, it becomes possible to obtain a transistor whose off-state current is reduced to 1 × 10⁻⁶. -13 [A] or smaller, and hardly changes with temperature variations, thus enabling the transistor to operate in a highly stable manner.

[0675] (Example 17)

[0676] In this embodiment, the measurement of the cutoff current using a test element group (also known as a TEG) will be described below.

[0677] Figure 28 The initial characteristics of a thin-film transistor with an actual L / W = 3μm / 10000μm are shown, wherein 200 thin-film transistors, each with an L / W = 3μm / 50μm, are connected in parallel. Additionally, a top view is shown... Figure 29A As shown, and its enlarged top view is as follows: Figure 29B As shown. Figure 29B The region enclosed by the dashed line represents a single-stage thin-film transistor with L / W = 3 μm / 50 μm and Lov = 1.5 μm. To measure the initial characteristics of the thin-film transistor, the source-drain current transfer characteristics (hereinafter referred to as drain current or Id), i.e., the Vg-Id characteristic, were measured under the following conditions: the substrate temperature was set to room temperature, the voltage between the source and drain (hereinafter referred to as drain voltage or Vd) was set to 10 V, and the voltage between the source and gate (hereinafter referred to as gate voltage or Vg) changed from -20 V to +20 V. Note that... Figure 28 The value of Vg is shown in the range from -20V to +5V.

[0678] like Figure 28 As shown, a thin-film transistor with a channel width W of 10000 μm exhibits 1 × 10⁻⁶ Vd at 1V and 10V. -13 A or less, which is less than or equal to the resolution (100 fA) of the measuring device (semiconductor parameter analyzer, Agilent 4156C manufactured by Agilent Technologies Inc.).

[0679] A method for manufacturing a thin-film transistor for measurement is described.

[0680] First, a silicon nitride layer is formed on a glass substrate as a base layer using a CVD method, and a silicon oxynitride layer is formed on top of the silicon nitride layer. A tungsten layer is formed on top of the silicon oxynitride layer as a gate electrode layer using a sputtering method. Here, the gate electrode layer is formed by selectively etching the tungsten film.

[0681] Then, a 100 nm thick silicon oxynitride layer is formed on the gate electrode layer as a gate insulating layer using a CVD method.

[0682] Then, a 50 nm thick oxide semiconductor layer is formed on the gate insulating layer by sputtering using an In-Ga-Zn-O based metal oxide target (with a molar ratio of In2O3:Ga2O3:ZnO = 1:1:2). Here, island-shaped oxide semiconductor layers are formed by selectively etching the oxide semiconductor layer.

[0683] Then, the oxide semiconductor layer is subjected to a first heat treatment at 450°C for 1 hour in a clean furnace under a nitrogen atmosphere.

[0684] Then, a titanium layer (150 nm thick) is formed on the oxide semiconductor layer as both the source and drain electrode layers by sputtering. Here, the source and drain electrode layers are formed by selective etching, such that 200 thin-film transistors, each with a channel length L of 3 μm and a channel width of 50 μm, are connected in parallel to obtain thin-film transistors with an actual L / W = 3 μm / 10000 μm.

[0685] Then, a 300 nm thick silicon oxide layer, serving as a protective insulating layer, is formed in contact with the oxide semiconductor layer using reactive sputtering. Here, the opening is formed on the gate electrode layer, source electrode layer, and drain electrode layer by selectively etching the silicon oxide layer as a protective layer. Subsequently, a second heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere.

[0686] Then, before measuring the Vg-Id properties, a heat treatment was performed at 150°C for 10 hours.

[0687] The bottom-gate thin-film transistor is manufactured through the above process.

[0688] Thin-film transistors, such as Figure 28 The figure shown has approximately 1×10 -13 The reason for the cutoff current of A is that the hydrogen concentration in the oxide semiconductor layer can be sufficiently reduced during the aforementioned manufacturing process. The hydrogen concentration in the oxide semiconductor is 5 × 10⁻⁶. 19 / cm 3 Or smaller, preferably 5×10 18 / cm 3 Or smaller, more preferably 5×10 17 / cm 3 Or even less. Note that the hydrogen concentration in the oxide semiconductor layer is measured using secondary ion mass spectrometry (SIMS).

[0689] While examples using In-Ga-Zn-O based oxide semiconductors are described, this embodiment is not specifically limited to this. Other oxide semiconductor materials, such as In-Sn-Zn-O based semiconductors, Sn-Ga-Zn-O based oxide semiconductors, Al-Ga-Zn-O based oxide semiconductors, Sn-Al-Zn-O based oxide semiconductors, In-Zn-O based oxide semiconductors, In-Sn-O oxide semiconductors, Sn-Zn-O based oxide semiconductors, Al-Zn-O based oxide semiconductors, In-O based oxide semiconductors, Sn-O based oxide semiconductors, or Zn-O based oxide semiconductors, can also be used as oxide semiconductor materials. Furthermore, as an oxide semiconductor material, AlO2 with 2.5 wt% to 10 wt% of Al2O3 can be used. x Mixed In-Al-Zn-O based oxide semiconductors or with 2.5wt% to 10wt% SiOx Hybrid In-Zn-O based oxide semiconductor.

[0690] The carrier concentration of the oxide semiconductor layer, as measured by the carrier measurement device, is preferably less than or equal to 1.45 × 10⁻⁶. 10 / cm 3 This is the intrinsic carrier density of silicon. Specifically, the carrier concentration is 5 × 10⁻⁶. 14 / cm 3 Preferably, it is 5×10 12 / cm 3 In other words, it allows the carrier concentration of the oxide semiconductor layer to be as close to zero as possible.

[0691] Thin-film transistors can also have channel lengths L (including both ends) ranging from 10 nm to 1000 nm, which enables increased circuit operating speed and extremely low off-state current, resulting in further reductions in power consumption.

[0692] In addition, in circuit design, when the thin-film transistor is in the off state, the oxide semiconductor layer can be regarded as an insulator.

[0693] Next, the temperature characteristics of the cut-off current of the thin-film transistor manufactured in this embodiment are evaluated. Temperature characteristics are important when considering the environmental resistance, performance retention, etc., of the final product in which the thin-film transistor is used. It should be understood that smaller variations are preferred, as this increases the degree of design freedom.

[0694] For temperature characteristics, the Vg-Id characteristics were obtained using a constant temperature chamber under the following conditions: the substrate equipped with the thin-film transistor was kept at the corresponding constant temperatures of -30°C, 0°C, 25°C, 40°C, 60°C, 80°C, 100°C and 120°C, the drain voltage was set to 6V, and the gate voltage was changed from -20V to +20V.

[0695] Figure 30A The Vg-Id characteristics measured at the above temperatures and overlapping with each other are shown. Figure 30B Show Figure 30A An enlarged view of the range of the cutoff-state current enclosed by the dashed line. The rightmost curve indicated by the arrow in the simplified diagram is the curve obtained at -30°C, the leftmost curve is the curve obtained at 120°C, and the curves obtained at other temperatures lie in between. The temperature dependence of the on-state current is almost imperceptible. On the other hand, as... Figure 30B The magnified view clearly shows that the cutoff-state current is less than or equal to 1 × 10⁻⁶ at all temperatures except near a gate voltage of -20 V. -12A, this is close to the resolution of the measuring device, and no temperature dependence was observed. In other words, even at a high temperature of 120°C, the cutoff current remains less than or equal to 1 × 10⁻⁶. -12 A, and also considering that the effective channel width W is 10000μm, it can be seen that the cutoff current is quite small.

[0696] Thin-film transistors (TFTs) incorporating the aforementioned purified oxide semiconductor (purified OS) exhibit almost no temperature dependence on their cutoff current. This is also due to the fact that oxide semiconductors have a bandgap of 3 eV or higher and contain very few intrinsic carriers. Furthermore, the source and drain regions are in a degenerate state, which is another factor contributing to the lack of temperature dependence. TFTs operate primarily by injecting carriers from the degenerate source region into the oxide semiconductor, and the aforementioned characteristic (temperature independence of the cutoff current) can be explained by the temperature independence of the carrier density.

[0697] When thin-film transistors with such extremely small cutoff current are used in the manufacture of memory circuits (memory elements), there is a very small leakage due to the small cutoff current. Therefore, memory data can be retained for a relatively long time.

[0698] This application is based on Japanese Patent Application No. 2009-238914, filed with the Japan Patent Office on October 16, 2009, the entire contents of which are incorporated herein by reference.

[0699] Reference number explanation

[0700] 11: Thin-film transistor, 12: Thin-film transistor, 13: Thin-film transistor, 14: Thin-film transistor, 15: Capacitor, 21: Thin-film transistor, 22: Thin-film transistor, 23: Thin-film transistor, 24: Thin-film transistor, 25: Capacitor, 31: Thin-film transistor, 41: Thin-film transistor, 101: Thin-film transistor, 102: Thin-film transistor, 103: Thin-film transistor, 104: Thin-film transistor, 105: Capacitor, 110: Pulse output circuit, 111: Thin-film transistor, 112: Thin-film transistor, 113: Thin-film transistor, 114: Thin-film transistor, 115: Capacitor, 120: Pulse output circuit, 121: Thin-film transistor, 122: Thin-film transistor, 123: Thin-film transistor Transistor, 124: Thin-film transistor, 125: Capacitor, 130: Pulse output circuit, 201: Thin-film transistor, 202: Thin-film transistor, 203: Thin-film transistor, 204: Thin-film transistor, 205: Capacitor, 210: Pulse output circuit, 211: Thin-film transistor, 212: Thin-film transistor, 213: Thin-film transistor, 214: Thin-film transistor, 215: Capacitor, 220: Pulse output circuit, 221: Thin-film transistor, 222: Thin-film transistor, 223: Thin-film transistor, 224: Thin-film transistor, 225: Capacitor, 230: Pulse output circuit, 300: Substrate, 302: Gate insulating layer, 303: Protective insulating layer, 310: Thin-film transistor, 3 11: Gate electrode layer, 313: Channel formation region, 314a: High-resistance source region, 314b: High-resistance drain region, 315a: Source electrode layer, 315b: Drain electrode layer, 316: Oxide insulating layer, 320: Substrate, 322: Gate insulating layer, 323: Protective insulating layer, 330: Oxide semiconductor layer, 331: Oxide semiconductor layer, 332: Oxide semiconductor layer, 340: Substrate, 342: Gate insulating layer, 343: Protective insulating layer, 345: Oxide semiconductor layer, 346: Oxide semiconductor layer, 350: Thin film transistor, 351: Gate electrode layer, 352: Oxide semiconductor layer, 355a: Source electrode layer, 355b: Drain electrode layer, 356: Oxide insulating layer, 3 60: Thin-film transistor; 361: Gate electrode layer; 362: Oxide semiconductor layer; 363: Channel formation region; 364a: High-resistance source region; 364b: High-resistance drain region; 365a: Source electrode layer; 365b: Drain electrode layer; 366: Oxide insulating layer; 370: Substrate; 372a: First gate insulating layer; 372b: Second gate insulating layer; 373: Protective insulating layer; 380: Thin-film transistor; 381: Gate electrode layer; 382: Oxide semiconductor layer; 385a: Source electrode layer; 385b: Drain electrode layer; 386: Oxide insulating layer; 390: Thin-film transistor; 391: Gate electrode layer; 392: Oxide semiconductor layer; 393: Oxide semiconductor layer; 394: Substrate.395a: Source electrode layer, 395b: Drain electrode layer, 396: Oxide insulating layer, 397: Gate insulating layer, 398: Protective insulating layer, 399: Oxide semiconductor layer, 400: Substrate, 402: Gate insulating layer, 407: Insulating layer, 410: Thin film transistor, 411: Gate electrode layer, 412: Oxide semiconductor layer, 414a: Wiring layer, 414b: Wiring layer, 415a: Source or drain electrode layer, 415b: Source or drain electrode layer, 420: Silicon substrate, 421a: Opening, 421b: Opening, 422: Insulating layer, 423: Opening, 424: Conductive layer, 425: Thin film transistor, 426: Thin film transistor, 427: Conductive layer, 450: Substrate, 452: Gate 457: Insulating layer; 460: Thin film transistor; 461: Gate electrode layer; 461a: Gate electrode layer; 461b: Gate electrode layer; 462: Oxide semiconductor layer; 464: Wiring layer; 465a: Source or drain electrode layer; 465a1: Source or drain electrode layer; 465a2: Source or drain electrode layer; 465b: Source or drain electrode layer; 468: Wiring layer; 580: Substrate; 581: Thin film transistor; 583: Silicon oxide layer; 584: Protective insulating layer; 585: Insulating layer; 587: Electrode layer; 588: Electrode layer; 590a: Black area; 590b: White area; 594: Cavity; 595: Filler; 596: Against substrate; 1600: Mobile phone; 1601: 1602: Housing; 1603a: Display section; 1603b: Operation button; 1604: External connection port; 1605: Speaker; 1606: Microphone; 1800: Housing; 1801: Housing; 1802: Display panel; 1803: Speaker; 1804: Microphone; 1805: Operation button; 1806: Pointer; 1807: Camera lens; 1808: External connection terminal; 1810: Keyboard; 1811: External memory slot; 2700: E-book reader; 2701: Housing; 2703: Housing; 2705: Display section; 2707: Display section; 2711: Hinge; 2721: Power switch; 2723: Operation button; 27... 25: Speaker; 4001: Substrate; 4002: Pixel portion; 4003: Signal line driver circuit; 4004: Scan line driver circuit; 4005: Sealant; 4006: Substrate; 4008: Liquid crystal layer; 4010: Thin film transistor; 4011: Thin film transistor; 4013: Liquid crystal element; 4015: Connecting terminal electrode; 4016: Terminal electrode; 4018: FPC; 4019: Anisotropic conductive film; 4021: Insulating layer; 4030: Pixel electrode layer; 4031: Counter electrode layer; 4032: Insulating layer; 4033: Insulating layer; 4040: Conductive layer; 4041: Insulating layer; 4042: Insulating layer; 4501: Substrate; 4502: Pixel portion.4503a: Signal line driver circuit, 4503b: Signal line driver circuit, 4504a: Scan line driver circuit, 4504b: Scan line driver circuit, 4505: Sealant, 4506: Substrate, 4507: Filler, 4509: Thin film transistor, 4510: Thin film transistor, 4511: Light-emitting element, 4512: Electroluminescent layer, 4513: Electrode, 4515: Connecting terminal electrode, 4516: Terminal electrode, 4517: Electrode, 4518a: FPC, 4518b: FPC, 4519: Anisotropic conductive layer, 4520: Spacer, 4540: Conductive layer, 4542: Silicon oxide layer, 4543: Capping layer, 4 544: Insulating layer, 4545: Color filter layer, 4550: Wiring layer, 4551: Insulating layer, 6400: Pixel, 6401: Switching transistor, 6402: Driving transistor, 6403: Capacitor, 6404: Light-emitting element, 6405: Signal line, 6406: Scan line, 6407: Power line, 6408: Common potential line, 7001: Driving TFT, 7002: Light-emitting element, 7003: Electrode, 7004: EL layer, 7005: Electrode, 7009: Spacer, 7011: Driving TFT, 7012: Light-emitting element, 7013: Electrode, 7014: EL layer, 7015: Electrode, 7016: Shielding film, 7017: 7019: Conductive layer; 7021: Driving TFT; 7022: Light-emitting element; 7023: Electrode; 7024: EL layer; 7025: Electrode; 7026: Electrode; 7027: Conductive layer; 7029: Spacer; 7031: Insulating layer; 7032: Insulating layer; 7033: Color filter layer; 7034: Capping layer; 7035: Protective insulating layer; 7036: Planarized gate insulating layer; 7041: Insulating layer; 7042: Insulating layer; 7043: Color filter layer; 7044: Capping layer; 7045: Protective insulating layer; 7046: Planarized gate insulating layer; 7051: Silicon oxide layer; 7052: Protective insulating layer; 7053: Planarized gate. 7055: Insulating layer; 7056: Planarized gate insulating layer; 9600: Television set; 9601: Housing; 9603: Display section; 9605: Stand; 9607: Display section; 9609: Operation buttons; 9610: Remote control; 9700: Digital photo frame; 9701: Housing; 9703: Display section; 9881: Housing; 9882: Display section; 9883: Display section; 9884: Speaker section; 9885: Operation buttons; 9886: Recording medium insertion section; 9887: Connection terminal; 9888: Sensor; 9889: Microphone; 9890: LED light; 9891: Housing; 9893: Connecting part.

Claims

1. A display device, wherein the display portion includes: a light-emitting element; A color filter located below and overlapping the light-emitting element; and a transistor located below and electrically connected to the light-emitting element. The transistor has: a first conductive layer; and a first insulating layer on the first conductive layer; An oxide semiconductor layer located on the first insulating layer and having a channel formation region; a second insulating layer on the oxide semiconductor layer; A second conductive layer having a region overlapping the channel forming region; And a third conductive layer and a fourth conductive layer, electrically connected to the oxide semiconductor layer, The display device has a third insulating layer on the transistor. The color filter is located above the third insulating layer. The light-emitting element has: a first electrode located above the third insulating layer; and an EL layer on the first electrode; and the second electrode on the EL layer, The display device has a partition wall located above the first electrode and having a region that contacts the upper surface of the first electrode. The first conductive layer functions as the first gate electrode of the transistor. The second conductive layer functions as the second gate electrode of the transistor. The third conductive layer has a region that contacts the upper surface of the second insulating layer. The second insulating layer has a first opening portion for connecting the third conductive layer and the oxide semiconductor layer. The first opening overlaps with the first conductive layer. The third insulating layer has a region that contacts the upper surface of the second conductive layer; The area in contact with the upper surface of the third conductive layer; and the area in contact with the upper surface of the fourth conductive layer, The second, third, and fourth conductive layers are made of the same material. The oxide semiconductor layer contains indium, gallium, and zinc. The partition wall has an area that overlaps with the channel forming area.

2. The display device as claimed in claim 1, wherein, The light-emitting element emits light toward one side of the color filter.

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