An 8T2R non-volatile SRAM unit circuit

Abstract

The present invention discloses an 8T2R non-volatile SRAM unit circuit, including a non-volatile data storage circuit composed of two resistive random access memories RRAM, a resistive random access memory UR on the top and a resistive random access memory BR on the bottom; a transmission gate circuit composed of an N-type MOSFET and a P-type MOSFET, the N-type MOSFET is recorded as NT, and the P-type MOSFET is recorded as PT; two P-type MOSFETs and two N-type MOSFETs constitute two inverters, and the two inverters are connected end to end, the two P-type MOSFETs are respectively recorded as a left pull-up transistor LUT and a right pull-up transistor RUT, the two N-type MOSFETs are respectively recorded as a left pull-down transistor LDT and a right pull-down transistor RDT, and the left access transistor LAT and the right access transistor RAT constitute a storage unit of a 6T-SRAM. The circuit adds a non-volatile unit RRAM on the basis of the read, write and hold capabilities of the SRAM, so that the SRAM has the ability to not lose power-off data and to recover power-on data.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an 8T2R non-volatile SRAM unit circuit. Background Art

[0002] Static Random Access Memory (SRAM) is an indispensable part of most electronic device integrated circuits. In the System on Chip (SOC), the area of ​​SRAM accounts for about 70% of the entire chip area, so the static power consumption problem caused by SRAM becomes particularly prominent. However, the characteristic of SRAM data loss when power is off limits its application scenarios and ultra-low power performance. Resistive Random Access Memory (RRAM) is a new type of storage device in the past decade. It has broad prospects in replacing traditional non-volatile memory with its advantages of non-volatility, low power consumption, high integration, high durability, 3D stacking and long life.

[0003] RRAM devices can be divided into unipolar and bipolar devices. Unipolar RRAM switches between different resistance values ​​by controlling devices with the same phase and different voltage amplitudes; bipolar RRAM switches between different resistance values ​​by controlling devices with opposite phase and different voltage amplitudes. The resistance value is used to store data. At present, the control of RRAM resistance cannot be stabilized within a small range, but the window of high resistance and low resistance can be controlled above 90kΩ, which is sufficient to meet the requirements of storing data "0" and "1". In addition, the resistance fluctuation and write delay problems of RRAM devices limit their application in ultra-high precision storage and computing integrated devices. Therefore, how to combine RRAM devices on the basis of traditional SRAM storage units to integrate the advantages of both has become an urgent research topic. Summary of the invention

[0004] The purpose of the present invention is to provide an 8T2R non-volatile SRAM unit circuit, which adds a non-volatile unit RRAM on the basis of the read, write and hold capabilities of SRAM, so that the SRAM has the ability to maintain data loss during power-off and restore data on power-on, thereby improving the application scenarios of the SRAM circuit.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] An 8T2R non-volatile SRAM unit circuit, the circuit comprising:

[0007] A non-volatile data storage circuit composed of two resistive random access memories RRAM, including an upper resistive random access memory UR and a lower resistive random access memory BR, is called a 2R circuit;

[0008] The 2R circuit is connected to the storage node Q of the SRAM by a transmission gate circuit consisting of an N-type MOSFET and a P-type MOSFET, where the N-type MOSFET is denoted as NT and the P-type MOSFET is denoted as PT;

[0009] Two P-type MOSFETs and two N-type MOSFETs form two inverters, and the two inverters are connected end to end to form a bistable storage unit circuit, wherein the upper left and upper right P-type MOSFETs are respectively recorded as left pull-up transistors LUT and right pull-up transistors RUT, and the lower left and lower right N-type MOSFETs are respectively recorded as left pull-down transistors LDT and right pull-down transistors RDT;

[0010] The N-type MOSFETs on the left and right sides of the bistable memory cell circuit are access transistors of the storage node of the memory circuit, and are respectively denoted as the left access transistor LAT and the right access transistor RAT;

[0011] The left pull-up transistor LUT, the right pull-up transistor RUT, the left pull-down transistor LDT, the right pull-down transistor RDT, the left access transistor LAT and the right access transistor RAT constitute a 6T-SRAM storage cell of a bistable structure;

[0012] in:

[0013] The power source VDD is connected to the source electrodes of the left pull-up transistor LUT and the right pull-up transistor RUT;

[0014] The ground line VSS is connected to the source electrodes of the left pull-down transistor LDT and the right pull-down transistor RDT;

[0015] The gates of the left pull-up transistor LUT and the right pull-up transistor RUT are connected to the gates of the left pull-down transistor LDT and the right pull-down transistor RDT, respectively, and the connection nodes correspond to the storage nodes QB and Q, respectively;

[0016] The drains of the left pull-up transistor LUT and the right pull-up transistor RUT are connected to the drains of the left pull-down transistor LDT and the right pull-down transistor RDT, respectively, and the connection nodes correspond to the storage nodes Q and QB, respectively;

[0017] The sources of the left access transistor LAT and the right access transistor RAT are connected to the storage nodes Q and QB, respectively;

[0018] The bottom electrode of UR is connected to the top electrode of BR, and the connection node is QZ; the top electrode of UR is connected to the top electrode signal control line TEL of the 2R circuit, and the bottom electrode of BR is connected to the bottom electrode signal control line BEL of the 2R circuit;

[0019] The source of NT and PT is connected to the storage node Q, and the drain is connected to the node QZ; the gate of NT is connected to the control signal TGCL signal line of the transmission gate circuit, and the gate of PT is connected to the control signal TGCL negation signal line of the transmission gate circuit;

[0020] The word line WL is connected to the gates of the left access transistor LAT and the right access transistor RAT, and the left and right bit lines LBL and RBL are connected to the drains of the left access transistor LAT and the right access transistor RAT, respectively.

[0021] It can be seen from the technical solution provided by the present invention that the above circuit adds a non-volatile unit RRAM on the basis of the read, write and retention capabilities of SRAM, so that the SRAM has the ability to maintain data loss during power-off and restore data on power-on, thereby improving the application scenarios of the SRAM circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the structure of an 8T2R non-volatile SRAM unit circuit provided by an embodiment of the present invention;

[0024] Figure 2 Schematic diagram of an array structure and a part of a control circuit composed of an 8T2R non-volatile SRAM unit circuit according to an embodiment of the present invention;

[0025] Figure 3 A circuit schematic diagram of an 8T2R nonvolatile SRAM unit circuit provided in an embodiment of the present invention storing data "0" in an SRAM into an RRAM device;

[0026] Figure 4 A circuit schematic diagram of an 8T2R nonvolatile SRAM unit circuit provided in an embodiment of the present invention storing data "1" in an SRAM into an RRAM device;

[0027] Figure 5A current waveform diagram of an 8T2R non-volatile SRAM cell provided by an embodiment of the present invention when data "0" is stored in an RRAM device in four different initialization states of the non-volatile device;

[0028] Figure 6 A current waveform diagram of the 8T2R non-volatile SRAM cell provided by an embodiment of the present invention when data "1" is stored in the RRAM device in the non-volatile device under four different initialization states;

[0029] Figure 7 A circuit schematic diagram of an 8T2R non-volatile SRAM unit provided in an embodiment of the present invention restoring data in a non-volatile RRAM device to an SRAM;

[0030] Figure 8 A waveform diagram of the 8T2R non-volatile SRAM cell provided by an embodiment of the present invention from storing data into a 2R circuit to restoring data when the initial state of the non-volatile RRAM device is a low-resistance state. DETAILED DESCRIPTION

[0031] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] like Figure 1 The figure shows a schematic diagram of the structure of an 8T2R non-volatile SRAM unit circuit provided by an embodiment of the present invention, where "T" and "R" in 8T2R represent a metal-oxide-semiconductor field-effect transistor (MOSFET) and a resistive random access memory (RRAM), respectively. The circuit includes:

[0033] A nonvolatile data storage circuit composed of two resistive random access memories RRAM includes an upper resistive random access memory (Upper RRAM, abbreviated as UR) and a lower resistive random access memory (Below RRAM, abbreviated as BR), and the nonvolatile data storage circuit is called a 2R circuit; in the specific implementation, the present embodiment adopts a bipolar RRAM, when the voltage V between the top electrode (Top Electrode) and the bottom electrode (Bottom Electrode) TB Greater than the SET voltage of the RRAM (V SET), the resistance changes from High Resistance State (HRS) to Low Resistance State (LRS); when V TB Less than the RRAM RESET voltage (V RESET ), the resistance value changes from LRS to HRS;

[0034] exist Figure 1 The 2R circuit is connected to the storage node Q of the SRAM by a transmission gate circuit consisting of an N-type MOSFET and a P-type MOSFET, where the N-type MOSFET is denoted as NT and the P-type MOSFET is denoted as PT;

[0035] Two P-type MOSFETs and two N-type MOSFETs form two inverters, and the two inverters are connected head to tail to form a bistable storage unit circuit, wherein the upper left and upper right P-type MOSFETs are respectively recorded as a left pull-up transistor (Left Pull-Up Transistor, abbreviated as LUT) and a right pull-up transistor (Right Pull-Up Transistor, abbreviated as RUT), and the lower left and lower right N-type MOSFETs are respectively recorded as a left pull-down transistor (Left Pull-Down Transistor, abbreviated as LDT) and a right pull-down transistor (Right Pull-Down Transistor, abbreviated as RDT);

[0036] The N-type MOSFETs on the left and right sides of the bistable memory cell circuit are access transistors of the storage node of the memory circuit, and are respectively denoted as the left access transistor (Left Access Transistor, abbreviated as LAT) and the right access transistor (Right Access Transistor, abbreviated as RAT);

[0037] The left pull-up transistor LUT, the right pull-up transistor RUT, the left pull-down transistor LDT, the right pull-down transistor RDT, the left access transistor LAT and the right access transistor RAT constitute a 6T-SRAM storage cell of a bistable structure;

[0038] in:

[0039] The power source VDD is connected to the source electrodes of the left pull-up transistor LUT and the right pull-up transistor RUT;

[0040] The ground line VSS is connected to the source electrodes of the left pull-down transistor LDT and the right pull-down transistor RDT;

[0041] The gates of the left pull-up transistor LUT and the right pull-up transistor RUT are connected to the gates of the left pull-down transistor LDT and the right pull-down transistor RDT, respectively, and the connection nodes correspond to the storage nodes QB and Q, respectively;

[0042] The drains of the left pull-up transistor LUT and the right pull-up transistor RUT are connected to the drains of the left pull-down transistor LDT and the right pull-down transistor RDT, respectively, and the connection nodes correspond to the storage nodes Q and QB, respectively;

[0043] The sources of the left access transistor LAT and the right access transistor RAT are connected to the storage nodes Q and QB, respectively;

[0044] The bottom electrode of UR is connected to the top electrode of BR, and the connection node is QZ; the top electrode of UR is connected to the top electrode signal line (Top Electrode Line, abbreviated as TEL) of the 2R circuit, and the bottom electrode of BR is connected to the bottom electrode signal line (Bottom Electrode Line, abbreviated as BEL) of the 2R circuit;

[0045] The source of NT and PT is connected to the storage node Q, and the drain is connected to the node QZ; the gate of NT is connected to the control signal line of the transmission gate circuit (Transmission Gate Control Signal Line, abbreviated as TGCL), and the gate of PT is connected to Connected;

[0046] The word line (Word Line, abbreviated as WL) is connected to the gates of the left access transistor LAT and the right access transistor RAT, and the left bit line (Left Bit Line, abbreviated as LBL) and the right bit line (Right Bit Line, abbreviated as RBL) are connected to the drains of LAT and RAT respectively.

[0047] Based on the above circuit structure, when performing storage operation:

[0048] The data in the inverter storage node is written into the 2R circuit, at which time the word line WL is at a low level and TGCL is at a high level;

[0049] If the data in the storage node Q is "0", the operation of storing "0" is as follows:

[0050] In the first step, the control lines TEL and BEL at both ends of the 2R circuit are set to a high level, and the node QZ in the 2R circuit is at a low level under the action of the storage node Q. At this time, UR is SET operated, and the resistance state is changed to a low resistance state LRS; BR is RESET operated, and the resistance state is changed to a high resistance state HRS;

[0051] In the second step, the control lines TEL and BEL at both ends of the 2R circuit are set to a low level, and the node QZ in the 2R circuit is at a low level under the action of the storage node Q. At this time, the resistance state of UR does not change and remains in the low resistance state LRS; the resistance state of BR does not change and remains in the high resistance state HRS, and the "0" storage operation is completed;

[0052] If the data in the storage node Q is "1", the operation of storing "1" is as follows:

[0053] In the first step, the two RRAMs in the 2R circuit, namely UR and BR, do not change their resistance state;

[0054] In the second step, UR in the 2R circuit changes to a high-resistance state HRS, and BR changes to a low-resistance state LRS, and the "1" storage operation is completed;

[0055] Among them, when UR in the 2R circuit is in the low resistance state LRS and BR is in the high resistance state HRS, it means that the stored data is "0"; when UR in the 2R circuit is in the high resistance state HRS and BR is in the low resistance state LRS, it means that the stored data is "1".

[0056] In addition, when performing a recovery operation based on the circuit:

[0057] At this time, the control line TEL is set to a low level, the control line BEL is set to a high level, the control signal TGCL signal line of the transmission gate circuit is a high level, and the storage nodes Q and QB are in a high impedance state HRS;

[0058] When the data stored in the 2R circuit is "0", UR is in the low resistance state LRS, BR is in the high resistance state HRS, and the voltage on the node QZ is V RESET / 11, V RESET is the RESET voltage of RRAM; this voltage acts on the storage node Q after passing through the transmission gate circuit composed of NT and PT, turning on the right pull-up transistor RUT and turning off RDT; then the power supply VDD acts on the source of the left pull-up transistor LUT and the right pull-up transistor RUT, the storage node QB is pulled up to a high level by RUT, then the left pull-up transistor LUT is turned off, RDT is turned on, and the storage node Q is pulled down to a low level by RDT;

[0059] After the recovery is successful, the TGCL signal line is set to a low level, and the circuit can perform normal SRAM read and write hold operations;

[0060] When performing a write operation, assuming that a write "1" operation is performed on the circuit, the TGCL signal line is at a low level, the word line WL is at a high level, and the write circuit is enabled to set the left bit line LBL to a high level and the right bit line RBL to a low level. At this time, the storage nodes Q and QB are set to a high level and a low level under the voltage of the left and right bit lines LBL and RBL. At the same time, the bistable structure composed of the left pull-up transistor LUT, the right pull-up transistor RUT, the left pull-down transistor LDT and the right pull-down transistor RDT further stabilizes the high level of the storage node Q and the low level of the storage node QB, and the write "1" operation is completed;

[0061] When performing a read operation, the TGCL signal line is at a low level. Assuming that the data stored in the circuit is "1", LBL and RBL are first precharged to a high level, and then WL is set to a high level. At this time, LBL is maintained at a high level by the high level of the storage node Q, and RBL is set to a low level by the storage node QB; thereby, the voltage of the storage node in the cell is read to the bit line, and the pre-read "1" operation is completed;

[0062] When the hold operation is performed, the TGCL signal line is at a low level, the word line WL is at a low level, and the stored data will be stably stored in the storage node under the action of the bistable structure composed of two inverters.

[0063] In a specific implementation, the circuit can be used to form an array structure, such as Figure 2 FIG. 1 is a schematic diagram of an array structure and a partial control circuit composed of an 8T2R non-volatile SRAM unit circuit according to an embodiment of the present invention, wherein:

[0064] The drain of the left access transistor LAT in all SRAM unit circuits in one column of the array structure is connected to the left bit line LBL of the array, and the drain of RAT is connected to the right bit line RBL of the array; the gate of NT is connected to the TGCL signal line of the array, and the gate of PT is connected to the TGCL negation signal line of the array;

[0065] The control lines TEL and BEL are connected to a three-state NOT gate respectively, where:

[0066] The enable ends of the two tri-state NOT gates are connected to form an enable end EN of the signal on a column of control lines TEL and BEL. The input end of the tri-state NOT gate connected to the control line TEL is TE, and the input end of the tri-state NOT gate connected to the control line BEL is BE.

[0067] When the above array structure is used to perform read, write, store, and restore operations, the truth table of the memory array operation is shown in Table 1 below:

[0068] Table 1

[0069]

[0070]

[0071] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to professional and technical personnel in the field.

[0072] In order to more clearly demonstrate the technical solution and the technical effects provided by the present invention, the circuit according to the embodiment of the present invention is described in detail below with reference to the accompanying drawings, specifically including:

[0073] like Figure 3 The circuit schematic diagram of the 8T2R non-volatile SRAM unit circuit provided by the embodiment of the present invention stores the data "0" in the SRAM into the RRAM device. In the "0" operation Step 1, i UR 、i BR Represent the current on UR and BR respectively, and the corresponding light gray dashed line with arrow and dark gray dashed line indicate the current direction, such as Figure 3 As shown in the second step circuit diagram, at this time, the two RRAM devices in the 2R circuit maintain the resistance state of the first step because the voltages of TEL, BEL and node Q are "0".

[0074] like Figure 4 The figure shows a circuit schematic diagram of the 8T2R non-volatile SRAM unit circuit provided by an embodiment of the present invention storing data "1" in the SRAM into the RRAM device. The first step circuit diagram shows that at this time, the two RRAM devices in the 2R circuit are both kept in the initial resistance state because the voltages of TEL, BEL and node Q are "1".

[0075] like Figure 5 FIG. 4 is a current waveform diagram of the 8T2R nonvolatile SRAM cell provided by an embodiment of the present invention when data “0” is stored in the RRAM device in the nonvolatile device under four different initialization states, as shown in FIG. Figure 6 The figure shows the current waveform diagram of the 8T2R non-volatile SRAM unit provided by the embodiment of the present invention when the data "1" is stored in the RRAM device in the non-volatile device under four different initialization states, wherein (a) is the voltage signal waveform of TEL and BEL, (b), (c), (d), and (e) respectively show the simulation waveform diagrams of the storage "0" operation and the storage "1" operation of the 2R circuit in the 8T2R non-volatile memory cell circuit when the initialization states of UR and BR in the 2R circuit are LRS and LRS, LRS and HRS, HRS and LRS, and HRS and HRS, respectively. Figure 5The grey curves in (b), (c), (d), and (e) are the current waveforms in BR, and the black curve is the current waveform in UR; the current waveform of BR in the grey dotted box indicates that BR is RESET to HRS, and the current waveform of UR in the black dotted box indicates that UR is SET to LRS. Figure 6 In (b), (c), (d), and (e), the gray curve is the current waveform in BR, and the black curve is the current waveform in UR; the current waveform of BR in the gray dotted box indicates that BR is SET to LRS, and the current waveform of UR in the black dotted box indicates that UR is RESET to HRS.

[0076] like Figure 7 FIG. 1 is a circuit schematic diagram of an 8T2R nonvolatile SRAM unit provided by an embodiment of the present invention for restoring data in a nonvolatile RRAM device to an SRAM. Figure 7 In the example, TEL is at a low level, BEL is at a high level, TGCL is at a high level, and VDD_4T becomes a high level after the 2R circuit works for a period of time, while TGCL is set to a low level.

[0077] like Figure 8 FIG. 1 is a waveform diagram of the 8T2R nonvolatile SRAM cell provided by the embodiment of the present invention, from data storage into the 2R circuit to data recovery when the initial state of the nonvolatile RRAM device is LRS. Figure 8 When the initial states Q=0 and Q=1 in the 8T2R nonvolatile SRAM cell, the voltage changes thereon show that the 8T2R nonvolatile SRAM cell completes data preservation and recovery.

[0078] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. An 8T2R non-volatile SRAM unit circuit, characterized in that: The circuit comprises: A non-volatile data storage circuit composed of two resistive random access memories RRAM, including an upper resistive random access memory UR and a lower resistive random access memory BR, is called a 2R circuit; The 2R circuit is connected to the storage node Q of the SRAM by a transmission gate circuit consisting of an N-type MOSFET and a P-type MOSFET, where the N-type MOSFET is denoted as NT and the P-type MOSFET is denoted as PT; Two P-type MOSFETs and two N-type MOSFETs form two inverters, and the two inverters are connected end to end to form a bistable storage unit circuit, wherein the upper left and upper right P-type MOSFETs are respectively recorded as left pull-up transistors LUT and right pull-up transistors RUT, and the lower left and lower right N-type MOSFETs are respectively recorded as left pull-down transistors LDT and right pull-down transistors RDT; The N-type MOSFETs on the left and right sides of the bistable memory cell circuit are access transistors of the storage node of the memory circuit, and are respectively denoted as the left access transistor LAT and the right access transistor RAT; The left pull-up transistor LUT, the right pull-up transistor RUT, the left pull-down transistor LDT, the right pull-down transistor RDT, the left access transistor LAT and the right access transistor RAT constitute a 6T-SRAM storage cell of a bistable structure; in: The power source VDD is connected to the source electrodes of the left pull-up transistor LUT and the right pull-up transistor RUT; The ground line VSS is connected to the source electrodes of the left pull-down transistor LDT and the right pull-down transistor RDT; The gates of the left pull-up transistor LUT and the right pull-up transistor RUT are connected to the gates of the left pull-down transistor LDT and the right pull-down transistor RDT, respectively, and the connection nodes correspond to the storage nodes QB and Q, respectively; The drains of the left pull-up transistor LUT and the right pull-up transistor RUT are connected to the drains of the left pull-down transistor LDT and the right pull-down transistor RDT, respectively, and the connection nodes correspond to the storage nodes Q and QB, respectively; The sources of the left access transistor LAT and the right access transistor RAT are connected to the storage nodes Q and QB, respectively; The bottom electrode of UR is connected to the top electrode of BR, and the connection node is QZ; the top electrode of UR is connected to the top electrode signal control line TEL of the 2R circuit, and the bottom electrode of BR is connected to the bottom electrode signal control line BEL of the 2R circuit; The source of NT and PT is connected to the storage node Q, and the drain is connected to the node QZ; the gate of NT is connected to the control signal TGCL signal line of the transmission gate circuit, and the gate of PT is connected to the control signal TGCL negation signal line of the transmission gate circuit; The word line WL is connected to the gates of the left access transistor LAT and the right access transistor RAT, and the left and right bit lines LBL and RBL are connected to the drains of the left access transistor LAT and the right access transistor RAT, respectively.

2. The 8T2R non-volatile SRAM unit circuit according to claim 1, characterized in that: When performing storage operations based on the circuit: The data in the inverter storage node is written into the 2R circuit, at which time the word line WL is at a low level and the control signal TGCL signal line of the transmission gate circuit is at a high level; If the data in the storage node Q is "0", the operation of storing "0" is as follows: In the first step, the control lines TEL and BEL at both ends of the 2R circuit are set to a high level, and the node QZ in the 2R circuit is at a low level under the action of the storage node Q. At this time, UR is SET operated, and the resistance state is changed to a low resistance state LRS; BR is RESET operated, and the resistance state is changed to a high resistance state HRS; In the second step, the control lines TEL and BEL at both ends of the 2R circuit are set to a low level, and the node QZ in the 2R circuit is at a low level under the action of the storage node Q. At this time, the resistance state of UR does not change and remains in the low resistance state LRS; the resistance state of BR does not change and remains in the high resistance state HRS, and the "0" storage operation is completed; If the data in the storage node Q is "1", the operation of storing "1" is as follows: In the first step, the two RRAMs in the 2R circuit, namely UR and BR, do not change their resistance state; In the second step, UR in the 2R circuit changes to a high-resistance state HRS, and BR changes to a low-resistance state LRS, and the "1" storage operation is completed; Among them, when UR in the 2R circuit is in the low resistance state LRS and BR is in the high resistance state HRS, it means that the stored data is "0"; when UR in the 2R circuit is in the high resistance state HRS and BR is in the low resistance state LRS, it means that the stored data is "1".

3. The 8T2R non-volatile SRAM unit circuit according to claim 1, characterized in that: When performing a recovery operation based on the circuit described: At this time, the control line TEL is set to a low level, the control line BEL is set to a high level, the control signal TGCL signal line of the transmission gate circuit is a high level, and the storage nodes Q and QB are in a high impedance state HRS; When the data stored in the 2R circuit is "0", UR is in the low impedance state LRS, BR is in the high impedance state HRS, and the voltage on the node QZ is V RESET / 11, V RESET is the RESET voltage of RRAM; this voltage acts on the storage node Q after passing through the transmission gate circuit composed of NT and PT, turning on the right pull-up transistor RUT and turning off the right pull-down transistor RDT; then the power supply VDD acts on the source of the left pull-up transistor LUT and the right pull-up transistor RUT, the storage node QB is pulled up to a high level by the right pull-up transistor RUT, then the left pull-up transistor LUT is turned off, the right pull-down transistor RDT is turned on, and the storage node Q is pulled down to a low level by the right pull-down transistor RDT; After the recovery is successful, the TGCL signal line is set to a low level, and the circuit can perform normal SRAM read and write hold operations; When performing a write operation, assuming that a write "1" operation is performed on the circuit, the TGCL signal line is at a low level, the word line WL is at a high level, and the write circuit is enabled to set the left bit line LBL to a high level and the right bit line RBL to a low level. At this time, the storage nodes Q and QB are set to a high level and a low level under the voltage of the left and right bit lines LBL and RBL. At the same time, the bistable structure composed of the left pull-up transistor LUT, the right pull-up transistor RUT, the left pull-down transistor LDT and the right pull-down transistor RDT further stabilizes the high level of the storage node Q and the low level of the storage node QB, and the write "1" operation is completed; When performing a read operation, the TGCL signal line is at a low level. Assuming that the data stored in the circuit is "1", LBL and RBL are first precharged to a high level, and then WL is set to a high level. At this time, LBL is maintained at a high level by the high level of the storage node Q, and RBL is set to a low level by the storage node QB; thereby, the voltage of the storage node in the cell is read to the bit line, and the pre-read "1" operation is completed; When the hold operation is performed, the TGCL signal line is at a low level, the word line WL is at a low level, and the stored data will be stably stored in the storage node under the action of the bistable structure composed of two inverters.

4. The 8T2R non-volatile SRAM unit circuit according to claim 1, characterized in that: The circuit is used to form an array structure, wherein: The drain of the left access transistor LAT in all SRAM unit circuits in one column of the array structure is connected to the left bit line LBL of the array, and the drain of the right access transistor RAT is connected to the right bit line RBL of the array; the gate of NT is connected to the TGCL signal line of the array, and the gate of PT is connected to the TGCL negation signal line of the array; The control lines TEL and BEL are connected to a three-state NOT gate respectively, where: The enable ends of the two tri-state NOT gates are connected to form an enable end EN of the signal on a column of control lines TEL and BEL. The input end of the tri-state NOT gate connected to the control line TEL is TE, and the input end of the tri-state NOT gate connected to the control line BEL is BE.

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