Semiconductor memory devices

Abstract

A semiconductor memory device is provided. The device may include: a lower gate line disposed on a substrate and extending along a first direction; an upper gate line perpendicularly overlapping the lower gate line and extending along the first direction; a first capacitor disposed between the lower gate line and the upper gate line; a second capacitor disposed between the lower gate line and the upper gate line and spaced apart from the first capacitor in the first direction; a lower semiconductor pattern configured to pass through the lower gate line and be connected to the first capacitor; an upper semiconductor pattern configured to pass through the upper gate line and be connected to the second capacitor; and a lower insulating pattern disposed between the second capacitor and the lower gate line to cover an entire area of ​​the bottom surface of the second capacitor.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0085543, filed on July 10, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor memory devices, and more specifically, to semiconductor memory devices having improved electrical characteristics and higher reliability. Background Technology

[0004] To meet the growing demand for highly integrated semiconductor devices, metal-oxide-semiconductor (MOSFETs) field-effect transistors are being actively scaled down. However, the reduction in the minimum feature size, or critical size (CD), of semiconductor devices leads to an increase in the resistance of interconnects and the electrostatic capacitance between them, making it difficult to achieve high-speed operation of semiconductor devices. Therefore, various studies are underway to overcome the technical limitations associated with the miniaturization of semiconductor memory devices and to realize semiconductor memory devices with high-performance properties. Summary of the Invention

[0005] Embodiments of the present invention provide semiconductor memory devices with improved electrical characteristics and higher reliability.

[0006] According to an embodiment of the present invention, a semiconductor memory device may include: a lower gate line disposed on a substrate and extending longitudinally along a first direction; an upper gate line perpendicularly overlapping the lower gate line and extending longitudinally along the first direction; a first capacitor disposed between the lower gate line and the upper gate line; a second capacitor disposed between the lower gate line and the upper gate line and spaced apart from the first capacitor in the first direction; a lower semiconductor pattern configured to pass through the lower gate line and connect to the first capacitor; an upper semiconductor pattern configured to pass through the upper gate line and connect to the second capacitor; and a lower insulating pattern disposed between the second capacitor and the lower gate line to cover the entire area of ​​the bottom surface of the second capacitor.

[0007] According to an embodiment of the present invention, a semiconductor memory device may include: a lower gate line disposed on a substrate and extending longitudinally along a first direction; a lower conductive line disposed between the substrate and the lower gate line and extending longitudinally along a second direction perpendicular to the first direction; an upper gate line perpendicularly overlapping the lower gate line and extending longitudinally along the first direction; an upper conductive line disposed on the upper gate line and extending longitudinally along the second direction; a first capacitor disposed between the lower gate line and the upper gate line; and a second capacitor disposed between the lower gate line and the upper gate line. The first conductive line is spaced apart from the first capacitor in the first direction; a lower insulating pattern is disposed between the first capacitor and the lower gate line, and between the second capacitor and the lower gate line; an upper insulating layer is disposed between the first capacitor and the upper gate line, and between the second capacitor and the upper gate line; a lower semiconductor pattern is configured to pass through the lower gate line and the lower insulating pattern, and connect the first capacitor to one of the lower conductive lines; and an upper semiconductor pattern is configured to pass through the upper gate line and the upper insulating layer, and connect the second capacitor to one of the upper conductive lines. The distance between two adjacent lower conductive lines may be greater than the distance between the first capacitor and the second capacitor.

[0008] According to an embodiment of the present invention, a semiconductor memory device may include: a lower gate line disposed on a substrate and extending longitudinally along a first direction; an upper gate line perpendicularly overlapping the lower gate line and extending longitudinally along the first direction; a capacitor located between the lower gate line and the upper gate line, the capacitor including a first electrode and a second electrode located on the first electrode; an upper conductive line disposed on the upper gate line and extending longitudinally along a second direction perpendicular to the first direction; an upper semiconductor pattern configured to pass through the upper gate line and connect the upper conductive line to the second electrode; and a lower insulating pattern disposed between a top surface of the lower gate line and a bottom surface of the first electrode.

[0009] According to an embodiment of the present invention, a semiconductor memory device may include: a lower gate line disposed on a substrate and extending longitudinally along a first direction; a lower conductive line disposed between the substrate and the lower gate line and extending longitudinally along a second direction perpendicular to the first direction; an upper gate line perpendicularly overlapping the lower gate line and extending longitudinally along the first direction; a capacitor disposed between the lower gate line and the upper gate line and spaced apart from each other in the first direction; an oxide semiconductor pattern including a first portion located between the substrate and the lower conductive line and a second portion located between the lower conductive lines; and a lower insulating pattern located between the oxide semiconductor pattern and the lower conductive line. Attached Figure Description

[0010] The exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments described herein.

[0011] Figure 1 This is a perspective view schematically illustrating a portion of a semiconductor memory device according to an exemplary embodiment of the present invention.

[0012] Figure 2 This is a top view illustrating an example embodiment of a semiconductor memory device according to a concept conceived in the present invention.

[0013] Figures 3A to 3C They are respectively along Figure 2 The cross-sectional views taken from lines I-I', II-II', and III-III'.

[0014] Figure 4 This illustrates multiple portions (e.g., corresponding to) an example embodiment of a semiconductor memory device according to a concept of the present invention. Figure 3A Enlarged cross-sectional view of part AA and part BB.

[0015] Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 and Figure 21 This is a top view illustrating a method for manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention.

[0016] Figure 6A , Figure 8A , Figure 10A , Figure 12A , Figure 14A , Figure 16A , Figure 18A , Figure 20A and Figure 22A They are respectively along Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 and Figure 21 The cross-sectional view taken from line I-I'.

[0017] Figure 6B , Figure 8B , Figure 10B , Figure 12B , Figure 14B , Figure 16B , Figure 18B , Figure 20B and Figure 22B They are respectively along Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 and Figure 21 The cross-sectional view taken from line II-II'.

[0018] Figure 23 This illustrates multiple portions (e.g., corresponding to) an example embodiment of a semiconductor memory device according to a concept of the present invention. Figure 3A Enlarged cross-sectional view of part AA and part BB.

[0019] Figure 24 It is along Figure 2 A cross-sectional view taken by line I-I' to illustrate a semiconductor memory device according to an exemplary embodiment of the present invention.

[0020] Figures 25A to 25C They are respectively along Figure 2 The cross-sectional views taken by lines I-I', II-II', and III-III' are shown to illustrate a semiconductor memory device according to an exemplary embodiment of the present invention.

[0021] Figure 26 It is along Figure 2 A cross-sectional view taken by line I-I' to illustrate a semiconductor memory device according to an exemplary embodiment of the present invention. Detailed Implementation

[0022] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments. In the drawings, the same reference numerals consistently denote the same elements.

[0023] Figure 1 This is a perspective view schematically illustrating a portion of a semiconductor memory device according to an exemplary embodiment of the present invention.

[0024] Reference Figure 1 A semiconductor memory device according to an example embodiment of the present invention may include a lower selection region 10, an upper selection region 20, and a data storage region 30 located between the lower selection region 10 and the upper selection region 20.

[0025] The data storage region 30 may include a plurality of capacitors 350. The capacitors 350 may be arranged along a first direction D1 and a second direction D2 parallel to the top surface of the substrate 100. Each capacitor 350 may be combined with either the lower selection region 10 or the upper selection region 20 to form a unit storage cell. If charge is supplied from the lower selection region 10 or the upper selection region 20, each capacitor 350 may store one or more bits of data. To store charge, each capacitor 350 may include a first electrode 354 and a second electrode 352 disposed adjacent to each other.

[0026] The lower selection region 10 may be located below the data storage region 30. The lower selection region 10 may include a lower conductive line 210, a lower gate line 220, and a lower channel structure 310. Both the lower conductive line 210 and the lower gate line 220 may be rod-shaped or cylindrical patterns extending in a specific direction. The lower gate line 220 may extend longitudinally along a first direction D1 parallel to the top surface of the substrate 100. The lower conductive line 210 may extend longitudinally between the lower gate line 220 and the substrate 100 along a second direction D2 parallel to the top surface of the substrate 100. The second direction D2 may be perpendicular to the first direction D1. The lower gate line 220 and the lower conductive line 210 may be spaced apart from each other in a third direction D3 perpendicular to the top surface of the substrate 100. When viewed in a top view, each lower gate line 220 may be configured to intersect with the lower conductive line 210. A term is defined as an item, layer, or part of an item or layer that extends “longitudinally” along a particular direction, having a length in that particular direction and a width perpendicular to that direction, wherein the length is greater than the width.

[0027] A lower channel structure 310 may be disposed between the lower conductive line 210 and the capacitor 350. Each lower channel structure 310 may be configured to pass through the lower gate line 220 and connect a corresponding capacitor 350 to the lower conductive line 210. For example, a portion of the sidewall of the lower channel structure 310 may be surrounded by the lower gate line 220. The lower channel structures 310 located on the lower conductive line 210 may be spaced apart from each other in the second direction D2. For example, the lower selection region 10 may be connected to some of the capacitors 350 arranged along the second direction D2 via the lower channel structure 310. Other capacitors 350 spaced apart from some of the capacitors 350 in the first direction D1 may not be connected to the lower selection region 10.

[0028] Specifically, the lower channel structure 310 may include a lower semiconductor pattern 312 and a lower gate insulating pattern 314. The lower semiconductor pattern 312 may be configured to pass through the lower gate line 220 and connect the lower conductive line 210 to the first electrode 354. A current path may be formed in the lower semiconductor pattern 312 between the lower conductive line 210 and the first electrode 354, depending on the voltage applied to the lower gate line 220. The lower semiconductor pattern 312 may be a frustoconical or cylindrical shape with a downwardly decreasing width. For example, the width of the lower semiconductor pattern 312 may decrease in the direction toward the lower conductive line 210. The lower semiconductor pattern 312 may be formed of at least one of a doped semiconductor material or an oxide semiconductor, or may include at least one of a doped semiconductor material or an oxide semiconductor. The lower gate insulating pattern 314 may be disposed between the lower semiconductor pattern 312 and the lower gate line 220. The lower gate insulating pattern 314 may surround the lower semiconductor pattern 312. The lower gate insulating pattern 314 may serve as a gate insulating layer that electrically disconnects the lower gate line 220 from the lower semiconductor pattern 312.

[0029] The upper selection region 20 can be disposed on the data storage region 30. The upper selection region 20 can be spaced apart from the lower selection region 10 in the third direction D3, and the data storage region 30 is located between the upper selection region 20 and the lower selection region 10. The upper selection region 20 can be connected to a capacitor 350 that is not connected to the lower selection region 10. The upper selection region 20 may include an upper conductive line 240, an upper gate line 230, and an upper channel structure 320. Both the upper conductive line 240 and the upper gate line 230 can be rod-shaped or cylindrical patterns extending in a specific direction.

[0030] The upper gate line 230 may overlap perpendicularly with the lower gate line 220 and may extend along a first direction D1. An upper conductive line 240 may be disposed on the upper gate line 230 and may extend along a second direction D2. When viewed in a top view, the upper conductive line 240 may not overlap with the lower conductive line 210. The upper conductive line 240 may be spaced apart from the lower conductive line 210 in the first direction D1. The upper conductive line 240 and the upper gate line 230 may be spaced apart from each other in a third direction D3.

[0031] An upper channel structure 320 may be disposed between the upper conductive line 240 and the capacitor 350. The upper channel structure 320 may be arranged along a second direction D2. When viewed in a top view, the upper channel structure 320 may not overlap with the lower channel structure 310 and may be spaced apart from the lower channel structure 310 in a first direction D1. The upper channel structure 320 may include an upper semiconductor pattern 322 and an upper gate insulating pattern 324. The upper semiconductor pattern 322 may be configured to pass through the upper gate line 230 and connect the capacitor 350 to the upper conductive line 240. Depending on the voltage applied to the upper gate line 230, a current path may be formed in the upper semiconductor pattern 322 between the upper conductive line 240 and the capacitor 350.

[0032] The upper semiconductor pattern 322 can be a truncated cone or cylinder with a downwardly decreasing width. For example, the width of the upper semiconductor pattern 322 can decrease in the direction toward the capacitor 350. The upper semiconductor pattern 322 can be formed of at least one of a doped semiconductor material or an oxide semiconductor, or include at least one of a doped semiconductor material or an oxide semiconductor. An upper gate insulating pattern 324 can be disposed between the upper semiconductor pattern 322 and the upper gate line 230. The upper gate insulating pattern 324 can surround the upper semiconductor pattern 322. The upper gate insulating pattern 324 can serve as a gate insulating layer that electrically disconnects the upper gate line 230 from the upper semiconductor pattern 322.

[0033] According to an exemplary embodiment of the present invention, a unit memory cell of a semiconductor memory device may consist of a transistor and a capacitor. The lower channel structure 310 and the lower gate line 220 may constitute the lower transistor. The upper channel structure 320 and the upper gate line 230 may constitute the upper transistor. Each capacitor 350 in the data storage region 30 may be selectively connected to one of the lower transistor and the upper transistor. A capacitor 350 connected to the lower transistor may not be connected to the upper transistor, and a capacitor 350 connected to the upper transistor may not be connected to the lower transistor.

[0034] Figure 2 This is a top view illustrating an example embodiment of a semiconductor memory device according to a concept conceived in the present invention. Figure 3A , Figure 3B and Figure 3CThey are respectively along Figure 2 The cross-sectional views are taken from lines I-I', II-II', and III-III'. For the sake of brevity, the previous references are... Figure 1 The described elements may be identified by the same reference numerals without repeating their description.

[0035] Reference Figure 2 as well as Figures 3A to 3C A first lower insulating layer 102 and a second lower insulating layer 112 may be disposed on a substrate 100. The bottom surface of the first lower insulating layer 102 may contact the top surface of the substrate 100, and the bottom surface of the second lower insulating layer 112 may contact the top surface of the first lower insulating layer 102. The substrate 100 may include at least one of a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The first lower insulating layer 102 and the second lower insulating layer 112 may include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer. As used herein, the term "contact" means directional connection (i.e., touching), unless the context otherwise indicates.

[0036] The lower conductive line 210 can be disposed on the first lower insulating layer 102. The bottom surface of the lower conductive line 210 can contact the top surface of the first lower insulating layer 102. The lower conductive line 210 can extend longitudinally along the second direction D2 and can be spaced apart from each other in the first direction D1. The side surface of the lower conductive line 210 can be covered by the second lower insulating layer 112. For example, the second lower insulating layer 112 can contact the side surface of the lower conductive line 210. The top surface of the lower conductive line 210 can be located at the same vertical height as the top surface of the second lower insulating layer 112. The lower conductive line 210 can be formed of at least one conductive material, or include at least one conductive material. For example, the conductive material can be one of the following: doped semiconductor materials (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metallic materials (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0037] The lower conductive lines 210 can be spaced apart from each other by a distance greater than the distance between the capacitors 350. Specifically, two adjacent lower conductive lines 210 can be spaced apart from each other by a first distance ds1 in the first direction D1, and two adjacent capacitors 350 can be spaced apart from each other by a second distance ds2 in the first direction D1. The first distance ds1 can be greater than the second distance ds2. For example, the first distance ds1 can be more than twice the second distance ds2. Furthermore, the first distance ds1 can be two or more times the width of the capacitors 350 in the first direction D1.

[0038] The lower conductive line 210 can be positioned below some of the capacitors 350 arranged along the second direction D2, such as... Figure 3BAs shown. The lower conductive line 210 can be commonly connected to a plurality of capacitors 350 stacked perpendicular to the lower conductive line 210 via a lower channel structure 310 arranged along the second direction D2. The lower conductive line 210 may not be located below some of the capacitors 350 arranged along the second direction D2, such as... Figure 3C As shown.

[0039] A third lower insulating layer 132 may be disposed on the lower conductive line 210 and the second lower insulating layer 112. The bottom surface of the third lower insulating layer 132 may be at the same vertical height as the bottom surface of the lower channel structure 310. The third lower insulating layer 132 may be disposed between the lower conductive line 210 and the lower gate line 220 to electrically disconnect them from each other. The third lower insulating layer 132 may extend along the first direction D1 and the second direction D2 to completely cover the top surface of the lower conductive line 210 and the top surface of the second lower insulating layer 112. The third lower insulating layer 132 may include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0040] A fourth lower insulating layer 142 may be disposed on the third lower insulating layer 132. For example, the bottom surface of the fourth lower insulating layer 142 may contact the top surface of the third lower insulating layer 132. The fourth lower insulating layer 142 may have a lower trench 143 extending longitudinally along a first direction D1. The lower trench 143 may be arranged along a second direction D2 and may be disposed below the capacitor 350. The fourth lower insulating layer 142 may include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0041] The lower gate line 220 may be disposed in the fourth lower insulating layer 142. For example, the bottom surface of the lower gate line 220 may contact the top surface of the third lower insulating layer 132. The lower gate line 220 may be perpendicularly spaced from the lower conductive line 210. The lower gate line 220 may be disposed in the lower trench 143 and may extend longitudinally along the first direction D1. The lower gate lines 220 may be spaced apart from each other in the second direction D2. The lower gate line 220 may be formed of at least one conductive material, or may include at least one conductive material. For example, the conductive material may be one of the following: doped semiconductor material (doped silicon, doped germanium, etc.), conductive metal nitride (titanium nitride, tantalum nitride, etc.), metallic material (tungsten, titanium, tantalum, etc.), and metal semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0042] The lower gate lines 220 can be spaced apart from each other by a distance smaller than the distance between the lower conductive lines 210. Specifically, the distance ds4 between two adjacent lower gate lines 220 in the second direction D2 can be smaller than the distance ds1 between two adjacent lower conductive lines 210 in the first direction D1. In an example embodiment, the lower gate lines 220 can be disposed below all the capacitors 350.

[0043] A lower insulating pattern 222 may be disposed on the lower gate line 220. For example, the bottom surface of the lower insulating pattern 222 may contact the top surface of the lower gate line 220. The lower insulating pattern 222 may be a cover pattern formed to fill the upper portion of the lower trench 143, thereby electrically disconnecting the lower gate line 220 from the first electrode 354 of the capacitor 350. The lower insulating pattern 222 may include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer. The lower insulating pattern 222 may fill the remaining area of ​​the lower trench 143 that is partially filled by the lower gate line 220. The top surface of the lower insulating pattern 222 may be located at the same vertical height as the top surface of the fourth lower insulating layer 142 and the top surface of the lower channel structure 310. The lower insulating pattern 222 may extend longitudinally along a first direction D1 and may be arranged in a second direction D2.

[0044] An interlayer insulating layer 150 may be disposed on the fourth lower insulating layer 142 and the lower insulating pattern 222. For example, the bottom surface of the interlayer insulating layer 150 may contact the top surface of the fourth lower insulating layer 142 and the top surface of the lower insulating pattern 222. The thickness of the interlayer insulating layer 150 in the third direction D3 may be thicker than the thickness of the first to fourth lower insulating layers 102, 112, 132 and 142 in the third direction D3. The interlayer insulating layer 150 may have a vertical hole 151 formed therethrough. The vertical hole 151 may be arranged in the first direction D1 and the second direction D2.

[0045] A capacitor 350 may be disposed in a vertical hole 151 of the interlayer insulating layer 150. The capacitor 350 may be disposed between the lower gate line 220 and the upper gate line 230, and may perpendicularly overlap with the lower gate line 220 and the upper gate line 230. The capacitor 350 may be disposed on the lower gate line 220 and may extend along a third direction D3. When viewed in a top view, the capacitor 350 may be disposed at the intersection of the lower conductive line 210 and the lower gate line 220 or at the intersection of the upper conductive line 240 and the upper gate line 230. Each capacitor 350 may include a first electrode 354, a dielectric layer 356, and a second electrode 352.

[0046] A portion of the first electrode 354 can be connected to the lower conductive line 210 via the lower channel structure 310. This portion of the first electrode 354 can receive charge from the lower conductive line 210 via the lower semiconductor pattern 312 of the lower channel structure 310. The second electrode 352 can be configured to fill the internal space of the first electrode 354.

[0047] Both the first electrode 354 and the second electrode 352 may be formed of at least one of a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a doped semiconductor material (e.g., doped silicon or doped germanium), or may include at least one of the aforementioned materials. The dielectric layer 356 may be formed of a high-k dielectric material (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof), or may include a high-k dielectric material.

[0048] The dielectric layer 356 can cover the top surface and inner surface of the first electrode 354, and can contact the top surface and inner surface of the first electrode 354. The dielectric layer 356 can cover the lower surface and side surface of the second electrode 352, and can contact the lower surface and side surface of the second electrode 352.

[0049] The first upper insulating layer 162 can be configured to cover the interlayer insulating layer 150 and the capacitor 350. For example, the bottom surface of the first upper insulating layer 162 can contact the top surface of the interlayer insulating layer 150 and the top surface of the capacitor 350. The bottom surface of the first upper insulating layer 162 can be at the same vertical height as the bottom surface of the upper channel structure 320. The first upper insulating layer 162 can be disposed between the upper gate line 230 and the capacitor 350 to electrically disconnect them from each other.

[0050] The second upper insulating layer 172 may be disposed on the first upper insulating layer 162. For example, the bottom surface of the second upper insulating layer 172 may contact the top surface of the first upper insulating layer 162. The second upper insulating layer 172 may include an upper trench 173 extending longitudinally along the first direction D1.

[0051] The upper gate line 230 can be disposed in the upper trench 173. The upper gate lines 230 can be spaced apart from each other in the second direction D2 and can extend longitudinally along the first direction D1. The upper gate lines 230 can be formed of at least one conductive material, or include at least one conductive material. For example, the conductive material can be one of the following: doped semiconductor material (doped silicon, doped germanium, etc.), conductive metal nitride (titanium nitride, tantalum nitride, etc.), metal material (tungsten, titanium, tantalum, etc.), and metal semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0052] An upper insulating pattern 232 may be disposed on the upper gate line 230. The upper insulating pattern 232 may be a cover pattern formed to fill the upper portion of the upper trench 173, thereby electrically disconnecting the upper gate line 230 from the upper conductive line 240. The upper insulating pattern 232 may include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer. The upper insulating pattern 232 may fill the remaining area of ​​the upper trench 173, which is partially filled by the upper gate line 230. The top surface of the upper insulating pattern 232 may be located at the same vertical height as the top surface of the second upper insulating layer 172 and the top surface of the upper channel structure 320. The upper insulating pattern 232 may extend longitudinally along a first direction D1 and may be arranged in a second direction D2.

[0053] A third upper insulating layer 182 may be disposed on the upper insulating pattern 232 and the second upper insulating layer 172. For example, the bottom surface of the third upper insulating layer 182 may contact the top surface of the upper insulating pattern 232 and the top surface of the second upper insulating layer 172. The third upper insulating layer 182 may cover the side surface of the upper conductive line 240 to contact the side surface of the upper conductive line 240. The third upper insulating layer 182 may include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0054] Figure 4 This illustrates multiple portions (e.g., corresponding to) an example embodiment of a semiconductor memory device according to a concept of the present invention. Figure 3A Enlarged cross-sectional view of parts AA and BB.

[0055] Reference Figure 3A and Figure 4 The capacitor 350 may include a first capacitor 3501 connected to the lower channel structure 310 and a second capacitor 3502 connected to the upper channel structure 320. The first capacitor 3501 and the second capacitor 3502 may be disposed between the lower gate line 220 and the upper gate line 230. The first capacitor 3501 and the second capacitor 3502 may be spaced apart from each other in a first direction D1 or in the extension direction of the lower gate line 220. The first capacitor 3501 and the second capacitor 3502 may overlap perpendicularly with the lower gate line 220 and the upper gate line 230.

[0056] The first electrode 354 of the first capacitor 3501 can be connected to the lower conductive line 210 via the lower semiconductor pattern 312 of the lower channel structure 310. Furthermore, the top surface 352t of the second electrode 352 of the first capacitor 3501 can be completely covered by the first upper insulating layer 162. The second electrode 352 of the second capacitor 3502 can be connected to the upper conductive line 240 via the upper semiconductor pattern 322 of the upper channel structure 320. Furthermore, the bottom surface 352b of the first electrode 354 of the second capacitor 3502 can be completely covered by the lower insulating pattern 222.

[0057] Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 and Figure 21 This is a top view illustrating a method for manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention. Figure 6A , Figure 8A , Figure 10A , Figure 12A , Figure 14A , Figure 16A , Figure 18A , Figure 20A and Figure 22A They are respectively along Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 and Figure 21 The cross-sectional view taken from line I-I'. Figure 6B , Figure 8B , Figure 10B , Figure 12B , Figure 14B , Figure 16B , Figure 18B , Figure 20B and Figure 22B They are respectively along Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 and Figure 21 The cross-sectional view taken from line II-II'.

[0058] Reference Figure 5 , Figure 6A and Figure 6B A first lower insulating layer 102 may be formed on the substrate 100, and a lower conductive line 210 may be formed on the first lower insulating layer 102. The first lower insulating layer 102 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer. The formation of the lower conductive line 210 may include forming a metal layer to cover the first lower insulating layer 102 and patterning the metal layer.

[0059] Reference Figure 7 , Figure 8A and Figure 8BA second lower insulating layer 112, a third lower insulating layer 132, and a fourth lower insulating layer 142 can be formed. The formation of the second lower insulating layer 112 may include: forming an insulating layer to cover the side and top surfaces of the lower conductive line 210; and removing a portion of the insulating layer such that the top surface of the insulating layer is at the same height as the top surface of the lower conductive line 210. The third lower insulating layer 132 can be formed to cover the top surface of the lower conductive line 210 and the top surface of the second lower insulating layer 112. The third lower insulating layer 132 can be formed to have a smaller thickness than the second lower insulating layer 112. Thickness may refer to the thickness or height measured in a direction perpendicular to the top surface of the substrate 100 (e.g., third direction D3).

[0060] A fourth lower insulating layer 142 may be formed on the third lower insulating layer 132. The formation of the fourth lower insulating layer 142 may include: forming an insulating layer to cover the third lower insulating layer 132; and patterning the insulating layer to form a lower trench 143 extending along the first direction D1.

[0061] Subsequently, a first sacrificial pattern 221 may be formed in the lower trench 143 of the fourth lower insulating layer 142. The first sacrificial pattern 221 may be formed of, or include, at least one material having etch selectivity relative to the third lower insulating layer 132 and the fourth lower insulating layer 142. As an example, the third lower insulating layer 132 and the fourth lower insulating layer 142 may be formed of silicon oxide, and the first sacrificial pattern 221 may be formed of or include silicon nitride.

[0062] Reference Figure 9 , Figure 10A and Figure 10B A second sacrificial pattern 311 may be formed on the lower conductive line 210. The second sacrificial pattern 311 may be formed to pass through the first sacrificial pattern 221 and the third lower insulating layer 132, and to contact the top surface of the lower conductive line 210. The top surface of the second sacrificial pattern 311 may be at the same vertical height as the top surface of the fourth lower insulating layer 142 and the top surface of the first sacrificial pattern 221. The second sacrificial pattern 311 may be a truncated cone or cylinder with a downwardly decreasing width. The second sacrificial pattern 311 may be formed of, or include, at least one material selected to have etch selectivity relative to the first sacrificial pattern 221. As an example, the first sacrificial pattern 221 may be formed of or include silicon nitride, and the second sacrificial pattern 311 may be formed of or include silicon oxide.

[0063] Reference Figure 11 , Figure 12A and Figure 12BThe first sacrificial pattern 221 can be removed. Since the first sacrificial pattern 221 has been removed, the inner surface of the lower trench 143 and the side surface of the second sacrificial pattern 311 can be exposed.

[0064] Reference Figure 13 , Figure 14A and Figure 14B The lower gate line 220 and the lower channel structure 310 can be formed in the lower trench 143.

[0065] A lower gate line 220 may be formed in the lower trench 143. The formation of the lower gate line 220 may include performing a deposition process to form a conductive layer filling the lower trench 143; and performing an etching process to partially remove the conductive layer.

[0066] Subsequently, a lower channel hole 313 can be formed in the lower gate line 220 and the third lower insulating layer 132 by removing the second sacrificial pattern 311. The lower channel hole 313 may have a downwardly decreasing width.

[0067] A lower gate insulating pattern 314 can be formed to conformally cover the inner surface of the lower channel hole 313, and a lower semiconductor pattern 312 can be formed to fill the remaining area of ​​the lower channel hole 313. The lower semiconductor pattern 312 can be formed using a deposition process. The deposition process for forming the lower semiconductor pattern 312 can include, for example, one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). In an exemplary embodiment of the invention, a doping process can be performed during the deposition process to form the lower semiconductor pattern 312. For example, the doping process can be performed in situ in the same chamber as the chamber used for the deposition process. In an exemplary embodiment of the invention, the lower semiconductor pattern 312 can be formed of, or comprise, undoped semiconductor material or intrinsic semiconductor material. In this case, the doping process can be omitted.

[0068] Reference Figure 15 , Figure 16A and Figure 16B A portion of the lower gate line 220 can be recessed, allowing a lower insulating pattern 222 to be formed in the lower trench 143. Due to the partial recess of the lower gate line 220, the top surface of the lower gate line 220 can be located at a vertical height lower than the top surface of the fourth lower insulating layer 142. The lower insulating pattern 222 can be formed in the upper portion of the lower trench 143. The lower insulating pattern 222 can extend longitudinally along a first direction D1 and can be arranged in a second direction D2. The lower insulating pattern 222 can be formed to fill the remaining area of ​​the lower trench 143, and the top surface of the lower insulating pattern 222 can be located at the same vertical height as the top surface of the fourth lower insulating layer 142.

[0069] Reference Figure 17 , Figure 18A and Figure 18B An interlayer insulating layer 150 can be formed on the fourth lower insulating layer 142. Then, an etching process can be performed on the interlayer insulating layer 150 to form vertical vias 151 passing through the interlayer insulating layer 150 along a third direction D3. The vertical vias 151 can be arranged on the lower gate line 220. Some vertical vias 151 can perpendicularly overlap with the lower conductive line 210, while others may not. Vertical vias 151 perpendicularly overlapping with the lower conductive line 210 can be formed to expose the top surface of the lower channel structure 310. Vertical vias 151 not perpendicularly overlapping with the lower conductive line 210 can expose the top surface of the lower insulating pattern 222.

[0070] Reference Figure 19 , Figure 20A and Figure 20B A capacitor 350 can be formed in the vertical hole 151. Each capacitor 350 may include a first electrode 354 conformally covering the inner surface of the vertical hole 151, a second electrode 352 inserted into the first electrode 354, and a dielectric layer 356 between the first electrode 354 and the second electrode 352.

[0071] Reference Figure 21 , Figure 22A and Figure 22B A first upper insulating layer 162 can be formed on the capacitor 350 and the interlayer insulating layer 150. The first upper insulating layer 162 can be formed to completely cover the top surface of the capacitor 350 and the top surface of the interlayer insulating layer 150.

[0072] Next, a second upper insulating layer 172 can be formed, and then an upper gate line 230 and an upper channel structure 320 can be formed in the second upper insulating layer 172. The distance between the top and bottom surfaces of the upper gate insulating pattern 324 can be greater than the thickness of the upper gate line 230. This can be achieved by referring to a reference... Figures 7 to 14B The same method described for the lower gate line 220 and the lower channel structure 310 is used to perform the process for forming the upper gate line 230 and the upper channel structure 320.

[0073] Return to reference Figure 2 , Figure 3A , Figure 3B and Figure 3CA third upper insulating layer 182 can be formed, and an upper conductive line 240 can be formed in the third upper insulating layer 182. Before forming the third upper insulating layer 182 and the upper conductive line 240, an upper insulating pattern 232 can be formed on the upper gate line 230. The upper insulating pattern 232 can be formed to fill the upper portion of the upper trench 173. Next, the third upper insulating layer 182 and the upper conductive line 240 can be formed on the top surface of the upper insulating pattern 232 and the top surface of the second upper insulating layer 172. In an example embodiment, the third upper insulating layer 182 can be formed by performing a deposition process on the top surface of the upper insulating pattern 232 and the top surface of the second upper insulating layer 172. Afterwards, the upper conductive line 240 can be formed in the third upper insulating layer 182. In some embodiments, the upper conductive line 240 can be formed before forming the third upper insulating layer 182.

[0074] Figure 23 This illustrates multiple portions (e.g., corresponding to) an example embodiment of a semiconductor memory device according to a concept of the present invention. Figure 3A Enlarged cross-sectional views of portions AA and BB. For the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their descriptions.

[0075] Reference Figure 23 The lower semiconductor pattern 312 may be formed of at least one of silicon, germanium, or silicon-germanium, or may include at least one of silicon, germanium, or silicon-germanium. The lower semiconductor pattern 312 may include a first lower impurity region 316, a second lower impurity region 318, and a lower channel region 317. The lower portion of the lower channel region 317 may be connected to the first lower impurity region 316, and the upper portion of the lower channel region 317 may be connected to the second lower impurity region 318.

[0076] The first lower impurity region 316 can contact the top surface of the lower conductive line 210, and the top surface of the second lower impurity region 318 can contact the bottom surface of the first electrode 354. The first lower impurity region 316 can serve as one of the source region and the drain region, and the second lower impurity region 318 can serve as the other of the source region and the drain region. The first lower impurity region 316 and the second lower impurity region 318 can have a higher impurity concentration than the impurity concentration of the lower channel region 317. The first lower impurity region 316 and the second lower impurity region 318 can be of n-conductivity type or p-conductivity type.

[0077] The upper semiconductor pattern 322 may be formed of at least one of silicon, germanium, or silicon-germanium, or may include at least one of silicon, germanium, or silicon-germanium. The upper semiconductor pattern 322 may include a first upper impurity region 326, a second upper impurity region 328, and an upper channel region 327. The lower portion of the upper channel region 327 may be connected to the first upper impurity region 326, and the upper portion of the upper channel region 327 may be connected to the second upper impurity region 328.

[0078] The first upper impurity region 326 can contact the top surface of the second electrode 352, and the top surface of the second upper impurity region 328 can contact the bottom surface of the upper conductive line 240. The first upper impurity region 326 can serve as one of the source region and the drain region, and the second upper impurity region 328 can serve as the other of the source region and the drain region. The first upper impurity region 326 and the second upper impurity region 328 can have a higher impurity concentration than the impurity concentration of the upper channel region 327. The first upper impurity region 326 and the second upper impurity region 328 can be of n-conductivity type or p-conductivity type.

[0079] Each of the first upper impurity region 326, the upper channel region 327, and the second upper impurity region 328 may be formed of or comprise the same material as a corresponding one of the first lower impurity region 316, the lower channel region 317, and the second lower impurity region 318.

[0080] Figure 24 It is along Figure 2 The figure shows a cross-sectional view taken along line I-I' to illustrate a semiconductor memory device according to an exemplary embodiment of the invention. For the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their descriptions.

[0081] Reference Figure 24The lower oxide semiconductor pattern 410 may be disposed between the third lower insulating layer 132 and the substrate 100, and the upper oxide semiconductor pattern 420 may be disposed on the upper insulating pattern 232. The lower oxide semiconductor pattern 410 and the upper oxide semiconductor pattern 420 may contain indium (In), gallium (Ga), zinc (Zn), and oxygen (O). As an example, the lower oxide semiconductor pattern 410 and the upper oxide semiconductor pattern 420 may be indium gallium zinc oxide (IGZO) containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). Alternatively, the lower oxide semiconductor pattern 410 and the upper oxide semiconductor pattern 420 may contain oxygen (O) and at least one of indium (In), gallium (Ga), zinc (Zn), tungsten (W), hafnium (Hf), or tin (Sn). The lower oxide semiconductor pattern 410 and the upper oxide semiconductor pattern 420 can be formed from at least one of, for example, indium tin gallium oxide (ITGO), indium tungsten oxide (IWO), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), gallium silicon zinc oxide (IGSiZO), indium hafnium zinc oxide (IHZO), or indium hafnium gallium oxide (IHGO), or include at least one of, for example, indium tin gallium oxide (ITGO), indium tungsten oxide (IWO), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), gallium silicon zinc oxide (IGSiZO), indium hafnium zinc oxide (IHZO), or indium hafnium gallium oxide (IHGO). The lower oxide semiconductor pattern 410 and the upper oxide semiconductor pattern 420 can have an amorphous structure or a crystal structure of the CAAC or spinel manganese oxide type. The lower oxide semiconductor pattern 410 and the upper oxide semiconductor pattern 420 may be formed by, for example, amorphous IGZO or include, for example, amorphous IGZO.

[0082] The lower oxide semiconductor pattern 410 may include a first portion 412 located between the lower conductive lines 210 and a second portion 414 located between the lower conductive lines 210 and the substrate 100. The first portion 412 may be connected to the second portion 414. The first portions 412 may be electrically connected to each other through the second portions 414. The upper oxide semiconductor pattern 420 may include a third portion 422 disposed between the upper conductive lines 240 and a fourth portion 424 disposed on and connected to the third portion 422. The third portions 422 may be electrically connected to each other through the fourth portions 424.

[0083] According to an exemplary embodiment of the present invention, by applying a bias voltage to the lower oxide semiconductor pattern 410 and the upper oxide semiconductor pattern 420, interference problems can be prevented between adjacent lower conductive lines 210 in the lower conductive line 210 and between adjacent upper conductive lines 240 in the upper conductive line 240.

[0084] Figures 25A to 25C They are respectively along Figure 2 The figures are cross-sectional views taken along lines I-I', II-II', and III-III' to illustrate a semiconductor memory device according to an exemplary embodiment of the invention. For the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their descriptions.

[0085] Reference Figures 25A to 25C The dummy lower conductive line 210d can be set between the lower conductive lines 210, and the dummy upper conductive line 240d can be set between the upper conductive lines 240.

[0086] The dummy lower conductive line 210d can be formed simultaneously with the lower conductive line 210 and can include the same material as the lower conductive line 210. The dummy upper conductive line 240d can be formed simultaneously with the upper conductive line 240 and can include the same material as the upper conductive line 240. Both the dummy lower conductive line 210d and the dummy upper conductive line 240d can be electrically floating. For example, in a semiconductor memory device, the dummy lower conductive line 210d and the dummy upper conductive line 240d may not be connected to any ground wire. In an exemplary embodiment of the present invention, both the dummy lower conductive line 210d and the dummy upper conductive line 240d can be completely surrounded by an insulating material.

[0087] Figure 26 It is along Figure 2 The figure shows a cross-sectional view taken along line I-I' to illustrate a semiconductor memory device according to an exemplary embodiment of the invention. For the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their descriptions.

[0088] Reference Figure 26 The capacitor 350 can be connected to the lower channel structure 310 and the upper channel structure 320. Specifically, the first electrode 354 of the capacitor 350 can be connected to the lower conductive line 210 via the lower semiconductor pattern 312 of the lower channel structure 310. The second electrode 352 of the capacitor 350 can be connected to the upper conductive line 240 via the upper semiconductor pattern 322 of the upper channel structure 320. The lower channel structure 310 and the lower gate line 220 can constitute a lower transistor. The upper channel structure 320 and the upper gate line 230 can constitute an upper transistor. Each capacitor 350 can be connected to both the lower and upper transistors. For example, a unit memory cell of the semiconductor memory device according to this embodiment may include two transistors and one capacitor.

[0089] A lower oxide semiconductor pattern 410 can be disposed between the lower conductive lines 210, and an upper oxide semiconductor pattern 420 can be disposed between the upper conductive lines 240. When measured in the first direction D1, the width of the first portion 412 of the lower oxide semiconductor pattern 410 can be smaller than the width of the lower conductive lines 210. When measured in the first direction D1, the width of the third portion 422 of the upper oxide semiconductor pattern 420 can be smaller than the width of the upper conductive lines 240.

[0090] According to exemplary embodiments of the present invention, interference problems between conductive lines connected to a capacitor can be prevented by semiconductor patterning, thus providing a semiconductor memory device with improved electrical characteristics and higher reliability.

[0091] Although exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A lower gate line, wherein the lower gate line is disposed on a substrate and extends longitudinally along a first direction; An upper gate line, which overlaps perpendicularly with the lower gate line and extends longitudinally along the first direction; A first capacitor is disposed between the lower gate line and the upper gate line; The second capacitor is disposed between the lower gate line and the upper gate line, and each second capacitor is disposed between adjacent first capacitors of the first capacitor along the first direction and spaced apart from adjacent first capacitors in the first direction; A lower semiconductor pattern, wherein the lower semiconductor pattern is configured to pass through the lower gate line and be connected to the first capacitor respectively; An upper semiconductor pattern is provided, wherein the upper semiconductor pattern is configured to pass through the upper gate line and be connected to the second capacitor respectively; as well as A lower insulating pattern is disposed between the second capacitor and the lower gate line to cover the entire area of ​​the bottom surface of the second capacitor; Each of the first capacitors and each of the second capacitors respectively includes a first electrode and a second electrode located on the first electrode. Wherein, the lower semiconductor pattern is respectively connected to the first electrode of the first capacitor, and The upper semiconductor pattern is connected to the second electrode of the second capacitor.

2. The semiconductor memory device according to claim 1, wherein, The thickness of the lower insulating pattern is less than the thickness of the lower gate line.

3. The semiconductor memory device according to claim 1, wherein, The lower insulating pattern has the same width as the lower gate line in a second direction perpendicular to the first direction.

4. The semiconductor memory device according to claim 1, wherein, The lower semiconductor pattern is configured to pass vertically through the lower insulating pattern.

5. The semiconductor memory device according to claim 1, further comprising: A lower conductive line is disposed between the substrate and the lower gate line, and extends longitudinally along a second direction perpendicular to the first direction. The bottom surface of the lower semiconductor pattern is connected to the top surface of the lower conductive line, and the top surface of the lower semiconductor pattern is connected to the bottom surface of the first capacitor.

6. The semiconductor memory device according to claim 1, wherein, The lower semiconductor pattern includes an oxide semiconductor.

7. The semiconductor memory device according to claim 1, wherein, The underlying semiconductor pattern comprises indium, gallium, zinc, and oxygen.

8. The semiconductor memory device according to claim 1, further comprising: A lower conductive line is disposed between the substrate and the lower gate line and is connected to the lower semiconductor pattern; as well as An upper conductive line is disposed on the upper gate line and connected to the upper semiconductor pattern. The lower conductive line and the upper conductive line extend longitudinally along a second direction perpendicular to the first direction.

9. The semiconductor memory device according to claim 8, wherein, The lower conductive line and the upper conductive line are spaced apart from each other in the first direction.

10. The semiconductor memory device according to claim 1, further comprising: An upper insulating layer is disposed between the first capacitor and the upper gate line to cover the entire area of ​​the top surface of the first capacitor.

11. The semiconductor memory device according to claim 10, wherein, The thickness of the upper insulating layer is less than the thickness of the upper gate line.

12. A semiconductor memory device, the semiconductor memory device comprising: A lower gate line, wherein the lower gate line is disposed on a substrate and extends longitudinally along a first direction; A lower conductive line is disposed between the substrate and the lower gate line, and extends longitudinally along a second direction perpendicular to the first direction; An upper gate line, which overlaps perpendicularly with the lower gate line and extends longitudinally along the first direction; An upper conductive line is disposed on the upper gate line and extends longitudinally along the second direction; A first capacitor is disposed between the lower gate line and the upper gate line; The second capacitor is disposed between the lower gate line and the upper gate line. Each second capacitor is disposed between adjacent first capacitors of the first capacitor along the first direction and spaced apart from adjacent first capacitors in the first direction. The first capacitor and the second capacitor each include a first electrode and a second electrode located on the first electrode. A lower insulating pattern is disposed between the first capacitor and the lower gate line, and between the second capacitor and the lower gate line; An upper insulating layer is disposed between the first capacitor and the upper gate line, and between the second capacitor and the upper gate line; A lower semiconductor pattern, wherein the lower semiconductor pattern is configured to pass through the lower gate line and the lower insulating pattern, and respectively connect the first electrode of the first capacitor to the lower conductive line; and An upper semiconductor pattern is provided, wherein the upper semiconductor pattern is configured to pass through the upper gate line and the upper insulating layer, and to connect the second electrode of the second capacitor to the upper conductive line, respectively. Wherein, the first distance between two adjacent lower conductive lines is greater than the second distance between adjacent capacitors in the first capacitor and the second capacitor.

13. The semiconductor memory device according to claim 12, in, The first capacitor is disposed between two adjacent upper conductive lines, and The second capacitor is disposed between two adjacent lower conductive lines in the lower conductive line.

14. The semiconductor memory device according to claim 12, wherein, The lower conductive line does not overlap perpendicularly with the upper conductive line.

15. The semiconductor memory device according to claim 12, wherein, The distance between two adjacent upper conductive lines is greater than the distance between the first capacitor and the second capacitor.

16. A semiconductor memory device, the semiconductor memory device comprising: A lower gate line, wherein the lower gate line is disposed on a substrate and extends longitudinally along a first direction; An upper gate line, which overlaps perpendicularly with the lower gate line and extends longitudinally along the first direction; A first capacitor is located between the lower gate line and the upper gate line; The second capacitor is disposed between the lower gate line and the upper gate line. Each second capacitor is disposed between adjacent first capacitors of the first capacitor along the first direction and spaced apart from adjacent first capacitors in the first direction. The first capacitor and the second capacitor each include a first electrode and a second electrode located on the first electrode. An upper conductive line is disposed on the upper gate line and extends longitudinally along a second direction perpendicular to the first direction; A lower semiconductor pattern, wherein the lower semiconductor pattern is configured to penetrate the lower gate line and be connected to the first electrode of the first capacitor respectively; An upper semiconductor pattern, the upper semiconductor pattern being configured to pass through the upper gate line and respectively connect the second electrode of the second capacitor to the upper conductive line; and A lower insulating pattern is disposed between the top surface of the lower gate line and the bottom surface of the first electrode. The upper semiconductor pattern includes an oxide semiconductor.

17. The semiconductor memory device according to claim 16, wherein, The lower insulating pattern covers the entire area of ​​the bottom surface of the first electrode.

18. The semiconductor memory device according to claim 16, wherein, The lower insulating pattern has the same width as the lower gate line in the second direction.

19. The semiconductor memory device according to claim 16, wherein, The oxide semiconductor includes amorphous indium gallium zinc oxide.

20. The semiconductor memory device of claim 16, further comprising: An upper gate insulating pattern, wherein the upper gate insulating pattern is located between the upper semiconductor pattern and the upper gate line. The distance between the top and bottom surfaces of the upper gate insulating pattern is greater than the thickness of the upper gate line.

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