Rail-to-rail operational amplifier and method of constant transconductance

Abstract

The application provides a rail-to-rail operational amplifier and a constant-transconductance method, which comprises a rail-to-rail amplification module composed of an output stage and a rail-to-rail input stage, wherein the rail-to-rail input stage comprises a P-type submodule and an N-type submodule; an auxiliary module connected to the rail-to-rail amplification module and receiving an input signal; and when the N-type input tube or the P-type input tube in the rail-to-rail amplification module is cut off, the auxiliary module injects a compensation current into the P-type submodule or the N-type submodule based on the control of the input signal, so that the transconductance of the rail-to-rail operational amplifier remains constant in the rail-to-rail input range. The rail-to-rail operational amplifier and the constant-transconductance method of the application greatly expand the range in which the total transconductance is basically constant in the middle input range, greatly reduce the harmonic distortion of the operational amplifier, do not need to externally provide two reference voltages, and simplify the circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and in particular, to a rail-to-rail operational amplifier and a method for constant transconductance. BACKGROUND

[0002] In a rail-to-rail input operational amplifier, in order to ensure stability of the operational amplifier and low harmonic distortion performance of the circuit, the rail-to-rail input operational amplifier is generally required to have a constant transconductance characteristic. In order to reduce the offset voltage and improve the transconductance, the size of the input MOS transistor of the operational amplifier is generally set to be relatively large, and the input MOS transistor is in a sub-threshold state (of course, it can also work in a saturation state). Taking the input transistor of the operational amplifier working in a sub-threshold state as an example, the transconductance of the MOS transistor working in a sub-threshold state is proportional to the current passing through it, satisfying the following formula 1, where g m is the MOS transistor transconductance, I D is the current passing through the MOS transistor, n and V T are constants.

[0003]

[0004] In the prior art, although the input end of the operational amplifier is a rail-to-rail input end, the input transconductance is not constant in the rail-to-rail range. When the input voltage is close to 0, the NMOS input transistor is in a cut-off state, and the current passing through it is 0; when the input voltage is close to the power supply voltage AVDD, the PMOS input transistor is in a cut-off state, and the current passing through it is 0; this results in that the transconductance of the input end is small at both ends of the power supply and ground, and the transconductance in the middle is larger, and the formula derivation is as shown in formula 2-4, and the transconductance is as shown in formula 5. Figure 1

[0005]

[0006]

[0007]

[0008] ​In order to keep the transconductance of the operational amplifier constant in the range of rail-to-rail, a compensation method is provided in the industry. First, two reference voltages are set, Vrp (set as 2V as an example) and Vrn (set as 1V as an example). When the input of the operational amplifier is lower than Vrn, the NMOS input tube is cut off, the compensation path controlled by the reference voltage Vrp is closed, and the compensation path controlled by the reference voltage Vrn is turned on. At this time, the current flowing through the PMOS input tube is 4*I1. When the input is greater than Vrn and less than Vrp, the NMOS input tube and the PMOS input tube work normally, and the current flowing through them is I1. At this time, the total current flowing through the input tube is 4*I1. When the input is higher than Vrp, the PMOS input tube is cut off, the compensation path controlled by the reference voltage Vrp is turned on, and the compensation path controlled by the reference voltage Vrn is closed. At this time, the current flowing through the NMOS input tube is 4*I1. In summary, no matter whether the input is less than Vrn, greater than Vrn and less than Vrp, or greater than Vrp, the total current flowing through the input tube is 4*I1. The transconductance of the operational amplifier is basically equal in the range of rail-to-rail input, and the formula derivation is shown in formula 5 to formula 7.

[0009]

[0010]

[0011]

[0012] Figure 2 For the schematic diagram of the compensated transconductance, it can be seen that the transconductance is roughly constant in the range of rail-to-rail input, but due to the non-ideal characteristics of the circuit, the total transconductance will still change to some extent, especially in the most commonly used middle input range. The range of the total transconductance basically constant is relatively small, which will still affect the harmonic distortion performance of the operational amplifier in most cases, and two reference voltages Vrp and Vrn need to be provided externally, which increases the complexity of the circuit.

[0013] Therefore, how to simplify the rail-to-rail operational amplifier circuit with transconductance compensation, expand the range of the total transconductance basically constant in the middle input range, and reduce the harmonic distortion of the operational amplifier has become one of the problems to be solved by the person skilled in the art. SUMMARY

[0014] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a rail-to-rail operational amplifier and a constant transconductance method, which is used to solve the problems of small constant transconductance range, large harmonic distortion, and complex circuit structure of the rail-to-rail operational amplifier in the prior art.

[0015] In order to achieve the above-mentioned purpose and other related purposes, the present application provides a rail-to-rail operational amplifier, which at least comprises:

[0016] A rail-to-rail amplification module, comprising an output stage and a rail-to-rail input stage, the rail-to-rail input stage comprising a P-type sub-module and an N-type sub-module; the P-type sub-module and the N-type sub-module receive an input signal, the output stage connects the output ends of the P-type sub-module and the N-type sub-module, and the rail-to-rail amplification module amplifies the input signal and outputs a corresponding output signal;

[0017] An auxiliary module receives the input signal and connects the rail-to-rail amplification module; when an N-type input tube or a P-type input tube in the rail-to-rail amplification module is cut off, the auxiliary module compensates for the current flowing through the input tube, so that the transconductance of the rail-to-rail operational amplifier remains constant within the rail-to-rail input range.

[0018] Optionally, the P-type sub-module comprises a first P-type input tube, a second P-type input tube and a first current source; the sources of the first P-type input tube and the second P-type input tube are connected to the first current source, the gates are connected to a first input signal and a second input signal respectively, and the drains are connected to the output stage; the first input signal is equal to the second input signal.

[0019] More optionally, the N-type sub-module comprises a first N-type input tube, a second N-type input tube and a second current source; the sources of the first N-type input tube and the second N-type input tube are connected to the second current source, the gates are connected to the first input signal and the second input signal respectively, and the drains are connected to the output stage.

[0020] More optionally, the currents flowing through the first current source and the second current source are equal.

[0021] Optionally, the output stage comprises a third, fourth, fifth and sixth current source, a first P-type output tube, a second P-type output tube, a first N-type output tube and a second N-type output tube;

[0022] The source of the first P-type output tube is connected with the third current source and the first output end of the N-type sub-module, the gate is connected with the first bias voltage, and the drain is connected with the drain of the first N-type output tube; the source of the second P-type output tube is connected with the fourth current source and the second output end of the N-type sub-module, the gate is connected with the first bias voltage, and the drain is connected with the drain of the second N-type output tube; the source of the first N-type output tube is connected with the fifth current source and the first output end of the P-type sub-module, the gate is connected with the second bias voltage, and the drain is connected with the drain of the first P-type output tube; the source of the second N-type output tube is connected with the sixth current source and the second output end of the P-type sub-module, the gate is connected with the second bias voltage, and the drain is connected with the drain of the second P-type output tube; the drains of the first P-type output tube and the first N-type output tube output a first output signal, and the drains of the second P-type output tube and the second N-type output tube output a second output signal.

[0023] The currents flowing through the third, fourth, fifth and sixth current sources are equal.

[0024] Optionally, the auxiliary module comprises a first compensation unit and a second compensation unit; the first compensation unit is connected with the source of the P-type input tube in the P-type sub-module, and injects a compensation current into the source of the P-type input tube when the N-type input tube in the N-type sub-module is cut off; the second compensation unit is connected with the source of the N-type input tube in the N-type sub-module, and injects a compensation current into the source of the N-type input tube when the P-type input tube in the P-type sub-module is cut off.

[0025] More optionally, the first compensation unit comprises a seventh current source, an eighth current source, a first current mirror and a second current mirror.

[0026] The seventh current source is connected with the input signal, does not output current when the input signal cuts off the N-type input tube, and outputs current when the input signal turns on the N-type input tube;

[0027] The first end of the first current mirror is connected with the seventh current source, the second end is connected with the eighth current source, and the current ratio of the first end to the second end of the first current mirror is 1:1;

[0028] The first end of the second current mirror is connected with the eighth current source, the second end is connected with the source of the P-type input tube, and the current ratio of the first end to the second end of the second current mirror is k1:a;

[0029] The current flowing through the seventh current source and the eighth current source is equal, and the ratio of the current flowing through the seventh current source and the eighth current source to the current flowing through the current source in the N-type sub-module is k1:a.

[0030] More optionally, the second compensation unit comprises a ninth current source, a tenth current source, a third current mirror and a fourth current mirror.

[0031] The ninth current source is connected to the input signal, and when the input signal makes the P-type input tube cut off, the ninth current source does not output current, and when the input signal makes the P-type input tube conduct, the ninth current source outputs current.

[0032] The first end of the third current mirror is connected to the ninth current source, and the second end is connected to the tenth current source, and the current ratio of the first end to the second end of the third current mirror is 1:1.

[0033] The first end of the fourth current mirror is connected to the tenth current source, and the second end is connected to the source of the P-type input tube, and the current ratio of the first end to the second end of the fourth current mirror is k2:b.

[0034] The current flowing through the ninth current source and the tenth current source is equal, and the ratio of the current flowing through the ninth current source and the tenth current source to the current flowing through the current source in the P-type sub-module is k2:b; the ratio of the width-length ratio of the transistor connected to the tenth current source in the fourth current mirror to the third current mirror is less than 1.

[0035] To achieve the above object and other related objects, the application further provides a rail-to-rail amplifier constant transconductance method, which at least comprises:

[0036] When the N-type input tube in the N-type sub-module is cut off, compensation current is injected into the P-type sub-module based on the control of the input signal; when the P-type input tube in the P-type sub-module is cut off, compensation current is injected into the N-type sub-module based on the control of the input signal; and the transconductance is adjusted so that the transconductance when the N-type input tube or the P-type input tube is cut off is consistent with the transconductance when the N-type input tube and the P-type input tube are both turned on.

[0037] Optionally, when the N-type input tube is cut off, current is loaded to the source of the P-type input tube through a first preset proportion mirror, and the current loaded to the source of the P-type input tube is equal to the current flowing through the current source in the N-type sub-module; when the N-type input tube is turned on, the input signal opens a shunt branch to shunt the current loaded to the source of the P-type input tube, and no current is loaded to the source of the P-type input tube.

[0038] Optionally, when the P-type input tube is cut off, current is loaded to the source of the N-type input tube through a second preset proportion mirror, and the current loaded to the source of the N-type input tube is equal to the current flowing through the current source in the P-type sub-module; when the P-type input tube is turned on, the input signal opens a shunt branch to shunt the current loaded to the source of the N-type input tube, and no current is loaded to the source of the N-type input tube.

[0039] More optionally, the transconductance of the rail-to-rail amplifier satisfies:

[0040]

[0041] wherein g m (total) is the total transconductance, g m (PMOS) is the transconductance of the P-type input tube, g m (NMOS) is the transconductance of the N-type input tube, 2I1 is the current flowing through the current source in the N-type sub-module and the P-type sub-module, n is a constant, V T is the thermal voltage.

[0042] As described above, the rail-to-rail operational amplifier and the method for constant transconductance of the present application have the following beneficial effects:

[0043] The rail-to-rail operational amplifier and the method for constant transconductance of the present application greatly expand the range in which the total transconductance is basically constant in the middle input range, greatly reduce the harmonic distortion of the operational amplifier, and do not need to externally provide two reference voltages, thereby simplifying the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 A transconductance schematic diagram of a rail-to-rail amplifier in the prior art is shown.

[0045] Figure 2 A transconductance schematic diagram of another rail-to-rail amplifier in the prior art is shown.

[0046] Figure 3 A structure schematic diagram of the rail-to-rail operational amplifier of the present application is shown.

[0047] Figure 4 A transconductance schematic diagram of the rail-to-rail operational amplifier of the present application is shown.

[0048] Element No.

[0049] 1 rail-to-rail operational amplifier

[0050] 11 rail-to-rail amplification module

[0051] 111 P-type sub-module

[0052] 112 N-type sub-module

[0053] 113 output stage

[0054] 12 auxiliary module

[0055] 121 first compensation unit

[0056] 122 second compensation unit DETAILED DESCRIPTION

[0057] The present application is described herein with reference to particular non-limiting embodiments. Variations to those embodiments can be understood and effected within the broad scope of the application, and the application is not limited to the described embodiments, except as set forth in the appended claims. Other advantages and novel features of the present application will become readily apparent from the following detailed description of the application and from the drawings.

[0058] Reference will now be made to the drawings, wherein: Figures 3-4 It is to be understood that the drawings are schematic and that the actual numbers, shapes and sizes of the components may vary from those shown in the drawings. The actual layout and configuration of the components may also be more complex than that shown in the drawings.

[0059] Embodiment One

[0060] As shown in Figure 3 , the present embodiment provides a rail-to-rail operational amplifier 1, which comprises:

[0061] a rail-to-rail amplification module 11 and an auxiliary module 12.

[0062] As shown in Figure 3 , the rail-to-rail amplification module 11 comprises an output stage 113 and a rail-to-rail input stage. The rail-to-rail input stage comprises a P-type sub-module 111 and an N-type sub-module 112, which receive an input signal. The output stage 113 is connected to the output ends of the P-type sub-module 111 and the N-type sub-module 112. The rail-to-rail amplification module 11 amplifies the input signal and outputs a corresponding output signal, thereby achieving rail-to-rail amplification output.

[0063] Specifically, the P-type sub-module 111 includes a first P-type input transistor, a second P-type input transistor and a first current source; the source of the first P-type input transistor and the second P-type input transistor is connected to the first current source, the gate is connected to the first input signal Vin and the second input signal Vip respectively, and the drain is connected to the output stage 113. As shown, as an example, the P-type sub-module 111 includes a first PMOS transistor MP1, a second PMOS transistor MP2 and a third PMOS transistor MP3, constituting a rail-to-rail input structure. The first PMOS transistor MP1 serves as the first current source, the source of the first PMOS transistor MP1 is connected to the power supply voltage, the gate is connected to the third bias voltage VB3, and the current flowing through the first PMOS transistor MP1 is controlled to be 2*I1 through the third bias voltage VB3. The second PMOS transistor MP2 and the third PMOS transistor MP3 serve as P-type input transistors, the source of the second PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP1, the gate is connected to the first input signal Vin, and the drain is connected to the output stage 113; the source of the third PMOS transistor MP3 is connected to the drain of the first PMOS transistor MP1, the gate is connected to the second input signal Vip, and the drain is connected to the output stage 113. Figure 3

[0064] Specifically, the N-type sub-module 112 includes a first N-type input transistor, a second N-type input transistor and a second current source; the source of the first N-type input transistor and the second N-type input transistor is connected to the second current source, the gate is connected to the first input signal Vin and the second input signal Vip respectively, and the drain is connected to the output stage 113. As shown, as an example, the N-type sub-module 112 includes a first NMOS transistor MN1, a second NMOS transistor MN2 and a third NMOS transistor MN3, constituting a rail-to-rail input structure. The first NMOS transistor MN1 serves as the second current source, the source of the first NMOS transistor MN1 is connected to the ground, the gate is connected to the fourth bias voltage VB4, and the current flowing through the first NMOS transistor MN1 is controlled to be 2*I1 through the fourth bias voltage VB4. The second NMOS transistor MN2 and the third NMOS transistor MN3 serve as N-type input transistors, the source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1, the gate is connected to the first input signal Vin, and the drain is connected to the output stage 113; the source of the third NMOS transistor MN3 is connected to the drain of the first NMOS transistor MN1, the gate is connected to the second input signal Vip, and the drain is connected to the output stage 113. Figure 3

[0065] ​​Specifically, the output stage 113 comprises a third, fourth, fifth, sixth current source, a first P-type output tube, a second P-type output tube, a first N-type output tube and a second N-type output tube; the source of the first P-type output tube is connected to the third current source and the first output end of the N-type sub-module 112, the gate is connected to a first bias voltage VB1, and the drain is connected to the drain of the first N-type output tube; the source of the second P-type output tube is connected to the fourth current source and the second output end of the N-type sub-module 112, the gate is connected to the first bias voltage VB1, and the drain is connected to the drain of the second N-type output tube; the source of the first N-type output tube is connected to the fifth current source and the first output end of the P-type sub-module 111, the gate is connected to a second bias voltage VB2, and the drain is connected to the drain of the first P-type output tube; the source of the second N-type output tube is connected to the sixth current source and the second output end of the P-type sub-module 111, the gate is connected to the second bias voltage VB2, and the drain is connected to the drain of the second P-type output tube; the drains of the first P-type output tube and the first N-type output tube output a first output signal Vop, and the drains of the second P-type output tube and the second N-type output tube output a second output signal Von. As Figure 3As shown, the output stage 113 includes, as an example, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7. The fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are respectively the third current source and the fourth current source, the source of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 is connected to a power supply voltage, and the gate is connected to the third bias voltage VB3. The sixth PMOS transistor MP6 is the first P-type output transistor, the source of the sixth PMOS transistor MP6 is connected to the drain of the fourth PMOS transistor MP4, and the gate is connected to the first bias voltage VB1. The seventh PMOS transistor MP7 is the second P-type output transistor, the source of the seventh PMOS transistor MP7 is connected to the drain of the fifth PMOS transistor MP5, and the gate is connected to the first bias voltage VB1. The fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are respectively the fifth current source and the sixth current source, the source of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 is connected to ground, and the gate is connected to the fourth bias voltage VB4. The sixth NMOS transistor MN6 is the first N-type output transistor, the source of the sixth NMOS transistor MN6 is connected to the drain of the fourth NMOS transistor MN4, and the gate is connected to the second bias voltage VB2. The seventh NMOS transistor MN7 is the second N-type output transistor, the source of the seventh NMOS transistor MN7 is connected to the drain of the fifth NMOS transistor MN5, and the gate is connected to the second bias voltage VB2. The drain of the sixth PMOS transistor MP6 is connected to the drain of the sixth NMOS transistor MN6 and outputs the first output signal Vop, and the drain of the seventh PMOS transistor MP7 is connected to the drain of the seventh NMOS transistor MN7 and outputs the second output signal Von.

[0066] It should be noted that the third bias voltage VB3 and the fourth bias voltage VB4 are used to control the current flowing through the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5, respectively, so as to obtain the required current source. In this embodiment, the currents flowing through the third, fourth, fifth, and sixth current sources are equal, and are set to I2 as an example.

[0067] As shown in FIG. 1, the output stage 113 includes, as an example, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7. Figure 3As shown, the auxiliary module 12 receives the input signal and connects the rail-to-rail amplification module 11; when the N-type input tube or the P-type input tube in the rail-to-rail amplification module 11 is cut off, the auxiliary module 12 compensates the current flowing through the input tube, so that the transconductance of the rail-to-rail operational amplifier 1 remains constant in the rail-to-rail input range.

[0068] Specifically, the auxiliary module 12 includes a first compensation unit 121 and a second compensation unit 122; the first compensation unit 121 connects the source of the P-type input tube in the P-type submodule 111, and injects a compensation current into the source of the P-type input tube when the N-type input tube in the N-type submodule 112 is cut off; the second compensation unit 122 connects the source of the N-type input tube in the N-type submodule 112, and injects a compensation current into the source of the N-type input tube when the P-type input tube in the P-type submodule 111 is cut off.

[0069] More specifically, the first compensation unit 121 includes a seventh current source, an eighth current source, a first current mirror and a second current mirror; the seventh current source is connected to the input signal, and does not output current when the input signal makes the N-type input tube cut off, and outputs current when the input signal makes the N-type input tube conduct; the first end of the first current mirror is connected to the seventh current source, and the second end is connected to the eighth current source; the first end of the second current mirror is connected to the eighth current source, and the second end is connected to the source of the P-type input tube; wherein the currents flowing through the seventh current source and the eighth current source are equal. As Figure 3As shown, as an example, the first compensation unit 121 includes an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10 and an eleventh PMOS transistor MP11. The eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 serve as the seventh current source, the source of the eighth NMOS transistor MN8 is connected to ground, the gate is connected to the fourth bias voltage VB4, and the drain is connected to the source of the ninth NMOS transistor MN9; the gate of the ninth NMOS transistor MN9 is connected to the second input signal Vip (also connected to the first input signal Vin); when the second input signal Vip is close to 0 (the second NMOS transistor MN2 and the third NMOS transistor MN3 are cut off), the ninth NMOS transistor MN9 is cut off, and the seventh current source has no current output; when the second input signal Vip is close to the power supply voltage (the second NMOS transistor MN2 and the third NMOS transistor MN3 are turned on), the ninth NMOS transistor MN9 is turned on, and the seventh current source outputs a current of k*I1 controlled by the fourth bias voltage VB4. The eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 serve as the first current mirror, the drain and the gate of the eighth PMOS transistor MP8 are connected to the drain of the ninth NMOS transistor MN9, and the source is connected to the power supply voltage; the source of the ninth PMOS transistor MP9 is connected to the power supply voltage, and the gate is connected to the gate of the eighth PMOS transistor MP8; the width-length ratio of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 is 1:1. The tenth NMOS transistor MN10 serves as the eighth current source, the source of the tenth NMOS transistor MN10 is connected to ground, the gate is connected to the fourth bias voltage VB4, and the current flowing through the tenth NMOS transistor MN10 is controlled by the fourth bias voltage VB4 to be k*I1. The tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11 serve as the second current mirror, the drain and the gate of the tenth PMOS transistor P10 are connected to the drain of the tenth NMOS transistor MN10 and the drain of the ninth PMOS transistor MP9, and the source is connected to the power supply voltage; the source of the eleventh PMOS transistor MP11 is connected to the power supply voltage, the gate is connected to the gate of the tenth PMOS transistor MP10, and the drain is connected to the source of the second PMOS transistor MP2 and the third PMOS transistor MP3; the width-length ratio of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11 is k:2, and the current at the drain of the eleventh PMOS transistor MP11 when the ninth NMOS transistor MN9 is cut off is 2*I1, which is equal to the current flowing through the first NMOS transistor MN1.

[0070] It should be noted that the ratio of the width-length ratio of the tenth PMOS transistor MP10 to the ninth PMOS transistor MP9 is less than 1:1 (i.e. the width-length ratio of the transistor connected with the eighth current source in the second current mirror is less than the width-length ratio of the transistor connected with the eighth current source in the first current mirror), which makes the seventh current source and the eighth current source have k*I1 current when the N-type input transistor works normally (the input signal is close to the power supply voltage), the current flowing through the eighth PMOS transistor MP8 is k*I1, since the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are a 1:1 current mirror, and the width-length ratio of the tenth PMOS transistor MP10 is much smaller than the width-length ratio of the ninth PMOS transistor MP9, the current k*I1 of the eighth current source flows through the ninth PMOS transistor MP9 entirely, and the current flowing through the tenth PMOS transistor MP10 is 0, thereby making the first compensation unit 121 not output a compensation current. In the embodiment, the width-length ratio of the tenth PMOS transistor MP10 is smaller than the width-length ratio of the ninth PMOS transistor MP9, for example, the ratio is 0.9:1, 0.7:1, 0.5:1, 0.3:1, 0.1:1, 0.05:1, 0.02:1, 0.01:1, so that when the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are both turned on, the current in the tenth NMOS transistor MN10 basically flows through the ninth PMOS transistor MP9, and the current flowing through the tenth PMOS transistor MP10 is almost 0 (the current flowing through the tenth PMOS transistor MP10 is considered to be 0 within a set threshold range), and the specific ratio is not described here.

[0071] More specifically, the second compensation unit 122 includes a ninth current source, a tenth current source, a third current mirror and a fourth current mirror; the ninth current source is connected with the input signal, when the input signal makes the P-type input transistor cut off, the ninth current source does not output current, and when the input signal makes the P-type input transistor conduct, the ninth current source outputs current; the first end of the third current mirror is connected with the ninth current source, and the second end is connected with the tenth current source; the first end of the fourth current mirror is connected with the tenth current source, and the second end is connected with the source of the P-type input transistor; wherein the currents flowing through the ninth current source and the tenth current source are equal. As Figure 3As shown, as an example, the second compensation unit 122 includes twelfth PMOS transistor MP12, thirteenth PMOS transistor MP13, fourteenth PMOS transistor MP14, eleventh NMOS transistor MN11, twelfth NMOS transistor MN12, thirteenth NMOS transistor MN13 and fourteenth NMOS transistor MN14. The twelfth PMOS transistor MP12 and the thirteenth PMOS transistor MP13 serve as the ninth current source, the source of the twelfth PMOS transistor MP12 is connected to the power supply voltage, the gate is connected to the third bias voltage VB3, and the drain is connected to the source of the thirteenth PMOS transistor MP13; the gate of the thirteenth PMOS transistor MP13 is connected to the second input signal Vip (also connected to the first input signal Vin); when the second input signal Vip is close to 0 (the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned on), the thirteenth PMOS transistor MP13 is turned on, and the ninth current source outputs a current of k*I1; when the second input signal Vip is close to the power supply voltage (the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned off), the thirteenth PMOS transistor MP13 is turned off, and the ninth current source outputs no current. The eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 serve as the third current mirror, the drain and the gate of the eleventh NMOS transistor MN11 are connected to the drain of the thirteenth PMOS transistor MP13, and the source is connected to the ground; the source of the twelfth NMOS transistor MN12 is connected to the ground, and the gate is connected to the gate of the eleventh NMOS transistor MN11; the width-to-length ratio of the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 is 1:1. The fourteenth PMOS transistor MP14 serves as the tenth current source, the source of the fourteenth PMOS transistor MP14 is connected to the power supply voltage, the gate is connected to the third bias voltage VB3, and the current flowing through the fourteenth PMOS transistor MP14 is controlled by the third bias voltage VB3 to be k*I1. The thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 serve as the fourth current mirror, the drain and the gate of the thirteenth NMOS transistor MN13 are connected to the drain of the fourteenth PMOS transistor MP14 and the drain of the twelfth NMOS transistor MN12, and the source is connected to the ground; the source of the fourteenth NMOS transistor MN14 is connected to the ground, the gate is connected to the gate of the thirteenth NMOS transistor MN13, and the drain is connected to the source of the second NMOS transistor MN2 and the third NMOS transistor MN3; the width-to-length ratio of the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 is k:2, and the current at the drain of the fourteenth NMOS transistor MN14 is 2*I1 when the thirteenth PMOS transistor MP13 is turned off, which is equal to the current flowing through the first PMOS transistor MP1.

[0072] It should be noted that the ratio of the width-length ratio of the thirteenth NMOS transistor MN13 to the width-length ratio of the twelfth NMOS transistor MN12 is less than 1:1 (i.e., the width-length ratio of the transistor connected with the tenth current source in the fourth current mirror is less than the width-length ratio of the transistor connected with the tenth current source in the third current mirror), which makes the ninth current source and the tenth current source both have k*I1 current when the P-type input transistor works normally (the input signal is close to 0), the current flowing through the eleventh NMOS transistor MN11 is k*I1, since the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 are a 1:1 current mirror, and the width-length ratio of the thirteenth NMOS transistor MN13 is much smaller than the width-length ratio of the twelfth NMOS transistor MN12, the current k*I1 of the tenth current source all flows through the twelfth NMOS transistor MN12, and the current flowing through the thirteenth NMOS transistor MN13 is 0, thereby making the second compensation unit 122 not output a compensation current through shunt. In this embodiment, the width-length ratio of the thirteenth NMOS transistor MN13 is smaller than the width-length ratio of the twelfth NMOS transistor MN12, for example, the ratio is 0.9:1, 0.7:1, 0.5:1, 0.3:1, 0.1:1, 0.05:1, 0.02:1, 0.01:1, so that when the thirteenth NMOS transistor MN13 and the twelfth NMOS transistor MN12 are both turned on, the current in the fourteenth PMOS transistor MP14 basically flows through the twelfth NMOS transistor MN12, and the current flowing through the thirteenth NMOS transistor MN13 is almost 0 (the current flowing through the thirteenth NMOS transistor MN13 is considered to be 0 within a set threshold range), and the specific ratio is not described here.

[0073] Specifically, in the embodiment, the currents flowing through the first current source and the second current source are equal and set to 2*I1, so that the P-type input tube and the N-type input tube work in a sub-threshold state; the currents flowing through the seventh, eighth, ninth and tenth current sources are the same and set to k*I1. Correspondingly, the current ratio of the first end and the second end of the first current mirror is 1:1, the current ratio of the first end and the second end of the second current mirror is k:2, then, when the N-type input tube is cut off, the current compensated from the eleventh PMOS tube MP11 drain to the second PMOS tube MP2 and the third PMOS tube MP3 is 2*I1 (compensation current), and the current flowing into the P-type input tube is the sum of the current flowing through the first current source and the compensation current, that is, 4*I1. The current ratio of the first end and the second end of the third current mirror is 1:1, and the current ratio of the first end and the second end of the fourth current mirror is k:2, then, when the P-type input tube is cut off, the current compensated from the fourteenth NMOS tube MN14 drain to the second NMOS tube MN2 and the third NMOS tube MN3 is 2*I1 (compensation single current), and the current flowing into the N-type input tube is the sum of the current flowing through the first current source and the compensation current, that is, 4*I1. The following relationship is satisfied:

[0074]

[0075]

[0076]

[0077] wherein g m (total) is the total transconductance, g m (PMOS) is the transconductance of the P-type input tube, g m (NMOS) is the transconductance of the N-type input tube, 2I1 is the current flowing through the current source in the N-type sub-module and the P-type sub-module, n is a constant, V T is the thermal voltage (constant).

[0078] It should be noted that in actual use, the current flowing through the first current source and the current flowing through the second current source can not be equal, for example, the current flowing through the first current source is set to b*I1, and the current flowing through the second current source is set to a*I1; the currents flowing through the seventh, eighth, ninth and tenth current sources are not equal, for example, the currents flowing through the seventh current source and the eighth current source are set to k1*I1, and the currents flowing through the ninth current source and the tenth current source are set to k2*I1; correspondingly, the current ratio of the first end to the second end of the first current mirror is 1:1, the current ratio of the first end to the second end of the second current mirror is k1:a, and when the N-type input tube is cut off, the current compensated from the eleventh PMOS tube MP11 drain to the second PMOS tube MP2 and the third PMOS tube MP3 is a*I1 (compensation single current), and the current flowing into the P-type input tube is the sum of the current flowing through the first current source and the compensation current, that is, (a+b)*I1. The current ratio of the first end to the second end of the third current mirror is 1:1, the current ratio of the first end to the second end of the fourth current mirror is k2:b, and when the P-type input tube is cut off, the current compensated from the fourteenth NMOS tube MN14 drain to the second NMOS tube MN2 and the third NMOS tube MN3 is b*I1 (compensation single current), and the current flowing into the N-type input tube is the sum of the current flowing through the second current source and the compensation current, that is, (a+b)*I1. Thus, the same transconductance can be obtained when the input signal is close to 0, close to the power supply voltage, and between the two, as shown in Figure 4 Figure 1 and Figure 2 The total transconductance of the rail-to-rail operational amplifier of the present application is greatly expanded in the middle input range, which greatly reduces the harmonic distortion of the operational amplifier. The specific formula is similar to formula 8-10, which is not described here.

[0079] It should be noted that in the present embodiment, the input tube works in the sub-threshold region, and in actual use, the input tube can also work in the saturation region, at which time the transconductance is doubled, the circuit structure is consistent with the present embodiment, and the size of the compensation current can be adjusted. For example, the mirror ratio of the second current mirror and the fourth current mirror is set to k:6, and the mirror ratio of the current mirror can be adjusted based on actual needs, which is not limited to the present embodiment.

[0080] Embodiment two

[0081] The present embodiment provides a rail-to-rail amplifier constant transconductance method, which comprises:

[0082] ​When the N-type input tube is off, a compensation current is injected into the P-type sub-module based on the control of the input signal; when the P-type input tube is off, a compensation current is injected into the N-type sub-module based to the control of the input signal; the transconductance is adjusted so that the transconductance when the N-type input tube or the P-type input tube is off is consistent with the transconductance when the N-type input tube and the P-type input tube are both on.

[0083] As an implementation manner of the present application, when the N-type input tube is off, a current is mirrored through a first preset ratio to the source of the P-type input tube, and the current loaded to the source of the P-type input tube is equal to the current flowing through the current source in the N-type sub-module; when the N-type input tube is on, the input signal turns on a shunt branch to shunt the current loaded to the source of the P-type input tube, and no current is loaded to the source of the P-type input tube.

[0084] Specifically, as shown in Figure 3 When the input signal Vip, Vin of the rail-to-rail operational amplifier 1 approaches 0, the N-type input tube (the second NMOS tube MN2 and the third NMOS tube MN3) is in an off state; the gate voltage Vip (or Vin) of the ninth NMOS tube MN9 also approaches 0, and the ninth NMOS tube MN9 is also in an off state; thus the eighth PMOS tube MP8 is also in an off state, thereby causing the ninth PMOS tube MP9 to also be in an off state. Since the ninth PMOS tube MP9 is in an off state, the current flowing through the tenth PMOS tube MP10 is equal to the current flowing through the tenth NMOS tube MN10, that is, k*I1; since the tenth PMOS tube MP10 and the eleventh PMOS tube MP11 have a mirror relationship, the current flowing through the eleventh PMOS tube MP11 is 2*I1.

[0085] Specifically, as shown in Figure 3 When the input signal Vip, Vin of the rail-to-rail operational amplifier 1 approaches the power supply voltage, the N-type input tube is in an on state; the gate voltage Vip (or Vin) of the ninth NMOS tube MN9 also approaches the power supply voltage, and the ninth NMOS tube MN9 is also in an on state; the eighth PMOS tube MP8 and the ninth PMOS tube MP9 are both in an on state. Since the ninth PMOS tube MP9 is in an on state, the current flowing through the ninth PMOS tube MP9 is equal to the current flowing through the tenth NMOS tube MN10, that is, k*I1, and no current flows through the tenth PMOS tube MP10 or the eleventh NMOS tube MN11.

[0086] As an implementation manner of the present application, when the P-type input tube is cut off, the current is loaded to the source of the N-type input tube through the second preset proportional mirror, and the current loaded to the source of the N-type input tube is equal to the current flowing through the current source in the P-type sub-module; when the P-type input tube is turned on, the input signal opens the shunt branch to shunt the current loaded to the source of the N-type input tube, and no current is loaded to the source of the N-type input tube.

[0087] Specifically, as shown in Figure 3 When the input signal Vip, Vin of the rail-to-rail operational amplifier 1 approaches the power supply voltage, the P-type input tube (the second PMOS tube MP2 and the third PMOS tube MP3) is in the cut-off state; the gate voltage Vip (or Vin) of the thirteenth PMOS tube MP13 also approaches the power supply voltage, and the thirteenth PMOS tube MP13 is also in the cut-off state; thus the eleventh NMOS tube MN11 is also in the cut-off state, thereby causing the twelfth NMOS tube MN12 to also be in the cut-off state. Since the twelfth NMOS tube MN12 is in the cut-off state, the current flowing through the thirteenth NMOS tube MN13 is equal to the current flowing through the fourteenth PMOS tube MP14, that is, k*I1; since the thirteenth NMOS tube MN13 and the fourteenth NMOS tube MN14 have a mirror relationship, the current flowing through the fourteenth NMOS tube MN14 is 2*I1.

[0088] Specifically, as shown in Figure 3 When the input signal Vip, Vin of the rail-to-rail operational amplifier 1 approaches 0, the P-type input tube is in the on state; the gate voltage Vip (or Vin) of the thirteenth PMOS tube MP13 also approaches 0, and the thirteenth PMOS tube MP13 is also in the on state; the eleventh NMOS tube MN11 and the twelfth NMOS tube MN12 are both in the on state. Since the twelfth NMOS tube MN12 is in the on state, the current flowing through the twelfth NMOS tube MN12 is equal to the current flowing through the fourteenth PMOS tube MP14, that is, k*I1, no current flows through the thirteenth NMOS tube MN13, and no current flows through the fourteenth NMOS tube MN14.

[0089] Therefore, when the input signal Vip, Vin approaches 0, the sum of the currents flowing through the P-type input tubes is the sum of the currents flowing through the eleventh PMOS tube MP11 and the first PMOS tube MP1, which is 4*I1, the N-type input tubes are in the off state, and the current flowing through is 0, thus the total current flowing through the input tubes is 4*I1. When the input signal Vip, Vin approaches the power supply voltage, the sum of the currents flowing through the N-type input tubes is the sum of the currents flowing through the fourteenth NMOS tube MN14 and the first NMOS tube MN1, which is 4*I1, the P-type input tubes are in the off state, and the current flowing through is 0, thus the total current flowing through the input tubes is 4*I1. The formulas are shown in Formulas 8-10, which are not described herein.

[0090] It should be noted that, similarly, the mirror ratio of each current mirror can also be adjusted according to the different working states of the input tubes and the device parameters, which are not described herein.

[0091] It should be noted that, in the present embodiment, the method for maintaining the constant transconductance of the rail-to-rail amplifier is based on the rail-to-rail operational amplifier 1 of Embodiment 1, and in actual use, any hardware or software capable of implementing the present method is applicable, and the present embodiment is not limited.

[0092] In summary, the present application provides a rail-to-rail operational amplifier and a method for maintaining constant transconductance, which comprises: a rail-to-rail amplification module comprising an output stage and a rail-to-rail input stage, the rail-to-rail input stage comprising a P-type submodule and an N-type submodule; the P-type submodule and the N-type submodule receive an input signal, the output stage is connected to the output ends of the P-type submodule and the N-type submodule, and the rail-to-rail amplification module amplifies the input signal and outputs a corresponding output signal; an auxiliary module receives the input signal and is connected to the rail-to-rail amplification module; when the N-type input tube or the P-type input tube in the rail-to-rail amplification module is in the off state, the auxiliary module compensates the current flowing through the input tube, so that the transconductance of the rail-to-rail operational amplifier remains constant within the rail-to-rail input range. When the N-type input tube in the N-type submodule is in the off state, a compensation current is injected into the P-type submodule based on the control of the input signal; when the P-type input tube in the P-type submodule is in the off state, a compensation current is injected into the N-type submodule based on the control of the input signal; the transconductance is adjusted so that the transconductance when the N-type input tube or the P-type input tube is in the off state is consistent with the transconductance when the N-type input tube and the P-type input tube are both in the on state. The rail-to-rail operational amplifier and the method for maintaining constant transconductance of the present application greatly expand the range in which the total transconductance is basically constant in the middle input range, greatly reduce the harmonic distortion of the operational amplifier, and do not require external provision of two reference voltages, thus simplifying the circuit. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0093] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A rail-to-rail operational amplifier characterized by, The rail-to-rail operational amplifier at least comprises: a rail-to-rail amplification module comprising an output stage and a rail-to-rail input stage, the rail-to-rail input stage comprising a P-type sub-module and an N-type sub-module; the P-type sub-module and the N-type sub-module receive an input signal, the output stage is connected to the output ends of the P-type sub-module and the N-type sub-module, and the rail-to-rail amplification module amplifies the input signal and outputs a corresponding output signal; an auxiliary module connected to the rail-to-rail amplification module and receiving the input signal; when an N-type input tube or a P-type input tube in the rail-to-rail amplification module is cut off, the auxiliary module compensates the current flowing through the input tube, so that the transconductance of the rail-to-rail operational amplifier remains constant within the rail-to-rail input range; when the N-type input tube is cut off, a current is mirrored through a first preset ratio to the source of the P-type input tube, and the current loaded to the source of the P-type input tube is equal to the current flowing through the current source in the N-type sub-module; when the N-type input tube is turned on, the input signal opens a shunt branch to shunt the current loaded to the source of the P-type input tube, and no current is loaded to the source of the P-type input tube; when the P-type input tube is cut off, a current is mirrored through a second preset ratio to the source of the N-type input tube, and the current loaded to the source of the N-type input tube is equal to the current flowing through the current source in the P-type sub-module; when the P-type input tube is turned on, the input signal opens a shunt branch to shunt the current loaded to the source of the N-type input tube, and no current is loaded to the source of the N-type input tube.

2. The rail-to-rail operational amplifier of claim 1, wherein: The P-type sub-module comprises a first P-type input tube, a second P-type input tube and a first current source; the sources of the first P-type input tube and the second P-type input tube are connected to the first current source, the gates are connected to a first input signal and a second input signal respectively, and the drains are connected to the output stage; the first input signal is equal to the second input signal.

3. The rail-to-rail operational amplifier of claim 2, wherein: The N-type sub-module comprises a first N-type input tube, a second N-type input tube and a second current source; the sources of the first N-type input tube and the second N-type input tube are connected to the second current source, the gates are connected to the first input signal and the second input signal respectively, and the drains are connected to the output stage.

4. The rail-to-rail operational amplifier of claim 3, wherein: The currents flowing through the first current source and the second current source are equal.

5. The rail-to-rail operational amplifier of claim 1, wherein: The output stage comprises a third, fourth, fifth, sixth current source, a first P-type output tube, a second P-type output tube, a first N-type output tube and a second N-type output tube; the source of the first P-type output tube is connected to the third current source and a first output end of the N-type sub-module, the gate is connected to a first bias voltage, and the drain is connected to the drain of the first N-type output tube; the source of the second P-type output tube is connected to the fourth current source and a second output end of the N-type sub-module, the gate is connected to the first bias voltage, and the drain is connected to the drain of the second N-type output tube; the source of the first N-type output tube is connected to the fifth current source and a first output end of the P-type sub-module, the gate is connected to a second bias voltage, and the drain is connected to the drain of the first P-type output tube. The source of the second N-type output tube is connected with the sixth current source and the second output end of the P-type sub-module, the gate is connected with the second bias voltage, and the drain is connected with the drain of the second P-type output tube; the drains of the first P-type output tube and the first N-type output tube output a first output signal, and the drains of the second P-type output tube and the second N-type output tube output a second output signal. The currents flowing through the third, fourth, fifth and sixth current sources are equal.

6. The rail-to-rail operational amplifier of claim 1, wherein: The auxiliary module comprises a first compensation unit and a second compensation unit; the first compensation unit is connected with the source of a P-type input tube in the P-type sub-module, and injects a compensation current into the source of the P-type input tube when an N-type input tube in the N-type sub-module is cut off; the second compensation unit is connected with the source of an N-type input tube in the N-type sub-module, and injects a compensation current into the source of the N-type input tube when a P-type input tube in the P-type sub-module is cut off.

7. The rail-to-rail operational amplifier of claim 6, wherein: The first compensation unit comprises a seventh current source, an eighth current source, a first current mirror and a second current mirror. The seventh current source is connected with the input signal, does not output current when the input signal cuts off the N-type input tube, and outputs current when the input signal turns on the N-type input tube; The first end of the first current mirror is connected with the seventh current source, the second end is connected with the eighth current source, and the current ratio of the first end to the second end of the first current mirror is 1:1; The first end of the second current mirror is connected with the eighth current source, the second end is connected with the source of the P-type input tube, and the current ratio of the first end to the second end of the second current mirror is k1:a; The currents flowing through the seventh current source and the eighth current source are equal, and the current ratio of the currents flowing through the seventh current source and the eighth current source to the currents flowing through the current sources in the N-type sub-module is k1:a; the width-length ratio of the transistor connected with the eighth current source in the second current mirror and the first current mirror is less than 1.

8. The rail-to-rail operational amplifier of claim 6 or 7, wherein: The second compensation unit comprises a ninth current source, a tenth current source, a third current mirror and a fourth current mirror. The ninth current source is connected with the input signal, does not output current when the input signal cuts off the P-type input tube, and outputs current when the input signal turns on the P-type input tube; The first end of the third current mirror is connected with the ninth current source, the second end is connected with the tenth current source, and the current ratio of the first end to the second end of the third current mirror is 1:1; The first end of the fourth current mirror is connected with the tenth current source, the second end is connected with the source of the P-type input tube, and the current ratio of the first end to the second end of the fourth current mirror is k2:b; The currents flowing through the ninth current source and the tenth current source are equal, and the current ratio of the currents flowing through the ninth current source and the tenth current source to the currents flowing through the current sources in the P-type sub-module is k2:b; the width-length ratio of the transistor connected with the tenth current source in the fourth current mirror and the third current mirror is less than 1.

9. A method for rail-to-rail amplifier constant transconductance, implemented on the basis of a rail-to-rail operational amplifier as claimed in any one of claims 1-8, characterized by, The method for the constant transconductance of the rail-to-rail amplifier at least comprises: When the N-type input tube in the N-type sub-module is cut off, a compensation current is injected into the P-type sub-module based on the control of an input signal; when the P-type input tube in the P-type sub-module is cut off, a compensation current is injected into the N-type sub-module based on the control of the input signal; and the transconductance is adjusted so that the transconductance when the N-type input tube or the P-type input tube is cut off is consistent with the transconductance when the N-type input tube and the P-type input tube are both turned on.

10. The method of rail-to-rail amplifier constant transconductance as claimed in claim 9, wherein: The transconductance of the rail-to-rail amplifier satisfies: where g m is the total transconductance, g m is the transconductance of the P-type input transistor, g m is the transconductance of the N-type input transistor, 2I1is the current flowing through the current source in the N-type sub-module and the P-type sub-module, n is a constant, V T is the thermal voltage.

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