A pulse generator and clock multiplier

Abstract

The application discloses a pulse generator and a clock frequency multiplier, wherein the pulse generator comprises a first AND gate, a group of adjustable delay units and a second AND gate; the output end of the first AND gate is connected with the input end of the group of adjustable delay units, and the output end of the group of adjustable delay units is connected with the input end of the second AND gate; the first AND gate, the group of adjustable delay units and the second AND gate are further connected with a power supply voltage; and the input end of the group of adjustable delay units is further connected with the output end of a filter. The pulse generated by the pulse generator can adaptively adjust the pulse width at different PVT corners, and keep a fixed ratio, so that the clock frequency multiplication signal generated by a ring voltage-controlled oscillator is improved; a control voltage is output by a phase measurement unit, the pulse generator can adjust the pulse width according to the power supply voltage and the control voltage, the tracking bandwidth of the pulse injection locked oscillator is improved, and the clock frequency multiplication signal generated by the ring voltage-controlled oscillator is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of pulse generator, and particularly relates to a pulse generator and clock multiplier. BACKGROUND

[0002] Clock multipliers continue to play an important role in modern wired communication systems. With the rapid growth of per-lane data rates and the integration of large-capacity interfaces, higher requirements are placed on clock multipliers, including high operating speed, low jitter, small area occupation, and low power consumption. Thanks to the development of injection locking technology, the ring-oscillator pulse injection-locked clock multiplier (RPILCM) has become one of the most promising solutions to generate low-jitter clocks, and it has greater advantages in area occupation and power consumption. Its high power efficiency, compact circuit implementation, and high robustness further make it have special advantages in the design of clock multipliers, clock recovery circuits, and frequency synchronizers.

[0003] The main challenge of RPILCM is how to make the free-running frequency of the oscillator very close to the target frequency within the Process Voltage Temperature (PVT) variation range, so as to maintain the locked state and obtain excellent spurious and phase noise performance. This frequency deviation is particularly important when the multiplication factor increases linearly with the relevant cumulative phase shift within an injection period.

[0004] Another problem related to RPILCM is how to select the pulse width and its effect on variation at different PVT corners. The frequency tracking problem has attracted a lot of research interest, and although they have more or less some shortcomings, many techniques have been developed. Unlike the frequency tracking problem, the pulse width adjustment is an under-researched problem that has not attracted enough research interest in the past. However, the value of the pulse width and its variation will significantly affect the tracking bandwidth of the pulse injection-locked oscillator (PILO).

[0005] In summary, it is necessary to provide a pulse generator and clock multiplier capable of adjusting the pulse width, so that the pulse width and the injection period form a fixed ratio, thereby improving the performance of the tracking bandwidth of the pulse injection-locked oscillator. SUMMARY

[0006] To solve the above problems, the present application provides a pulse generator and clock multiplier.

[0007] In one aspect, the application provides a pulse generator, comprising: a first AND gate, a group of adjustable delay units, and a second AND gate;

[0008] An output terminal of the first AND gate is connected with an input terminal of the group of adjustable delay units, and an output terminal of the group of adjustable delay units is connected with an input terminal of the second AND gate;

[0009] The first AND gate, the group of adjustable delay units, and the second AND gate are further connected with a power supply voltage;

[0010] The input terminal of the group of adjustable delay units is further connected with an output terminal of a filter.

[0011] Preferably, the group of adjustable delay units comprises: a NOT gate, a transmission gate, three adjustable delay units, and three transistors;

[0012] The three adjustable delay units comprise a first adjustable delay unit, a second adjustable delay unit, and a third adjustable delay unit, wherein a positive input terminal of the first adjustable delay unit is connected with an output terminal of the NOT gate, a negative input terminal of the first adjustable delay unit is connected with an output terminal of the transmission gate, the first adjustable delay unit and the second adjustable delay unit, and the third adjustable delay unit are connected in series, and a positive input terminal of each adjustable delay unit is connected with a gate of a corresponding transistor, and a negative output terminal of each adjustable delay unit is connected with a source of the same transistor.

[0013] In a second aspect, the application provides a clock frequency multiplier, comprising: a pulse injection locking oscillation module and a tracking module connected with each other;

[0014] The pulse injection locking oscillation module comprises: a pulse generator as described above and a ring voltage-controlled oscillator connected in sequence;

[0015] The tracking module comprises: a loop selection state machine, a phase measurement unit, a frequency discriminator, a multiplexer, and a filter; input terminals of the multiplexer are connected with output terminals of the loop selection state machine, the phase measurement unit, and the frequency discriminator, respectively; an output terminal of the multiplexer is connected with an input terminal of the filter; an output terminal of the filter is connected with input terminals of the pulse generator and the ring voltage-controlled oscillator; input terminals of the loop selection state machine, the phase measurement unit, and the frequency discriminator are connected with an output terminal of the ring voltage-controlled oscillator; input terminals of the loop selection state machine and the frequency discriminator are further connected with a reference input signal; and an input terminal of the phase measurement unit is further connected with an output terminal of the pulse generator.

[0016] Preferably, the phase measurement unit comprises: a phase measurer and a first charge pump connected in sequence.

[0017] The phase measurer comprises a plurality of first transistors for comparing the phase of the reference input signal and the pulse generated by the pulse injection locked oscillation module, generating a phase output signal and sending the phase output signal to the first charge pump.

[0018] The first charge pump comprises a plurality of second transistors and a comparator for converting the phase output signal into a current.

[0019] Preferably, the phase measurement unit further comprises a polarity detector connected to the first charge pump.

[0020] Preferably, the frequency and phase detector comprises a frequency divider, a frequency and phase detector and a second charge pump connected in sequence.

[0021] The frequency divider is used for dividing the clock multiplication signal output by the pulse injection locked oscillation module to obtain a divided clock multiplication signal and sending the divided clock multiplication signal to the frequency and phase detector.

[0022] The frequency and phase detector is used for comparing the frequency and phase of the divided clock multiplication signal and the reference input signal, determining an error signal and sending the error signal to the second charge pump.

[0023] The second charge pump is used for converting the error signal into a current and sending the current to the multiplexer.

[0024] Preferably, the loop selection state machine comprises a frequency lock detector and a loop selector.

[0025] The frequency lock detector comprises two D flip-flops and a first XOR gate, wherein the outputs of the two D flip-flops are connected to the two inputs of the first XOR gate.

[0026] The loop selector comprises a second XOR gate, an edge counter and a timer, wherein the output of the second XOR gate is connected to the input of the edge counter and the output of the timer is connected to the input of the edge counter.

[0027] Preferably, the pulse generator generates a pulse according to the reference input signal, a power supply voltage and a control voltage generated by the tracking module.

[0028] The ring voltage controlled oscillator generates a clock multiplication signal according to the power supply voltage, or generates a clock multiplication signal according to the power supply voltage and the control voltage, or generates a clock multiplication signal according to the power supply voltage, the pulse and the control voltage.

[0029] Preferably, the tracking module comprises two loops, one of which is a phase-locked loop and the other of which is a timing adjustment loop.

[0030] The loop selection state machine selects one of the two loops according to the frequency of the reference input signal, the frequency of the clock multiplication signal generated by the ring voltage-controlled oscillator and the currently running loop, generates a loop control signal and sends it to the multiplexer;

[0031] The phase measurement unit determines a first current according to the pulse and the clock multiplication signal and sends it to the multiplexer;

[0032] The frequency and phase discriminator determines a second current according to the reference input signal and the clock multiplication signal and sends it to the multiplexer;

[0033] The multiplexer opens the timing adjustment loop to output the first current or opens the phase-locked loop to output the second current according to the loop control signal;

[0034] The filter filters the first current or the second current to obtain a control voltage and sends it to the pulse injection locked oscillator module.

[0035] The pulse generator can adaptively adjust the pulse width at different PVT corners and keep a fixed ratio, thereby improving the clock multiplication signal generated by the ring voltage-controlled oscillator. BRIEF DESCRIPTION OF DRAWINGS

[0036] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a better understanding of the preferred practical embodiments, and are not to be considered as limitations on the present application. Moreover, like reference numerals will be used to designate like components throughout the accompanying drawings. In the drawings:

[0037] Figure 1 is a circuit schematic diagram of a pulse generator provided by the present application;

[0038] Figure 2 is a circuit schematic diagram of an adjustable delay unit group in a pulse generator provided by the present application;

[0039] Figure 3 is a schematic diagram of a clock multiplier provided by the present application;

[0040] Figure 4 is a detailed schematic diagram of a clock multiplier provided by the present application;

[0041] Figure 5 is a circuit schematic diagram of a ring voltage-controlled oscillator of a clock multiplier provided by the present application;

[0042] Figure 6 is a circuit schematic diagram of a conventional pulse generator;

[0043] Figure 7 Figure 1 is a circuit schematic of a delay cell in a ring VCO of a clock multiplier provided by the present application;

[0044] Figure 8 Figure 2 is a circuit schematic of a phase measurement unit of a clock multiplier provided by the present application;

[0045] Figure 9 Figure 3 is an equivalent logic schematic of a phase measurer of a clock multiplier provided by the present application;

[0046] Figure 10 Figure 4 is an equivalent logic and polarity selection schematic of a phase measurer of a clock multiplier provided by the present application;

[0047] Figure 11 Figure 5 is a schematic of a polarity detector of a clock multiplier provided by the present application;

[0048] Figure 12(a) is a schematic of a lock condition of a clock multiplier provided by the present application;

[0049] Figure 12(b) is a schematic of another lock condition of a clock multiplier provided by the present application;

[0050] Figure 13 Figure 13 is a circuit schematic of a loop selection state machine of a clock multiplier provided by the present application;

[0051] Figure 14(a) is a signal level schematic of a target harmonic lock of a frequency tracking of a clock multiplier provided by the present application;

[0052] Figure 14(b) is a signal level schematic of a harmonic miss lock of a frequency tracking of a clock multiplier provided by the present application;

[0053] Figure 14(c) is a signal level schematic of a regular frequency deviation;

[0054] Figure 15 Figure 15 is a circuit schematic of a filter of a clock multiplier provided by the present application. DETAILED DESCRIPTION

[0055] Example embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thoroughly and completely understood, and will fully convey the scope of the present disclosure to those skilled in the art.

[0056] According to embodiments of the present application, a pulse generator is provided, such as Figure 1As shown in the figure, the adjustable delay unit group RDCs comprises a NOT gate, a transmission gate, three adjustable delay units and three transistors. The three adjustable delay units comprise a first adjustable delay unit RDC1, a second adjustable delay unit RDC2 and a third adjustable delay unit RDC3. The positive input end of the first adjustable delay unit is connected with the output end of the NOT gate, and the reverse input end of the first adjustable delay unit is connected with the output end of the transmission gate. The first adjustable delay unit and the second adjustable delay unit and the third adjustable delay unit are connected in series. The positive input end of each adjustable delay unit is connected with the gate of a corresponding transistor, and the reverse output end of each adjustable delay unit is connected with the source of the same transistor.

[0057] As shown in the figure, the adjustable delay unit group RDCs comprises a NOT gate, a transmission gate, three adjustable delay units and three transistors. The three adjustable delay units comprise a first adjustable delay unit RDC1, a second adjustable delay unit RDC2 and a third adjustable delay unit RDC3. The positive input end of the first adjustable delay unit is connected with the output end of the NOT gate, and the reverse input end of the first adjustable delay unit is connected with the output end of the transmission gate. The first adjustable delay unit and the second adjustable delay unit and the third adjustable delay unit are connected in series. The positive input end of each adjustable delay unit is connected with the gate of a corresponding transistor, and the reverse output end of each adjustable delay unit is connected with the source of the same transistor. Figure 2

[0058] According to the embodiment of the present application, a clock frequency multiplier is also provided, as shown in the figure, comprising a pulse injection locking oscillation module 101 and a tracking module 102 connected with each other. Figure 3

[0059] As shown in the figure, the adjustable delay unit group RDCs comprises a NOT gate, a transmission gate, three adjustable delay units and three transistors. The three adjustable delay units comprise a first adjustable delay unit RDC1, a second adjustable delay unit RDC2 and a third adjustable delay unit RDC3. The positive input end of the first adjustable delay unit is connected with the output end of the NOT gate, and the reverse input end of the first adjustable delay unit is connected with the output end of the transmission gate. The first adjustable delay unit and the second adjustable delay unit and the third adjustable delay unit are connected in series. The positive input end of each adjustable delay unit is connected with the gate of a corresponding transistor, and the reverse output end of each adjustable delay unit is connected with the source of the same transistor. Figure 4

[0060] The tracking module comprises a loop selection state machine, a phase measurement unit, a frequency and phase discriminator, a multiplexer and a filter. The input ends of the multiplexer are connected with the output ends of the loop selection state machine, the phase measurement unit and the frequency and phase discriminator respectively, and the output end of the multiplexer is connected with the input end of the filter. The output end of the filter is connected with the input ends of the pulse generator and the ring voltage controlled oscillator. The input ends of the loop selection state machine and the frequency and phase discriminator are also connected with the reference input signal, and the input end of the phase detection unit is also connected with the output end of the pulse generator.

[0061] The phase measurement unit comprises a phase measurer and a first charge pump connected in series.

[0062] ​​​The phase measurer comprises a plurality of first transistors for comparing the phase of the reference input signal and the pulse generated by the pulse injection locked oscillator module, generating a phase output signal, and sending the phase output signal to the first charge pump.

[0063] The first charge pump comprises a plurality of second transistors and a comparator for converting the phase output signal into a current.

[0064] The phase measurement unit further comprises a polarity detector connected to the first charge pump.

[0065] The phase frequency detector comprises a frequency divider, a phase frequency detector and a second charge pump connected in sequence.

[0066] The frequency divider is used for dividing the clock multiplication signal output by the pulse injection locked oscillator module to obtain a divided clock multiplication signal, and sending the divided clock multiplication signal to the phase frequency detector.

[0067] The phase frequency detector is used for comparing the frequency and phase of the divided clock multiplication signal and the reference input signal, determining an error signal, and sending the error signal to the second charge pump.

[0068] The second charge pump is used for converting the error signal into a current and sending the current to the multiplexer.

[0069] The loop selection state machine comprises a frequency lock detector and a loop selector.

[0070] The frequency lock detector comprises two D flip-flops and a first XOR gate, wherein the outputs of the two D flip-flops are connected to the two inputs of the first XOR gate, respectively.

[0071] The loop selector comprises a second XOR gate, an edge counter and a timer, wherein the output of the second XOR gate is connected to the input of the edge counter, and the output of the timer is connected to the input of the edge counter.

[0072] The pulse generator generates a pulse according to the reference input signal, a power supply voltage and a control voltage generated by the tracking module.

[0073] The ring voltage controlled oscillator generates a clock multiplication signal according to the power supply voltage, or generates a clock multiplication signal according to the power supply voltage and the control voltage, or generates a clock multiplication signal according to the power supply voltage, the pulse and the control voltage.

[0074] The ring voltage-controlled oscillator can directly generate a clock multiplication signal according to a power supply voltage. The ring voltage-controlled oscillator generates the clock multiplication signal according to the power supply voltage and a control voltage, or generates the clock multiplication signal according to the power supply voltage, the pulse and the control voltage, and adjusts and outputs the generated clock multiplication signal according to the power supply voltage and the control voltage, or according to the power supply voltage, the control voltage and the pulse.

[0075] The tracking module includes two loops, one of which is a phase-locked loop and the other is a timing adjustment loop.

[0076] The loop selection state machine selects one of the two loops according to the frequency of the reference input signal, the frequency of the clock multiplication signal generated by the ring voltage-controlled oscillator and the currently running loop, generates a loop control signal and sends it to the multiplexer.

[0077] The phase measurement unit determines a first current according to the pulse and the clock multiplication signal and sends it to the multiplexer.

[0078] The phase-frequency detector determines a second current according to the reference input signal and the clock multiplication signal and sends it to the multiplexer.

[0079] The multiplexer opens the timing adjustment loop and outputs the first current or opens the phase-locked loop and outputs the second current according to the loop control signal.

[0080] The filter filters the first current or the second current to obtain a control voltage and sends it to the pulse injection locked oscillator module.

[0081] The pulse generator is opened with the opening of the timing adjustment loop and is closed with the opening of the phase-locked loop.

[0082] The frequency lock detector is used to compare the frequency of the reference input signal and the frequency of the clock multiplication signal to determine whether the frequency deviation times exceed a threshold value, and if so, sends a first control signal to the loop selector.

[0083] The loop selector determines the loop control signal according to the first control signal and sends it to the multiplexer, starts a timer, and if the timer runs to a time threshold, generates a second control signal as the loop control signal and sends it to the multiplexer.

[0084] The phase output signal is an error signal obtained by comparing the phase of the reference input signal and the pulse.

[0085] The first control signal is used to open the phase-locked loop and the second control signal is used to open the timing adjustment loop.

[0086] The following further illustrates the embodiments of the present application, as shown in Figure 4 .

[0087] The pulse injection locking oscillation module comprises a ring voltage-controlled oscillator and a pulse generator. The tracking module is a mixed frequency tracking loop, comprising two loops, one loop being a timing adjustment loop through a phase measurement unit, a multiplexer and a filter, and the other loop being a phase-locked loop through a frequency and phase discriminator, a multiplexer and a filter. The frequency and phase discriminator is intermittently operated, and the pulse generator is operated with the phase measurement unit.

[0088] The control voltage is used to control the ring voltage-controlled oscillator and the pulse generator to adjust the width and frequency of the pulse, so that the width of the pulse and the oscillation period maintain a suitable ratio. The control voltage of the ring voltage-controlled oscillator and the pulse generator is adaptively adjusted by the tracking module, so that the free running frequency of the ring voltage-controlled oscillator tracks the target output frequency, and the pulse width of the injection signal (injected pulse) is close to a certain ratio of the oscillation period.

[0089] When the device is powered on, the pulse generator and the phase measurement unit do not work, and the ring voltage-controlled oscillator directly generates the clock multiplication signal according to the power supply voltage. Since the frequency difference between the reference input signal (Fref) and the clock multiplication signal (Fout) is too large, the loop selection state machine controls the multiplexer to open the phase-locked loop according to the frequency difference between the reference input signal and the clock multiplication signal, at this time, the frequency discriminator and phase detector work, and the timer starts timing. The frequency discriminator and phase detector determine the second current according to the reference input signal and the clock multiplication signal, and send it to the multiplexer. The second current passes through the multiplexer and is filtered by the filter to obtain the control voltage, which is input to the ring voltage-controlled oscillator. The ring voltage-controlled oscillator generates the clock multiplication signal according to the control voltage and the power supply voltage. When the working time of the frequency discriminator and phase detector reaches the time threshold, the loop selection state machine controls the multiplexer to open the timing adjustment loop. The pulse generator generates pulses according to the reference input signal, the power supply voltage and the control voltage, and sends them to the phase measurer and the ring voltage-controlled oscillator. The ring voltage-controlled oscillator generates the clock multiplication signal according to the pulses, the control voltage and the power supply voltage. The phase measurer determines the first current according to the pulses and the clock multiplication signal, and inputs it to the filter through the multiplexer. The filter filters the first current to obtain the control voltage, which is input to the pulse generator and the ring voltage-controlled oscillator, and the ring voltage-controlled oscillator generates the clock multiplication signal according to the pulses, the power supply voltage and the control voltage. The loop selection state machine determines the to-be-run loop according to the frequency of the reference input signal and the clock multiplication signal, the frequency of the clock multiplication signal and the currently running running loop, generates the loop control signal and sends it to the multiplexer. If the frequency deviation times of the reference input signal and the clock multiplication signal do not exceed the threshold, the multiplexer is continuously controlled to make the timing adjustment loop conductive; if the frequency deviation times of the reference input signal and the clock multiplication signal exceed the threshold, the multiplexer is controlled to make the phase-locked loop conductive, and the frequency discriminator and phase detector work, and the timer starts timing.

[0090] As shown in Figure 1 The two input ends of the first AND gate G1 of the pulse generator are input with the reference input signal and the enable signal respectively, and the power supply voltage is also connected. The output end of the first AND gate G1 is connected with the adjustable delay unit group RDCs, and the adjustable delay unit group RDCs also input the control voltage and the power supply voltage. The two output signals of the adjustable delay unit group RDCs are connected with the input end and the reverse input end of the second AND gate G2 respectively, and the output pulse INJ is output.

[0091] As shown in Figure 2As shown, the circuit schematic diagram of the adjustable delay cell group in the pulse generator of the embodiment of the present application is shown. The adjustable delay cell group includes one NOT gate, one transmission gate, three adjustable delay cells and three transistors. The signal is divided into two paths, and after passing through the NOT gate and the transmission gate, the signal is input to the input end of the first adjustable delay cell RDC1, wherein the output end of the NOT gate is connected with the positive input end of the first adjustable delay cell RDC1, and the output end of the transmission gate is connected with the reverse input end of the adjustable delay cell RDC1. The input end of each adjustable delay cell is connected with a transistor, specifically, the positive input end of the first adjustable delay cell RDC1 is connected with the gate of the transistor T31, the reverse input end of the first adjustable delay cell RDC1 is connected with the source of the transistor T31, and the gates of the transistors T31, T32 and T33 are grounded. The reverse output end of the first adjustable delay cell RDC1 is connected with the positive input end of the second adjustable delay cell RDC2 and the gate of the transistor T32, and the positive output end of the first adjustable delay cell RDC1 is connected with the reverse input end of the second adjustable delay cell RDC2 and the source of the transistor T32. The positive output end of the second adjustable delay cell RDC2 is connected with the reverse input end of the third adjustable delay cell RDC3 and the gate of the transistor T33, and the reverse output end of the second adjustable delay cell RDC2 is connected with the positive input end of the third adjustable delay cell RDC3 and the source of the transistor T33. Each adjustable delay cell also inputs a power supply voltage. One path of the positive output BP1 of the first adjustable delay cell RDC1 and one path of the reverse output BPN3 of the third adjustable delay cell RDC3 serve as two outputs of the adjustable delay cell group, and are input to two input ends of the second AND gate, respectively.

[0092] As shown, Figure 1 The delay between the two signals reaching the next AND gate is generated by the adjustable delay cell group. As shown, Figure 2 The reference input signal is first converted into a differential signal, reaches the first adjustable delay cell RDC1, and is then fed to the next two cascaded adjustable delay cells. The positive output end of the first adjustable delay cell RDC1 and the reverse output end of the third adjustable delay cell RDC3 generate two signals BP1 and BN3, respectively, and perform AND operation. Accordingly, the pulse width of the pulse (injection pulse) injected into the ring voltage-controlled oscillator should be equal to twice the delay time of the adjustable delay cell group. The pulse generator can adaptively adjust the pulse width at different PVT corners by sharing the same power supply voltage VPVCO and control voltage VCTRL with the ring voltage-controlled oscillator. In the embodiment of the present application, the corner change can be adapted by manually changing the configuration of the low-dropout regulator, and the temperature change can be automatically tracked by the timely adjusted control voltage.

[0093] As shown, Figure 5As shown in Fig. 1, the ring voltage-controlled oscillator is used for pulse locking. The ring voltage-controlled oscillator comprises four delay units and four transistors.

[0094] As shown in Fig. 2, the traditional pulse generator comprises two AND gates and a delay unit group DU. The output of the third AND gate G3 is connected to the delay unit group DU and one input of the fourth AND gate G4 respectively, and the inverting output of the delay unit group DU is connected to the other input of the fourth AND gate G4. Figure 6

[0095] The delay unit in the ring voltage-controlled oscillator and the delay unit group in the traditional pulse generator have the same function, and the specific internal structure can be the same or different.

[0096] As shown in Fig. 3, the pulse INJ injected into the ring voltage-controlled oscillator is applied to one of the four delay units (DC3 as shown in the figure), and the injection transistors (T41, T42 and T44) connected with the delay units are connected to the ground to avoid interrupting the injection. The free-running frequency of the ring voltage-controlled oscillator is jointly adjusted by the power supply voltage VPVCO and the control voltage VCTRL. The power supply voltage is adjusted to cover different process corners, and the control voltage is used to adaptively adjust the ring voltage-controlled oscillator to track the temperature change. Figure 5

[0097] As shown in Fig. 4, it is a circuit schematic diagram of the delay unit in the ring voltage-controlled oscillator. It comprises four NOT gates (G5, G6, G7 and G8), two transmission gates and two voltage-controlled capacitors (C1 and C2). Figure 7 As shown in Fig. 5, it is a circuit schematic diagram of the phase measurement unit, which comprises a first charge pump and a phase measurer. The first charge pump further comprises a switch circuit. As shown in Fig. 6, the phase measurement unit comprises 26 transistors and a comparator. The transistors in the phase measurer are first transistors, and the transistors in the first charge pump are second transistors. Among them, transistors T1, T2, T3, T4, T5, T6, T7, T8, T9 and T10 are P-channel transistors, and transistors T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, T24, T25 and T26 are N-channel transistors. The first charge pump uses large-size thick-oxide transistors working in the 2.5V power domain to achieve high matching accuracy, and the phase measurer uses 1.2V transistors to support high working speed.

[0098] Figure 8 Figure 8

[0099] ​​​​​The switching circuit in the first charge pump includes transistors T9, T10, T15, and T16, and a comparator. The positive input terminal of the comparator is connected to the drains of transistors T10 and T16 at point C, with a current of iCP at point C. The output terminal of the comparator is connected to the drains of transistors T19 and T15 at point D, and the negative input terminal of the comparator is also connected to the output terminal. The sources of transistors T9 and T10 are connected to point E, and the sources of transistors T15 and T16 are connected to point F. The gates of T9 and T16 are connected to EN_P, and the gates of T10 and T15 are connected to EN_N.

[0100] In the first charge pump, the sources of transistors T1, T3, T5, and T7 are all connected to the power supply. The gate of T1 is connected to the gate of T7, with a current amplification factor of β. The gate of T17 is connected to the gate of T18, with a current amplification factor of β. The gate of T3 is connected to the gate of T5 at point P. The drains of T13, T14, and T4 are also connected to point P. The gate of T4 is connected to the gate of T6 at VBP. The gate of T12 is connected to the gate of T13 at PO_N. The gates of T2, T4, T6, and T8 are connected to VBP. The gates of T11 and T14 are connected to PO_P. The drain of T1 is connected to the source of T2. The drain of T2 is connected to the gate of T1, the drain of T11, and the drain of T12 at point N. The drain of T3 is connected to the source of T4, the drain of T5 is connected to the source of T6, the drain of T6 is connected to the drain of T17 and the gate of T17, and the source of T17 is grounded. The drain of T7 is connected to the source of T8, the source of T8 is connected to point E, the drain of T18 is connected to point F, and the source of T18 is grounded. The sources of T11 and T13 are connected to point A, and the sources of T12 and T14 are connected to point B.

[0101] like Figure 9 The diagram shows the equivalent logic of the phase meter. Point A is connected to one end of switch S1, and the other end of S1 is connected to the PS_P terminal and ground. Point B is connected to one end of switch S2, and the other end of S2 is connected to the PS_N terminal and ground.

[0102] like Figure 10 The diagram shows the equivalent logic and polarity selection of the phase meter. Point N is connected to one end of switch S3, and the other end of S3 is connected to the PSP_P terminal and ground. Point P is connected to one end of switch S4, and the other end of S4 is connected to the PSP_N terminal and ground. The input current of the parts of N and P connected to switches S3 and S4 is Icp, and the current Icp is equal to the current iCP.

[0103] The drain of transistor T19 and the drain of T20 in the phase measurer are connected to point A, and the drain of T23 and the drain of T24 are connected to point B. The source of T19 and the drain of T21 are connected, and the source of T21 is connected to ground. The source of T20 and the drain of T22 are connected, and the source of T22 is connected to ground. The source of T23 and the drain of T25 are connected, and the source of T25 is connected to ground. The source of T24 and the drain of T26 are connected, and the source of T26 is connected to ground.

[0104] The phase measurement unit also includes a polarity detector, which is introduced to maintain edge-independent output. As shown in Figure 11 , the polarity detector includes two D flip-flops, Dl and D2. The clocked frequency signal is divided into CLK_P and CLK_N, where CLK_P and the pulse are input into Dl to output the PO_P signal, and CLK_N and the pulse are input into D2 to output the PO_N signal. The pulse Pulse (i.e., the pulse INJ) is input into the clock input end of the D flip-flop.

[0105] As shown in FIG. 12(a), it is a schematic diagram of one locking condition. As shown in FIG. 12(b), it is a schematic diagram of another locking condition. The phase measurement unit first divides the injected pulse into two parts by the crossing point of the complementary clock: and Then, the width difference is converted into current by the subsequent first charge pump, where the instantaneous current is determined by the threshold voltage of the polarity selection transistor and the equivalent on-resistance of the phase detection transistor. As shown in Figure 12(a) and 12(b) , the rising edge and the falling edge of the ring voltage-controlled oscillator (the rising edge and the falling edge of CLK_P, and the rising edge and the falling edge of CLK_N) can be locked to the injected pulse in the two locking conditions. This makes the detected phase difference (i.e., the width difference of the two pulses in PS_P and PS_N) present edge-dependent signs. In order to solve this problem, the polarity detector is introduced to distinguish the edge type of the injection moment. In particular, when the injection position is exchanged between the two locking conditions, the connection of the detected pulses of PS_P and PS_N will be exchanged by the polarity selection signals of PO_P and PO_N. Therefore, for Figure 12(a) and 12(b) , the equivalent pulses of PSP_P and PSP_N can be obtained, and thus the edge-dependent output and positive feedback can be avoided.

[0106] As shown in Figure 13The diagram shows a loop selection state machine, including a frequency lock detector (FLD) and a loop selector (LS). The frequency lock detector takes a clock multiplier signal (DIV4_90) divided by 4 and a reference input signal (REF_CLK) as input, and outputs a first control signal (FRE_LOCK) to the loop selector. The loop selector determines the loop control signals based on the first control signal and the INJ_LOCK signal. The loop control signals include a TPD_EN signal controlling the opening of the timing adjustment loop and a PFD_EN signal controlling the opening of the phase-locked loop. The INJ_LOCK signal is obtained by delaying the PO_P signal generated by the polarity detector.

[0107] like Figure 13 As shown, the frequency lock detector includes two D flip-flops, D3 and D4, and an XOR gate XOR1. The clock multiplier signal, after being divided by 4, is input to the D input of D3 and the clock input of D4. The reference input signal is input to the clock input of D3 and the D input of D4. The output signals FD1 of D3 and FD2 of D4 are both input to the XOR gate XOR1. The output signal of XOR1 is the first control signal, which is input to the loop selector.

[0108] The loop selector includes an XOR gate (XOR2), a saturation edge counter (SEC), and a timer. The XOR gate (XOR2) receives the INJ_LOCK signal and a first control signal at its two inputs, respectively. Its output is connected to the saturation edge counter, inputting the output signal IND_LOCK into the counter. The saturation edge counter determines the loop control signal based on the IND_LOCK signal and the reset signal RST. The second loop control signal is generated when the timer reaches a time threshold, controlling the multiplexer to activate the timing adjustment loop. The saturation edge counter is also connected to the timer, which includes three inverters (G21, G22, and G23), two transistors (T51 and T52), a capacitor C11, and a resistor R11, used to start timing based on the PFD_EN signal. For example, at 60ns, when the timer reaches the time threshold of 60ns, a reset signal RST is generated and sent to the saturation edge counter.

[0109] As shown in Figure 14(a), it can be seen that when the distance between the clock rising edge of REF CLK and the clock low level of DIV4_90 and FD1 signal, and the clock high level of REF CLK and FD2 is always kept in a fixed ratio, the injection locking of the ring VCO is achieved. As shown in Figure 14(b), when the ratio cannot be kept fixed, the lock is lost. The frequency lock detector can quickly indicate the false harmonic lock or large frequency deviation by generating edge jumps, but as the frequency difference becomes smaller, as shown in Figure 14(c), the conventional frequency deviation generates a period slip which takes more time. In order to speed up the lock loss detection, INJ_LOCK (i.e. the delayed version of PO_P generated by the polarity detector) is also applied to the loop selector. The total edge jumps of INJ_LOCK and FRE_LOCK signals are recorded by a saturation counter in the loop selector. In the loop selector, the edge transitions on INJ_LOCK signal and FRE_LOCK signal are first calculated by XOR, and then recorded by the saturation counter. Once the number reaches a certain value, the loop selector controls the multiplexer to switch the loop from the timing adjustment loop to the phase-locked loop to start the lock acquisition process. At the same time, a timer with a time constant of about 60 ns is started to charge node A in Figure 13. When the voltage rises to the threshold of the inverter, the loop selector will reset and switch the phase-locked loop back to the timing adjustment loop to enable injection locking. If the ring VCO successfully locks to the injection signal of the target frequency, both INJ_LOCK and FRE_LOCK will remain static, and the loop selector will also remain static, which is the lock loss detection and lock recovery process. Otherwise, the lock loss detection and lock recovery process will be repeated until injection locking is achieved. During the initial start-up, injection locking can be obtained by repeating the lock loss detection and lock recovery process. During normal operation, lock loss can be detected in time to activate the lock loss detection and lock recovery process. Since there is no signal jump in the loop selection state machine during the injection locking mode, the power cost in this lock loss detection and lock recovery process can be negligible. Figure 13

[0110] As shown in Figure 13, the filter is a circuit diagram. The filter includes a switch S1, three capacitors (C21, C22 and C23) and two resistors (R21 and R22), and the switch S1 is closed when the timing adjustment loop is turned on. Figure 15

[0111] ​​The pulse generator of the present application can automatically track the changes of PVT and keep the pulse width at about twice the delay cell. By controlling the pulse generator and the ring voltage-controlled oscillator with the control voltage output by the timing adjustment loop, adaptive pulse width adjustment can be achieved, which can optimize the pulse variation from 9.32ps to 1.47ps and make the tracking bandwidth show good stability. The compact and simple signal connection of the circuit in the phase measurement unit enables it to support high operating speed with low power consumption; the circuit improves the matching accuracy and operating margin of each current mirror, thereby optimizing the current matching accuracy; the competition condition between the injection locking and the frequency tracking loop locking in the traditional design is eliminated in this design. The lock loss detection and lock recovery process of the loop selection state machine improve the lock acquisition capability, and the start-up failure and possible injection lock loss are completely solved.

[0112] In the embodiments of the present application, the pulse generated by the pulse generator can adaptively adjust the pulse width at different PVT corners, always keeping a fixed ratio, so as to ensure that the clock frequency multiplier is always in the best performance state; by determining the loop according to the reference input signal and the clock frequency multiplication signal through the loop selection state machine, the control voltage output by the phase measurement unit can control the pulse generator in the pulse injection locking oscillator module to adjust the width of the pulse according to the power supply voltage and the control voltage, improve the tracking bandwidth of the pulse injection locking oscillator, and thus improve the clock frequency multiplication signal generated by the ring voltage-controlled oscillator. The embodiments of the present application can also effectively prevent the mutual pulling problem in the traditional injection locking and phase-locked loop, while maintaining good in-band noise suppression performance and high operating robustness, making it a competitive choice in practical applications. The phase measurer closely combined with the well-matched first charge pump is used to detect the frequency deviation to generate the control voltage; by controlling the pulse generator and the ring voltage-controlled oscillator with the control voltage output by the timing adjustment loop, adaptive pulse width adjustment can be achieved, which can keep the specific pulse width of the PVT corner; the lock loss detection and lock recovery process are performed in real time by the loop selection state machine, which can quickly detect the lock loss and quickly start the lock recovery process, thereby improving the lock acquisition capability.

[0113] The above merely describes the preferred embodiments of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A pulse generator, characterized by, The adjustable delay unit group comprises a NOT gate, a transmission gate, three adjustable delay units and three transistors. The first AND gate, the adjustable delay unit group and the second AND gate are also connected with a power supply voltage. The input end of the adjustable delay unit group is also connected with the output end of the filter. The adjustable delay unit group comprises a NOT gate, a transmission gate, three adjustable delay units and three transistors. The three adjustable delay units comprise a first adjustable delay unit, a second adjustable delay unit and a third adjustable delay unit. The first adjustable delay unit is connected with the output end of the NOT gate at a positive input end, and is connected with the output end of the transmission gate at a reverse input end. The first adjustable delay unit and the second adjustable delay unit and the third adjustable delay unit are connected in series.

2. A clock frequency multiplier, characterized by The positive input end of each adjustable delay unit is connected with the gate of a corresponding transistor, and the reverse output end is connected with the source of the same transistor. The pulse injection locking oscillation module and the tracking module are connected with each other. The pulse injection locking oscillation module comprises a pulse generator and a ring voltage-controlled oscillator connected in sequence. The tracking module comprises a loop selection state machine, a phase detection unit, a frequency discriminator, a multiplexer and a filter.

3. The clock frequency multiplier of claim 2, wherein, The input ends of the multiplexer are connected with the output ends of the loop selection state machine, the phase detection unit and the frequency discriminator respectively. The output end of the multiplexer is connected with the input end of the filter. The output end of the filter is connected with the input ends of the pulse generator and the ring voltage-controlled oscillator.

4. The clock frequency multiplier of claim 2, wherein, The input ends of the loop selection state machine, the phase detection unit and the frequency discriminator are connected with the output end of the ring voltage-controlled oscillator.

5. The clock frequency multiplier of claim 2, wherein, The input ends of the loop selection state machine and the frequency discriminator are also connected with a reference input signal. The input end of the phase detection unit is also connected with the output end of the pulse generator. The phase detection unit comprises a phase measurer and a first charge pump connected in sequence. The phase measurer comprises a plurality of first transistors.

6. The clock frequency multiplier of claim 2, wherein, The phase measurer compares the phase of the reference input signal and the pulse generated by the pulse injection locking oscillation module, generates a phase output signal and sends it to the first charge pump. The first charge pump comprises a plurality of second transistors and a comparator. The first charge pump converts the phase output signal into a current. The phase detection unit further comprises a polarity detector connected with the first charge pump. The frequency discriminator compares the frequency and phase of the frequency-multiplied signal output by the pulse injection locking oscillation module and the reference input signal, determines an error signal and sends it to the second charge pump. The second charge pump converts the error signal into a current and sends it to the multiplexer. The loop selection state machine comprises a frequency lock detector and a loop selector. The frequency lock detector comprises two D flip-flops and a first XOR gate, wherein the outputs of the two D flip-flops are connected to the two inputs of the first XOR gate respectively; The loop selector comprises a second XOR gate, an edge counter and a timer, wherein the output of the second XOR gate is connected to the input of the edge counter, and the output of the timer is connected to the input of the edge counter.

7. The clock frequency multiplier of claim 2, wherein, The pulse generator generates a pulse according to the reference input signal, the power supply voltage and the control voltage generated by the tracking module; The ring voltage-controlled oscillator generates a clock frequency multiplication signal according to the power supply voltage; Or generates a clock frequency multiplication signal according to the power supply voltage and the control voltage; Or generates a clock frequency multiplication signal according to the power supply voltage, the pulse and the control voltage.

8. The clock frequency multiplier of claim 2, wherein, The tracking module comprises two loops, one of which is a phase-locked loop and the other of which is a timing adjustment loop; The loop selection state machine selects one of the two loops according to the frequency of the reference input signal, the frequency of the clock frequency multiplication signal generated by the ring voltage-controlled oscillator and the currently running loop, generates a loop control signal and sends it to the multiplexer; The phase detection unit determines a first current according to the pulse and the clock frequency multiplication signal and sends it to the multiplexer; The frequency and phase detection unit determines a second current according to the reference input signal and the clock frequency multiplication signal and sends it to the multiplexer; The multiplexer opens the timing adjustment loop and outputs the first current or opens the phase-locked loop and outputs the second current according to the loop control signal; The filter filters the first current or the second current to obtain a control voltage and sends it to the pulse injection lock oscillator module.

Images