An ultrathin integrated chip and a manufacturing method thereof
By using support layers and etching processes made of materials such as SiO2, SiON, and SiN in photonic chip manufacturing, combined with back-side grinding and wet etching, the problems of difficult thickness control and low yield in existing technologies for photonic chips have been solved, and efficient production of thin photonic chips has been achieved.
Patent Information
- Application Number
- CN201980088796.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-01-11
- Filing Date
- 2019-12-26
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2040-06-24
AI Technical Summary
Existing technologies make it difficult to reliably manufacture photonic chips with a thickness of less than 50µm. The chips are easily damaged during back-side grinding and pick-up, resulting in low yield.
The support layer is formed from materials such as SiO2, SiON, and SiN. The device thickness is controlled by etching process, and the chip is separated by back-side grinding and wet etching process. The chip separation is supported by an etchable film.
This has enabled the controllable thickness and high yield manufacturing of thin photonic chips, avoiding chip damage and improving production efficiency.
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Figure CN113924643B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to ultra-thin integrated chips and methods of manufacturing the same, in particular, but not exclusively, to an ultra-thin integrated photonic chip. BACKGROUND
[0002] In all fields or integrated circuits, chips or semiconductor devices are becoming smaller and smaller. With the reduction in size, there are more problems associated with implementing a reliable method of manufacturing thin and ultra-thin chips. This is a particular problem for so-called photonic chips which use light rather than electricity. Photonic chips have many uses and are considered particularly useful for use as probes in molecular environments and the like.
[0003] Currently, standard photonic chips have a thickness of about 750 pm. These are generally reliably manufactured using current techniques as discussed in more detail below. A recent requirement is to find photonic chips with a thickness of less than 50 pm. Current techniques do not give a reliable yield and often the whole wafer can be destroyed by the necessary techniques of the method.
[0004] There are a number of proposals. Currently, wafer backgrinding after photonic device fabrication is the preferred way for manufacturing. However, this backgrinding process is only reliable when the target thickness is greater than 100 pm.
[0005] For target thicknesses of less than 50 pm, it is extremely difficult to control the backgrinding thickness as it is simply too thin for existing methods, especially for processed photonic wafers which have wafer topography and thickness non-uniformities. Picking or removing such thin chips from the wafer is also very difficult and can introduce micro-cracks and chip breakage in the delamination process. Therefore, during wafer backgrinding and / or chip picking or collection of ultra-thin devices, most of the devices can be destroyed.
[0006] Figure 1 An example of a typical process for manufacturing a photonic chip is shown. The substrate 100 is a process of adding, for example, a buried oxide layer (BOX) layer 102 on top of the substrate. Waveguides 104 are deposited and a cladding layer 106 is applied. The device is processed to include a number of deep trenches 108 (two of which are shown). These are to enable individual chips to be separated from each other at a later stage. Once the processing of the chips is complete, a backgrinding process is carried out on the wafer (mounted on an adhesive backing sheet (not shown)) to produce a device as shown in Figure 1 If the thickness requirement is not too thin, the final wafer will have a uniform spread of viable devices. However, for thinner devices and for other problems associated with backgrinding, the whole wafer can be damaged so that there are almost no chips remaining after backgrinding. The wafer is thinned directly by mechanical backgrinding. For thin chips, the thickness control and yield will be very low.
[0007] Other solutions have been proposed to address the need for thinner devices. These include dicing through thinning. This involves temporarily bonding the device wafer into a handling wafer. Thereafter, wafer backgrinding is performed, followed by an automated die singulation process. The same problems exist for thin wafers and chips, i.e. backgrinding and separation of the chips is difficult and yields are low or non-existent. The thickness required for ultra-thin devices is not achievable.
[0008] Another proposal is thinning with buried cavities. This requires defining local buried cavities. Wafer handling is followed by trench etching and chip monolithic singulation by pick and place. This type of process is not feasible for thin devices due to poor yield and reliability. Furthermore, the need to locally pre-define cavities will incur additional process costs.
[0009] Another approach is the known epitaxial growth and selective etching technique. A silicon (Si) epitaxial layer with a highly doped film is deposited on a wafer, followed by a Si epitaxial layer with a lightly doped film. The wafer is backgrinded to thin it, followed by Si etching to thin it further. Again, the use of epitaxial layers and backgrinding do not work well for photonic applications and the failure rate is too high for the method to be suitable for chips with thicknesses in the order of magnitude of 100 pm. The method has a high cost epitaxial process and long process times, and cannot be simply applied to photonic use due to the high losses that can be caused by the doped films.
[0010] It is an object of the present invention to provide a simple manufacturing method to produce thin and more controllable thickness results of integrated photonic chips in an easy to remove manner.
[0011] It is another object of the present invention to achieve an ultra-thin photonic chip and manufacturing method that overcomes at least some of the problems associated with the prior art.
[0012] The embodiments described below are not limited to implementations that solve any or all of the disadvantages of the prior art. SUMMARY
[0013] This Summary is provided to introduce a selection of concepts that are further described below in the of the Invention. This Summary does not necessarily identify key or essential
[0014] According to one aspect of the present invention, there is provided a semiconductor device comprising a support layer formed of a material that is not sensitive to etching processes and which can be deposited to a predetermined thickness in the manufacturing, thereby precisely controlling the thickness required for the device.
[0015] Preferably, the support layer comprises a buffer layer.
[0016] Preferably, the buffer layer comprises SiO2, SiON, SiN.
[0017] Preferably, the support layer further comprises an additional etch stop layer.
[0018] Preferably, the support layer is of the order of tens of pm.
[0019] Preferably, the device is a photonic chip.
[0020] Preferably, the device is an ultra-thin device.
[0021] According to an aspect of the application, there is provided a method comprising: forming a substrate; forming a support layer from a first type of material that is not susceptible to an etching process; the support layer having a predetermined thickness related to a desired thickness of a semiconductor device; forming a device on the support layer; forming at least one layer of cladding material on the device; forming a plurality of trenches in the layer extending at least down to the substrate; applying a film on the cladding material; using an etching process to at least partially remove the substrate to separate the device from other devices on the wafer.
[0022] Preferably, further comprising removing the substrate using a combination of backside grinding and a wet etching process.
[0023] Preferably, further comprising forming an additional etch stop layer on the support layer.
[0024] Preferably, the support layer comprises a buffer layer and comprises at least one of SiO2, SiON and SiN.
[0025] Preferably, further comprising separating the chip by removing the film such that the edges of the individual devices are defined by the trenches.
[0026] Preferably, further comprising forming trenches around each side of the device.
[0027] Preferably, further comprising controlling the formation of the support layer to produce a device having a desired thickness.
[0028] Preferably, the film is a non-etchable material.
[0029] Preferred features can be suitably combined, as will be apparent to those skilled in the art, and can be combined with any of the aspects of the application. BRIEF DESCRIPTION OF DRAWINGS
[0030] Embodiments of the application will be described, by way of example, with reference to the following drawings, in which:
[0031] Figure 1 A schematic diagram illustrating a first prior art method is shown;
[0032] Figure 2 A schematic of a process for manufacturing ultra-thin photonic chips according to an embodiment of the present application is shown.
[0033] Common reference numerals are used throughout the drawings to indicate like features. DETAILED DESCRIPTION
[0034] Embodiments of the present application are described herein below by way of example only. These examples represent the best ways of putting the present application into practice according to the current knowledge of the Applicant, although they are not the only ways in which this could be achieved. The description sets forth the functions and sequence of steps for constructing and operating the examples. However, the same or equivalent functions and sequences can be accomplished by different examples.
[0035] The present application relates to a simple manufacturing method for manufacturing thin integrated chips or semiconductor devices, such as photonic chips that can easily be singulated. The present application enables an increase in yield and a controllable thickness.
[0036] Figure 2 An example method of manufacturing photonic chips having a thickness ranging from a few µm to several tens of µm is shown.
[0037] A silicon substrate 200 is employed. This can be of any suitable size, for example 725 µm (± 25 µm). According to the present application, the material of the substrate needs to be etchable so that it can be removed at a later stage of the process. This will be described in more detail below. The preferred material is silicon, but other substrates can also be used, provided that the material can be removed as required below. For most applications, a silicon substrate is used. However, a glass wafer is also usable, in which case the layers and process flow will be adapted to suit the relevant materials.
[0038] A buffer layer 202 is deposited on the substrate. The thickness of this buffer layer controls the thickness of the final chip. The thickness of the chip is thus precisely controlled, as the thickness of the deposition can be carefully controlled and have a predetermined thickness as required. The buffer layer can be of any suitable material that can act as an etch stop layer during etching of the substrate, including for example SiO2, SiON, SiN, etc. The buffer oxide layer is chosen to be a material that is not etchable or has a high etch selectivity through the later wet etch process.
[0039] Once the overall device thickness is decided, the manufacturer knows the normal thickness of all the necessary device layers, and can then calculate the required thickness of the buffer layer to achieve the required overall device thickness.
[0040] As shown above, the thickness of the buffer layer defines the thickness of the final chip. Different types of chips can be made in different thicknesses, or the same type of chip can require different predetermined thicknesses for one application or another. For example, for neurophotonics applications, the buffer layer can be 20-30 pm.
[0041] In the next step of the process, another etch stop layer 204 is deposited on the buffer layer using a chemical vapor deposition (CVD) process. The thickness of this layer is in the order of a few pm to tens of pm, and can include, for example, SiN, SiON, typically used to separate the BOX layer and the buffer layer, depending on the requirements. The etch stop layer is used to stop etching in subsequent steps of the process, as will be described in more detail below. This layer has essentially two different purposes. The first is to separate the BOX layer and the buffer layer. The second is to act as an etch stop for the cladding etch of the buffer layer, in case the buffer layer is an oxide, before etching the buffer layer. The etch stop layer can be omitted based on the application, as well as design requirements and the material used.
[0042] In the next step of the process, a BOX layer 206 is deposited on the etch stop layer. The thickness of this layer is a few pm, including, for example, an oxide. This is a photonic functional layer with a low refractive index compared to the waveguide layer, in order to be used for optical light confinement.
[0043] In the next step of the process, a waveguide 208 is deposited on the BOX layer. The thickness of this layer is between tens of nm to a few pm, including, for example, silicon, silicon nitride (SiN), silicon oxynitride (SiON), polysilicon, or amorphous silicon. For example, in a photonic chip, the waveguide is deposited above the BOX layer. Different devices can be fabricated at this point, depending on the requirements of the proposed chip. Other devices can be fabricated for different types of chips. Any appropriate equipment can be added depending on the application and functionality of the chip.
[0044] In the next step of the process, a cladding layer 210 is deposited on the device, as required. The thickness of this layer is a few pm, including, for example, an oxide layer.
[0045] In the next process step, deep trenches 212 are applied on the wafer. In the example shown, two are located on either side of the waveguide. The trenches are formed by any appropriate process, and can include, for example, reactive ion etching (RIE) or inductively coupled plasma etching (ICP). The trenches are formed to be as deep as the substrate only, and there is essentially no trench in the substrate. The reason for this will be explained in more detail below. Although not shown, there are trenches separating each chip from the next in both the X and Y directions on the wafer.
[0046] After the wafer has been fabricated and the trenches formed, the wafer is attached to a film, such as a Mylar film (not shown) or a UV tape. At the next stage of the process, the film is applied to the cladding to hold the chips in place. Once supported by the film, the wafer will undergo a process to remove the entire substrate. This can include, at least in part, a backgrinding process. Using backgrinding, the substrate is reduced from its original thickness to about 50 pm (± 25 pm) to ensure that the total remaining thickness is about 100 pm, which is the minimum thickness to ensure that the backgrinding yield is sufficient. The amount of substrate removed by backgrinding is selected to be optimal for preventing damage to the overlying surface of the wafer. The resulting device is shown in Figure 2 The backgrinding process includes grinding away a portion of the substrate while the wafer is supported on the film using a grinder.
[0047] The material of the film is desirably non-etchable so that the wafer remains intact during subsequent wet etching.
[0048] In the next stage of the invention, as shown in Figure 2 The ground wafer undergoes a silicon wet etching process that removes the remaining portion of the substrate. The wet etching process includes exposing the substrate silicon to a solution such as tetramethylammonium hydroxide (TMAH) to remove the remaining silicon and automatically separate from the chips.
[0049] As shown in Figure 2 The wet etching process removes all of the material of the deep trench from top to bottom. The buffer layer is not etched because it is made of a non-etchable material. The thickness of the buffer layer is predetermined so that the resulting chip has the desired thickness. Thus, the resulting device will have the buffer layer as a support layer instead of the substrate, which is typically used for that purpose.
[0050] It should be noted that the removal of the substrate to leave the buffer layer as a support layer for the device can be performed in one or more different steps. For example, backgrinding and wet etching; in some cases, only wet etching; or any other appropriate step or combination of steps.
[0051] As a result of the trenching, the individual devices can be easily separated from each other on the wafer area. Once the substrate is etched away, there is nothing holding the individual chips together except the film carrier. The individual chips are either held in place by the film (not shown) or, if the film is etched, can be restored after etching.
[0052] The method of the invention and the resulting chip are photonic chips. However, it should be understood that the process can be used for other types of ultra-thin processing methods and chips. Included are, for example, thin devices such as flexible displays.
[0053] The present invention can include a variety of variations and alternatives to the above examples. These are intended to be included within the scope of the present invention. The present invention is particularly useful for photonic chips, but can also be used for other types of devices, such as flexible electronic devices.
[0054] According to an aspect of the present invention, there is provided a semiconductor device, the semiconductor device comprising a support layer formed of a material that is not susceptible to an etching process and which can be deposited to a predetermined thickness in manufacture, thereby to accurately control the thickness required of the device.
[0055] Preferably, the support layer comprises a buffer layer.
[0056] Preferably, the buffer layer comprises SiO2, SiON, SiN.
[0057] Preferably, the support layer further comprises an additional etch stop layer.
[0058] Preferably, the support layer is of the order of tens of μm.
[0059] Preferably, the device is a photonic chip.
[0060] Preferably, the device is an ultra-thin device.
[0061] According to an aspect of the present invention, there is provided a method, the method comprising: forming a substrate; forming a support layer from a first type of material that is not susceptible to an etching process; the support layer having a predetermined thickness related to a required thickness of a semiconductor device; forming a device on the support layer; forming at least one layer of cladding material on the device; forming a plurality of trenches in the layer extending at least down to the substrate; applying a film on the cladding material; using an etching process to at least partially remove the substrate to separate the device from other devices on the wafer.
[0062] Preferably, further comprising removing the substrate using a combination of backside grinding and a wet etching process.
[0063] Preferably, further comprising forming an additional etch stop layer on the support layer.
[0064] Preferably, the support layer comprises a buffer layer and comprises at least one of SiO2, SiON and SiN.
[0065] Preferably, further comprising separating the chip by removing the film such that the edges of the individual devices are defined by the trenches.
[0066] Preferably, further comprising forming trenches around each side of the device.
[0067] Preferably, further comprising controlling the formation of the support layer to produce a device having a required thickness.
[0068] Preferably, the film is a non-etchable material.
[0069] It will be apparent to those skilled in the art that any range or device value given herein can be extended or modified without losing the intended effect. Similarly, any material can be replaced by another material having similar properties.
[0070] It will be understood that the benefits and advantages described above relate to one embodiment or can relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.
[0071] Reference to the term "one" throughout this document refers to one or more of these. The term "comprising" is used herein to mean including the recited method blocks or elements, but not exclusive of additional blocks or elements. The term "method" refers to methods of any suitable process, whether or not any acts are performed by computers or computer-enabled devices.
[0072] The steps of the methods described herein can be performed in any suitable order, or simultaneously where appropriate. In addition, individual blocks can be deleted from any of the methods without departing from the spirit and scope of the subject matter described herein. Aspects of any of the examples described above can be combined with aspects of any other example described to form further examples without losing the intended effect.
[0073] It will be appreciated that the above descriptions of preferred embodiments are given by way of example only, and that various modifications can be made by those skilled in the art. Although various embodiments have been described above with a certain degree of particularity, the skilled person can make numerous alterations to the disclosed embodiments without departing from the spirit or scope of the present invention.
Claims
1. A semiconductor device, characterized by, including a buffer layer and an etch stop layer deposited on the buffer layer; the buffer layer including at least one of SiO2, SiON, SiN and having a predetermined thickness; the buffer layer serving as a support layer for the semiconductor device after removal of a substrate of the semiconductor device; and the semiconductor device having a thickness of less than 50 μm.
2. The semiconductor device according to claim 1, wherein The buffer layer has a thickness of 3 to 30 μm.
3. The semiconductor device according to claim 1 or 2, wherein The semiconductor device is a photonic chip.
4. A method of manufacturing a semiconductor device, characterized by, The method includes: forming a substrate; forming a buffer layer on the substrate, the buffer layer including at least one of SiO2, SiON, and SiN and having a predetermined thickness related to a desired thickness of the semiconductor device; forming an etch stop layer on the buffer layer; forming a plurality of devices on the etch stop layer; forming at least one layer of cladding material on the plurality of devices; forming a plurality of trenches in the cladding material, the etch stop layer, and the buffer layer, the plurality of trenches extending at least down to the substrate; applying a film on the at least one layer of cladding material; and removing the substrate at least partially using an etching process to separate the semiconductor device from other devices on a wafer, the buffer layer of the separated semiconductor device serving as a support layer for the semiconductor device after removal of a substrate of the semiconductor device; and the separated semiconductor device having a thickness of less than 50 μm.
5. The method of claim 4, wherein, further including removing the substrate using a combination of backside grinding and a wet etching process.
6. The method according to claim 4 or 5, characterized in that, further including separating the semiconductor device by removing the film such that edges of the individual semiconductor device are defined by the plurality of trenches.
7. The method according to claim 4 or 5, characterized in that, The forming a plurality of trenches includes forming a trench around each side of the semiconductor device.
8. The method according to claim 4 or 5, characterized in that, further including controlling formation of the buffer layer to produce the semiconductor device having a desired thickness.
Citation Information
Patent Citations
Method for producing semiconductor device
CN101140861A
Silicon photonics wafer using standard silicon-on-insulator processes through substrate removal or transfer
CN103258735A