A method for preparing a nanogrid and applications thereof

Abstract

The application provides a preparation method of a nanometer grid, and the structure of the nanometer grid prepared by the method comprises a wafer, a first isolation layer, a nanometer grid, a second isolation layer, a third isolation layer formed by stacking the first isolation layer, and a composite isolation layer formed by stacking the second isolation layer, and the application also provides a preparation method and application thereof. The method of the application can simplify the preparation of the nanometer grid, accurately control the size of the grid, realize the preparation of the nanometer grid device, and further improve the performance of the electronic device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor device preparation, not only discrete devices, but also integrated circuit preparation, and in particular to a method for preparing a nanometer gate using thin film deposition technology and its application. BACKGROUND

[0002] In the field of integrated circuits, the development is towards higher integration, and new processes and technologies are constantly developed to achieve smaller line width chips, and gradually approach their physical limits.

[0003] The gate is the control terminal of the transistor, and the gate size has an important influence on the performance of the electronic device. At present, the nanometer gate length size processing of the device becomes increasingly difficult. When using the existing photolithography technology to prepare electronic devices, the gate length size not only depends on the resolution of the photolithography equipment, but also depends on the type of photoresist, baking temperature, exposure dose, developing temperature and time and other factors in the photolithography process. This leads to the gate length size of the device not easy to be accurately controlled, especially the preparation of nanometer gate. At present, the main way to prepare nanometer gate is to use extreme ultraviolet photolithography machine combined with FIN-FET process to prepare, which requires high cost and large demand for equipment, and is not easy to produce.

[0004] In addition to using extreme ultraviolet photolithography machine to prepare 100 nm and below size micro-pattern, electron beam exposure technology (EBL) can also be used to prepare. The de Broglie wavelength of the electron is very short, and a fine structure below 10 nm can be prepared. However, for EBL, its efficiency is low, and has a strong proximity effect, and has a high requirement for the stability of the device, and the development and etching process for electron beam exposure also has great problems.

[0005] In order to maintain the continuous development of the integrated circuit industry, new preparation methods need to be developed to simplify the preparation of nanometer gate, accurately control the gate length size, and realize the preparation of nanometer gate device, and further improve the performance of electronic devices. SUMMARY

[0006] The purpose of the present application is to overcome the shortcomings of the current means, to prepare and obtain nanometer gate, and to propose a method for preparing nanometer gate by combining thin film deposition technology, to improve the preparation process of the device and reduce the preparation cost of the device.

[0007] Before describing the content of the present application, the terms used in this paper are defined as follows:

[0008] The term "ALD" refers to: Atomic layer deposition.

[0009] The term "CMP" refers to: Chemical Mechanical Polishing.

[0010] The term "RIE" refers to: Reaction Ion etching.

[0011] The term "PECVD" refers to: Plasma Enhanced Chemical Vapor Deposition.

[0012] The term "ICP-CVD" refers to: Inductive Coupled Plasma Chemical Vapor Deposition.

[0013] The term "DUV lithography" refers to: Deep Ultra Violet lithography.

[0014] The term "EUV lithography" refers to: Extreme Ultra Violet lithography.

[0015] The term "HEMT" refers to: High Electron Mobility Transistor.

[0016] The term "NAND" refers to: Not AND, computer flash memory device.

[0017] The term "PSG" refers to: Phosphosilicate Glass.

[0018] The term "ICP" refers to: Inductive Coupled Plasma.

[0019] The term "MESFET" refers to: Metal-Semiconductor Field Effect Transistor.

[0020] The term "MOSFET" refers to: Metal-Oxide-Semiconductor Field-Effect Transistor.

[0021] A first aspect of the present invention provides a method of fabricating a nanogrid as described in the first aspect, the method comprising the steps of:

[0022] (1) providing a wafer required for the process fabrication;

[0023] (2) depositing a first isolation layer material on the wafer;

[0024] (3) patterning the first isolation layer;

[0025] (4) depositing a second isolation layer material to cover the patterned structure;

[0026] (5) depositing a third isolation layer material to fill the trench and cover the surface; wherein the third isolation layer material is the same as the first isolation layer material;

[0027] (6) planarizing the surface of the material obtained in step (5) to obtain a structure in which the first isolation layer, the second isolation layer and the third isolation layer are arranged alternately;

[0028] (7) etching to remove the second isolation layer between the first isolation layer and the composite isolation layer to the surface of the wafer;

[0029] (8) depositing a nanometer grid material to fill the trench and cover the surface;

[0030] (9) planarizing the surface of the material obtained in step (8) to remove the nanometer grid material on the surface to obtain the nanometer grid;

[0031] Preferably, the materials of the first isolation layer and the third isolation layer are the same.

[0032] More preferably, the material of the nanometer grid is selected from one or more of gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, and polysilicon.

[0033] According to the preparation method of the first aspect of the present application, the line width of the nanometer grid is 100 nm or less, preferably 28 nm or less, preferably 14 nm or less, preferably 7 nm or less, more preferably 5 nm or less, and most preferably 3 nm or less.

[0034] According to the preparation method of the first aspect of the present application, the wafer material is selected from one or more of silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphorus, and germanium.

[0035] Preferably, the wafer is a wafer with a functional layer.

[0036] According to the preparation method of the first aspect of the present application, the material of the isolation layer is selected from one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide.

[0037] The thickness of the first isolation layer is 5 nm or more.

[0038] According to the preparation method of the first aspect of the present application, wherein the distance between the patterns in step (3) is not less than 2 times the thickness of the second isolation layer.

[0039] According to the preparation method of the second aspect of the present application, wherein the pattern preparation technique in step (3) is selected from one or more of the following: photolithography, electron beam exposure, laser direct writing, etc.

[0040] Preferably, the photolithography is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.

[0041] According to the preparation method of the first aspect of the present application, wherein the thickness of the second isolation layer material in step (4) is 1 nm or more, and the thickness is less than one half of the thickness of the first isolation layer.

[0042] The planarization method in step (6) and step (9) is selected from one or more of the following: CMP technology, PSG technology (deposition of PSG material combined with heating to make the surface flat), ion selective bombardment (use of ion selective bombardment to make the surface flat), large area etching (including argon ion etching, RIE technology, ICP technology).

[0043] Preferably, the CMP technology.

[0044] According to the preparation method of the first aspect of the present application, wherein the thickness of the second isolation layer is consistent with the line width of the nanometer grid,

[0045] The method further comprises the following steps:

[0046] (10) treating the non-nanometer grid reserved area with a conventional process to obtain the desired mesa structure;

[0047] Preferably, the conventional process is selected from one or more of the following: photolithography, wet etching, dry etching, etc.

[0048] The second aspect of the present application provides a nanometer grid, the structure of which comprises a wafer and a first isolation layer, a nanometer grid, and a second isolation layer superimposed on the third isolation layer to form a composite isolation layer (hereinafter referred to as a composite isolation layer) arranged alternately on the wafer;

[0049] Wherein, the line width of the nanometer grid is 100 nm or less, preferably 28 nm or less, preferably 14 nm or less, preferably 7 nm or less, more preferably 5 nm or less, and most preferably 3 nm or less;

[0050] The material of the nanometer grid is selected from one or more of the following: gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polysilicon;

[0051] The etching selectivity ratio of the material of the first and second isolation layers is greater than 1:2.

[0052] According to the nanometer grid of the first aspect of the application, wherein the wafer material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphorus, germanium;

[0053] Preferably, the wafer is a wafer with a functional layer.

[0054] According to the nanometer grid of the first aspect of the application, wherein the material of the isolation layer is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, polyimide.

[0055] The second aspect of the application provides a semiconductor device comprising a nanometer grid prepared according to the preparation method of the first aspect;

[0056] Preferably, the semiconductor device is selected from one or more of the following: integrated circuit, HEMT, MESFET, MOSFET, NAND Flash, NOR Flash, DRAM.

[0057] The present application relates to the field of semiconductor device preparation, not only to discrete devices, but also to the field of integrated circuit preparation.

[0058] The present application provides a nanometer grid prepared by combining thin film deposition technology, the structure of the nanometer grid is as follows from bottom to top:

[0059] Wafer required by the process;

[0060] The first isolation layer, the nanometer grid, the second isolation layer and the third isolation layer form a composite isolation layer;

[0061] The material surface after planarization.

[0062] Preferably, the wafer includes but is not limited to silicon substrate, sapphire substrate, etc.

[0063] Preferably, the wafer refers to a wafer with a functional layer;

[0064] Preferably, the material of the isolation layer includes but is not limited to silicon nitride, silicon oxide, etc.

[0065] Preferably, the material of the first isolation layer is the same as that of the third isolation layer;

[0066] Preferably, the etching selectivity ratio between the first isolation layer and the second isolation layer is greater than 1:2;

[0067] Preferably, the preparation method of the first isolation layer, the second isolation layer and the third isolation layer comprises, but is not limited to, ALD, PECVD, ICP-CVD and the like;

[0068] Preferably, the material of the nanometer grid comprises, but is not limited to, gold, nickel, aluminum, polysilicon, titanium nitride and the like;

[0069] Preferably, the preparation method of the nanometer grid comprises, but is not limited to, electron beam evaporation, sputtering and the like.

[0070] The application provides a method for preparing a nanometer grid by using a thin film deposition technology, comprising the following steps:

[0071] Providing a wafer with a planarized surface required by the process;

[0072] Growing a first isolation layer material on the wafer surface by using a thin film deposition technology;

[0073] Preparing a related pattern structure by using a photolithography technology or other pattern preparation technology;

[0074] Growing a second isolation layer material by using a thin film deposition technology to coat the pattern structure;

[0075] Growing a third isolation layer material by using a thin film deposition technology to fill the trench and cover the surface;

[0076] Obtaining a planar surface and exposing the structure of the first, second and second isolation layers alternately arranged with the composite isolation layer of the third isolation layer by using a CMP technology;

[0077] Removing the second isolation layer material between the adjacent first isolation layer and the composite isolation layer until the wafer surface by using an etching technology;

[0078] Depositing a nanometer grid material by using a material deposition technology to fill the trench and cover the surface;

[0079] Removing the surface nanometer grid material and exposing the structure of the first isolation layer, the nanometer grid and the second isolation layer alternately arranged with the composite isolation layer of the third isolation layer by using a CMP technology;

[0080] Performing a subsequent process required for preparing the structure.

[0081] The wafer comprises not only common substrate materials such as silicon, gallium arsenide, silicon carbide and the like, but also wafers with functional layers;

[0082] The thin film deposition technology for depositing the first isolation layer material on the wafer comprises, but is not limited to, ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering and the like;

[0083] The first isolation layer material is deposited on the wafer by thin film deposition technology, and the isolation layer material includes but is not limited to silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride and the like.

[0084] The first isolation layer material is deposited on the wafer by thin film deposition technology, and the thickness should be at least 5nm.

[0085] The first isolation layer is prepared by using photolithography technology or other pattern preparation technology to obtain the related pattern structure, wherein the photolithography technology includes controllable photolithography technology such as ordinary ultraviolet photolithography, DUV photolithography, EUV photolithography, immersion photolithography and the like.

[0086] The first isolation layer is prepared by using photolithography technology or other pattern preparation technology to obtain the related pattern structure, wherein the other pattern preparation technology includes but is not limited to controllable pattern preparation technology such as electron beam exposure technology, laser direct writing technology and the like.

[0087] The second isolation layer material is deposited by using thin film deposition technology to cover the pattern structure, and the isolation layer material includes but is not limited to silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride and the like.

[0088] The second isolation layer material is grown by using thin film deposition technology to cover the pattern structure, and the thickness of the isolation layer material should be at least 1nm.

[0089] The third isolation layer material is grown by using thin film deposition technology, which is consistent with the material of the first isolation layer.

[0090] The first isolation layer material and the second isolation layer material are grown by using thin film deposition technology, and the two materials should have a large etching selectivity ratio, and the etching selectivity ratio of the materials of the first isolation layer and the second isolation layer is greater than 1:2.

[0091] The material is deposited by using material deposition technology to fill the gate trench and cover the surface, and the deposition technology includes but is not limited to electron beam evaporation, sputtering, chemical deposition and the like.

[0092] The material is deposited by using material deposition technology to fill the gate trench and cover the surface, and the material includes but is not limited to gold, aluminum, nickel, titanium, polysilicon, tungsten, titanium nitride and the like.

[0093] In the process, the non-nano gate reserved area can be treated by conventional process to obtain the required mesa structure.

[0094] The thickness of the second isolation layer determines the final line width, and the thickness is not particularly limited, and can cover the current 100nm, 28nm, 14nm, 7nm process, and can even be widened to 5nm, 3nm process, etc.

[0095] The process result is a nanometer grid structure, and subsequent processes of the nanometer grid include but are not limited to microelectronic devices such as HEMT, memory devices such as NAND.

[0096] The method of the present application can have the following beneficial effects:

[0097] The method of the present application can simplify the preparation of nanoscale gates, accurately control the gate length size, and realize the preparation of nanometer grid devices, thereby improving the performance of electronic devices. BRIEF DESCRIPTION OF DRAWINGS

[0098] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings, in which:

[0099] Figure 1 The flowchart of embodiments 1-2 of the present application is shown.

[0100] Figure 2 The schematic diagram of preparing the first isolation layer in embodiments 1-2 of the present application is shown.

[0101] Figure 3 The schematic diagram of preparing a patterned structure on the first isolation layer in embodiments 1-2 of the present application is shown.

[0102] Figure 4 The schematic diagram of coating the patterned structure with the second isolation layer in embodiments 1-2 of the present application is shown.

[0103] Figure 5 The schematic diagram of filling the trench with the third isolation layer in embodiments 1-2 of the present application is shown.

[0104] Figure 6 The schematic diagram after surface planarization by CMP in embodiments 1-2 of the present application is shown.

[0105] Figure 7 The schematic diagram of removing the second isolation layer between the adjacent first isolation layer and the composite isolation layer by etching technology in embodiments 1-2 of the present application is shown.

[0106] Figure 8 The schematic diagram of preparing a gate by material deposition technology in embodiments 1-2 of the present application is shown.

[0107] Figure 9 The schematic diagram of removing the surface gate material by CMP technology in embodiments 1-2 of the present application is shown.

[0108] Figure 10 Embodiment 1-2 of the present application removes the isolation material between the gate materials, forming nanogates isolated by air.

[0109] Figure 11 A flow chart of Embodiment 3 of the present application is shown.

[0110] Figure 12 A schematic diagram of preparing the first isolation layer in Embodiment 3 of the present application is shown.

[0111] Figure 13 A schematic diagram of preparing a patterned structure on the first isolation layer in Embodiment 3 of the present application is shown.

[0112] Figure 14 A schematic diagram of coating the patterned structure with the second isolation layer in Embodiment 3 of the present application is shown.

[0113] Figure 15 A schematic diagram of filling the trench with the third isolation layer in Embodiment 3 of the present application is shown.

[0114] Figure 16 A schematic diagram after surface planarization by CMP in Embodiment 3 of the present application is shown.

[0115] Figure 17 A schematic diagram of removing the second isolation layer between the adjacent first isolation layer and the composite isolation layer by etching in Embodiment 3 of the present application is shown.

[0116] Figure 18 A schematic diagram of preparing the gate by metal deposition in Embodiment 3 of the present application is shown.

[0117] Figure 19 A schematic diagram of removing the surface metal by CMP in Embodiment 3 of the present application is shown.

[0118] Figure 20 A schematic diagram of preparing the source-drain pattern by photolithography in Embodiment 3 of the present application is shown.

[0119] Figure 21 A schematic diagram of removing the exposed first isolation layer by etching in Embodiment 3 of the present application is shown.

[0120] Figure 22 A schematic diagram of preparing the source-drain electrode by metal deposition in Embodiment 3 of the present application is shown.

[0121] Explanation of reference signs:

[0122] 1, wafer; 2, first isolation layer material; 3A, 3B, 3C, second isolation layer material; 4, third isolation layer material; 5, gate material; 6, wafer with HEMT functional layer; 7, photoresist, 8, source-drain electrode metal. DETAILED DESCRIPTION

[0123] The present application will be further described by way of specific examples. It should be understood that these examples are for illustration only and should not be construed as limiting the present application in any way.

[0124] This section generally describes the materials used in the experiments of the present application and the experimental methods. Although many of the materials and methods used to achieve the objectives of the present application are known in the art, the present application is described in as much detail as possible. It is clear to those skilled in the art that, in the context, the materials and methods used in the present application are known in the art if not specifically mentioned.

[0125] Example 1

[0126] This example is used to illustrate the method for preparing a nanometer grid using thin film deposition technology according to the present application.

[0127] The specific process is shown in Figure 1 and comprises the following steps:

[0128] S100: providing a wafer 1 required for the process;

[0129] S200: depositing a first isolation layer material 2;

[0130] S300: preparing the first isolation layer 2 into a strip-shaped pattern structure;

[0131] S400: depositing a second isolation layer material 3, which is divided into 3A, 3B, and 3C according to different deposition positions;

[0132] S500: depositing a third isolation layer material 4 to fill the trench;

[0133] S600: planarizing the surface of the material to obtain a structure in which the first, second, and second isolation layers are arranged alternately with the third isolation layer;

[0134] S700: etching to remove the second isolation layer 3B between the adjacent first isolation layer and the composite isolation layer;

[0135] S800: depositing a gate material 5;

[0136] S900: planarizing the surface of the material to remove the gate material 5 on the surface.

[0137] In this example, the material of the wafer 1 in S100 can be selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium, and a wafer with a functional layer.

[0138] In one preferred embodiment, the material of wafer 1 is selected to be a (001) oriented silicon substrate.

[0139] The deposition method in S200 is a thin film deposition technique selected from one or more of the following: ALD, PECVD, ICP-CVD, and reactive ion magnetron sputtering.

[0140] The thickness of the first isolation layer material 2 in S200 is 5 nm or more.

[0141] The material of the isolation layer in this embodiment is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, polyimide, etc.

[0142] The etching selectivity of the materials of the first and second isolation layers is at least 1:2.

[0143] In one preferred embodiment, a 100 nm thick first isolation layer material 2 of aluminum oxide is deposited using a CVD technique, as shown in Figure 2

[0144] The patterning technique in S300 is selected from one or more of the following: photolithography, electron beam exposure, and laser direct writing; the photolithography is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, and immersion lithography.

[0145] In one preferred embodiment, a photolithography plate with a line width of 180 nm, a pitch of 200 nm, and a period of 380 nm is used in combination with photolithography exposure and development to obtain the corresponding photoresist pattern structure.

[0146] In one preferred embodiment, the following method is used to transfer the strip structure to the aluminum oxide: using photoresist as a mask, combining with RIE etching technology, using BCl3 as the etching gas, a power of 150 W, and an etching time of 3 min, the photoresist pattern is transferred to the aluminum oxide, with a line width of 180 nm and a groove width of 200 nm between two aluminum oxide structures, as shown in Figure 3

[0147] The deposition method in S400 is a thin film deposition technique selected from one or more of the following: ALD, PECVD, ICP-CVD, and reactive ion magnetron sputtering.

[0148] The thickness of the second isolation layer material 3A, 3B, 3C in S400 is 1 nm or more.

[0149] ​​In a preferred embodiment, the second isolation layer material 3A, 3B, 3C is grown by ALD technology, the deposition temperature of the 10 nm thick silicon dioxide is 200 °C, the precursor material is aminosilane and water vapor, the deposition time is 1 h, and the surface pattern structure is coated, as shown in Figure 4 .

[0150] The deposition method in S500 is a thin film deposition technology selected from one or more of the following: ALD, PECVD, ICP-CVD, and reactive ion magnetron sputtering.

[0151] In a preferred embodiment, the third isolation layer material 4 is deposited by CVD technology, and the thickness of the 180 nm thick aluminum oxide material is filled in the patterned trench, as shown in Figure 5 .

[0152] The planarization method in S600 is selected from one or more of the following: CMP technology, PSG technology, ion selective bombardment, and large area etching.

[0153] In a preferred embodiment, surface planarization is performed by CMP technology: polishing treatment is performed using a polishing machine combined with an aluminum oxide polishing liquid, the polishing rate is 10 nm / min, the height of the remaining isolation layer is the height of the initially deposited first isolation layer material 2 aluminum oxide, i.e. 100 nm, so that the surface exposes the pattern of alternating aluminum oxide, silicon oxide, and aluminum oxide, as shown in Figure 6 .

[0154] The etching method in S700 is selected from one or more of the following: RIE and ICP.

[0155] In a preferred embodiment, the exposed second isolation layer material 3B silicon dioxide is etched by RIE etching technology: CHF3 and O2 are used as etching gas, the power is set to 150 w, the flow rates are CHF3: 25 sccm and O2: 25 sccm, respectively, the etching time is 3 min, and a groove structure with a width of 10 nm is obtained, as shown in Figure 7 .

[0156] The deposition method in S800 is selected from one or more of the following: electron beam evaporation technology, sputtering, ALD, etc.

[0157] The material of the gate in S800 is selected from one or more of the following: gold, aluminum, nickel, titanium, germanium, platinum, chromium, polysilicon, titanium nitride, etc.

[0158] In a preferred embodiment, metal aluminum is deposited by electron beam evaporation technology: metal aluminum is evaporated using an electron beam evaporation device at a rate of 1 A / s, the etched trench is filled, and full coverage of the surface layer is achieved, as shown in Figure 8 .

[0159] The planarization method in S900 is selected from one or more of the following: CMP technology, PSG technology, ion selective bombardment.

[0160] In a preferred embodiment, the surface is planarized by CMP technology: the surface is polished by a polishing machine combined with a polishing solution of aluminum metal, at a polishing rate of 10 nm / min, to remove the surface gate metal 5 aluminum metal. Finally, a device structure with aluminum metal as the gate is obtained, as shown in Figure 9 .

[0161] Figure 2 A schematic diagram corresponding to the growth of silicon oxide on the silicon surface in this embodiment; Figure 3 A schematic diagram corresponding to the preparation of a patterned structure on the silicon oxide in this embodiment; Figure 4 A schematic diagram corresponding to the growth of silicon nitride covering the silicon oxide structure in this embodiment; Figure 5 A schematic diagram corresponding to the deposition of a full trench of silicon oxide material in this embodiment; Figure 6 A schematic diagram corresponding to the surface planarization by CMP in this embodiment; Figure 7 A schematic diagram corresponding to the etching and removal of exposed silicon nitride; Figure 8 A schematic diagram corresponding to the deposition of aluminum metal by electron beam; Figure 9 A schematic diagram corresponding to the surface planarization by CMP to remove the surface aluminum metal in this embodiment.

[0162] Example 2

[0163] The embodiment of the present application relates to a method for preparing a nanometer gate by thin film deposition technology, and a specific process is shown in Figure 1 , which comprises the following steps:

[0164] S100: providing a wafer 1 required for process preparation;

[0165] S200: depositing a first isolation layer material 2;

[0166] S300: preparing the first isolation layer 2 into a strip-shaped pattern structure;

[0167] S400: depositing a second isolation layer material 3, marked as 3A, 3B and 3C according to different deposition positions;

[0168] S500: depositing a third isolation layer material 4 to fill the trench;

[0169] S600: planarizing the surface of the material to obtain a structure in which the first, second and second isolation layers are stacked with the third isolation layer arranged alternately;

[0170] S700: etching to remove the second isolation layer 3B between the adjacent first isolation layer and the composite isolation layer;

[0171] S800: depositing a gate material 5;

[0172] S900: planarizing the material surface to remove the gate material 5 on the surface.

[0173] In this embodiment, first, a 7-nm first isolation layer material 2, i.e., silicon oxide material, is deposited on a provided silicon substrate with a (001) crystal orientation by using the ALD technique, the deposition temperature is 200°C, the precursor material used is aminosilane and water vapor, and the deposition time is 0.5 h, as shown in FIG. 1A. Figure 2

[0174] Then, a photoetching technique is used to expose and develop the photoresist pattern in combination with a photoetching plate with a line width of 7 nm, a pitch of 14 nm, and a period of 20 nm, the exposure time is 4 s, and the development time is 30 s, to obtain the corresponding photoresist pattern structure.

[0175] Then, the strip structure is transferred to the aluminum oxide: the photoresist is used as a mask, the RIE etching technique is used, BCl3 is used as the etching gas, the power is 150 W, and the etching time is 1 min, to transfer the photoresist pattern to the aluminum oxide, the width of the silicon oxide strip structure is 7 nm, and the width of the groove between the two silicon oxide structures is 13 nm, as shown in FIG. 2A. Figure 3

[0176] Then, the ALD technique is used to grow 3-nm second isolation layer materials 3A, 3B, and 3C, i.e., silicon nitride, the deposition temperature is 200°C, the precursor material used is aminosilane and nitrogen, the deposition time is 0.3 h, and the surface pattern structure is coated, as shown in FIG. 3A. Figure 4

[0177] Next, the ALD technique is used to deposit a 5-nm-thick third isolation layer material 4, i.e., silicon oxide material, the deposition temperature is 200°C, the precursor material used is aminosilane and water vapor, the deposition time is 0.5 h, and the groove of the pattern is filled, as shown in FIG. 4A. Figure 5

[0178] Then, the CMP technique is used for surface planarization: a polishing machine is used in combination with an aluminum oxide polishing liquid for polishing treatment, the polishing rate is 2 nm / min, the height of the residual isolation layer is the height of the initially deposited silicon oxide, i.e., 5 nm, and the surface is exposed to the pattern of the silicon oxide, silicon nitride, and silicon oxide arranged alternately, as shown in FIG. 5A. Figure 6

[0179] ​​​​​Next, the exposed second isolation layer material 3 silicon nitride is etched using RIE etching technology with CHF2 as the etching gas. The power is set to 150 W, the flow rate of CHF2 is 25 sccm, and the etching time is 3 min. A groove structure with a width of 3 nm is obtained, as shown in Figure 7 .

[0180] Then, metal aluminum is deposited using electron beam evaporation technology at a rate of 1 A / s to fill the etched trench and achieve full coverage of the surface layer, as shown in Figure 8 .

[0181] Finally, the surface is planarized using CMP technology. The surface is polished using a polishing machine combined with a metal aluminum polishing liquid at a polishing rate of 2 nm / min to remove the surface metal aluminum. Finally, a device structure with a gate electrode of metal aluminum as the gate electrode is obtained, as shown in Figure 9 .

[0182] Figure 2 A schematic diagram corresponding to the growth of silicon oxide on the silicon surface in the present embodiment; Figure 3 A schematic diagram corresponding to the preparation of a patterned structure on the silicon oxide in the present embodiment; Figure 4 A schematic diagram corresponding to the growth of silicon nitride covering the silicon oxide structure in the present embodiment; Figure 5 A schematic diagram corresponding to the deposition of silicon oxide material full coverage of the trench in the present embodiment; Figure 6 A schematic diagram corresponding to the surface planarization using CMP in the present embodiment; Figure 7 A schematic diagram corresponding to the etching removal of the exposed silicon nitride; Figure 8 A schematic diagram corresponding to the deposition of metal aluminum using electron beam; Figure 9 A schematic diagram corresponding to the surface planarization using CMP to remove the surface metal aluminum in the present embodiment.

[0183] The etching selectivity ratio of the materials of the first isolation layer and the second isolation layer is greater than 1:2.

[0184] After obtaining the metal gate in the above steps, if the process requires, all the isolation layer materials can be removed by a wet etching method, for example, using HF to remove silicon oxide and using HCl to remove aluminum oxide, thereby obtaining a metal gate structure separated by an air layer.

[0185] Example 3

[0186] The present embodiment relates to a method for preparing a nanometer gate using thin film deposition technology, and the specific process is shown in Figure 11 , which comprises the following steps:

[0187] S100: providing a wafer 6 required for process preparation;

[0188] S200: depositing a first isolation layer material 2;

[0189] S300: preparing the first isolation layer 2 into a strip-shaped pattern structure;

[0190] S400: depositing a second isolation layer material 3, marked as 3A, 3B, 3C at different deposition positions;

[0191] S500: depositing a third isolation layer material 4 to fill the trench;

[0192] S600: planarizing the material surface to obtain a structure in which the first, second, and second isolation layers are arranged alternately with the third isolation layer;

[0193] S700: etching to remove the second isolation layer 8B between the adjacent first isolation layer and the composite isolation layer;

[0194] S800: depositing a gate metal 10;

[0195] S900: planarizing the material surface to remove the surface gate metal 10;

[0196] S1000: using a lithography process to prepare a source-drain electrode pattern 11;

[0197] S1100: using an etching process to remove the exposed first first isolation layer material 2 and the second isolation layer material 3C;

[0198] S1200: depositing a source-drain electrode 12 using electron beam technology and removing the excess metal using a lift-off technology.

[0199] In this embodiment, first, a functional layer capable of preparing a HEMT device is provided on a (001) gallium arsenide wafer 6. Next, a 300 nm first isolation layer material silicon oxide is deposited using a PECVD technology, the process gas used is silane and nitric oxide, the deposition temperature is 380°C, and the deposition time is 5 min, as shown in Figure 12 ;

[0200] A strip-shaped pattern structure is prepared using a photoresist development technology, the strip width is 200 um, the pattern spacing is 260 um, and the period is 460 um; combined with the photoetching technology, exposure and development processing are performed, the exposure time is 4 s, the development time is 30 s, and the corresponding photoresist pattern structure is obtained; then, the RIE etching technology is used to transfer the pattern to the silicon oxide, the etching gas used is CHF3 and O2; the power is 150 W, and the etching time is 4 min, as shown in Figure 13 ;

[0201] Then, the second isolation layer material, aluminum oxide, is grown using ALD technology to a thickness of 100 nm at a deposition temperature of 200 °C using trimethylaluminum and water vapor as precursor materials, as shown in FIG. 4B. Figure 14

[0202] Next, the third isolation layer material, silicon oxide, is deposited using PECVD technology to a thickness of 400 nm to cover the surface pattern using silane and laughing gas as process gases at a deposition temperature of 380 °C for a deposition time of 10 min, as shown in FIG. 4C. Figure 15

[0203] Then, the surface is planarized using CMP technology by polishing using a polishing machine with a silicon oxide polishing liquid at a polishing rate of 2 nm / min to leave the height of the remaining isolation layer at the height of the initially deposited silicon oxide, so that the surface exposes the pattern of alternating silicon oxide, aluminum oxide, and silicon oxide, as shown in FIG. 4D. Figure 16

[0204] Next, the exposed second isolation layer material, aluminum oxide, is etched away using RIE etching technology using CHF2as the etching gas at a power of 150 W and a flow rate of 25 seem for CHF2for an etching time of 3 min to obtain a groove structure with a width of 100 nm, as shown in FIG. 4E. Figure 17

[0205] Then, the gate metal, Ni / AuGe / Ni / Au, is deposited using electron beam evaporation technology at a deposition rate of Au: 1 A / s; Ni: 0.5 A / s; Ge: 0.5 A / s and a deposition thickness of 20 nm / 100 nm / 50 nm / 50 nm / 500 nm, as shown in FIG. 4F. Figure 18

[0206] Next, the surface is planarized using CMP technology by polishing using a polishing machine with a metal aluminum polishing liquid at a polishing rate of 2 nm / min to remove the surface metal, as shown in FIG. 4G. Figure 19

[0207] Next, the source and drain electrode pattern is prepared using a photolithography development process with a pitch of 1 um, a photoresist film is prepared on the surface using a uniform coating machine, and the photoresist pattern structure is obtained by exposure and development processing using the obtained photoetching plate and combining the photolithography technology with an exposure time of 4 s and a development time of 30 s, as shown in FIG. 4H. Then, the exposed silicon oxide is etched away using RIE etching technology using CHF3and O2as the etching gas at a power of 150 W for an etching time of 4 min, as shown in FIG. 4I. Figure 20 Figure 21

[0208] ​​​​​​​​Then, the source and drain electrodes are deposited by electron beam evaporation, Ni / AuGe / Ni / Au, with deposition rates of Au: 1 A / s, Ni: 0.5 A / s, Ge: 0.5 A / s, and deposition thicknesses of 20 nm / 100 nm / 50 nm / 50 nm / 500 nm, respectively.

[0209] Finally, the excess metal is removed by lift-off process, as shown in Fig. 6. Figure 22

[0210] Figure 12 A schematic diagram corresponding to the growth of silicon oxide on the surface of the functional layer in this embodiment; Figure 13 A schematic diagram corresponding to the preparation of a patterned structure on the silicon oxide in this embodiment; Figure 14 A schematic diagram corresponding to the growth of aluminum oxide covering the silicon oxide structure in this embodiment; Figure 15 A schematic diagram corresponding to the deposition of silicon oxide material covering the trench in this embodiment; Figure 16 A schematic diagram corresponding to the surface planarization by CMP in this embodiment; Figure 17 A schematic diagram corresponding to the etching and removal of exposed aluminum oxide; Figure 18 A schematic diagram corresponding to the deposition of gate metal by electron beam; Figure 19 A schematic diagram corresponding to the surface planarization by CMP and removal of surface metal in this embodiment; Figure 20 A schematic diagram corresponding to the preparation of source and drain electrode patterns by photolithography in this embodiment; Figure 21 A schematic diagram corresponding to the removal of exposed isolation layer by etching in this embodiment; Figure 22 A schematic diagram corresponding to the deposition of source and drain electrode metal by electron beam in this embodiment.

[0211] In this embodiment, the process preparation of the source and drain electrodes can be placed before the preparation of the gate electrode process by changing the conventional process.

[0212] Although the present application has been described to a certain degree of particularity, it should be understood that various alterations and modifications thereof will occur to those skilled in the art without departing from the spirit and scope of the present application. It is understood that the present application is not limited to the embodiments described, but is intended to cover any alternatives, modifications and equivalents falling within the scope of the claims.​

Claims

1. A method for preparing a nanogate, characterized in that: The method comprises the following steps: (1) Provide wafers required for process preparation; (2) depositing a first isolation layer material on the wafer; (3) preparing the first isolation layer into a patterned structure; (4) depositing a second isolation layer material to cover the graphic structure; (5) depositing a third isolation layer material to fill the trench and cover the surface; wherein the third isolation layer material is the same as the first isolation layer material; (6) planarizing the surface of the material obtained in step (5) to obtain a structure in which a first isolation layer, a second isolation layer, and a third isolation layer superimposed on the second isolation layer are arranged alternately as a composite isolation layer; (7) etching and removing the second isolation layer between the first isolation layer and the composite isolation layer to the wafer surface; (8) depositing nanogate material to fill the trenches and cover the surface; (9) Flattening the surface of the material obtained in step (8) to remove the nanograting material on the surface to obtain the nanograting.

2. The method according to claim 1, characterized in that The material of the nanogate is selected from one or more of the following: gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, and polysilicon.

3. The method according to claim 1, characterized in that The line width of the nanogate is less than 100 nm.

4. The method according to claim 3, characterized in that The line width of the nanogate is less than 28 nm.

5. The method according to claim 4, characterized in that The line width of the nanogate is less than 14 nm.

6. The method according to claim 5, characterized in that The line width of the nanogate is less than 7 nm.

7. The method according to claim 6, characterized in that The line width of the nanogate is less than 5 nm.

8. The method according to claim 7, characterized in that The line width of the nanogate is less than 3 nm.

9. The method according to any one of claims 1 to 8, characterized in that The wafer material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, and germanium.

10. The method according to claim 9, characterized in that The wafer is a wafer with a functional layer.

11. The method according to any one of claims 1 to 8, characterized in that The materials of the first isolation layer, the second isolation layer and the third isolation layer are all selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitrogen, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide.

12. The method according to any one of claims 1 to 8, characterized in that The deposition method in step (2) is a thin film deposition technology, and the thin film deposition technology is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and electron beam evaporation; The thickness of the first isolation layer is greater than 5 nm.

13. The method according to any one of claims 1 to 8, characterized in that The spacing between the patterns of the graphic structure described in step (3) is not less than twice the thickness of the second isolation layer.

14. The method according to any one of claims 1 to 8, characterized in that The preparation technology of the graphic structure in step (3) is selected from one or more of the following: photolithography technology, electron beam exposure technology, and laser direct writing technology.

15. The method according to claim 14, characterized in that The photolithography technology is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, and immersion lithography.

16. The method according to any one of claims 1 to 8, characterized in that In step (4), the thickness of the second isolation layer material is greater than 1 nm and less than half the thickness of the first isolation layer; The planarization method in step (6) is selected from one or more of the following: CMP technology, PSG technology, and ion selective bombardment; The process for removing the surface nano-gate material in step (9) is selected from one or more of the following: CMP technology, PSG technology, ion selective bombardment, argon ion etching, RIE technology, and ICP technology.

17. The method according to claim 16, characterized in that The planarization method in step (6) and the process for removing the surface nano-gate material in step (9) are both CMP technologies.

18. The method according to any one of claims 1 to 8, characterized in that The thickness of the second isolation layer is consistent with the line width of the nanogate; and / or The method further comprises the following steps: (10) Processing the non-nanogate retained area to obtain the desired mesa structure.

19. The method according to claim 18, characterized in that In step (10), a photolithography process is used to process the non-nanogate retained area.

20. The method according to claim 18, wherein In step (10), a wet etching process is used to treat the non-nanogate retained area.

21. The method according to claim 18, wherein In step (10), a dry etching process is used to process the non-nanogate retained area.

22. A semiconductor device, characterized in that: The semiconductor device comprises a nanogate manufactured according to the manufacturing method according to any one of claims 1 to 21.

23. The semiconductor device according to claim 22, wherein: The semiconductor device is an integrated circuit.

24. The semiconductor device according to claim 22, wherein: The semiconductor device is selected from one or more of the following: HEMT, MESFET, MOSFET, NAND Flash, NOR Flash, and DRAM.

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