Method for manufacturing memory bit and method for manufacturing MRAM

Abstract

The application provides a preparation method of a storage bit and a preparation method of an MRAM. The preparation method comprises the following steps: providing a first base body with a first surface, the first surface being provided with a first tunnel junction material layer and a first mask layer, the first mask layer being located on a side of the first tunnel junction material layer away from the first base body; etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer, the second tunnel junction material layer having a first exposed sidewall; forming a sacrificial layer on the first surface, the sacrificial layer at least partially covering the first sidewall; etching the second tunnel junction material layer and the sacrificial layer through the first mask layer to remove the sacrificial layer and form a magnetic tunnel junction from the second tunnel junction material layer. By dividing the etching process of the magnetic tunnel junction into two times, short circuit caused by sidewall metal deposition in the etching process of the magnetic tunnel junction is avoided, and the magnetic and electric performance of the magnetic tunnel junction is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor memory chip manufacturing, in particular to a memory bit preparation method and an MRAM preparation method. BACKGROUND

[0002] Magnetic random access memory (MRAM) uses magnetic tunnel junction (MTJ) as information storage bit, records information 0 and 1 by using high and low states of TMR resistance value, has fast read-write speed, non-volatility, anti-radiation and other excellent properties, and is a very potential next-generation non-volatile storage technology. However, the MRAM preparation process integration technology faces many difficulties.

[0003] 1) MTJ etching is difficult, in order to avoid RIE chemical corrosion from damaging its electromagnetic performance, IBE method is generally used for MTJ etching, and IBE etching is accompanied by side wall metal deposition and plasma bombardment phenomenon, which will cause serious short circuit and magnetic damage;

[0004] 2) The industry generally removes the side wall metal deposition and magnetic damage layer caused by IBE through increasing over-etching, and the excessive over-etching depth will affect the bottom electrode and the bottom via, and reduce or damage the performance thereof; and in order to avoid affecting the metal connection (metal leakage and diffusion, etc.), the industry usually increases the height of the via below the MTJ bit, and such method will occupy a large amount of metal interlayer space, which is not conducive to its application in embedded memory. SUMMARY

[0005] The main purpose of the present application is to provide a memory bit preparation method and an MRAM preparation method, so as to solve the problem of short circuit caused by side wall metal deposition due to magnetic tunnel junction etching in the prior art.

[0006] In order to achieve the above purpose, according to one aspect of the present application, a memory bit preparation method is provided, comprising the following steps: providing a first base body with a first surface, the first surface being provided with a first tunnel junction material layer and a first mask layer, the first mask layer being located on the side of the first tunnel junction material layer away from the first base body; etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer, the second tunnel junction material layer having a first exposed side wall; forming a sacrificial layer on the first surface, the sacrificial layer at least partially covering the first side wall; etching the second tunnel junction material layer and the sacrificial layer through the first mask layer to remove the sacrificial layer and form a magnetic tunnel junction from the second tunnel junction material layer.

[0007] Further, the first tunnel junction material layer is subjected to IBE etching or RIE etching to form the second tunnel junction material layer.

[0008] Further, the first tunnel junction material layer comprises a fixed layer, a barrier layer and a free layer stacked in sequence along a direction away from the first surface, and the step of etching the first tunnel junction material layer to form the second tunnel junction material layer comprises: etching the first tunnel junction material layer through the first mask layer to form the second tunnel junction material layer comprising the free layer, and the first sidewall at least comprises an exposed surface of the free layer; or etching the first tunnel junction material layer through the first mask layer to form the second tunnel junction material layer comprising the free layer and the barrier layer, and the first sidewall at least comprises exposed surfaces of the free layer and the barrier layer; or etching the first tunnel junction material layer through the first mask layer to form the second tunnel junction material layer comprising the free layer, the barrier layer and the fixed layer, and the first sidewall comprises exposed surfaces of the free layer, the barrier layer and the fixed layer.

[0009] Further, the step of forming the sacrificial layer comprises: forming a sacrificial preliminary layer on the first surface, so that the sacrificial preliminary layer covers the first mask layer and the second tunnel junction material layer; etching the sacrificial preliminary layer to expose the first mask layer, and the remaining sacrificial preliminary layer forms the sacrificial layer covering the first sidewall. Preferably, the sacrificial preliminary layer is etched by a self-aligned process, and more preferably, before the step of etching the sacrificial preliminary layer by the self-aligned process, the sacrificial preliminary layer is planarized to expose a side surface of the first mask layer away from the first substrate.

[0010] Further, the sacrificial preliminary layer is etched by RIE to expose the first mask layer.

[0011] Further, the material of the sacrificial layer is an insulator, and preferably, the material of the sacrificial layer is selected from any one or more of silicon oxide, silicon nitride and silicon carbide.

[0012] Further, the second tunnel junction material layer is etched by a self-aligned process to form the magnetic tunnel junction.

[0013] Further, in the step of etching the second tunnel junction material layer and the sacrificial layer, the etching process has a first etching rate on the first sidewall and a second etching rate in a direction perpendicular to the first surface, and the first etching rate is greater than the second etching rate.

[0014] Further, the first substrate comprises a bottom electrode and a connecting metal layer stacked in sequence, a side surface of the bottom electrode away from the connecting metal layer is part of the first surface, and the step of forming the first mask layer comprises: sequentially forming a first tunnel junction material layer, a first mask material layer and a second mask material layer on the first surface, so that the first tunnel junction material layer covers the bottom electrode; patterning the second mask material layer to form the second mask layer; and etching the first mask material layer through the second mask layer to form the first mask layer.

[0015] Furthermore, after the step of forming the magnetic tunnel junction, the first mask layer is the top electrode layer, and the preparation method further includes the following steps: forming a protective film covering the magnetic tunnel junction and the top electrode on the first surface; forming a conductive channel connected to the top electrode in the protective film.

[0016] According to another aspect of the present invention, a method for fabricating MRAM is provided, comprising the step of forming at least one memory bit, wherein the memory bit is formed using the above-described fabrication method.

[0017] The present invention provides a method for fabricating memory bits. This method involves providing a first substrate having a first tunnel junction material layer and a first mask layer on a first surface. The first tunnel junction material layer is etched through the first mask layer to form a second tunnel junction material layer, resulting in an exposed first sidewall. A sacrificial layer is then formed on the first surface, at least partially covering the first sidewall. The second tunnel junction material layer and the sacrificial layer are etched through the first mask layer to remove the sacrificial layer and form a magnetic tunnel junction. This method divides the etching process of the magnetic tunnel junction into two steps. The first step primarily involves etching to obtain independent memory bits or to ensure that the memory bits are not yet fully electrically separated. The second step introduces the sacrificial layer and then finely modifies the first sidewall. This avoids short circuits caused by sidewall metal deposition during the etching process of the magnetic tunnel junction and improves the magnetoelectric properties of the magnetic tunnel junction. Attached Figure Description

[0018] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0019] Figure 1 The diagram shows a cross-sectional structure of the substrate after a first tunnel junction material layer, a first mask material layer, a second mask material layer, and a patterned photoresist are sequentially formed on a first substrate in the method for fabricating storage bits provided in this application.

[0020] Figure 2 It shows that Figure 1 The diagram shows a cross-sectional structure of the substrate after the second mask material layer is formed.

[0021] Figure 3 It shows that Figure 2 The diagram shows a cross-sectional structure of the substrate after the first mask material layer is formed.

[0022] Figure 4 It shows that Figure 3The substrate cross-sectional structure schematic diagram after etching the first tunnel junction material layer to form the second tunnel junction material layer, wherein the second tunnel junction material layer comprises a free layer;

[0023] Figure 5 The first tunnel junction material layer is etched to form the second tunnel junction material layer, and the second tunnel junction material layer comprises a free layer and a barrier layer. Figure 3 The first tunnel junction material layer is etched to form the second tunnel junction material layer, and the second tunnel junction material layer comprises a free layer and a barrier layer.

[0024] Figure 6 The first tunnel junction material layer is etched to form the second tunnel junction material layer, and the second tunnel junction material layer comprises a free layer, a barrier layer and a fixed layer. Figure 3 The first tunnel junction material layer is etched to form the second tunnel junction material layer, and the second tunnel junction material layer comprises a free layer, a barrier layer and a fixed layer.

[0025] Figure 7 The sacrificial layer covering the first sidewall is formed, and the substrate cross-sectional structure schematic diagram is shown. Figure 6 The sacrificial layer covering the first sidewall is formed, and the substrate cross-sectional structure schematic diagram is shown.

[0026] Figure 8 The sacrificial layer covering the first sidewall is formed, and the substrate cross-sectional structure schematic diagram is shown. Figure 7 The sacrificial layer covering the first sidewall is formed, and the substrate cross-sectional structure schematic diagram is shown.

[0027] Figure 9 The sacrificial layer covering the first sidewall is formed, and the substrate cross-sectional structure schematic diagram is shown. Figure 8 The sacrificial layer covering the first sidewall is formed, and the substrate cross-sectional structure schematic diagram is shown.

[0028] Figure 10 The second tunnel junction material layer and the sacrificial layer are etched to form a magnetic tunnel junction, and the substrate cross-sectional structure schematic diagram is shown. Figure 9 The second tunnel junction material layer and the sacrificial layer are etched to form a magnetic tunnel junction, and the substrate cross-sectional structure schematic diagram is shown.

[0029] Figure 11 The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown. Figure 9 The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown. The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown.

[0030] The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown. Figure 12 The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown. Figure 10 The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown. The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown.

[0031] The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown. Figure 13 The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown. Figure 12 The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown. The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown.

[0032] The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown. The protective film covering the magnetic tunnel junction and the top electrode is formed, and the substrate cross-sectional structure schematic diagram is shown.

[0033] 100, insulating medium layer; 10, connecting metal layer; 20, bottom electrode; 30, magnetic tunnel junction; 301, first tunnel junction material layer; 302, second tunnel junction material layer; 310, fixed layer; 311, fixed material layer; 320, barrier layer; 321, barrier material layer; 330, free layer; 331, free material layer; 40, first mask layer; 410, first mask material layer; 50, second mask layer; 510, second mask material layer; 60, patterned photoresist; 70, sacrificial layer; 710, sacrificial preliminary layer; 80, protective film; 90, interlayer medium layer; 110, conductive channel. DETAILED DESCRIPTION

[0034] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0035] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings and in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the scope of protection of the present application.

[0036] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0037] As introduced in the background, the magnetic tunnel junction etching in the prior art is easy to cause short circuit due to sidewall metal deposition. In order to solve the above technical problem, the applicant of the present application provides a preparation method of a storage bit, comprising the following steps: providing a first substrate with a first surface, the first surface being provided with a first tunnel junction material layer and a first mask layer, the first mask layer being located at a side of the first tunnel junction material layer away from the first substrate, etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer, the second tunnel junction material layer having a first exposed sidewall; forming a sacrificial layer on the first surface, the sacrificial layer at least partially covering the first sidewall; etching the second tunnel junction material layer and the sacrificial layer through the first mask layer to remove the sacrificial layer and form a magnetic tunnel junction from the second tunnel junction material layer.

[0038] By adopting the above preparation method of the present application, the etching process of the magnetic tunnel junction is divided into two times, the first time is mainly to obtain an independent storage bit or to make the storage bit not yet achieve complete conductive separation, and the second time is to introduce a sacrificial layer and then to finely modify the first sidewall, thereby avoiding short circuit caused by sidewall metal deposition in the etching process of the magnetic tunnel junction, and improving the magnetic and electric performance of the magnetic tunnel junction.

[0039] The above and other aspects of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: Figures 1 to 13 Exemplary embodiments of the preparation method of a storage bit according to the present application will be described in more detail hereinafter with reference to the attached drawings. However, these exemplary embodiments can be implemented in various different forms, and should not be construed as being limited to only the embodiments set forth herein. It should be understood that the exemplary embodiments are provided in order to make the present application complete and comprehensive, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0040] First, a first substrate with a first surface is provided, the first surface being provided with a first tunnel junction material layer 301 and a first mask layer 40, the first mask layer 40 being located at a side of the first tunnel junction material layer 301 away from the first substrate.

[0041] In a preferred embodiment, the above first substrate comprises a laminated connection metal layer 10 and a bottom electrode 20, a side surface of the bottom electrode 20 away from the connection metal layer 10 being a part of the first surface, and the first tunnel junction material layer 301 covering the surface of the bottom electrode 20, as shown in FIG. 1. Figure 1 The above bottom electrode 20 can be formed on the surface of the connection metal layer 10 in the insulating dielectric layer 100, and those skilled in the art can reasonably select the materials for forming the above connection metal layer 10 and bottom electrode 20 according to the prior art, which will not be described herein.

[0042] The above-described preparation method of the present invention further includes the step of sequentially forming a first tunnel junction material layer 301 and a first mask layer 40 on a first surface of a first substrate. The step of forming the first tunnel junction material layer 301 may include: sequentially depositing a fixed material layer 311, a barrier material layer 321, and a free material layer 331 on the first surface, such as... Figure 1 As shown, after etching, a magnetic tunnel junction 30 is obtained, comprising a reference layer, a barrier layer 320, and a free layer 330. Figure 8 .

[0043] The aforementioned free material layer 331 is used to form a free layer 330 after etching, and data is stored through the spin direction of the free layer 330. The fixed material layer 311 may contain magnetic metals such as cobalt iron boron, and the barrier material layer 321 may be a dielectric material such as magnesium oxide or aluminum oxide.

[0044] It should be noted that the structure of the first tunnel junction material layer 301 is different depending on the type of magnetic tunnel junction 30 to be formed. The magnetic tunnel junction 30 can include, but is not limited to, in-plane MTJ, vertical MTJ, top pinned MTJ, bottom pinned MTJ, double-layer MgO MTJ, single-layer MgO MTJ, and polymorphic MTJ. In this case, the barrier layer 320 in the magnetic tunnel junction 30 can be the first barrier layer, and functional layers such as the second barrier layer, pinning layer, capping layer, and buffer layer can be added.

[0045] In a preferred embodiment, the step of forming the first mask layer 40 includes: sequentially forming a first mask material layer 410 and a second mask material layer 510 on the first tunnel junction material layer 301; covering the second mask material layer 510 with photoresist; patterning the photoresist through photolithography and development processes; and etching the second mask material layer 510 using the patterned photoresist 60 as a mask to obtain a second mask layer 50 with a pattern consistent with the patterned photoresist 60. Figure 1 and Figure 2 As shown; then the first mask material layer 410 is etched through the second mask layer 50 to transfer the pattern of the patterned photoresist 60 to obtain the first mask layer 40, as shown. Figure 3 As shown.

[0046] In the preferred embodiment described above, the first mask layer 40 can serve as the top electrode of the storage bit after the etching process that forms the magnetic tunnel junction 30. Those skilled in the art can rationally select the materials for the first mask layer 40 and the second mask layer 50 based on existing technology. For example, the material forming the first mask layer 40 can be Ta, TaN, TiN, etc., and the material forming the second mask layer 50 can be SiO. x SiN x wait.

[0047] The skilled in the art can also reasonably set the process conditions of the above photoetching process according to the prior art. The photoresist can be selected to have different structures such as PR / ARC / LTO / SOC and PR / ARC according to the thickness of the first mask layer 40 and the second mask layer 50 and the light source of the photoetching machine. When the photoresist is etched, the etching is performed in a layer-by-layer transfer manner, i.e., PR etches ARC, ARC etches LTO, and LTO etches SOC.

[0048] Then, the first tunnel junction material layer 301 is etched by the first mask layer 40 to form a second tunnel junction material layer 302. The second tunnel junction material layer 302 has an exposed first sidewall, as shown in Figures 4 to 6 The etching process can be IBE etching or RIE etching.

[0049] In a first alternative embodiment, the step of etching the first tunnel junction material layer 301 to form the second tunnel junction material layer 302 includes etching the first tunnel junction material layer 301 by the first mask layer 40 to form the second tunnel junction material layer 302 including the free layer 330. The first sidewall includes at least an exposed surface of the free layer 330, as shown in Figure 4 .

[0050] In the above alternative embodiment, the free material layer 331 is formed into the free layer 330 by etching the first tunnel junction material layer 301. The barrier material layer 321 can also be etched, but at this time the barrier material layer 321 has not yet formed the barrier layer 320, and the fixed material layer 311 has not been etched, so the fixed layer 310 has not been formed. Thus, the formed second tunnel junction material layer 302 has a plurality of magnetic tunnel junctions that have not yet been shaped and are connected by the barrier material layer 321, and complete conductive separation has not been achieved.

[0051] In a second alternative embodiment, the step of etching the first tunnel junction material layer 301 to form the second tunnel junction material layer 302 includes etching the first tunnel junction material layer 301 by the first mask layer 40 to form the second tunnel junction material layer 302 including the free layer 330 and the barrier layer 320. The first sidewall includes at least an exposed surface of the free layer 330 and the barrier layer 320, as shown in Figures 5 to 6 .

[0052] In the above alternative embodiment, the free material layer 331 is formed into the free layer 330 and the barrier material layer 321 is formed into the barrier layer 320 by etching the first tunnel junction material layer 301. The fixed material layer 311 can also be etched, but at this time the fixed material layer 311 has not yet formed the fixed layer 310. Thus, the formed second tunnel junction material layer 302 has a plurality of magnetic tunnel junctions that have not yet been shaped and are connected by the fixed material layer 311, and complete conductive separation has not been achieved.

[0053] In the third optional embodiment, the step of etching the first tunnel junction material layer 301 to form the second tunnel junction material layer 302 includes: etching the first tunnel junction material layer 301 through the first mask layer 40 to form the second tunnel junction material layer 302 including the free layer 330, the barrier layer 320 and the fixed layer 310, the first sidewall including exposed surfaces of the free layer 330, the barrier layer 320 and the fixed layer 310, as shown in FIG. 3D. Figure 6

[0054] In the above optional embodiment, the free material layer 331 is formed into the free layer 330, the barrier material layer 321 is formed into the barrier layer 320, and the fixed material layer 311 is formed into the fixed layer 310 by etching the first tunnel junction material layer 301, at this time, the second tunnel junction material layer 302 including the above-mentioned free layer 330, the above-mentioned barrier layer 320 and the above-mentioned fixed layer 310 can form multiple independent and achieve complete electrical separation, but the first sidewall has etching residue impurities.

[0055] In order to remove the above-mentioned impurities remaining on the first sidewall, after the step of etching to form the second tunnel junction material layer 302, a sacrificial layer 70 is formed on the first surface, the sacrificial layer 70 at least partially covers the first sidewall, as shown in FIG. 3E. Figures 7 to 9 Then, the second tunnel junction material layer 302 and the sacrificial layer 70 are etched through the first mask layer 40 to remove the sacrificial layer 70 and form the magnetic tunnel junction of the second tunnel junction material layer 302, as shown in FIG. 3F. Figure 10

[0056] The above-mentioned sacrificial layer 70 is non-conductive and non-magnetic, preferably, the material forming the above-mentioned sacrificial layer 70 can be selected from any one or more of silicon oxide, silicon nitride and silicon carbide, the step of forming the above-mentioned sacrificial layer 70 can include: forming a sacrificial preliminary layer 710 on the first surface, so that the sacrificial preliminary layer 710 covers the first mask layer 40 and the second tunnel junction material layer 302, as shown in FIG. 3E; etching the sacrificial preliminary layer 710 to expose the first mask layer 40, the remaining sacrificial preliminary layer 710 forms the sacrificial layer 70 covering the first sidewall, as shown in FIG. 3E and FIG. 3F. Figure 7 Figure 8 Figure 9

[0057] In the above-mentioned step of forming the above-mentioned sacrificial layer 70, preferably, the RIE etching is performed on the sacrificial preliminary layer 710, and the above-mentioned etching process can obtain a better selection ratio, so that the etching rate of the sacrificial preliminary layer 710 is greater than the etching rate of the second tunnel junction material layer 302 and the first mask layer 40.

[0058] ​​​​​In a preferred embodiment, the sacrificial preparation layer 710 is directly etched by a self-alignment process to form the remaining sacrificial preparation layer 710 as the sacrificial layer 70 covering the first sidewall, as shown in Figure 9

[0059] In another preferred embodiment, the sacrificial preparation layer 710 is planarized to expose the first mask layer 40 away from the side surface of the first substrate, and then the sacrificial preparation layer 710 is directly etched by a self-alignment process to form the remaining sacrificial preparation layer 710 as the sacrificial layer 70 covering the first sidewall, as shown in Figure 8 Figure 9

[0060] After forming the sacrificial layer 70 covering the first sidewall, the second tunnel junction material layer 302 is etched to form the magnetic tunnel junction 30, and the sacrificial layer 70 is removed to perform a trimming etching on the magnetic tunnel junction 30, so that the metal impurities and other impurities remaining on the first sidewall can be removed, as shown in Figure 10

[0061] In the process of forming the magnetic tunnel junction 30 from the second tunnel junction material layer 302, the second tunnel junction material layer 302 can be etched by a self-alignment process to form the magnetic tunnel junction 30, and the etching time and etching endpoint can be determined according to the degree of sidewall deposition or magnetic destruction. When the second tunnel junction material layer 302 has not been completely conductively separated, the over-etching amount of etching the second tunnel junction material layer 302 needs to be sufficient to achieve the conductive separation between the magnetic tunnel junctions 30.

[0062] In the step of etching the second tunnel junction material layer 302 and the sacrificial layer 70, the etching process preferably has a first etching rate on the first sidewall and a second etching rate in the direction perpendicular to the first surface, and the first etching rate is greater than the second etching rate.

[0063] After the step of forming the magnetic tunnel junction 30, the first mask layer 40 can be used as a top electrode layer of the storage bit, and the preparation method of the present application can further include the following steps: forming a protective film 80 covering the magnetic tunnel junction 30 and the top electrode on the first surface, as shown in Figure 11 Figure 12 Figure 13

[0064] ​​​​​​​Specifically, the second tunnel junction material layer 302 is etched to form a plurality of magnetic tunnel junctions 30 on the first surface of the first substrate, after the step of forming the protective film 80 covering the magnetic tunnel junctions 30 and the top electrode, an interlayer dielectric layer 90 covering the protective film 80 can be formed on the first surface first, then a conductive via penetrating to the top electrode is formed in the interlayer dielectric layer 90 and the protective film 80, and then a conductive material is deposited in the conductive via to form the conductive channel 110 described above; before the step of forming the conductive via described above, the interlayer dielectric layer 90 can also be subjected to a planarization treatment such as CMP polishing first, and the polishing stop position can be above the magnetic tunnel junction 30 or can be just flush with the surface of the magnetic tunnel junction 30.

[0065] The protective film 80 described above is non-conductive and non-magnetic, and preferably the material forming the protective film 80 is selected from any one or more of silicon oxide, silicon nitride, tantalum nitride, silicon carbon nitride, silicon oxynitride and aluminum oxide, but is not limited to the preferred types described above, and those skilled in the art can reasonably select the specific type according to the prior art; the material of the interlayer dielectric layer 90 can be silicon oxide, silicon nitride, silicon carbide and low K material, etc.

[0066] Those skilled in the art can also reasonably select the process for depositing the protective film 80 and the interlayer dielectric layer 90 described above according to the prior art, for example, chemical vapor deposition or atomic layer deposition can be used; and the conductive via described above can be formed by a double damascene etching process.

[0067] According to another aspect of the present application, a method for manufacturing an MRAM is also provided, comprising the step of forming at least one storage bit using the manufacturing method described above.

[0068] From the above description, it can be seen that the embodiments of the present application achieve the following technical effects:

[0069] By dividing the etching process of the magnetic tunnel junction into two steps, the first step mainly obtains an independent storage bit or makes the storage bit not completely conductively separated, and the second step introduces a sacrificial layer and then finely modifies the first sidewall, the present application avoids the short circuit caused by the deposition of metal on the sidewall during the etching process of the magnetic tunnel junction, and improves the magnetic and electrical properties of the magnetic tunnel junction.

[0070] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a storage bit, characterized in that, Includes the following steps: A first substrate having a first surface is provided, on which a first tunnel junction material layer and a first mask layer are disposed, the first mask layer being located on the side of the first tunnel junction material layer away from the first substrate; The first tunnel junction material layer is etched through the first mask layer to form a second tunnel junction material layer, the second tunnel junction material layer having an exposed first sidewall; A sacrificial layer is formed on the first surface, the sacrificial layer at least partially covering the first sidewall; The second tunnel junction material layer and the sacrificial layer are etched through the first mask layer to remove the sacrificial layer and form a magnetic tunnel junction from the second tunnel junction material layer.

2. The preparation method according to claim 1, characterized in that, The first tunnel junction material layer is etched by IBE or RIE to form the second tunnel junction material layer.

3. The preparation method according to claim 1, characterized in that, The first tunnel junction material layer includes a fixed material layer, a barrier material layer, and a free material layer sequentially stacked in a direction away from the first surface. The step of etching the first tunnel junction material layer to form the second tunnel junction material layer includes: The first tunnel junction material layer is etched through the first mask layer to form a second tunnel junction material layer including a free layer, wherein the first sidewall includes at least the exposed surface of the free layer; or The first tunnel junction material layer is etched through the first mask layer to form a second tunnel junction material layer including a free layer and a barrier layer, wherein the first sidewall includes at least the exposed surfaces of the free layer and the barrier layer; or The first tunnel junction material layer is etched through the first mask layer to form a second tunnel junction material layer comprising a free layer, a barrier layer, and a fixed layer, wherein the first sidewall comprises the exposed surfaces of the free layer, the barrier layer, and the fixed layer.

4. The preparation method according to claim 1, characterized in that, The steps for forming the sacrificial layer include: A sacrificial preparation layer is formed on the first surface such that the sacrificial preparation layer covers the first mask layer and the second tunnel junction material layer; The sacrificial preparation layer is etched to expose the first mask layer, and the remaining sacrificial preparation layer forms the sacrificial layer covering the first sidewall.

5. The preparation method according to claim 4, characterized in that, The sacrificial preparation layer is etched using a self-aligned process.

6. The preparation method according to claim 5, characterized in that, Before etching the sacrificial preparation layer using a self-aligned process, the sacrificial preparation layer is planarized to expose the surface of the first mask layer away from the first substrate.

7. The preparation method according to claim 4, characterized in that, The sacrificial preparation layer is subjected to RIE etching to expose the first mask layer.

8. The preparation method according to any one of claims 1 to 7, characterized in that, The material forming the sacrificial layer is an insulator.

9. The preparation method according to claim 8, characterized in that, The material forming the sacrificial layer is selected from one or more of silicon oxide, silicon nitride, and silicon carbide.

10. The preparation method according to any one of claims 1 to 7, characterized in that, The second tunnel junction material layer is etched using a self-aligned process to form the magnetic tunnel junction.

11. The preparation method according to any one of claims 1 to 7, characterized in that, In the step of etching the second tunnel junction material layer and the sacrificial layer, the etching process used has a first etching rate on the first sidewall and a second etching rate in a direction perpendicular to the first surface, wherein the first etching rate is greater than the second etching rate.

12. The preparation method according to any one of claims 1 to 7, characterized in that, The first substrate includes a stacked connecting metal layer and a bottom electrode, wherein the surface of the bottom electrode away from the connecting metal layer is part of the first surface, and the step of forming the first mask layer includes: A first tunnel junction material layer, a first mask material layer, and a second mask material layer are sequentially formed on the first surface, such that the first tunnel junction material layer covers the bottom electrode; The second mask material layer is patterned to form the second mask layer; The first mask material layer is etched through the second mask layer to form the first mask layer.

13. The preparation method according to any one of claims 1 to 7, characterized in that, After the step of forming the magnetic tunnel junction, the first mask layer is a top electrode layer, and the fabrication method further includes the following steps: A protective film is formed on the first surface covering the magnetic tunnel junction and the top electrode; A conductive channel connected to the top electrode is formed in the protective film.

14. A method for fabricating MRAM, comprising the step of forming at least one storage bit, characterized in that, The storage bit is formed using the preparation method described in any one of claims 1 to 13.

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