Load Modulation Amplifier

Abstract

The load modulation amplifier includes: a high-frequency circuit board; an input distribution circuit unit having a distributor and a phase delay circuit, the distributor distributing one input signal into a first input signal and a second input signal, the phase delay circuit being formed on the signal line of the second input signal after distribution; a carrier amplifier that amplifies the first input signal through a first high-frequency transistor; a peak amplifier that amplifies the second input signal through a second high-frequency transistor; and an output combining circuit unit having a 90-degree phase delay circuit, a combiner, and an impedance transformation circuit, the 90-degree phase delay circuit being formed on the signal line of the output of the carrier amplifier, the combiner combining the output of the 90-degree phase delay circuit and the output of the peak amplifier, the impedance transformation circuit transforming the output impedance of the combiner, the input distribution circuit unit, the carrier amplifier, the peak amplifier, and the output combining circuit unit being respectively formed on the high-frequency circuit board, and the carrier amplifier and the peak amplifier being directly connected to the output combining circuit unit without transforming the output impedance.

Description

[0001] This application is a divisional application of the Chinese national application No.

[0002] 201680082159X (PCT / JP2016 / 055214) (Load modulation amplifier), the content of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a load modulation amplifier for terrestrial microwave communication, mobile communication, etc. Background Art

[0004] In recent terrestrial microwave communication and mobile communication, signals with a large difference between the peak power and the average power are mostly used. In this case, the difference between the saturation output power of the amplifier that amplifies the signal and the peak power of the signal increases, so the signal distortion increases and the operation efficiency of the amplifier decreases. Therefore, in order to make the amplifier operate efficiently, sometimes a load modulation amplifier typified by the Doherty amplifier disclosed in Patent Document 1 below is used, for example.

[0005] The Doherty amplifier roughly divides the input high-frequency input signal into two signals. One of the divided signals is input to the carrier amplifier, and the other is input to the peak amplifier after being subjected to a phase delay of 90 degrees, that is, 1 / 4λ. Both the carrier amplifier and the peak amplifier have matching circuits for impedance matching on the input side and the output side, respectively. The carrier amplifier operates, for example, with class A or AB bias and always amplifies the input signal. On the other hand, the peak amplifier operates with class C bias and amplifies an input signal having a power greater than or equal to a specified power. The signals after passing through the two amplifiers are synthesized in the synthesis circuit section after passing through the impedance conversion section, respectively. The synthesis circuit section also has a 1 / 4 wavelength phase delay line that applies a 90-degree phase delay to the output on the carrier amplifier side before synthesis. And the synthesized signal is output via the impedance conversion section.

[0006] Regarding the Doherty amplifier, there are ideally two output powers at which the drain efficiency reaches the maximum, so the output power range with high drain efficiency can be expanded. Therefore, in a system using a signal with a large difference between the peak power and the average power, it can be said that the Doherty amplifier is one of the effective methods for realizing high-efficiency characteristics.

[0007] In addition, the Doherty amplifier will be described in detail later.

[0008] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2010-50611 Summary of the Invention

[0009] However, in existing Doherty amplifiers, i.e., load modulation amplifiers, there are the following problems, namely,

[0010] In the case where the frequency of a high-frequency input signal changes, due to the frequency dependence of the impedance of the 1 / 4-wavelength phase delay line and the variation of characteristics caused by the parasitic capacitance components of the high-frequency transistors constituting the carrier amplifier and the peak amplifier, the desired high-frequency characteristics cannot be obtained over a wide bandwidth.

[0011] Due to the output matching circuit of the amplifier and the correction circuit for increasing the impedance at the cut-off of the peak amplifier, the size of the amplifier becomes large.

[0012] The present invention has been proposed to solve the above problems, and its object is to achieve high-efficiency characteristics in a smaller size and over a wider bandwidth for a load modulation amplifier such as a Doherty amplifier used in a system for processing a signal with a large difference between the peak power and the average power.

[0013] The present invention relates to a load modulation amplifier and the like, which has: a high-frequency circuit board; an input distribution circuit section having a distributor and a phase delay circuit, the distributor distributing one input signal into a first input signal and a second input signal, the phase delay circuit being formed on the signal line of the second input signal after distribution; a carrier amplifier having a first high-frequency transistor, the carrier amplifier amplifying the first input signal from the input distribution circuit section; a peak amplifier having a second high-frequency transistor, the peak amplifier amplifying the second input signal from the input distribution circuit section; and an output combining circuit section having a 90-degree phase delay circuit, a combiner, and an impedance transformation circuit, the 90-degree phase delay circuit being formed on the signal line of the output of the carrier amplifier, the combiner combining the output of the 90-degree phase delay circuit and the output of the peak amplifier, the impedance transformation circuit transforming the output impedance of the combiner, the input distribution circuit section, the carrier amplifier, the peak amplifier, and the output combining circuit section being respectively formed on the high-frequency circuit board, the carrier amplifier having a first resonance circuit that resonates with the parasitic capacitance of the first high-frequency transistor, the drain terminal of the first high-frequency transistor being directly connected to the output combining circuit section without passing through the output impedance transformation circuit, the peak amplifier having a second resonance circuit that resonates with the parasitic capacitance of the second high-frequency transistor, the drain terminal of the second high-frequency transistor being directly connected to the output combining circuit section without passing through the output impedance transformation circuit.

[0014] Effects of the Invention

[0015] In the present invention, it is possible to provide a load modulation amplifier that achieves high-efficiency characteristics in a smaller size and over a wider bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic circuit diagram of the load modulation amplifier according to Embodiment 1 of the present invention.

[0017] Figure 2 This is a diagram for explaining an example of the circuit structure between each amplifier and the output combining circuit section of Figure 1

[0018] Figure 3 This is a diagram for explaining the effect of the load modulation amplifier according to Embodiment 1 of the present invention.

[0019] Figure 4 This is a schematic circuit diagram of the load modulation amplifier according to Embodiment 2 of the present invention.

[0020] Figure 5 This is a diagram for explaining an example of the circuit structure between each amplifier and the output combining circuit section of Figure 4

[0021] Figure 6 This is a diagram for explaining another example of the circuit structure between each amplifier and the output combining circuit section of Figure 4

[0022] Figure 7 This is a schematic circuit diagram of the load modulation amplifier according to Embodiment 3 of the present invention.

[0023] Figure 8 This is a diagram for explaining a modified example of the load modulation amplifier according to Embodiment 3 of the present invention.

[0024] Figure 9 This is a schematic circuit diagram of another example of the load modulation amplifier according to Embodiment 3 of the present invention.

[0025] Figure 10 This is a schematic circuit diagram of an example of a Doherty amplifier as a normal load modulation amplifier.

[0026] Figure 11 This is a diagram for explaining the characteristics of a normal load modulation amplifier of Figure 10 Detailed Embodiment

[0027] First, a normal load modulation amplifier will be described in more detail. Figure 10This is a schematic circuit structure diagram of an example of a Doherty amplifier, which is a typical load modulation amplifier disclosed in Patent Document 1 above, for example. In the case of the Doherty amplifier 1000, a carrier amplifier 101, a peak amplifier 102, an input distribution circuit section 103, and an output combining circuit section 104 are formed on a high-frequency circuit board CB.

[0028] The input distribution circuit section 103 distributes the high-frequency input signal input to the high-frequency input terminal 105 into two signals in an equal-power manner, for example, through a distributor 103a. One of the distributed signals is input to the carrier amplifier 101, and the other is input to the peak amplifier 102 via a 1 / 4-wavelength phase delay line 103b for applying a 90-degree phase delay.

[0029] The carrier amplifier 101 includes: a carrier amplification element 101b, and an input matching circuit 101a and an output matching circuit 101c respectively located on the input side and the output side of the carrier amplification element 101b.

[0030] The peak amplifier 102 includes: a peak amplification element 102b, and an input matching circuit 102a and an output matching circuit 102c respectively located on the input side and the output side of the peak amplification element 102b.

[0031] The carrier amplification element 101b operates with, for example, class A or class AB biasing and always amplifies the input signal. On the other hand, the peak amplification element 102b operates with class C biasing and amplifies an input signal having a power greater than or equal to a specified power.

[0032] The two signals after passing through each amplifier are combined by the output combining circuit section 104. The output combining circuit section 104 has a compensation (offset) line 104a and a 1 / 4-wavelength phase delay line 104b for applying a 90-degree phase delay on the carrier amplifier side. In addition, it has a compensation line 104d on the peak amplifier side. And it also has a combiner 104c and an impedance transformation circuit 104e. The impedance transformation circuit 104e outputs the output of the load modulation amplifier from the high-frequency output terminal 106.

[0033] Here, for example, the output matching circuit 101c connected to the carrier amplification element 101b matches the output impedance of the high-frequency transistor constituting the carrier amplification element 101b with the characteristic impedance (for example, 50 Ω) of the 1 / 4-wavelength phase delay line 104b. That is, when the output impedance of the high-frequency transistor is 5 Ω, it is matched with the characteristic impedance 50 Ω of the 1 / 4-wavelength phase delay line 104b.

[0034] The 1 / 4-wavelength phase delay line 104b applies a 90-degree phase delay to the output side of the carrier amplifier 101. As a result, the outputs of the carrier amplifier 101 and the peak amplifier 102 are combined in a phase-matched state at the combining point during the saturation operation of the carrier amplifier 101 and the peak amplifier 102.

[0035] The electrical length of the compensation line 104a is set so that the impedance of the peak amplifier 102 observed from the combining point during the back-off operation is high, and in an ideal case, it becomes an open-circuit state. In addition, the electrical length of the compensation line 104a is made the same as the electrical length of the compensation line 104d.

[0036] The signal synthesized in the synthesizer 104c has its output impedance transformed by the impedance transformation circuit 104e and is output from the high-frequency output terminal 106.

[0037] In addition, Figure 10 Each circuit of the Doherty amplifier 1000 shown is connected by a high-frequency signal line SL.

[0038] Figure 11 is a graph showing the drain efficiency of the above-described conventional Doherty amplifier with respect to the output voltage. As Figure 11 shown, when the output power is the saturated output, both the carrier amplifier 101 and the peak amplifier 102 become the saturated power, so the drain efficiency reaches the maximum. On the other hand, at the output level where the output power is backed off by 6 dB from the saturated power, only the carrier amplifier 101 becomes the saturated power, and the peak amplifier 102 does not amplify the signal. In this case, the drain efficiency also reaches the maximum. That is, when only the carrier amplifier 101 operates, the load becomes twice that when both the carrier amplifier 101 and the peak amplifier 102 operate. Therefore, when only the carrier amplifier 101 operates, compared with the case where both the carrier amplifier 101 and the peak amplifier 102 operate, the current becomes 1 / 2 and the output power becomes 1 / 4. Therefore, when only the carrier amplifier 101 operates, the drain efficiency reaches the maximum at the output with a 6-dB back-off.

[0039] As described above, for a Doherty amplifier, there are ideally two output powers at which the drain efficiency reaches the maximum, so the output power range with a high drain efficiency can be expanded. Therefore, in a system using a signal with a large difference between the peak power and the average power, it can be said that the Doherty amplifier is one of the effective methods for achieving high-efficiency characteristics.

[0040] However, in Figure 10In the Doherty amplifier shown above, as described above, particularly on the output combining circuit section side, when the frequency of the high-frequency input signal changes, the reactance component of the quarter-wavelength phase delay line is large. Therefore, the frequency dependence of the impedance cannot be ignored, and there is a problem that the desired high-frequency characteristics cannot be obtained.

[0041] Similarly, when the frequency of the high-frequency input signal changes, due to the parasitic capacitance component of high-frequency transistors such as FETs that make up the carrier amplifier and the peak amplifier, the load modulation depending on the output power at the intrinsic nodes of the high-frequency transistors is not correctly performed, and there is a problem that the characteristics of high efficiency cannot be obtained over a wide frequency band.

[0042] In addition, since the output side matching circuit is connected to the output side of the peak amplifier, it is difficult to sufficiently increase the impedance of the peak amplifier observed from the combining point during the back-off operation, and there is a possibility that the efficiency during the back-off operation deteriorates.

[0043] Moreover, since the quarter-wavelength phase delay line is long, there is a problem that the size of the amplifier becomes large.

[0044] Hereinafter, the load modulation amplifier according to the present invention for eliminating the above problems will be described according to each embodiment with reference to the drawings. In addition, in each embodiment, the same or corresponding parts are denoted by the same reference numerals, and repeated descriptions are omitted.

[0045] Embodiment 1.

[0046] Figure 1 FIG. is a schematic circuit configuration diagram of a Doherty amplifier which is a load modulation amplifier according to Embodiment 1 of the present invention. In the Doherty amplifier 2000, a carrier amplifier 1, a peak amplifier 2, an input distribution circuit section 3, and an output combining circuit section 4 are formed on a high-frequency circuit board CB. Each circuit and its structural elements of the Doherty amplifier 2000 are connected, for example, by high-frequency signal lines SL, and a part thereof is constituted by the high-frequency signal lines SL which are formed by microstrip lines or the like formed on the high-frequency circuit board CB.

[0047] The input distribution circuit section 3 distributes the high-frequency input signal input to the high-frequency input terminal 5 into two signals composed of a first input signal and a second input signal in an equal-power manner, for example, by a distributor 3a. One of the distributed signals is the first input signal here and is input to the carrier amplifier 1, and the other is the second input signal here and is input to the peak amplifier 2 via a phase delay circuit 3b. In addition, the phase delay circuit 3b can also be constituted by a phase delay line which is formed by the high-frequency signal lines SL, for example.

[0048] The carrier amplifier 1 is composed of a first high-frequency transistor 1a and an input matching circuit 1b. The first high-frequency transistor 1a is composed of, for example, an FET (Field Effect Transistor). The carrier amplifier 1 does not have an impedance transformation circuit such as a matching circuit on the output side.

[0049] In addition, the peak amplifier 2 is composed of a second high-frequency transistor 2a and an input matching circuit 2b. The second high-frequency transistor 2a is composed of, for example, an FET. Similarly, the peak amplifier 2 does not have an impedance transformation circuit such as a matching circuit on the output side.

[0050] Here, the carrier amplifier 1 operates, for example, with class A or AB bias and always amplifies the input signal. The peak amplifier 2 operates with class C bias and amplifies an input signal having a power greater than or equal to a specified power.

[0051] The signals after passing through the two amplifiers 1 and 2 are combined by an output combining circuit section 4. The output combining circuit section 4 is composed of a 90-degree phase delay circuit 4a, a combiner 4b, and an impedance transformation circuit 4c. The 90-degree phase delay circuit 4a is directly connected to the carrier amplifier 1. The combiner 4b combines the output signal of the 90-degree phase delay circuit 4a and the output signal of the peak amplifier 2. The impedance transformation circuit 4c transforms the output impedance. The signals of the carrier amplifier 1 and the peak amplifier 2 are combined at the combining point, that is, the combiner 4b, in a state where the phases are the same when operating in saturation through the 90-degree phase delay circuit 4a. The combined signal is output from the high-frequency output terminal 6 via the impedance transformation circuit 4c.

[0052] Figure 2 is a diagram for explaining an example of the circuit structure of the first high-frequency transistor 1a of the carrier amplifier 1, the second high-frequency transistor 2a of the peak amplifier 2, and the 90-degree phase delay circuit 4a of the output combining circuit section 4 for Figure 1 . Here, it is assumed that the 90-degree phase delay circuit 4a is composed of a phase delay line, and the phase delay line is composed of, for example, a signal line SL. The phase delay line is equivalently represented by a parallel capacitance component and a series inductance component as shown in the 90-degree phase delay circuit 4a of Figure 7 described later, for example. As already shown, in a Doherty amplifier, there is a problem that due to the parasitic capacitance component of a high-frequency transistor such as an FET that constitutes a high-frequency amplification element, load modulation depending on the output power is not correctly performed at the intrinsic node of the high-frequency transistor. Therefore, as Figure 2As shown, by using the parasitic capacitance components of the high-frequency transistors that make up the carrier amplifier 1 and the peak amplifier 2 as the shunt capacitance components of the phase delay line that makes up the 90-degree phase delay circuit 4a, the load modulation of the Doherty amplifier can be achieved normally, and high-efficiency characteristics can be realized.

[0053] Figure 3 is a graph showing the frequency characteristics of the drain efficiency of the Doherty amplifier with respect to the output power back-off amount. At Figure 3 in,

[0054] the frequencies are two points: the fundamental frequency shown as X1 and the fundamental frequency × 1.3 shown as X2.

[0055] In addition, at each frequency, the ideal case without the parasitic capacitance of the high-frequency transistor is shown as A (condition 1),

[0056] the case where the phase delay line absorbs the parasitic capacitance, that is, the case where the parasitic capacitance is used in the phase delay line is shown as B (condition 2: Embodiment 1 of the present invention),

[0057] the case where there is parasitic capacitance and an output matching circuit is connected is shown as C, D (conditions 3, 4: existing structures).

[0058] A (condition 1) is shown by a dotted line, B (condition 2) is shown by a solid line, C (condition 3) is shown by a dashed line, and D (condition 4) is shown by a dot-dashed line.

[0059] Conditions 3 and 4 assume different output matching circuit losses. As Figure 3 shown, it can be seen that at the fundamental frequency (X1), for the ideal case (A) and the structure (B) shown in Embodiment 1 of the present invention, equivalent high-efficiency characteristics are achieved, but for the existing structures (C, D), the efficiency characteristics deteriorate corresponding to the loss of the output matching circuit.

[0060] In addition, it can be seen that when the frequency changes to the fundamental frequency × 1.3 (X2), by adopting the structure (B) shown in Embodiment 1 of the present invention, the efficiency can be improved by about 10 points compared with the existing structures (C, D).

[0061] As described above, in the Figure 1 load modulation amplifier, that is, the Doherty amplifier shown, by making the 90-degree phase delay circuit 4a of the output combining circuit section 4 absorb the parasitic capacitance components of the first high-frequency transistor 1a of the carrier amplifier 1 and the second high-frequency transistor 2a of the peak amplifier 2, the load modulation of the Doherty amplifier can be achieved normally, and high-efficiency characteristics can be realized.

[0062] That is, the 90-degree phase delay circuit 4a has circuit constants that incorporate the parasitic capacitance components of the first high-frequency transistor and the second high-frequency transistors 1a and 2a.

[0063] Moreover, for the carrier amplifier 1 and the peak amplifier 2, they are connected to the output combining circuit section 4 without an impedance transformation circuit such as a matching circuit, enabling miniaturization of the amplifier size. Additionally, since there is no loss caused by the matching circuit, high efficiency can be achieved, and the impedance of the peak amplifier 2 observed from the combining point during the back-off operation can be increased, also enabling high efficiency during the back-off operation.

[0064] Embodiment 2.

[0065] Figure 4 It is a schematic circuit structure diagram of a load modulation amplifier, namely a Doherty amplifier, according to Embodiment 2 of the present invention. For the Doherty amplifier 2000, the carrier amplifier 1, the peak amplifier 2, the input distribution circuit section 3, and the output combining circuit section 4 are formed on the high-frequency circuit substrate CB.

[0066] The carrier amplifier 1 is composed of a first high-frequency transistor 1a, an input matching circuit 1b, and a first resonance circuit 1c that resonates with the parasitic capacitance of the first high-frequency transistor 1a, and does not have an impedance transformation circuit such as a matching circuit on the output side.

[0067] Furthermore, the peak amplifier 2 is composed of a second high-frequency transistor 2a, an input matching circuit 2b, and a second resonance circuit 2c that resonates with the parasitic capacitance of the second high-frequency transistor 2a, and similarly does not have an impedance transformation circuit such as a matching circuit on the output side.

[0068] Here, the carrier amplifier 1 operates with, for example, class A or class AB biasing and always amplifies the input signal. The peak amplifier 2 operates with class C biasing and amplifies an input signal with a power greater than or equal to a specified power.

[0069] Figure 5 It is a diagram for explaining Figure 4 an example of the circuit structures of the first high-frequency transistor 1a and the resonance circuit 1c of the carrier amplifier 1, the second high-frequency transistor 2a and the resonance circuit 2c of the peak amplifier 2, and the 90-degree phase delay circuit 4a of the output combining circuit section 4. As already shown, in the Doherty amplifier, there is the following problem: due to the parasitic capacitance components of high-frequency transistors such as FETs that constitute the high-frequency amplification elements, load modulation depending on the output power is not correctly performed at the intrinsic nodes of the high-frequency transistors. Therefore, as Figure 5As shown, the parasitic capacitance components of the high-frequency transistors that make up the carrier amplifier 1 and the peak amplifier 2 are canceled out by the resonant circuits 1c and 2c, so that the load modulation of the Doherty amplifier is normally achieved, and high-efficiency characteristics are realized. In this case, the frequency characteristics of the drain efficiency of the Doherty amplifier with respect to the output power back-off amount are the same as those of Figure 3 roughly the same.

[0070] In addition, when the sizes of the high-frequency transistors that make up the carrier amplifier 1 and the peak amplifier 2 are different, the connected resonant circuits 1c and 2c may sometimes also be different. Also, as Figure 6 shown, a part of the parasitic capacitance components of the high-frequency transistors is canceled out by the resonant circuits 1c and 2c. As in Embodiment 1, the 90-degree phase delay circuit 4a composed of the phase delay line absorbs the remaining parasitic capacitance components, so that the same high-efficiency characteristics can also be achieved.

[0071] In addition, in Figure 5 , Figure 6 , as an example, the resonant circuit 1c and the resonant circuit 2c are shown as a structure composed of inductance elements connected in parallel with the signal line SL, but the structure of the resonant circuit is not limited to this.

[0072] As described above, in the load modulation amplifier, that is, the Doherty amplifier shown in Figure 4 , the parasitic capacitance components of the high-frequency transistors, that is, the first high-frequency transistor 1a of the carrier amplifier 1 and the second high-frequency transistor 2a of the peak amplifier 2, are canceled out by the resonant circuits 1c and 2c, or a part of them is canceled out, and the 90-degree phase delay circuit 4a absorbs the remaining capacitance components, whereby the load modulation of the Doherty amplifier can be normally achieved, and high-efficiency characteristics can be realized.

[0073] That is, the resonant circuits 1c and 2c have circuit constants that cancel out all or part of the parasitic capacitance components of the high-frequency transistors 1a and 2a, and the 90-degree phase delay circuit 4a has circuit constants that incorporate a part of the capacitance components remaining after being canceled out.

[0074] And, similar to Embodiment 1 above, for the carrier amplifier 1 and the peak amplifier 2, they are connected to the output combining circuit section 4 in a state without an impedance transformation circuit such as a matching circuit, so that miniaturization of the amplifier size can be achieved. In addition, since there is no loss caused by the matching circuit, high efficiency can be achieved, and the impedance of the peak amplifier 2 observed from the combining point during the back-off operation can be increased, and high efficiency during the back-off operation can also be achieved.

[0075] Embodiment 3.

[0076] Figure 7This is a schematic circuit structure diagram of a load modulation amplifier, namely a Doherty amplifier, related to Embodiment 3 of the present invention. For the Doherty amplifier 2000, the carrier amplifier 1, the peak amplifier 2, the input distribution circuit section 3, and the output combining circuit section 4 are formed using a semiconductor substrate such as gallium arsenide (GaAs) as a monolithic integrated circuit. In Figure 7 the semiconductor substrate of the monolithic integrated circuit is shown as the semiconductor substrate SCB.

[0077] The carrier amplifier 1 is composed of a first high-frequency transistor 1a and an input matching circuit 1b, and does not have an impedance transformation circuit such as a matching circuit on the output side.

[0078] The drain bias line of the first high-frequency transistor 1a composed of an FET is composed of a line SL1 or an inductance element 1dd provided on the semiconductor substrate SCB, and also serves as a resonance circuit for canceling the parasitic capacitance component of the first high-frequency transistor 1a, thereby achieving miniaturization of the size in addition to the high efficiency of the Doherty amplifier.

[0079] In addition, the peak amplifier 2 is composed of a second high-frequency transistor 2a and an input matching circuit 2b, and similarly does not have an impedance transformation circuit such as a matching circuit on the output side.

[0080] The drain bias line of the second high-frequency transistor 2a composed of an FET is composed of a line SL2 or an inductance element 2dd provided on the semiconductor substrate SCB, and also serves as a resonance circuit for canceling the parasitic capacitance component of the second high-frequency transistor 2a, thereby achieving the same effect as in the case of the carrier amplifier 1.

[0081] The outputs of the carrier amplifier 1 and the peak amplifier 2 are directly connected to the output combining circuit section 4 without being connected to an impedance transformation circuit such as a matching circuit. That is, the output of the carrier amplifier 1 passes through an LPF (low-pass filter)-type circuit element serving as a 90-degree phase delay circuit 4a, and then, in a synthesizer 4b composed of lines, is in-phase combined with the output of the peak amplifier 2. Here, in Figure 7 it is assumed that the output of the carrier amplifier 1 is input to an LPF-type circuit element or a circuit group of LPF-type circuit elements, but even in the case of being input to Figure 8 the HPF (high-pass filter)-type circuit element or the circuit group of HPF-type circuit elements shown, there is no problem.

[0082] The output impedance of the carrier amplifier 1 depends on the size of the high-frequency transistor 1a, but in the case of requiring a peak output power of several hundred milliwatts, it becomes about 20Ω. Therefore, Figure 7The characteristic impedance of the 90-degree phase delay circuit 4a is set to about 20 Ω. For example, when using a line provided on a GaAs semiconductor substrate to implement a 1 / 4 wavelength phase delay with a characteristic impedance of 20 Ω, i.e., a 90-degree phase delay, the line width exceeds 200 μm, making the chip layout of the amplifier difficult and potentially increasing the size of the amplifier. In the above case, it is effective to use LPF-type or HPF-type circuit elements.

[0083] That is, the 90-degree phase delay circuit 4a can also be composed of a line on the GaAs semiconductor substrate SCB, and can also be composed of circuit elements. When the 90-degree phase delay circuit 4a is composed of circuit elements, the circuit element or group of circuit elements can be either LPF-type or HPF-type.

[0084] After output synthesis, the output of the synthesizer 4b is connected to the impedance transformation circuit 4c. When the output impedances of the carrier amplifier 1 and the peak amplifier 2 are 20 Ω, the output impedance after output synthesis during saturation operation becomes 10 Ω. Therefore, the impedance transformation circuit 4c performs a transformation from 10 Ω to 50 Ω as the load impedance. In Figure 7 this case, the impedance transformation circuit 4c uses an LPF-type circuit element or group of circuit elements. Also, similar to the 90-degree phase delay circuit 4a, the impedance transformation circuit 4c can also be implemented by a line SL provided on the GaAs semiconductor substrate SCB, and can also use Figure 8 the HPF-type circuit element or group of circuit elements shown.

[0085] When a transmission amplifier is used in a system that seeks high communication quality such as mobile communication, a circuit for suppressing harmonics of an LPF or the like is usually mounted on the output side. As a result, sometimes the size of the entire transmitter becomes larger and the cost becomes higher. However, as Figure 7 shown, by using an LPF-type circuit element or group of circuit elements to form the 90-degree phase delay circuit 4a and the impedance transformation circuit 4c, the harmonic level at the output of the Doherty amplifier can be suppressed, the LPF that is usually connected to the output side of the amplifier can be deleted or the filter order can be reduced, which also contributes to the miniaturization and cost reduction of the entire transmitter.

[0086] In addition, similar to the 90-degree phase delay circuit 4a and the impedance transformation circuit 4c, regarding the phase delay circuit 3b of the input distribution circuit section 3, as Figure 9 shown, it can also be composed of a line on the GaAs semiconductor substrate SCB, and can also be composed of circuit elements. When the phase delay circuit 3b is composed of circuit elements, the circuit element or group of circuit elements can be either LPF-type or Figure 8 the HPF-type shown.

[0087] Furthermore, the present invention is not limited to the above-described embodiments, including all possible combinations thereof.

[0088] Industrial Applicability

[0089] The present invention is applicable to load modulation amplifiers for communication devices in various fields.

Claims

1. A load modulation amplifier, comprising: A high-frequency circuit board; An input distribution circuit section having a distributor and a phase delay circuit, the distributor distributing one input signal into a first input signal and a second input signal, and the phase delay circuit being formed on the signal line of the distributed second input signal; A carrier amplifier having a first high-frequency transistor that amplifies the first input signal from the input distribution circuit section; A peak amplifier having a second high-frequency transistor that amplifies the second input signal from the input distribution circuit section; And An output combining circuit section having a 90-degree phase delay circuit, a combiner, and an impedance transformation circuit. The 90-degree phase delay circuit is formed on the signal line of the output of the carrier amplifier. The combiner combines the output of the 90-degree phase delay circuit and the output of the peak amplifier. The impedance transformation circuit transforms the output impedance of the combiner. The input distribution circuit section, the carrier amplifier, the peak amplifier, and the output combining circuit section are respectively formed on the high-frequency circuit substrate. The carrier amplifier has a first resonance circuit that resonates with the parasitic capacitance of the first high-frequency transistor. The drain terminal of the first high-frequency transistor is directly connected to the output combining circuit section without passing through an output impedance transformation circuit. The peak amplifier has a second resonance circuit that resonates with the parasitic capacitance of the second high-frequency transistor. The drain terminal of the second high-frequency transistor is directly connected to the output combining circuit section without passing through an output impedance transformation circuit. The first resonance circuit has a circuit constant that cancels all or part of the parasitic capacitance component of the first high-frequency transistor. The second resonance circuit has a circuit constant that cancels all or part of the parasitic capacitance component of the second high-frequency transistor.

2. The load modulation amplifier according to claim 1, wherein The first resonance circuit and the second resonance circuit each include an inductance element connected in parallel with the signal line.

3. The load modulation amplifier according to claim 1 or 2, wherein The load modulation amplifier is a monolithic integrated circuit, and the 90-degree phase delay circuit of the output combining circuit section is formed by a signal line on the high-frequency circuit substrate.

4. The load modulation amplifier according to claim 1 or 2, wherein The load modulation amplifier is a monolithic integrated circuit, and the 90-degree phase delay circuit of the output combining circuit section is formed by HPF-type or LPF-type circuit elements.

5. The load modulation amplifier according to claim 3, wherein The load modulation amplifier is a monolithic integrated circuit, and the phase delay circuit of the input distribution circuit section is formed by a signal line on the high-frequency circuit substrate.

6. The load modulation amplifier according to claim 4, wherein The load modulation amplifier is a monolithic integrated circuit, and the phase delay circuit of the input distribution circuit section is formed by a signal line on the high-frequency circuit substrate.

7. The load modulation amplifier according to claim 3, wherein The load modulation amplifier is a monolithic integrated circuit, and the phase delay circuit of the input distribution circuit section is formed by HPF-type or LPF-type circuit elements.

8. The load modulation amplifier according to claim 4, wherein The load modulation amplifier is a monolithic integrated circuit, and the phase delay circuit of the input distribution circuit section is formed by HPF-type or LPF-type circuit elements.

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