Amplifier and voltage generation circuit including the same

Abstract

An amplifier and a voltage generating circuit including the same are disclosed. The voltage generating circuit includes an amplifier configured to detect a difference between a reference voltage and a feedback voltage according to a control signal and a bias current, and configured to generate a driving signal. The voltage generating circuit further includes a driver configured to generate an internal voltage by driving an external voltage according to the driving signal. The amount of bias current can be forcibly adjusted by means of the control signal.

Description

TECHNICAL FIELD

[0001] Various embodiments relate generally to a semiconductor circuit, and more particularly to an amplifier and a voltage generating circuit including the same. BACKGROUND

[0002] A semiconductor circuit uses a voltage generating circuit to generate various internal voltages necessary for operation of internal circuits of the semiconductor circuit from an external voltage.

[0003] In order to cause the semiconductor memory circuit to switch to an active mode for data input / output operation and the like, the voltage generating circuit is designed to have a fast response speed by increasing a driving capability of the voltage generating circuit. When the voltage generating circuit is designed to have a fast response speed, a peak current problem can be caused at the start of operation such as a power-on state. SUMMARY

[0004] Various embodiments relate to providing an amplifier capable of reducing a peak current for stable operation and a voltage generating circuit including the same.

[0005] In one embodiment, the amplifier can include a first stage configured to detect and output a difference between a reference voltage and a feedback voltage according to a control signal and a bias current, wherein the amount of bias current can be forcibly adjusted by means of the control signal.

[0006] In one embodiment, the voltage generating circuit can include an amplifier configured to detect a difference between a reference voltage and a feedback voltage according to a control signal and a bias current, and configured to generate a driving signal, and a driver configured to generate an internal voltage by driving an external voltage according to the driving signal, wherein the amount of bias current can be forcibly adjusted by means of the control signal.

[0007] In one embodiment, the voltage generation circuit can include: a first transistor array commonly applied with an external voltage and having gate terminals commonly applied with a bias voltage; a second transistor array electrically connected with the first transistor array and having gate terminals commonly input with a control signal; a third transistor electrically connected with the first transistor array and the second transistor array and configured to receive a reference voltage; a fourth transistor electrically connected between the third transistor and a ground voltage terminal; a fifth transistor electrically connected with the first transistor array and the second transistor array and configured to receive a feedback voltage; and a sixth transistor electrically connected between the fifth transistor and the ground voltage terminal and configured to generate a driving signal; a driver configured to generate an internal voltage by driving the external voltage according to the driving signal; and a distributed resistor configured to generate the feedback voltage by distributing the internal voltage, wherein an amount of bias current flowing through the first transistor array and the second transistor array according to the bias voltage can be forcibly adjusted according to the control signal. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 FIG. 1 is a diagram illustrating a configuration of a voltage generation circuit according to one embodiment.

[0009] Figure 2 FIG. 2 is a diagram illustrating a configuration of an amplifier of one embodiment of Figure 1

[0010] Figure 3 FIG. 3 is a diagram illustrating signal waveforms according to Figure 2

[0011] Figure 4 FIG. 4 is a diagram illustrating a configuration of a voltage generation circuit according to another embodiment.

[0012] Figure 5 FIG. 5 is a diagram illustrating a configuration of an amplifier of one embodiment of Figure 4

[0013] Figure 6 FIG. 6 is a diagram illustrating signal waveforms according to Figure 5

[0014] Figure 7 FIG. 7 is a diagram illustrating a configuration of another embodiment of an amplifier of Figure 4

[0015] Figure 8 FIG. 8 is a diagram illustrating a configuration of yet another embodiment of an amplifier of Figure 4 ​​​​​​DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the disclosure are described in more detail with reference to the drawings.

[0017] Figure 1 FIG. 1 is a diagram illustrating a configuration of a voltage generating circuit 10 according to one embodiment.

[0018] Referring to Figure 1 , the voltage generating circuit 10 can generate an internal voltage VDDI according to a bias voltage VBIAS, a reference voltage VREF, and a feedback voltage VFB.

[0019] The voltage generating circuit 10 can include an amplifier 100, a driver 300, a distributed resistor 500, and a capacitor 700.

[0020] The amplifier 100 can generate a driving signal DRV according to the bias voltage VBIAS, the reference voltage VREF, and the feedback voltage VFB.

[0021] The driver 300 can generate the internal voltage VDDI by driving an external voltage VDD according to the driving signal DRV.

[0022] The driver 300 can have a source terminal to which the external voltage VDD is applied, a gate terminal to which the driving signal DRV is input, and a drain terminal electrically connected with a terminal of the internal voltage VDDI.

[0023] The distributed resistor 500 can generate the feedback voltage VFB by distributing the internal voltage VDDI.

[0024] The capacitor 700 can be electrically connected in parallel with the distributed resistor 500 between a terminal of the internal voltage VDDI and a terminal of a ground voltage VSS.

[0025] The capacitor 700 can be loaded as an output terminal of the voltage generating circuit 10.

[0026] The capacitor 700 can be designed to have a larger capacitance than a capacitance of a transistor of the voltage generating circuit 10.

[0027] Figure 2 FIG. 2 is a diagram illustrating a configuration of the amplifier 100 according to one embodiment. Figure 1

[0028] Referring to Figure 2 , the amplifier 100 can include a comparator 111 and a current mirror 112.

[0029] The comparator 111 can compare the reference voltage VREF and the feedback voltage VFB and output a comparison result.

[0030] ​The current mirror 112 can generate a driving signal DRV according to an output of the comparator 111.

[0031] The comparator 111 can include a first transistor 111-1 to a fifth transistor 111-5.

[0032] The first transistor 111-1 can have a source terminal to which an external voltage VDD is applied, and a gate terminal to which a bias voltage VBIAS is applied.

[0033] The second transistor 111-2 can have a source terminal electrically connected to a drain terminal of the first transistor 111-1, and a gate terminal to which a reference voltage VREF is applied.

[0034] The third transistor 111-3 can have a source terminal to which a ground voltage VSS is applied, and a drain terminal electrically connected to a gate terminal thereof and a drain terminal of the second transistor 111-2.

[0035] The fourth transistor 111-4 can have a source terminal electrically connected to a drain terminal of the first transistor 111-1, and a gate terminal to which a feedback voltage VFB is applied.

[0036] The fifth transistor 111-5 can have a source terminal to which the ground voltage VSS is applied, and a drain terminal electrically connected to a gate terminal thereof and a drain terminal of the fourth transistor 111-4.

[0037] The current mirror 112 can include a first transistor 112-1 to a fourth transistor 112-4.

[0038] The first transistor 112-1 can have a source terminal to which an external voltage VDD is applied, and a gate terminal electrically connected to a drain terminal thereof.

[0039] The second transistor 112-2 can have a source terminal to which a ground voltage VSS is applied, and a drain terminal electrically connected to a drain terminal of the first transistor 112-1.

[0040] The gate terminal of the second transistor 112-2 can be electrically connected to the drain terminal of the third transistor 111-3 of the comparator 111.

[0041] The third transistor 112-3 can have a source terminal to which the external voltage VDD is applied, and a gate terminal electrically connected to a gate terminal of the first transistor 112-1.

[0042] The fourth transistor 112-4 can have a source terminal to which the ground voltage VSS is applied, and a drain terminal electrically connected to a drain terminal of the third transistor 112-3.

[0043] The gate terminal of the fourth transistor 112-4 can be electrically connected with the drain terminal of the fifth transistor 111-5 of the comparator 111.

[0044] Figure 3 is a diagram showing signal waveforms according to Figure 2

[0045] Referring to Figure 3 The operation of the voltage generating circuit 10 is described as follows.

[0046] During the power-up process of the semiconductor device, as the level of the external voltage VDD increases, the level of the reference voltage VREF also increases.

[0047] As the level of the reference voltage VREF increases, the level of the gate terminal of the fourth transistor 112-4 of the current mirror 112 increases, such that the level of the drive signal DRV decreases, and thus the level of the internal voltage VDDI can increase.

[0048] Then, by comparing the levels of the reference voltage VREF and the feedback voltage VFB, the level of the drive signal DRV is increased or decreased, and thus the level of the internal voltage VDDI can be substantially maintained at the target level.

[0049] On the other hand, the level of the internal voltage VDDI needs to increase in proportion to the increase in the level of the reference voltage VREF, but since the capacitor 700 is designed to have a large capacitance, the level of the internal voltage VDDI can not increase, and thus the level of the feedback voltage VFB can not increase.

[0050] Since the level of the feedback voltage VFB does not increase with the increase in the level of the reference voltage VREF (that is, since the level of the feedback voltage VFB is relatively lower than the level of the reference voltage VREF), a relatively large current due to the bias voltage VBIAS can flow through the fourth transistor 111-4 compared to the second transistor 111-2.

[0051] Since a relatively large current flows through the fourth transistor 111-4, the level of the gate terminal of the fourth transistor 112-4 can rapidly increase.

[0052] As the level of the gate terminal of the fourth transistor 112-4 rapidly increases, the level of the drive signal DRV rapidly decreases, and thus the output voltage drive current (that is, the current I DRV flowing to the capacitor 700 via the driver 300) can rapidly increase, resulting in an increase in the peak current.

[0053] Figure 4 is a diagram showing a configuration of a voltage generating circuit 11 according to another embodiment.

[0054] Referring to​Figure 4 The voltage generation circuit 11 can generate the internal voltage VDDI according to the bias voltage VBIAS, the control signal CTR, the reference voltage VREF, and the feedback voltage VFB.

[0055] The voltage generation circuit 11 can differentially adjust a slew rate of the driving signal DRV before and after a level of the external voltage VDD reaches a set level according to the control signal CTR, and generate the internal voltage VDDI according to the driving signal DRV having the adjusted slew rate.

[0056] In the semiconductor device, a power-on reset (POR) signal for initializing various circuits after power-up can be used as the control signal CTR.

[0057] During a power-up process, a level of the power-on reset signal can increase as the external voltage VDD increases to substantially maintain a high level, and can transition to a low level when the level of the external voltage VDD is equal to or exceeds the set level.

[0058] The voltage generation circuit 11 can include an amplifier 101, a driver 300, a distributed resistor 500, and a capacitor 700.

[0059] The amplifier 101 can generate the driving signal DRV according to the bias voltage VBIAS, the control signal CTR, the reference voltage VREF, and the feedback voltage VFB.

[0060] The amplifier 101 can generate the driving signal DRV by detecting a difference between the reference voltage VREF and the feedback voltage VFB according to a bias current.

[0061] When a level of the bias voltage VBIAS is constant, the bias current amount can be continuously maintained according to the bias voltage VBIAS.

[0062] Although the level of the bias voltage VBIAS is constant, the embodiment of the disclosure can forcibly adjust the bias current amount within a maximum value determined according to the bias voltage VBIAS, using the control signal CTR.

[0063] The driver 300 can generate the internal voltage VDDI by driving the external voltage VDD according to the driving signal DRV.

[0064] The driver 300 can have a source terminal to which the external voltage VDD is applied, a gate terminal to which the driving signal DRV is input, and a drain terminal electrically connected to a terminal of the internal voltage VDDI.

[0065] The driver 300 can be configured as a PMOS transistor.

[0066] The distributed resistor 500 can generate the feedback voltage VFB by distributing the internal voltage VDDI.

[0067] The capacitor 700 can be electrically connected in parallel with the distributed resistor 500 between a terminal of the internal voltage VDD and a terminal of the ground voltage VSS.

[0068] The capacitor 700 can serve as an output terminal load of the voltage generation circuit 11.

[0069] The capacitor 700 can be designed to have a larger capacitance than that of a transistor of the voltage generation circuit 11.

[0070] Figure 5 is a diagram showing a configuration of one embodiment 101-1 of the amplifier. Figure 4

[0071] Referring to Figure 5 , the amplifier 101-1 can include multiple stages, for example, a comparator 121 as a first stage and a current mirror 122 as a second stage.

[0072] The comparator 121 can detect and output a difference between the reference voltage VREF and the feedback voltage VFB according to a bias voltage VBIAS and a control signal CTR.

[0073] The comparator 121 can detect and output a difference between the reference voltage VREF and the feedback voltage VFB according to a bias current.

[0074] The bias current amount can be determined according to the bias voltage VBIAS.

[0075] The bias current amount can be forcibly adjusted within a maximum value determined according to the bias voltage VBIAS by means of the control signal CTR.

[0076] The current mirror 122 can generate a drive signal DRV according to an output of the comparator 121.

[0077] The comparator 121 can include a first transistor array 121-1, a second transistor array 121-2, and third to sixth transistors 121-3 to 121-6.

[0078] The first transistor array 121-1 can include a plurality of transistors having source terminals to which an external voltage VDD is commonly applied and gate terminals to which a bias voltage VBIAS is commonly applied.

[0079] ​The second transistor array 121-2 can include a plurality of transistors having source terminals electrically connected to drain terminals of the transistors of the first transistor array 121-1, except for one transistor 121-1n among the transistors of the first transistor array 121-1, respectively, and gate terminals commonly input with a control signal CTR.

[0080] The plurality of transistors of the first transistor array 121-1 and the second transistor array 121-2 can be configured as PMOS transistors.

[0081] The third transistor 121-3 can be configured for a first input terminal to receive a reference voltage VREF.

[0082] The third transistor 121-3 can have a source terminal electrically connected to the first transistor array 121-1 and the second transistor array 121-2, and a gate terminal to which the reference voltage VREF is applied.

[0083] The source terminal of the third transistor 121-3 can be electrically connected in common with the drain terminal of the one transistor 121-1n among the plurality of transistors of the first transistor array 121-1 and the drain terminals of the transistors of the second transistor array 121-2, and the gate terminal of the third transistor 121-3 can receive the reference voltage VREF.

[0084] The fourth transistor 121-4 can have a source terminal to which a ground voltage VSS is applied, and a drain terminal electrically connected to its own gate terminal and the drain terminal of the third transistor 121-3.

[0085] The fifth transistor 121-5 can be configured for a second input terminal to receive a feedback voltage VFB.

[0086] The fifth transistor 121-5 can have a source terminal electrically connected to the first transistor array 121-1 and the second transistor array 121-2, and a gate terminal to which the feedback voltage VFB is applied.

[0087] The source terminal of the fifth transistor 121-5 can be electrically connected in common with the drain terminal of the one transistor 121-1n among the plurality of transistors of the first transistor array 121-1 and the drain terminals of the transistors of the second transistor array 121-2, and the gate terminal of the fifth transistor 121-5 can receive the feedback voltage VFB.

[0088] The sixth transistor 121-6 can have a source terminal to which the ground voltage VSS is applied, and a drain terminal electrically connected to its own gate terminal and the drain terminal of the fifth transistor 121-5.

[0089] The third transistor 121-3 and the fifth transistor 121-5 can be configured as PMOS transistors.

[0090] The fourth transistor 121-4 and the sixth transistor 121-6 can be configured as NMOS transistors.

[0091] The gate width of the plurality of transistors of the first transistor array 121-1 and the plurality of transistors of the second transistor array 121-2 can be narrower than the gate width of the third transistor 121-3 to the sixth transistor 121-6.

[0092] For example, when the gate width of each of the third transistor 121-3 to the sixth transistor 121-6 is "N", the gate width of the plurality of transistors of the first transistor array 121-1 can be "1 / N".

[0093] The gate width of each of the plurality of transistors of the second transistor array 121-2 can also be "1 / N".

[0094] The sum of the current driving forces of both the first transistor array 121-1 and the second transistor array 121-2 can be substantially the same as the current driving force of each of the third transistor 121-3 to the sixth transistor 121-6.

[0095] The current mirror 122 can include a first transistor 122-1 to a fourth transistor 122-4.

[0096] The first transistor 122-1 can have a source terminal to which an external voltage VDD is applied, and a gate terminal electrically connected to its own drain terminal.

[0097] The second transistor 122-2 can have a source terminal to which a ground voltage VSS is applied, and a drain terminal electrically connected to the drain terminal of the first transistor 122-1.

[0098] The gate terminal of the second transistor 122-2 can be electrically connected to the drain terminal of the fourth transistor 121-4 of the comparator 121.

[0099] The third transistor 122-3 can have a source terminal to which an external voltage VDD is applied, and a gate terminal electrically connected to the gate terminal of the first transistor 122-1.

[0100] The fourth transistor 122-4 can have a source terminal to which a ground voltage VSS is applied, and a drain terminal electrically connected to the drain terminal of the third transistor 122-3.

[0101] The gate terminal of the fourth transistor 122-4 can be electrically connected to the drain terminal of the sixth transistor 121-6 of the comparator 121.

[0102] The first transistor 122-1 and the third transistor 122-3 can be configured as PMOS transistors.

[0103] The second transistor 122-2 and the fourth transistor 122-4 can be configured as NMOS transistors.

[0104] Figure 6 is a graph showing signal waveforms according to Figure 5

[0105] Referring to Figure 6 The operation of the voltage generation circuit 11 is described as follows.

[0106] During the power-up process of the semiconductor device, as the level of the external voltage VDD increases, the level of the reference voltage VREF also increases.

[0107] As the level of the external voltage VDD increases, the voltage level of the control signal CTR also increases, and when the voltage level of the control signal CTR reaches a high level based on a logic level, the second transistor array 121-2 can be turned off.

[0108] When the second transistor array 121-2 is turned off, a current corresponding to the bias voltage VBIAS can flow only through the one transistor 121-1n of the plurality of transistors of the first transistor array 121-1.

[0109] The level of the internal voltage VDDI needs to increase in proportion to the increase in the level of the reference voltage VREF, but since the capacitor 700 is designed to have a large capacitance, the level of the internal voltage VDDI can not increase, and thus the level of the feedback voltage VFB can not increase.

[0110] Since the level of the feedback voltage VFB does not increase as the level of the reference voltage VREF increases (that is, since the level of the feedback voltage VFB is relatively lower than the level of the reference voltage VREF), a relatively large amount of current corresponding to the bias voltage VBIAS can flow through the fifth transistor 121-5 compared to the third transistor 121-3.

[0111] As the amount of current increases but the bias current decreases, the level of the gate terminal of the fourth transistor 122-4 of the current mirror 122 can gently increase.

[0112] The amount of current can refer to the amount of current flowing through the fifth transistor 121-5 compared to the third transistor 121-3, and the bias current can refer to the amount of current supplied to the third transistor 121-3 and the fifth transistor 121-5 according to the bias voltage VBIAS via the first transistor array 121-1 and the second transistor array 121-2.​

[0113] When the control signal CTR is at a high level, the bias current amount is 1 / N when the current flows only through the one transistor 121-1n of the plurality of transistors of the first transistor array 121-1. Thus, the bias current amount can be reduced compared to the bias current amount N when the current flows through all of the plurality of transistors of the first transistor array 121-1.

[0114] When the level of the gate electrode of the fourth transistor 122-4 increases gently, the level of the drive signal DRV decreases gently, and thus the output voltage drive current (i.e., the current I DRV flowing to the capacitor 700 via the driver 300) can increase gently, thereby increasing the peak current during the power-up process.

[0115] When the level of the external voltage VDD increases and is equal to or greater than the set level, the control signal CTR can transition to a low level.

[0116] When the control signal CTR transitions to a low level, the second transistor array 121-2 can be turned on.

[0117] When the second transistor array 121-2 is turned on, a current corresponding to the bias voltage VBIAS can flow through all of the plurality of transistors of the first transistor array 121-1.

[0118] When the level of the external voltage VDD stabilizes to the set level, the bias current amount can return to N.

[0119] Then, by comparing the levels of the reference voltage VREF and the feedback voltage VFB, the level of the drive signal DRV can be increased or decreased, and thus the level of the internal voltage VDDI can be substantially maintained at the target level.

[0120] According to this embodiment, it is possible to reduce the peak current by using the control signal to reduce the bias current amount before the power-up period (i.e., before the level of the external voltage VDD stabilizes to the set level), and it is possible to substantially maintain the internal voltage VDDI at a normal level by increasing the bias current amount after the level of the external voltage VDD stabilizes to the set level.

[0121] Figure 7 is a diagram showing a configuration of another embodiment 101-2 of the amplifier of Figure 4 .

[0122] Referring to Figure 7 , the amplifier 101-2 can compare the reference voltage VREF and the feedback voltage VFB according to the bias voltage VBIAS and the control signal CTR, and generate the drive signal DRV according to a comparison result.

[0123] The amplifier 101-2 can detect and output a change in the amount of current relative to the difference between the reference voltage VREF and the feedback voltage VFB based on the bias current.

[0124] The amount of bias current can be determined according to the bias voltage VBIAS.

[0125] The amount of bias current can be forcibly adjusted within a maximum value determined according to the bias voltage VBIAS by means of the control signal CTR.

[0126] The amplifier 101-2 can be configured as a single stage.

[0127] The single stage can include a first transistor array 131-1, a second transistor array 131-2, and a third transistor 131-3 to a sixth transistor 131-6.

[0128] The first transistor array 131-1 can include a plurality of transistors having source terminals to which an external voltage VDD is commonly applied, and gate terminals to which a bias voltage VBIAS is commonly applied.

[0129] The second transistor array 131-2 can include a plurality of transistors having source terminals electrically connected to drain terminals of the transistors of the first transistor array 131-1, respectively, except for one transistor 131-1n among the transistors of the first transistor array 131-1, and gate terminals to which a control signal CTR is commonly input.

[0130] The plurality of transistors of the first transistor array 131-1 and the second transistor array 131-2 can be configured as PMOS transistors.

[0131] The third transistor 131-3 can have a source terminal electrically connected to the first transistor array 131-1 and the second transistor array 131-2, and a gate terminal to which a feedback voltage VFB is applied.

[0132] The source terminal of the third transistor 131-3 can be electrically connected to a drain terminal of the one transistor 131-1n among the plurality of transistors of the first transistor array 131-1 and drain terminals of the transistors of the second transistor array 131-2, and the gate terminal of the third transistor 131-3 can receive the feedback voltage VFB.

[0133] The fourth transistor 131-4 can have a source terminal to which a ground voltage VSS is applied, a drain terminal electrically connected to a drain terminal of the third transistor 131-3, and a gate terminal electrically connected to the drain terminal thereof.

[0134] The fifth transistor 131-5 may have: a source terminal electrically connected to the first transistor array 131-1 and the second transistor array 131-2; and a gate terminal to which a reference voltage VREF is applied.

[0135] The source terminal of the fifth transistor 131-5 can be electrically connected to the drain terminal of one of the transistors 131-1n in the first transistor array 131-1 and the drain terminal of the transistor in the second transistor array 131-2, and the gate terminal of the fifth transistor 131-5 can receive a reference voltage VREF.

[0136] The sixth transistor 131-6 may have: a source terminal to which a ground voltage VSS is applied; a drain terminal electrically connected to the drain terminal of the fifth transistor 131-5; and a gate terminal electrically connected to the gate terminal of the fourth transistor 131-4.

[0137] The drive signal DRV can be generated through the drain terminal of the sixth transistor 131-6.

[0138] The third transistor 131-3 and the fifth transistor 131-5 can be configured as PMOS transistors.

[0139] The fourth transistor 131-4 and the sixth transistor 131-6 can be configured as NMOS transistors.

[0140] The gate widths of multiple transistors in the first transistor array 131-1 and multiple transistors in the second transistor array 131-2 may be narrower than the gate widths of the third transistor 131-3 to the sixth transistor 131-6.

[0141] For example, when the gate width of each transistor in the third transistor 131-3 to the sixth transistor 131-6 is “N”, the gate width of each transistor in the plurality of transistors in the first transistor array 131-1 can be “1 / N”.

[0142] The gate width of each transistor in the multiple transistors of the second transistor array 131-2 can also be "1 / N".

[0143] The sum of the current driving forces of the first transistor array 131-1 and the second transistor array 131-2 can be substantially the same as the current driving force of each transistor in the third transistor 131-3 to the sixth transistor 131-6.

[0144] and Figure 5 Compared to amplifier 101-1, Figure 7 The amplifier 101-2 has a single-stage structure that does not include a current mirror, which can reduce the circuit area.

[0145] With referenceFigure 5 and Figure 6 The way of describing the amplifier 101-1 is basically the same, Figure 7 The amplifier 101-2 is capable of reducing the peak current by reducing the amount of bias current using the control signal CTR before the power-up period (i.e., before the level of the external voltage VDD stabilizes to the set level), and is capable of substantially maintaining the internal voltage VDDI at the normal level by increasing the amount of bias current after the level of the external voltage VDD stabilizes to the set level.

[0146] Figure 8 is a diagram showing a configuration of yet another embodiment 101-3 of the amplifier. Figure 4

[0147] Referring to Figure 8 , the amplifier 101-3 can include a plurality of stages, for example, a comparator 141 as a first stage and a current mirror 142 as a second stage.

[0148] The comparator 141 can compare the reference voltage VREF and the feedback voltage VFB according to the bias voltage VBIAS and the control signal CTR, and output a comparison result.

[0149] The comparator 141 can detect and output a difference between the reference voltage VREF and the feedback voltage VFB according to the bias current.

[0150] The amount of bias current can be determined according to the bias voltage VBIAS.

[0151] The amount of bias current can be forcibly adjusted within a maximum value determined according to the bias voltage VBIAS by means of the control signal CTR.

[0152] The current mirror 142 can generate a drive signal DRV according to the output of the comparator 141.

[0153] The comparator 141 can include a first transistor array 141-1, a second transistor array 141-2, a third transistor 141-3 to a sixth transistor 141-6, and an inverter 141-7.

[0154] The inverter 141-7 can invert and output the control signal CTR.

[0155] The first transistor array 141-1 can include a plurality of transistors having source terminals commonly applied with the ground voltage VSS and gate terminals commonly applied with the bias voltage VBIAS.

[0156] ​The second transistor array 141-2 can include a plurality of transistors having source terminals electrically connected to drain terminals of other transistors of the first transistor array 141-1, except for one transistor 141-1n among the transistors of the first transistor array 141-1, respectively, and gate terminals to which an output signal of the common input inverter 141-7 is input.

[0157] The plurality of transistors of the first transistor array 141-1 and the second transistor array 141-2 can be configured as NMOS transistors.

[0158] The third transistor 141-3 can have a source terminal electrically connected to the first transistor array 141-1 and the second transistor array 141-2, and a gate terminal to which a reference voltage VREF is applied.

[0159] The source terminal of the third transistor 141-3 can be electrically connected to the drain terminal of the one transistor 141-1n among the plurality of transistors of the first transistor array 141-1 and the drain terminals of the transistors of the second transistor array 141-2, and the gate terminal of the third transistor 141-3 can receive the reference voltage VREF.

[0160] The fourth transistor 141-4 can have a source terminal to which an external voltage VDD is applied, and a drain terminal electrically connected to its own gate terminal and the drain terminal of the third transistor 141-3.

[0161] The fifth transistor 141-5 can have a source terminal electrically connected to the first transistor array 141-1 and the second transistor array 141-2, and a gate terminal to which a feedback voltage VFB is applied.

[0162] The source terminal of the fifth transistor 141-5 can be electrically connected to the drain terminal of the one transistor 141-1n among the plurality of transistors of the first transistor array 141-1 and the drain terminals of the transistors of the second transistor array 141-2, and the gate terminal of the fifth transistor 141-5 can receive the feedback voltage VFB.

[0163] The sixth transistor 141-6 can have a source terminal to which an external voltage VDD is applied, and a drain terminal electrically connected to its own gate terminal and the drain terminal of the fifth transistor 141-5.

[0164] The third transistor 141-3 and the fifth transistor 141-5 can be configured as NMOS transistors.

[0165] The fourth transistor 141-4 and the sixth transistor 141-6 can be configured as PMOS transistors.

[0166] The gate width of each of the plurality of transistors of the first transistor array 141-1 and the plurality of transistors of the second transistor array 141-2 can be narrower than the gate width of each of the third transistor 141-3 to the sixth transistor 141-6.

[0167] For example, when the gate width of each of the third transistor 141-3 to the sixth transistor 141-6 is "N", the gate width of each of the plurality of transistors of the first transistor array 141-1 can be "1 / N".

[0168] The gate width of each of the plurality of transistors of the second transistor array 141-2 can also be "1 / N".

[0169] The sum of the current driving forces of both the first transistor array 141-1 and the second transistor array 141-2 can be substantially the same as the sum of the current driving forces of each of the third transistor 141-3 to the sixth transistor 141-6.

[0170] The current mirror 142 can include a first transistor 142-1 to a fourth transistor 142-4.

[0171] The first transistor 142-1 can have a source terminal to which an external voltage VDD is applied, and a gate terminal electrically connected to the drain terminal of the fourth transistor 141-4 of the comparator 141.

[0172] The second transistor 142-2 can have a source terminal to which a ground voltage VSS is applied, a drain terminal electrically connected to the drain terminal of the first transistor 142-1, and a gate terminal electrically connected to the drain terminal thereof.

[0173] The third transistor 142-3 can have a source terminal to which an external voltage VDD is applied, and a gate terminal electrically connected to the drain terminal of the sixth transistor 141-6 of the comparator 141.

[0174] The fourth transistor 142-4 can have a source terminal to which a ground voltage VSS is applied, a drain terminal electrically connected to the drain terminal of the third transistor 142-3, and a gate terminal electrically connected to the gate terminal of the second transistor 142-2.

[0175] The first transistor 142-1 and the third transistor 142-3 can be configured as PMOS transistors.

[0176] The second transistor 142-2 and the fourth transistor 142-4 can be configured as NMOS transistors.

[0177] The amplifier 101-1 of Equation 1 Figure 5 compared to the amplifier 101-1 of Equation 1, Figure 8The amplifier 101-3 has essentially the same number of stages, but differs in that the input terminals for receiving the reference voltage VREF and the feedback voltage VFB are configured with NMOS transistors 141-3 and 141-5 instead of PMOS transistors.

[0178] With reference Figure 5 and Figure 6 The description of amplifier 101-1 is basically the same. Figure 8 The amplifier 101-3 can reduce the peak current by reducing the bias current through the control signal CTR before the power-on period (i.e. before the external voltage VDD level stabilizes to the set level), and can maintain the internal voltage VDDI at a normal level by increasing the bias current after the external voltage VDD level stabilizes to the set level.

[0179] This implementation may share a common feature: the bias current is adjusted according to the control signal CTR to reduce the peak current during the power-on period, and the internal voltage VDDI is basically maintained at a normal level after power-on.

[0180] This implementation method may include the following embodiments: Figure 5 As shown, the amplifier is configured as a first stage and a second stage, and the input terminals for receiving the reference voltage VREF and the feedback voltage VFB are configured as PMOS transistors; as Figure 7 As shown, the amplifier is configured as a single stage; as Figure 8 As shown, the amplifier is configured as a first stage and a second stage, and the input terminals for receiving the reference voltage VREF and the feedback voltage VFB are configured as NMOS transistors, etc.

[0181] Therefore, selective application is possible based on the characteristics of the implementation method and the characteristics of the semiconductor device used in the implementation method.

[0182] Those skilled in the art to which this disclosure pertains will understand that this disclosure may be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of this disclosure is defined by the claims provided below, rather than by a detailed description, and it should be understood that the meaning and scope of the claims, as well as all variations or modifications derived from their equivalents, are included within the scope of this disclosure.

[0183] Cross-reference of related applications

[0184] This application claims priority to Korean Application No. 10-2020-0088634, filed on July 17, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. An amplifier comprising: a first stage configured to receive a bias voltage and a control signal, detect a difference between a reference voltage and a feedback voltage according to the control signal and a bias current, and output the difference, wherein the control signal is increased from a first level until an external voltage becomes equal to or greater than a set level, and when the external voltage becomes equal to or greater than the set level, the control signal transitions to a second level, and wherein an amount of the bias current is maintained according to the bias voltage until the control signal has the second level, and when the control signal has the second level, the amount of the bias current is forcibly increased.

2. The amplifier of claim 1, wherein, The control signal is increased during a power-up process of a semiconductor device.

3. The amplifier of claim 1, wherein, The first stage includes: a first transistor array commonly applied with an external voltage and having gate terminals commonly applied with a bias voltage; a second transistor array electrically connected with the first transistor array and having gate terminals commonly input with the control signal; a third transistor electrically connected with the first transistor array and the second transistor array and configured to receive the reference voltage; a fourth transistor electrically connected between the third transistor and a ground voltage terminal; a fifth transistor electrically connected with the first transistor array and the second transistor array and configured to receive the feedback voltage; and a sixth transistor electrically connected between the fifth transistor and the ground voltage terminal.

4. The amplifier of claim 3, wherein, The first transistor array includes a plurality of transistors, all but one of which are respectively electrically connected with a plurality of transistors of the second transistor array.

5. The amplifier of claim 3, wherein, The third transistor is commonly electrically connected with one of a plurality of transistors of the first transistor array and a plurality of transistors of the second transistor array.

6. The amplifier of claim 3, wherein, The plurality of transistors of the first transistor array and the plurality of transistors of the second transistor array are configured to have a gate width narrower than a gate width of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

7. The amplifier of claim 3, wherein, The first stage is configured to make a sum of current driving forces of the first transistor array and the second transistor array equal to a current driving force of each of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

8. The amplifier of claim 1, wherein, The amount of the bias current is forcibly adjusted within a maximum value determined according to the bias voltage by means of the control signal.

9. A voltage generation circuit comprising: an amplifier configured to be input with a bias voltage and a control signal, detect a difference between a reference voltage and a feedback voltage according to the control signal and a bias current, and configured to generate a driving signal; and a driver configured to generate an internal voltage by driving an external voltage according to the driving signal, ​ wherein the control signal increases from a first level until the external voltage becomes equal to or greater than a set level, and when the external voltage becomes equal to or greater than the set level, the control signal transitions to a second level, and wherein an amount of the bias current is maintained according to the bias voltage until the control signal has the second level, and when the control signal has the second level, the amount of the bias current is forcibly increased.

10. The voltage generating circuit according to claim 9, wherein, The control signal increases during a power-up process of a semiconductor device. 11.The voltage generation circuit of claim 9, further comprising: a distributed resistor configured to generate the feedback voltage by distributing the internal voltage; and a capacitor electrically connected in parallel with the distributed resistor between a terminal outputting the internal voltage and a ground voltage terminal.

12. The voltage generating circuit of claim 9, wherein, The amplifier includes: a comparator configured to detect and output a difference between the reference voltage and the feedback voltage according to the bias current; and a current mirror configured to generate the drive signal according to the output of the comparator.

13. The voltage generating circuit of claim 12, wherein, The comparator includes: a first transistor array commonly applied with the external voltage and having gate terminals commonly applied with a bias voltage; a second transistor array electrically connected with the first transistor array and having gate terminals commonly inputted with the control signal; a third transistor electrically connected with the first transistor array and the second transistor array and configured to receive the reference voltage; a fourth transistor electrically connected between the third transistor and a ground voltage terminal; a fifth transistor electrically connected with the first transistor array and the second transistor array and configured to receive the feedback voltage; and a sixth transistor electrically connected between the fifth transistor and the ground voltage terminal.

14. The voltage generating circuit of claim 13, wherein, The first transistor array includes a plurality of transistors, among which all but one are electrically connected with a plurality of transistors of the second transistor array, respectively.

15. The voltage generating circuit of claim 13, wherein, The third transistor is commonly electrically connected with one of the plurality of transistors of the first transistor array and the plurality of transistors of the second transistor array.

16. The voltage generating circuit of claim 13, wherein, The plurality of transistors of the first transistor array and the plurality of transistors of the second transistor array are configured to have a gate width narrower than that of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

17. The voltage generating circuit of claim 13, wherein, The comparator is configured to make a sum of current driving forces of the first transistor array and the second transistor array equal to a current driving force of each of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

18. The voltage generating circuit of claim 12, wherein, The current mirror includes: a first transistor configured to receive the external voltage; a second transistor electrically connected between the first transistor and a ground voltage terminal; a third transistor configured to receive the external voltage and having a gate terminal electrically connected with the first transistor; and a fourth transistor electrically connected between the third transistor and the ground voltage terminal; wherein the drive signal is generated at a node to which the third transistor and the fourth transistor are electrically connected.

19. The voltage generating circuit of claim 9, wherein, the amount of the bias current is forcibly adjusted within a maximum value determined in accordance with the bias voltage by means of the control signal.

20. A voltage generation circuit comprising: a first transistor array to which an external voltage is commonly applied and having gate terminals to which a bias voltage is commonly applied; a second transistor array electrically connected with the first transistor array and having gate terminals to which a control signal is commonly input; a third transistor electrically connected with the first transistor array and the second transistor array and configured to receive a reference voltage; a fourth transistor electrically connected between the third transistor and a ground voltage terminal; a fifth transistor electrically connected with the first transistor array and the second transistor array and configured to receive a feedback voltage; a sixth transistor electrically connected between the fifth transistor and the ground voltage terminal and configured to generate a drive signal; a driver configured to generate an internal voltage by driving the external voltage in accordance with the drive signal; and a distributed resistor configured to generate the feedback voltage by distributing the internal voltage, wherein an amount of bias current flowing through the first transistor array and the second transistor array in accordance with the bias voltage is forcibly adjusted in accordance with the control signal. The control signal is maintained at a first level in accordance with a level of the external voltage during a power-up process of a semiconductor device, and the control signal transitions to a second level when the level of the external voltage becomes equal to or greater than a set level.

21. The voltage generating circuit of claim 20, wherein, The first transistor array includes a plurality of transistors, all but one of which are electrically connected with a plurality of transistors of the second transistor array, respectively.

22. The voltage generating circuit of claim 20, wherein, The third transistor is commonly electrically connected with one of the plurality of transistors of the first transistor array and the plurality of transistors of the second transistor array.

23. The voltage generating circuit of claim 20, wherein, The plurality of transistors of the first transistor array and the plurality of transistors of the second transistor array are configured to have a gate width narrower than that of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

24. The voltage generating circuit of claim 20, wherein, The voltage generation circuit is configured such that a sum of current driving forces of the first transistor array and the second transistor array is equal to a current driving force of each of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

25. The voltage generating circuit of claim 20, wherein, The amount of the bias current is forcibly adjusted within a maximum value determined in accordance with the bias voltage by means of the control signal.

26. The voltage generating circuit of claim 20, wherein, ​

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