Processing device and electronic device having the processing device

Abstract

A processing device and an electronic device having the same are provided. The processing device includes a plurality of bit cells, each of the plurality of bit cells including a variable resistor layer including a plurality of active variable resistors and a plurality of passive variable resistors, an active layer including a plurality of switches configured to control any one of a voltage to be applied between ends of each of the plurality of active variable resistors and a current flowing to each of the plurality of active variable resistors, and a plurality of metal layers including lines electrically connecting the plurality of active variable resistors to the plurality of switches, wherein at least one of the plurality of bit cells includes a via penetrating the variable resistor layer and connecting at least one of the plurality of switches to at least one of the plurality of active variable resistors.

Description

[0001] This application is a divisional application of patent application No. 202110447281.5, filed on April 25, 2021, entitled "Processing Apparatus and Electronic Device Having Processing Apparatus". Technical Field

[0002] The following description relates to a processing device and an electronic device having a processing device. Background Technology

[0003] Neural network devices can perform multiplicative summation (MAC) operations involving repeated multiplication and addition. A neural network can repeatedly perform a MAC operation at a specific node, multiplying the value of a previous layer's node by the weights mapped to that node and summing the results, and can also perform operations that apply activation functions to the results of the MAC operation. For this purpose, memory access operations that load appropriate inputs and weights at desired or predetermined time points can also be performed. However, using other hardware architectures instead of well-known digital computers may not be able to efficiently perform such neural network operations (such as MAC operations). Summary of the Invention

[0004] The present invention is provided in a brief form to introduce the choice of concepts further described in the following detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0005] In one general aspect, a processing apparatus includes: a plurality of bit cells, each of the plurality of bit cells including: a variable resistor layer including a plurality of active variable resistors and a plurality of passive variable resistors; an active layer including: a plurality of switches configured to control any one of a voltage to be applied between the ends of each of the plurality of active variable resistors and a current flowing to each of the plurality of active variable resistors; and a plurality of metal layers including lines electrically connecting the plurality of active variable resistors to the plurality of switches, wherein at least one of the plurality of bit cells includes a via penetrating the variable resistor layer and connecting at least one of the plurality of switches to at least one of the plurality of active variable resistors.

[0006] The arrangement of vias, active variable resistors, and passive variable resistors of at least one of the plurality of bit cells may be symmetrical about the boundary between adjacent bit cells.

[0007] Each of the plurality of bit units may include a via.

[0008] The plurality of bit cells may include bit cells connected in series, and the bit cells connected in series may include a via for every two adjacent bit cells.

[0009] The plurality of bit units may include 64 or more bit units connected in series.

[0010] The plurality of bit cells can form a bit cell array comprising 64 or more bit cell lines, and each bit cell line may include bit cells connected in series among the plurality of bit cells.

[0011] At least one of the plurality of switches in each of the plurality of bit units may include a common source and two electrically connected drains.

[0012] The processing device may be an in-memory processing unit.

[0013] An electronic device may include: a processing device, wherein the processing device is a neural network device; and a processor configured to control the functions of the neural network device.

[0014] In another general aspect, a processing apparatus includes: a variable resistor layer including a plurality of active variable resistors; an active layer including: a plurality of switches configured to control any one of a voltage to be applied between the ends of each of the plurality of active variable resistors and a current flowing to each of the plurality of active variable resistors; and a plurality of metal layers including lines electrically connecting the plurality of active variable resistors to the plurality of switches, wherein the variable resistor layer may include at least one via penetrating the variable resistor layer and connecting at least one of the plurality of switches to at least one of the plurality of active variable resistors.

[0015] The plurality of metal layers may include: a metal layer stacked on top of the variable resistor layer and including a line connecting the upper end of a via to the upper end of at least one of the plurality of active variable resistors.

[0016] The variable resistor layer may also include a plurality of passive variable resistors not electrically connected to the plurality of switches, and the minimum distance between the at least one via and the plurality of active variable resistors may be greater than the minimum distance between the at least one via and the plurality of passive variable resistors.

[0017] The variable resistor layer may include multiple vias, and the minimum distance between the multiple vias may be smaller than the minimum distance between the at least one via and the multiple passive variable resistors.

[0018] The minimum distance between the at least one via and the plurality of passive variable resistors may be greater than both the minimum distance between the plurality of passive variable resistors and the minimum distance between the plurality of passive variable resistors and the plurality of active variable resistors.

[0019] The variable resistor layer may include multiple vias, and the minimum distance between the multiple vias may be substantially within 0.10 μm to 0.40 μm.

[0020] The minimum distance between the at least one via and the plurality of active variable resistors can be substantially within 0.50 μm to 1.20 μm.

[0021] The minimum distance between the at least one via and the plurality of passive variable resistors can be substantially within 0.30 μm to 0.60 μm.

[0022] Each of the plurality of active variable resistors may be a magnetic tunnel junction (MTJ) device.

[0023] An electronic device may include: the processing means, wherein the processing means is a neural network device; and a processor configured to control the functions of the neural network device.

[0024] In another general aspect, an electronic device includes: a neural network device; and a processor configured to control the function of the neural network device, wherein the neural network device may include a plurality of bit units, each of the plurality of bit units including: a variable resistor layer including a plurality of active variable resistors and a plurality of passive variable resistors; an active layer including: a plurality of switches configured to control any one of a voltage to be applied to an end of each of the plurality of active variable resistors and a current flowing to each of the plurality of active variable resistors; and a plurality of metal layers including lines electrically connecting the plurality of active variable resistors to the plurality of switches, and wherein at least one of the plurality of bit units may include a via penetrating the variable resistor layer and connecting at least one of the plurality of switches to at least one of the plurality of active variable resistors.

[0025] The arrangement of vias, active variable resistors, and passive variable resistors of at least one of the plurality of bit cells may be symmetrical about the boundary between adjacent bit cells.

[0026] Each of the plurality of bit units may include: two active variable resistors connected in parallel with each other from the plurality of active variable resistors, and two switches from the plurality of switches respectively connected in series with the plurality of active variable resistors.

[0027] Each of the plurality of bit units may include a via.

[0028] The plurality of bit cells may include bit cells connected in series, and the bit cells connected in series may include a via for every two adjacent bit cells.

[0029] The plurality of bit units may include 64 or more bit units connected in series.

[0030] The plurality of bit cells can form a bit cell array comprising 64 or more bit cell lines, and each bit cell line may include bit cells connected in series among the plurality of bit cells.

[0031] At least one of the plurality of switches in each of the plurality of bit units may include a common source and two electrically connected drains.

[0032] In another general aspect, an electronic device includes: a neural network device; and a processor configured to control the function of the neural network device, wherein the neural network device may include: a variable resistor layer including a plurality of active variable resistors and a plurality of passive variable resistors; an active layer including: a plurality of switches configured to control any one of a voltage to be applied across each of the plurality of active variable resistors and a current flowing to each of the plurality of active variable resistors; and a plurality of metal layers including lines electrically connecting the plurality of active variable resistors to the plurality of switches, and the variable resistor layer may include at least one via penetrating the variable resistor layer and connecting at least one of the plurality of switches to at least one of the plurality of active variable resistors.

[0033] The plurality of metal layers may include metal layers stacked on top of the variable resistor layers and including lines connecting the upper end of a via to the upper end of at least one of the plurality of active variable resistors.

[0034] The variable resistor layer may also include a plurality of passive variable resistors not electrically connected to the plurality of switches, and the minimum distance between the at least one via and the plurality of active variable resistors may be greater than the minimum distance between the at least one via and the plurality of passive variable resistors.

[0035] The variable resistor layer may include multiple vias, and the minimum distance between the multiple vias may be smaller than the minimum distance between the at least one via and the multiple passive variable resistors.

[0036] The minimum distance between the at least one via and the plurality of passive variable resistors may be greater than both the minimum distance between the plurality of passive variable resistors and the minimum distance between the plurality of passive variable resistors and the plurality of active variable resistors.

[0037] The variable resistor layer may include multiple vias, and the minimum distance between the multiple vias may be substantially within 0.10 μm to 0.40 μm.

[0038] The minimum distance between the at least one via and the plurality of active variable resistors can be substantially within 0.50 μm to 1.20 μm.

[0039] The minimum distance between the at least one via and the plurality of passive variable resistors can be substantially within 0.30 μm to 0.60 μm.

[0040] Each of the plurality of active variable resistors may be a magnetic tunnel junction (MTJ) device.

[0041] In another general aspect, a processing apparatus includes: a plurality of bit units, wherein at least one of the plurality of bit units may include: a plurality of active variable resistors and a plurality of passive variable resistors; a plurality of switches configured to control either a voltage to be applied to the plurality of active variable resistors and a current flowing to the plurality of active variable resistors; and a via connecting at least one of the plurality of switches to at least one of the plurality of active variable resistors, wherein the distance between the via and the plurality of active variable resistors is greater than the distance between the via and the plurality of passive variable resistors.

[0042] The plurality of bit cells may include an array of active and passive variable resistors, the array including at least one active and passive variable resistor of the plurality of bit cells, the active variable resistor of the array being disposed at the center of the array and the passive variable resistor of the array surrounding the active variable resistor of the array.

[0043] The array can be symmetrical about the boundaries between adjacent bit cells of the plurality of bit cells.

[0044] At least two of the plurality of bit cells may belong to one bit cell line, and at least two other bit cells of the plurality of bit cells may belong to another bit cell line, and the bit cell line may be configured to perform operations of nodes of a layer of a neural network, and the other bit cell line may be configured to perform operations of another node of a layer of a neural network.

[0045] Other features and aspects will become clear from the following detailed description, drawings, and claims. Attached Figure Description

[0046] Figure 1 A neural network node model is shown according to one or more embodiments;

[0047] Figure 2 This is an example illustrating a neural network;

[0048] Figure 3An example of a circuit diagram showing a bit cell used in a processing device;

[0049] Figure 4A and Figure 4B An example of the structure and operation of a variable resistor applied to a bit cell is shown;

[0050] Figure 5A An example of a neural network is shown;

[0051] Figure 5B An example of a circuit diagram showing a processing device configured to perform neural network operations;

[0052] Figure 6 An example of a circuit diagram showing a processing device configured to perform neural network operations;

[0053] Figure 7 An example showing the connection relationship between a variable resistor and a switch;

[0054] Figure 8 An example of a horizontal cross-sectional view illustrating a variable resistor layer is shown;

[0055] Figure 9A An example of a vertical cross-sectional view of a bit cell is shown;

[0056] Figure 9B An example of a vertical cross-sectional view of a bit cell is shown;

[0057] Figure 10 An example showing a plan view of the active layer of a processing device;

[0058] Figure 11 An example showing a plan view of the seventh metal layer of the processing apparatus;

[0059] Figure 12 An example circuit diagram of a processing device with a switch and variable resistor connection structure that differs from that of other processing devices is shown.

[0060] Figure 13 An example showing the connection relationship between a variable resistor and a switch;

[0061] Figure 14 Examples of processing devices are shown; and

[0062] Figure 15 An example of an electronic device is shown. Detailed Implementation

[0063] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but may be changed as will become clear upon understanding this disclosure, except for operations that must occur in a specific order. Furthermore, for clarity and brevity, descriptions of features known in the art upon understanding this disclosure may be omitted.

[0064] Referring now to embodiments in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, one or more embodiments may have different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to illustrate various aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” following a column of elements modify the entire column of elements, rather than a single element within the column.

[0065] The terminology used herein is for the purpose of describing particular examples only and is not intended to limit disclosure. Unless the context clearly indicates otherwise, the singular form as used herein is intended to include the plural form as well. As used herein, the term “and / or” includes any one and any combination of any two or more of the associated listed items. As used herein, the terms “comprising,” “including,” and “having” indicate the presence of the stated features, quantities, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, elements, components, and / or combinations thereof. The use of the term “may” (e.g., what an example or embodiment may include or implement) with respect to an example or embodiment indicates the presence of at least one example or embodiment that includes or implements such a feature, and all examples are not limited thereto.

[0066] Furthermore, terms such as A, B, (a), (b), etc., may be used herein to describe components. Each of these terms is not intended to define the nature, order, or sequence of the corresponding component, but only to distinguish the corresponding component from one or more other components. Although the terms "first" or "second" are used herein to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teaching of the examples described herein, the first element, first component, first region, first layer, or first part referred to in the examples may also be referred to as a second element, second component, second region, second layer, or second part.

[0067] Throughout the specification, when an element (such as a layer, region, or substrate) is described as being "on" another element, "connected to," or "bonded to" another element, the element may be directly "on" said other element, "connected to," or "bonded to" said other element, or there may be one or more other elements in between. Conversely, when an element is described as being "directly on" another element, "directly connected to," or "directly bonded to" another element, there may be no other elements in between. Similarly, expressions such as "between" and "immediately between," and "adjacent" and "next to" may be interpreted as described above.

[0068] The embodiments described below relate to the technical field of processing devices (e.g., neuromorphic processors or neural processors), and detailed descriptions of well-known matters may be omitted.

[0069] According to embodiments, unlike general-purpose digital computers that exchange information using a common data bus, the processing apparatus of one or more embodiments may be provided with analog circuitry for processing multiplication and addition operations. In other words, the processing apparatus may perform in-memory processing or internal processing. Therefore, the processing apparatus may be referred to by various terms (such as in-memory processing apparatus, in-memory processor (PIM), and in-memory function (FIM)).

[0070] Figure 1 A neural network node model according to one or more embodiments is shown.

[0071] The neural network node model 11 may include the following computations as examples of neuromorphic computation: multiplication computations that multiply information from multiple neurons or nodes by synaptic weights; addition computations ∑ of values ​​ω0x0, ω1x1, ω2x2 obtained by multiplying by synaptic weights; and computations that apply a characteristic function b and an activation function f to the results of the addition computations. The neuromorphic computation results may be provided by neuromorphic computation. Here, values ​​such as x0, x1, x2, etc., correspond to axonal values, and values ​​such as ω0, ω1, ω2, etc., correspond to synaptic weights. Although the nodes, values, and weights of the neural network node model 11 may be referred to as “neurons,” “axonal values,” and “synaptic weights,” respectively, such designations are not intended to assign any relation to how the neural network architecture computationally maps or thereby intuitively identifies information in relation to how human neurons operate. That is, the terms are merely technical terms used to describe the nodes, values, and weights of the hardware implementation of the neural network node model 11.

[0072] Figure 2 An example of a neural network (e.g., neural network 20) ​​is shown.

[0073] Reference Figure 2 Neural network 20 is an example of a neural network implementing the neural network node model described above, and may correspond to a deep neural network (DNN). Although neural network 20 is shown as including two hidden layers (e.g., hidden layer 1 and hidden layer 2) for ease of illustration, neural network 20 may include various numbers of hidden layers (e.g., three or more hidden layers). Furthermore, although Figure 2 The neural network 20 is shown to include an input layer 21 for receiving input data, but the input data can be directly fed into the hidden layer.

[0074] In neural network 20, nodes in layers other than the output layer can be connected to nodes in the next layer via links used to send output signals. Values ​​obtained by multiplying the node values ​​of nodes included in the previous layer by the weights assigned to the links can be input to a node via the links. The node value pairs of the previous layer correspond to axon values, and the weights correspond to synaptic weights. Each weight can be referred to as a parameter of neural network 20. Activation functions can include sigmoid, hyperbolic tangent, and rectified linear units (ReLU), and nonlinearity can be formed in neural network 20 through activation functions.

[0075] For example, the output of any node 22 in the neural network 20 can be represented as shown in Equation 1 below.

[0076] Equation 1:

[0077]

[0078] Equation 1 can represent the output value y of the i-th node 22 in any layer for m input values. i In equation 1, x j w can represent the output value of the j-th node in the previous layer. j,i This can represent the weight applied to the connection between the j-th node in the previous layer and the i-th node in the current layer. Furthermore, f() can represent the activation function. As shown in Equation 1, the input value x... j and weight w j,i The sum of the products can be used for the activation function. In other words, at the desired or defined time point, the appropriate input value x is applied... j and weight w j,i The multiplicative accumulation (MAC) operation, which involves multiplication and addition, can be repeated. Besides the uses described above, there are various application areas where MAC operations are used. Therefore, processing devices capable of handling MAC operations in the analog circuit domain can be used.

[0079] Figure 3 An example circuit diagram illustrating an embodiment of a bit cell BC used in a processing device. Reference will now be made to... Figure 3 Describe the structure and operation of the bit cell BC.

[0080] Figure 3 The bit unit BC may have a circuit structure included in a processing device for implementing a neuromorphic processor, neural processor, etc. The processing device may be, for example, an in-memory processing unit that stores data in a memory (resistive memory device, etc.) and uses the stored data when necessary for operation.

[0081] The bit unit BC may include a pair of variable resistors R connected in parallel with each other. a and R b , respectively connected in series to the variable resistor R a and R b A pair of switches S a and S b and respectively connected to the first data line BDL a Second data line BDL b Switch S BDLa and S BDLb .However, Figure 3 The circuit structure of the bit cell BC is only an example, and the bit cell BC can be implemented by using equivalent circuits with different circuit devices.

[0082] A pair of variable resistors R a and R b It can be a resistor that can be set using different resistance values, and the variable resistor R a and R bThe resistance value can be determined by the weight applied to the bit unit BC. For example, the variable resistor R a and R b Each of them can have one of two resistance values ​​(e.g., 20Ω or 5Ω). For example, when the weight that can be applied to the bit cell BC is -1 or 1, and when the weight "1" is applied to the bit cell BC, the first variable resistor R a It can be set to 20Ω and the second variable resistor R b It can be set to 5Ω. On the other hand, when the weight "-1" is applied to the bit cell BC, the first variable resistor R... a It can be set to 5Ω and the second variable resistor R b It can be set to 20Ω. In other words, the variable resistor R a and R b The resistance values ​​can be set complementaryly, allowing the variable resistor R to... a and R b They have different resistance values.

[0083] In detail, the variable resistor R a and R b It can be a resistive memory device. A resistive memory device can switch between different resistance states depending on the voltage or current applied to its terminals, and therefore can have multiple resistance states. The resistive memory device can have a single-layer or multi-layer structure, including, for example, transition metal oxides, metal oxides (such as perovskite materials), phase change materials (such as chalcogenide materials), ferroelectric materials, ferromagnetic materials, etc. Furthermore, the operation of changing a resistive memory device from a high-resistance state to a low-resistance state is called a set operation, and the operation of changing a resistive memory device from a low-resistance state to a high-resistance state is called a reset operation.

[0084] The changes in the variable resistor R will now be described. a and R b The method for determining the resistance value. First, one end of the variable resistor to be changed can be connected to the first data line BDL. a Furthermore, the other end of the variable resistor can be connected to the second data line BDL. b When the first variable resistor R is shown and described a When, the first variable resistor R a one end ( Figure 3 The variable resistor R in a The upper end) can be switched via the bit data line S above. BDLb Connect to the second data line BDL b And the first variable resistor R a The other end ( Figure 3The variable resistor R in a The lower end) can be controlled by the first switch S a And the bit data line switch S below BDLa Connect to the first data line BDL a .

[0085] In one example, the bit data line switch S above BDLb It may not be included Figure 3 In the bit cell BC. For example, the bit data line switch S above. BDLb It can be included in the context of Figure 3 The switch in the adjacent bit cell (not shown) of bit cell BC, or an independent switch not included in any bit cell.

[0086] When the first variable resistor R a Connect to bit data line BDL a and BDL b At that time, it can be done via the bit data line BDL a and BDL b Control the first variable resistor R a The voltage across the two ends or the voltage across the first variable resistor R a The current flowing in is directed to the first variable resistor R a Perform a set or reset operation. However, when the second switch S at both ends of bit unit BC... b and bit data line switch S BDLa and S BDLb When closed, the second variable resistor R b Can be connected to bit data line BDL a and BDL b Therefore, it is possible to target the second variable resistor R. b Perform a set or reset operation.

[0087] Applied to change the variable resistor R a and R b The voltage and / or current at the resistance value can be compared to the reading of the variable resistor R. a and R b The voltage and / or current applied to the resistance value are much larger. In other words, the voltage and / or current applied to read the variable resistor R is much larger. a and R b The voltage and / or current that does not change the resistance value of the variable resistor R a and R b The resistance value (or possibly for the variable resistor R) a and R b The resistance value has a negligible effect.

[0088] Connected in series to the variable resistor R aand R b A pair of switches S a and S b The on / off operation can be performed based on what input is applied to the bit unit BC. Switch S a and S b They can operate complementaryly, such that when one switch is closed, the other switch is open. For example, when the input to the position-adjustable unit BC is "-1" or "1", it can be designed that when the input "1" is applied, the first switch S... a Close and the second switch S b Disconnect, and when the input "-1" is applied, the first switch S a Disconnect and the second switch S b closure.

[0089] Based on the above operating methods of the variable resistor and switch, from Figure 3 The resistance value measured across the bit cell BC can vary depending on the weights applied to the bit cell BC and the input. For example, the relationship between the weights, inputs, and resistance values ​​across the bit cell BC can be summarized in Table 1 below.

[0090] Table 1:

[0091]

[0092]

[0093] Referring to Table 1, the resistance of bit cell BC is 20Ω when the product of the input and weights is 1, and 5Ω when the product of the input and weights is -1. In other words, the product of the input and weights applied to bit cell BC can be determined when the resistance of bit cell BC is measured or when the voltage drop across bit cell BC due to a constant current is measured. A processing device (e.g., a neuromorphic processor) that obtains the sum of the products of the input and weights can be implemented by utilizing the characteristics of bit cell BC.

[0094] Figure 4A and Figure 4B The application unit is shown (e.g., Figure 3 An example of the structure and operation of a variable resistor (with a bit unit BC). Variable resistor R a and R b It can be implemented as a magnetic tunnel junction (MTJ) device, and each can have a resistance value that varies according to the magnitude and direction of the current (or voltage) and exhibit non-volatile characteristics that maintain the resistance value even when the input current (or voltage) is cut off.

[0095] Reference Figure 4A and Figure 4BThe MTJ device may include a pinned layer L3, a free layer L1, and a tunnel layer L2 between them. The magnetization direction of the pinned layer L3 is fixed, and the magnetization direction of the free layer L1 may be the same as or different from the magnetization direction of the pinned layer L3 depending on the conditions.

[0096] Figure 4A The magnetization directions of the free layer L1 and the pinned layer L3 in the MTJ device are shown to be parallel to each other. When the magnetization directions are parallel as shown above, the MTJ device can have a low resistance value (e.g., a resistance value of 5 Ω). Figure 4B The diagram shows that the magnetization directions of the free layer L1 and the pinned layer L3 in the MTJ device are antiparallel to each other. When the magnetization directions are antiparallel as shown above, the MTJ device can have a high resistance value (e.g., a resistance value of 20 Ω). Therefore, the resistance value of the variable resistor can be changed by changing the magnetization direction of the free layer L1.

[0097] The magnetization direction of the free layer L1 can be changed by electromagnetic factors disposed inside and / or outside the resistive memory cell. The free layer L1 may comprise a material with a changeable magnetization direction (e.g., a ferromagnetic material). The free layer L1 may comprise, for example, CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, Y3Fe5O 12 and / or combinations thereof.

[0098] The tunnel layer L2 may have a thickness thinner than the spin diffusion distance and may include non-magnetic materials (e.g., oxides of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium-zinc (MgZn), and magnesium-boron (MgB), titanium (Ti), vanadium (V), and / or combinations thereof).

[0099] The pinning layer L3 may have a magnetization direction fixed by the antiferromagnetic layer. The pinning layer L3 may comprise a ferromagnetic material (e.g., CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, Y3Fe5O). 12 (and / or combinations thereof), and may further include an antiferromagnetic layer and / or a synthetic antiferromagnetic layer for fixing the magnetization direction. The antiferromagnetic layer may include an antiferromagnetic material (e.g., PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeC). l2 ,FeO,CoC l2 CoO, NiCl2 (NiO, Cr and / or combinations thereof). Synthetic antiferromagnetic layers may include Cu, Ru, Ir and / or combinations thereof.

[0100] Figure 5A An example of a neural network (e.g., a neural network including a first layer with three nodes and a second layer with two nodes) is shown. Figure 5B This illustrates operations configured to perform neural network operations (e.g., configured to perform...). Figure 5A The processing device for the second layer operations of the neural network (e.g., using bit units (e.g., Figure 3 Example of a circuit diagram of a processing device 100 implemented by a bit unit BC.

[0101] Reference Figure 5A In the first node a1 of the second layer L2 (e.g., as in Equation 2 below), the inputs x1, x2, and x3 provided by the nodes of the first layer L1 are respectively coupled with weights w. 11 w 21 and w 31 The three multiplication operations and the MAC operation of summing the multiplication results can be performed. In the second node a2 of the second layer L2 (e.g., as in Equation 3 below), the inputs x1, x2, and x3 provided by the nodes of the first layer L1 are performed with weights w. 12 w 22 and w 32 The three multiplication operations and the MAC operation that sums the multiplication results can be executed.

[0102] Equation 2:

[0103] a1=x1·w 11 +x2·w 21 +x3·w 31

[0104] Equation 3:

[0105] a2=x1·w 12 +x2·w 22 +x3·w 32

[0106] Figure 5B The processing device 100 may include a device configured to perform Figure 5A The second layer L2 operation Figure 3 Some bit units BC.

[0107] Figure 5B The processing device 100 includes a first unit line BCL1 and a second unit line BCL2. The first unit line BCL1 includes three bit units BC connected in series with each other. 11 BC12 and BC 13 The second bit cell line BCL2 includes three bit cells BC connected in series with each other. 21 BC 22 and BC 23 In the first unit line BCL1, execution is possible. Figure 5A The operation of Equation 2 at the first node a1. This can be performed in the second unit line BCL2. Figure 5A The operation of equation 3 for the second node a2.

[0108] When a specific value of current I is applied to one of the bit cell lines BCL1 and BCL2, it can be obtained from bit cell BC. 11 BC 12 BC 13 BC 21 BC 22 and BC 23 The sum of the pressure drops that appear in each part is used to derive the values ​​of the applied pressure units BC. 11 BC 12 BC 13 BC 21 BC 22 and BC 23 The sum of the products of the weights and the inputs. For example, the inputs and weights will be described below by showing cases such as Table 2 below.

[0109] Table 2:

[0110] enter weight (first node a1) weight (second node a2) x1 = 1 <![CDATA[w 11 =1]]> <![CDATA[w 12 =-1]]> <![CDATA[x2=1]]> <![CDATA[w 21 =-1]]> <![CDATA[w 22 =-1]]> <![CDATA[x3=-1]]> <![CDATA[w 31 =-1]]> <![CDATA[w 32 =1]]>

[0111] For example, as shown in Table 3 below, a variable resistor R is included in the processing device 100. 11a R 11b R 12a R 12b ..., R 23a and R 23b The resistance value can be set using the weights in Table 2. For example, as shown in Table 4 below, a variable resistor R is connected in series. 11a ... and R 23b Switch S 11a S 11b S 12a S 12b S 23a and S 23b The open and closed states can be set by inputting from Table 2.

[0112] Table 3:

[0113]

[0114] Table 4:

[0115]

[0116] When a current of 1A is supplied to the first unit line BCL1 and the second unit line BCL2 as configured in Tables 3 and 4, a voltage drop may occur when the current flows to the variable resistor whose switch is closed, which is included in the variable resistor in each unit. At this time, when the voltage (e.g., V) is measured from the upper end of the first unit line BCL1 and the second unit line BCL2, a voltage drop may occur. T1 and V T2 When the voltage is measured, it corresponds to the sum of the voltage drops appearing in the bit cell. For example, bit cell BC included in the first bit cell line BCL1. 11 BC 12 and BC 13 The voltage drop that occurs can be shown in Table 5 below, and for example, the bit cell BC included in the second bit cell line BCL2. 21 BC 22 and BC 23 The pressure drop that occurs can be seen in Table 6 below.

[0117] Table 5:

[0118]

[0119] Table 6:

[0120]

[0121] The 45V voltage drop in the first bit cell line BCL1 and the 15V voltage drop in the second bit cell line BCL2 can represent the weights and inputs applied to the bit cells included in bit cell line BCL1 and the MAC operation results applied to the bit cells included in bit cell line BCL2, respectively. For example, the relationship between the voltage drop and the MAC operation results can be shown in Table 7 below.

[0122] Table 7:

[0123] Pressure drop (V) The sum of the products of the input and the weights 15 -3 30 -1 45 1 60 3

[0124] Referring to Table 7, the voltage drop in the first unit line BCL1 is measured to be 45V. Therefore, the sum of the product of the input and the weight applied to the first unit line BCL1 can be "1". The voltage drop in the second unit line BCL2 is measured to be 15V. Therefore, the sum of the product of the input and the weight applied to the second unit line BCL2 can be "-3".

[0125] Despite Figure 5BEach of the middle cell lines BCL1 and BCL2 includes three bit cells, but various numbers of bit cells, equal to or greater than one or more bit cells, may be included in the bit cell lines. For example, a number of bit cells ranging from 64 to 256 may be included in the bit cell lines. In one example, the processing device 100 may include 64 or more bit cells connected in series.

[0126] although Figure 5B The processing device 100 includes only two bit cell lines, but the processing device 100 may include a variety of numbers of bit cell lines (i.e., one or more bit lines). For example, the processing device 100 may include multiple bit cell lines ranging from 64 to 128. In one example, the bit cells of the processing device 100 may form a bit cell array comprising 64 or more bit cell lines.

[0127] The configuration of multiple bit cell lines, each comprising multiple bit cells, can be referred to as a bit cell array.

[0128] Figure 5B The processing device 100 can be an in-memory processing unit that stores values ​​corresponding to weights in a memory device including a variable resistor and performs operations using the stored values. Compared to the Von Neumann architecture where the memory and arithmetic units are separate, the in-memory processing unit provides faster data transfer and reduced power consumption.

[0129] The above has been referred to Figure 5B The embodiments describe a processing apparatus that applies a constant current I to series-connected bit cells and derives the result corresponding to the sum of the products from the voltage drops appearing in the bit cell lines. However, Figure 3 The structure of the bit unit BC can also be applied to different types of processing devices.

[0130] Figure 6 This shows a neural network configured to perform (e.g., Figure 5A An example of a circuit diagram of a processing device (e.g., processing device 200) that performs operations on a neural network. See also... Figure 6 ,and Figure 5B In comparison, capacitor BCL C1 and BCL C2 It can be set at the corresponding lower end of bit cell lines BCL1 and BCL2, and connected in series with the bit cells of bit cell line BCL1 and bit cell line BCL2, respectively. In other words, according to... Figure 6 In one embodiment, after a voltage V is applied to each of the bit cell lines BCL1 and BCL2, the processing device 200 may use a time-to-digital converter (TDC) method, which measures the capacitance BCL... C1and BCL C2 A method for determining the time period during which the voltage of each element rises to a specific value.

[0131] Figures 7 to 15 Instructions for use are shown. Figure 3 An example of the layout of a processing device (e.g., processing device 100 or processing device 200) implemented by a bit cell BC. Reference will also be made below. Figures 7 to 15 An example describing the structure of such a processing device.

[0132] Figure 7 An example of the connection structure between a variable resistor and a switch included in a bit unit within a processing device is shown. (By using...) Figure 5B Taking the first unit line BCL1 as an example, Figure 7 A cross-sectional view of a processing device including an active layer, a variable resistor layer, and a metal layer is shown.

[0133] Reference Figure 7 Including the switch S formed therein 11a S 12a and S 13b The active layer L100, the first metal layers M100 to the sixth metal layers M600, and the variable resistor layer L200 can be stacked sequentially. The positional relationship between the active layer L100 and the variable resistor layer L200 can depend on the fact that the active layer L100 is formed first and the metal lines and variable resistor R... 11a R 12a R 13b The process sequence for manufacturing on the active layer L100.

[0134] The active layer L100 may be included in the layer formed therein. Figure 5B Switch S 11a S 12a S 13b Therefore, the active layer L100 can be a switch S. 11a S 12a S 13b Layers formed on a silicon wafer using transistor fabrication processes, etc. For ease of explanation, Figure 7 The active layer L100 is shown in Figure 5B The first unit line BCL1 includes the switch S 11a S 11b S 12a S 12b S 13a S 13b S1, S 11 S 12 and S 13The switch S exists on the path of the current I flowing in the first unit line BCL1 due to the inputs and weights in Table 2. 11a S 12a and S 13b . Figure 5B The remaining switch S 11b S 12b S 13a S1, S 11 S 12 and S 13 Since it is in the off state, the current I applied to the first unit line BCL1 is not present in the remaining switch S. 11b S 12b S 13a S1, S 11 S 12 and S 13 The flow is in the middle, therefore, the remaining switch S 11b S 12b S 13a S1, S 11 S 12 and S 13 Not in Figure 7 As shown in the image. However, Figure 7 Not shown Figure 5B The remaining switch S 11b S 12b S 13a S1, S 11 S 12 and S 13 It can be formed in the active layer L100 and can be arranged with the switch S. 11a S 12a and S 13b At different positions on the horizontal level. Furthermore, in Figure 5B The second unit line BCL2 includes the switch S 21a S 21b S 22a S 22b S 23a S 23b S2, S 21 S 22 and S 23 It can be arranged similarly to the first unit line BCL1.

[0135] The variable resistor layer L200 may include a variable resistor R 11a R 12a R 13b Equal to the vias V formed in the variable resistor layer L200 11 V 12 and V 13The seventh metal layer M700 can be located above the variable resistor layer L200, and the sixth metal layer M600 can be located below the variable resistor layer L200.

[0136] Variable resistor R 11a R 12a R 13b Variable resistors can be formed vertically in the variable resistor layer L200, such that one end of each variable resistor is connected to the seventh metal layer M700 and the other end is connected to the sixth metal layer M600. In the following text, the vertically formed variable resistor R... 11a R 12a R 13b The corresponding end on the M700 side of the seventh metal layer can be referred to as the upper end of the variable resistor, the variable resistor R. 11a R 12a R 13b The corresponding end on the M600 side of the sixth metal layer can be referred to as the lower end of the variable resistor. Flow through the variable resistor R... 11a R 12a R 13b The current can flow in the direction from the upper end of each variable resistor to the lower end of each variable resistor, or from the lower end to the upper end.

[0137] Figure 7 The variable resistor layer L200 is shown as shown in Figure 5B The first unit line BCL1 includes a variable resistor R. 11a R 11b R 12a R 12b R 13a and R 13b The variable resistor R exists in the path of the current flowing due to the inputs and weights in Table 2. 11a R 12a and R 13b However, although not in Figure 7 As shown, however, the remaining variable resistor R 11b R 12b and R 13a It can also be formed in the variable resistor layer L200, and can be arranged with the variable resistor R. 11a R 12a and R 13b At different positions on the horizontal level.

[0138] Via V 11 V 12 and V 13It can penetrate the variable resistor layer L200 and electrically connect the seventh metal layer M700 to the sixth metal layer M600. The variable resistor (e.g., R) in the variable resistor of the bit cell exists in the path of the current flowing due to the inputs and weights in Table 2. 11a R 12a and R 13b It can be passed through via V 11 V 12 and V 13 They are connected in series, and their example connection structures will be described in more detail later.

[0139] The first metal layer M100 to the seventh metal layer M700 may have wires (such as those for connecting a variable resistor R) formed thereon. 11a R 12a and R 13b Connect to switch S 11a S 12a S 13b The wires, and the wires used to send the on / off signal to switch S 11a S 12a S 13b Layers (such as lines).

[0140] When description Figure 7 The switch S shown in the figure 11a S 12a and S 13b With variable resistor R 11a R 12a and R 13b When connecting the different variable resistors, they can be electrically connected to switch S. 11a and S 12a Each of the two ends. However, in one example, because switch S 13b Can Figure 5B The third unit BC shown is the last (at the bottom of the first unit line BCL1) of the first unit line BCL1. 13 Therefore, different variable resistors will not be electrically connected to switch S. 13b The two ends.

[0141] When showing and describing the second bit unit BC 12 The first switch S 12a When, switch S 12a One end is connected to the second bit unit BC 12 The first variable resistor R 12a Switch S 12a The other end is connected to the third bit unit BC 13 The second variable resistor R 13b For example, switch S12a One end is connected to the variable resistor R 12a At the lower end, switch S 12a The other end is through via V 12 Connected to variable resistor R 13b The upper end. As described above, because the active layer L100 is located below the variable resistor layer L200, the second bit cell BC penetrates the variable resistor layer L200. 12 via V 12 It can be used to switch S 12a Connected to variable resistor R 13b The upper part. (Refer to...) Figure 5B Switch S 12a via the second unit BC 12 via V 12 Connected to variable resistor R 13b The position of the upper end can be used as the second unit BC. 12 With the third unit BC 13 The "A" area connecting them. In other words, via V. 12 It can be used to transfer the second bit unit BC 12 Any switch connected to the third unit BC 13 Any variable resistor. Similarly, the first unit BC 11 via V 11 The first unit BC can be 11 Any switch electrically connected to the second unit BC 12 Any variable resistor. In other words, due to the structure of such a via, all the variable resistors in each bit cell can be connected in series with each other.

[0142] Figure 8 The illustration shows a variable resistor layer (e.g., Figure 7 Example of a horizontal cross-sectional view of the variable resistor layer L200.

[0143] Reference Figure 8 The variable resistor layer L200 may include four bit cell lines, each comprising three bit cells. Figure 5B The first unit line BCL1 and the second unit line BCL2 are shown. (Compared to...) Figure 5B compared to, Figure 8Four unit lines are shown to illustrate the layout of the variable resistors and vias. Besides the first unit line BCL1 and the second unit line BCL2, the four unit lines also include a third unit line BCL3 and a fourth unit line BCL4. Because the first unit line BCL1 and the third unit line BCL3 have the same structure, and the second unit line BCL2 and the fourth unit line BCL4 have the same structure, the variable resistors and vias for the third unit lines BCL3 and the fourth unit line BCL4 are not indicated by reference numerals.

[0144] Reference Figure 8 In addition to variable resistors and vias, each bit cell may also include a passive variable resistor. For example, besides Figure 5B Variable resistor R 11a and R 11b and via V 11 In addition, the first unit BC of the first unit line BCL1 11 It may also include nine passive variable resistors R i .

[0145] With the above-mentioned variable resistor R 11a and R 11b In comparison, the passive variable resistor R i It can be a variable resistor that is not used in the process and can be not electrically connected. Figure 5B Switch S 11a S 11b The variable resistor R used in the process, etc. 11a R 11b These can be referred to as active variable resistors, in contrast to passive variable resistors R. i Distinguish them. Passive variable resistor R i It can be formed to obtain an active variable resistor R with uniform electrical characteristics. 11a R 11b For example, due to the manufacturing process of the variable resistor layer 200 and / or the processing device, the variable resistors formed to be surrounded by other variable resistors (e.g., the variable resistors near the center of the array of variable resistors) can exhibit relatively uniform electrical characteristics compared to the variable resistors formed on the edge of the array. Therefore, only the variable resistors with good reliability (e.g., due to the relatively uniform electrical characteristics) and located in the center can be used in the processing, and the remaining variable resistors can be passive variable resistors that are not used in the processing.

[0146] Now will show and describe including Figure 8 The four bit units BC 11 BC 12 BC 21 and BC22 An example of a variable resistor. Eleven variable resistors can be formed in each bit cell, and four bit cells BC... 11 BC 12 BC 21 and BC 22 It may include a total of 44 variable resistors formed therein. Active variable resistors may be located in bit units (e.g., four bit units BC). 11 BC 12 BC 21 and BC 22 The center of the group is therefore surrounded by other variable resistors. In other words, in the four bit units BC 11 BC 12 BC 21 and BC 22 In the middle, it consists of 36 passive variable resistors R i The eight variable resistors R around 11a R 11b R 12a R 12b R 21a R 21b R 22a and R 22b It can correspond to eight active variable resistors.

[0147] Reference Figure 8 Via V 11 and V 12 Each of them can be formed in the variable resistor layer L200 to have a structure that penetrates the variable resistor layer L200, and via V 11 or V 12 It can be used to include via V 11 or V 12 The switch of a bit cell is connected to the upper end of any variable resistor in the bit cell adjacent to that bit cell. Via V 11 V 12 These can be arranged to be sufficiently spaced from the variable resistor (e.g., spaced at a predetermined distance). For example, in Figure 8 The first unit line BCL1, the first unit BC 11 In the middle, the active variable resistor R 11a R 11b and passive variable resistor R i It can be placed near the bottom right corner, and through hole V 11 It can be arranged in conjunction with the variable resistor R 11a R 11b and R iNear the fully spaced top left corner. Distance d1 can be the minimum distance between the via of the bit cell and the active variable resistor of the bit cell (e.g., distance d1 can be the first bit BC). 11 via V 11 With the first unit BC 11 Active variable resistor R 11a and R 11b The minimum distance between them, and it can be the second unit BC. 12 via V 12 With the second unit BC 12 Active variable resistor R 12a and R 12b The minimum distance between the bits is d2, and the distance d2 can be the minimum distance between the via of the bit cell and the passive variable resistor of the bit cell.

[0148] according to Figure 8 In the above layout, the via V of the bit cell 11 V 12 Equal to an active variable resistor R 11a R 11b R 12a R 12b The minimum distance d1 between them (e.g., bit cell BC) 11 via V 11 With active variable resistor R 11a R 11b The minimum distance or bit unit BC between them 12 via V 12 With active variable resistor R 12a R 12b The minimum distance between them is comparable to the via V of the bit cell. 11 V 12 Equivalent to a passive variable resistor R i The minimum distance d2 between them (e.g., bit cell BC) 11 via V 11 With passive variable resistor R i The minimum distance or bit unit BC between them 12 via V 12 With passive variable resistor R i The minimum distance between them is large. Via V 11 V 12 Equal to an active variable resistor R 11a R 11b R 12a R 12b The minimum distance d1 between them can be, for example, 0.50 μm to 1.20 μm, and the via V 11 V 12Equivalent to a passive variable resistor R i The minimum distance d2 between them can be, for example, 0.30 μm to 0.60 μm.

[0149] The minimum distance between the variable resistors of the bit unit (e.g., variable resistor R) 11a R 11b R 12a R 12b and R i (Minimum distance between any variable resistor and the nearest variable resistor) d3 Comparable bit cell via V 11 V 12 Active variable resistor R of equal-position unit 11a R 11b R 12a R 12b The minimum distance d1 between them or the via V of the bit cell 11 V 12 Passive variable resistor R of equal and equal units i The minimum distance d2 between them is small, and can be, for example, from 0.10 μm to 0.40 μm. Via V of the bit cell. 11 V 12 The minimum distance d4 between the nearest adjacent vias of the same bit cell is comparable to the via V of the adjacent bit cell. 11 V 12 Active variable resistor R of equal-position unit 11a R 11b R 12a R 12b The minimum distance d1 between them and the via V of the bit cell 11 V 12 Passive variable resistor R of equal and equal units i The minimum distance d2 between them is small and can be, for example, 0.10 μm to 0.40 μm.

[0150] The corresponding layout of variable resistors and / or vias in adjacent (or adjacent) bit cells can be perpendicularly symmetrical and / or bilaterally symmetrical about the boundary lines between adjacent (or adjacent) bit cells. For example, based on adjacent bit cells BC 11 With BC 12 The boundary line between them, including the first unit BC 11 The variable resistor R in 11a R 11b and R i and via V 11 The layout can be combined with the second unit BC. 12 The variable resistor R in 12a R 12b and R iand via V 12 The layout is vertically symmetrical. Similarly, based on adjacent bit cells BC... 11 With BC 21 The boundary line between them includes the first unit BC of the first unit line BCL1. 11 The variable resistor R in 11a R 11b and R i and via V 11 The layout can be combined with the first unit BC included in the second unit line BCL2. 21 The variable resistor R in 21a R 21b and R i The via layout is symmetrical on both sides.

[0151] Figure 9A Showing a vertical cross-sectional view of the bit cell (e.g., along) Figure 8 The bit cell BC intercepted by line X-X' 11 and BC 12 Example of a vertical sectional view. Figure 9B Showing a vertical cross-sectional view of the bit cell (e.g., along) Figure 8 The bit cell BC intercepted by the line Y-Y' 11 and BC 21 Example of a vertical sectional view.

[0152] Reference Figure 9A and Figure 9B The processing device 100 may include a plurality of switches S 11a S 11b The active layer L100, etc., has a variable resistor R formed thereon. 11a R 11b Equal to via V 11 V 12 The variable resistor layer L200 and multiple metal layers M100, M200, M300, M400, M500, M600 and M700.

[0153] The active layer L100 is formed with in-situ cells (e.g., Figure 5B BC 11 BC 12 BC 21 and BC 22 The switch in ) (e.g., Figure 5B S 11a S 11b (etc.) layers. Although Figure 9A Some switches (such as S) are shown in the cross section taken along line X-X'. 11a and S 11bHowever, other switches, not shown, may be formed in the active layer L100. The active layer L100 may be a silicon-based semiconductor layer. See also later. Figure 10 Describe switch S 11a S 11b The detailed structure of etc.

[0154] Multiple metal layers M100, M200, M300, M400, M500, M600, and M700 may include a means for mounting an active variable resistor R. 11a R 11b Connect to switch S 11a S 11b The wires are used to send the on / off signal to switch S. 11a S 11b Lines such as the active variable resistor R and the bit data lines. 11a The lower end can be connected to switch S through a through hole. 11a Drain S 11aD Vias connect metal layers M100, M200, M300, M400, M500, and M600 to each other. Although in Figure 9A and 9B The active variable resistor R is not shown in the diagram. 11a Connect to drain S 11aD The path along which the signal is transmitted can be provided through various designs. For example, the third metal layer M300 may include a means for sending an on / off signal to the switch S. 11a S 11b The fourth metal layer M400 may include lines such as... Figure 5B and / or Figure 6 BDL bit data line 1a BDL 1b BDL 2a and BDL 2b The seventh metal layer M700 may include, for example, a layer for embedding vias V. 11 and V 12 (For example, via V) 11 and V 12 The upper ends of the components are respectively connected to the active variable resistor R. 12a and R 13b The line at the upper end.

[0155] Figure 10 Show the active layer (e.g., Figure 9A Example of a planar diagram of the active layer L100.

[0156] Figure 10 Showing includes Figure 5B bit unit BC 11 BC 12 BC21 and BC 22 Switch S in 11a S 11b S 11 Examples of, etc. Now, regarding... Figure 10 The example details the example structure of the active layer L100. Figure 10 The first unit BC, including the first unit line BCL1, is shown. 11 The three switches S 11a S 11b and S 11 .

[0157] Including the switch S in the active layer L100 11a S 11b and S 11 These can be metal-oxide-semiconductor field-effect transistors (MOSFETs), each comprising a source, drain, and gate. A switch implemented with a MOSFET can operate in such a way that when a gate voltage (equal to or greater than a threshold voltage) is applied to the gate, the switch is turned on, thus electrically connecting the source and drain to each other; and when no gate voltage is applied to the gate, the switch is turned off, thus electrically disconnecting the source and drain from each other. For example, when a gate voltage is applied to the first switch S... 11a gate S 11aG At that time, the first switch S 11a It can conduct, therefore, the first switch S 11a The source of S 11CS1 Can be electrically connected to the first switch S 11a Drain S 11aD For example, when the gate voltage is applied to the second switch S 11b gate S 11bG At that time, the second switch S 11b It can conduct, therefore, the second switch S 11b The source of S 11CS1 Can be electrically connected to the second switch S 11b Drain S 11bD .exist Figure 10 In the middle, the first switch S 11a Second switch S 11b It can be implemented as having a common shared source pole S 11CS Structure. Bit data line switch S 11 It may have two gates S 11Ga and S 11Gb Two drain electrodes S 11Da and S 11Db and common source pole S 11CS2 Structure. Bit data line switch S 11It can be operated as a single transistor by using two transistors that receive the same signal. The switch S of the active layer L100 11a S 11b S 11 The bit cell (e.g., bit cell BC) can be connected to the first metal layer M100 in the marking region L110. In one embodiment, the bit cell (e.g., bit cell BC) 11 ) switch (e.g., S) 11a S 11b and S 11 The controllable force applied to the active variable resistor (e.g., R) can be controlled. 11a and R 11b Either the voltage between the two ends of each of the active variable resistors and the current flowing into each of the active variable resistors.

[0158] Figure 11 The seventh metal layer of the processing device is shown (e.g., Figure 9A Example of a plan view of the seventh metal layer (M700).

[0159] Reference Figure 11 The seventh metal layer M700 can be stacked on top of the variable resistor layer L200 and can provide a way to pass through the via V. 11 V 12 Connect to the active variable resistor R 12a R 13b The line at the upper end of the line, etc. For example, the first unit BC. 11 via V 11 The active variable resistor R of the second unit BC12 can be connected to the line M750 of the seventh metal layer M700. 12a and R 12b The upper part.

[0160] Reference Figure 11 as well as Figure 7 In one example, starting from the first unit BC 11 Active variable resistor R 11a and R 11b The upper ends of each flow to the active variable resistor R 11a and R 11b The current I at the lower end of each can flow downwards through metal layers M100 to M600 to the active layer L100, and can also pass through switches S respectively. 11a and S 11b Then, current I can again pass through metal layers M100 to M600 and via V. 11 And then it flows through the line M750 of the seventh metal layer M700 to the second unit BC. 12 Active variable resistor R 12a and R 12bThe upper end of each of them.

[0161] Metal layers M100, M200, M500, and M600 may provide wires for electrical connections between the aforementioned components. Insulating layers may be disposed between metal layers M100 to M600.

[0162] In the above example embodiment, the variable resistor layer L200 includes a via V for a bit cell. 11 or V 12 The structure has been shown and described. However, the number of vias included in the bit cell line may be greater than or less than the number of bit cells. For example, a via may be included in every two adjacent (or adjacent) bit cells within any bit cell line of the structure.

[0163] Figure 12 An example of a circuit diagram showing a processing device (e.g., processing device 300) having a connection with another processing device (e.g., including one having a connection with...). Figure 5B The connection structure between the switch and the variable resistor of the bit unit has different structures.

[0164] Reference Figure 12 The processing device 300 includes a bit unit BC 11 and BC 13 , bit unit BC 11 and BC 13 Each has a current I flowing in the in-situ unit line BCL1, which flows through a variable resistor (e.g., R, respectively). 11a or R 13b ) flows through the switch (e.g., S) before 11a or S 13b The structure of ).

[0165] when Figure 12 The first unit BC 11 Structure and Figure 5B The first unit BC 11 When making comparisons, in Figure 5B The first unit BC 11 The current I flowing through it passes through the first variable resistor R. 11a Flow to the first switch S 11a , and Figure 12 The first unit BC 11 The current I flowing in passes through the first switch S 11a The current flows to the first variable resistor R 11a In other words, in Figure 12 The first unit BC 11 Structure and Figure 5B The first unit BC 11 In the structure, based on the direction of current I, switch S 11a and S 11b Position and variable resistor R 11a and R 11b The positions are opposite.

[0166] In the processing device 300, such as Figure 12 The first unit BC 11 Such a switch S 11a and S 11b and variable resistor R 11a and R 11b The position of the bit cell that has been reversed can be compared with, for example Figure 5B The second unit BC 12 Such a switch S 12a and S 12b and variable resistor R 12a and R 12b The positions of the bit units are not alternated by inversion. In other words, in the processing device 300, the positions of the switch and the variable resistor are not alternated by the second bit unit BC. 12 The first unit BC, which can be arranged in the position of the switch and variable resistor, can be reversed. 11 With the third unit BC 13 between.

[0167] according to Figure 12 In the circuit structure of the processing device 300, current I can also flow in the bit unit line BCL1 without passing through the via V formed in the variable resistor layer L200. 11 V 12 Such vias. Now refer to... Figure 13 The connection relationship between the variable resistor and the switch associated with the processing device 300 is described in more detail.

[0168] Figure 13 This illustrates the connection relationship between the variable resistor and the switch (e.g., Figure 12 Example of a cross-section of the active layer, variable resistor layer and metal layer of the processing device 300.

[0169] Reference Figure 13 The current I flowing in the first unit line BCL1 can pass through the first unit BC. 11 The first switch S inside 11a After the first variable resistor R 11a The first unit BC 11 The first variable resistor R 11aOne end (upper end) can be connected to the second unit BC through the seventh metal layer M700. 12 The first variable resistor R 12a One end (upper end). Therefore, with Figure 7 In comparison, it has already passed through the first variable resistor R 11a The current I can flow to the second unit BC 12 The first variable resistor R 12a Without going through any switches. Bit data line switches S1, S 11 S 12 and S 13 It can be closed only when a weight is applied, and can remain open under other conditions (e.g., when no weight is applied). Therefore, after the weight is applied, current I will not flow from the bit data line BDL. 1a and BDL 1b The flow goes to the first cell line BCL1. It then passes through the second cell BC. 12 The first variable resistor R 12a The current I can be controlled by switch S 12a and S 13b Flow to the third unit BC 13 The second variable resistor R 13b As mentioned above, in Figure 13 In the first unit line BCL1, the current I flowing in the first unit line can pass through the via V formed in the variable resistor layer L200 without passing through it. 11 and V 13 Flowing under certain conditions.

[0170] Figure 13 via V 11 and V 13 It can provide a variable resistor R for changing 11a R 12a The path for the resistance value, etc. For example, it can be found in... Figure 13 The second variable resistor R 12a Use the first via V when the resistance value is being changed. 11 The above has already covered... Figure 3 The bit cell BC describes an example method for changing the resistance value of a variable resistor when a weight is applied to the bit cell. Return to reference. Figure 12 In order to change the second variable resistor R 12a The resistance value of the second variable resistor R 12a Both ends can be connected to the first data line BDL. 1a Second data line BDL 1b For example, the second variable resistor R 12a The upper end can be switched via the first data line S 11 Connect to the second data line BDL1b And the second variable resistor R 12a The lower end can be connected via the second bit unit BC 12 The first switch S 12a Second data line switch S 12 Connect to the first data line BDL 1a . Reference Figure 13 The second variable resistor R 12a The upper end can be accessed through the first through hole V 11 Connect to the first data line switch S 11 In other words, from Figure 13 It can be seen that the via V 11 or V 13 It can be provided to include via V 11 or V 13 Any variable resistor of a bit cell is connected to the path of the corresponding bit data line switch in the bit data line switch corresponding to that bit cell.

[0171] When in Figure 13 Each bit unit and Figure 7 When comparing the number of vias formed in the variable resistor layer L200 between each bit cell, Figure 7 This shows that each bit cell includes a via, while Figure 13 This shows that every two bit cells include a via. In detail, Figure 13 The first unit BC 11 Second unit BC 12 It may include only one via V 11 .although Figure 13 The bit cell line BCL1 is shown as having vias formed in odd-numbered bit cells (such as the first bit cell BC). 11 and the third unit BC 13 The structure in ) but Figure 13 The bit cell line BCL1 may have a structure including vias formed in the variable resistor layer of the even-number bit cells.

[0172] Figure 14 An example of a processing device (e.g., processing device 700) is shown.

[0173] Reference Figure 14 The processing device 700 may include a bit cell array 710, a controller 720, a row decoder 730, a column decoder 740, a weight driver 750, a current source controller 760, a data buffer 770, and a voltmeter 780. Figure 14 The processing apparatus 700 shown may include components related to the above embodiments. However, the disclosure is not limited thereto, and the processing apparatus 700 may also include, in addition to, Figure 14 General constituent elements other than those shown in the diagram.

[0174] The controller 720 can decode instructions for driving and operating the processing device 700. For example, the controller 720 can decode instructions (such as weight setting, weight setting test, input application, voltage measurement, etc.) and send signals to elements for executing these instructions.

[0175] The bit cell array 710 can be an array of bit cells including the aforementioned variable resistor and switch. The variable resistor can be an MTJ device with magnetic material.

[0176] The line decoder 730 receives a line address and an input signal, and applies the input value to the bit cell array 710. The line decoder 730 may include a digital-to-analog converter (DAC) or an analog-to-digital converter (ADC), and may apply a drive voltage to a switch connected in series with a variable resistor based on the input value. Furthermore, the line decoder 730 may change the resistance value of the variable resistor included in the bit cells of the bit cell array 710. In this state, the line decoder 730 may apply a drive voltage to the associated switch, causing the target variable resistor to be selected.

[0177] The column decoder 740 can receive column address and weight setting signals and apply voltage / current to a variable resistor. The column decoder 740 can select the bit cell lines for voltage measurement and the weight lines connected to the bit cells for weight setting.

[0178] During weight setting, weight driver 750 can send weight data to bit cells selected by row decoder 730 and column decoder 740. Weight driver 750 can drive the weight lines connected to column decoder 740 based on data received from data buffer 770, and perform weight setting and testing of the set weights. Weight driver 750 may include a current source for applying test current to the weight lines to test whether the desired resistance value is set to a variable resistor.

[0179] The current source controller 760 can receive signals from the controller 720 to drive the current source and apply current to the bit cell line.

[0180] The voltmeter 780 measures the voltage across a resistor or capacitor connected to one end of a bit cell line and stores the measured value in an external memory (not shown). The voltmeter 780 may include an ADC that outputs the measured value as a digital value. The processing device 700 may be or may include any of the processing devices described above (such as processing devices 100, 200, or 300).

[0181] Figure 15 An example of an electronic device (e.g., electronic device 800) is shown.

[0182] Reference Figure 15 The electronic device 800 can extract useful information by analyzing input data based on a neural network device 830, which includes (or serves as) a processing device, and determine the situation or control components of an electronic system equipped with the electronic device 800 based on the extracted information. For example, the electronic device 800 can be applied to drones, robotic devices (such as advanced driver assistance systems (ADAS)), smart TVs (TVs), smartphones, medical devices, mobile devices, image display devices, measuring devices, and IoT devices, and can be installed in at least one of a variety of other types of electronic devices.

[0183] In addition to the neural network device 830, the electronic device 800 may also include a processing unit 810 (e.g., one or more processors), random access memory (RAM) 820, memory 840, a sensor module 850, and a communication (Tx / Rx) module 860. The electronic device 800 may also include an input / output module, a security module, a power control device, etc. Some hardware components of the electronic device 800 may be mounted on a semiconductor chip. The neural network device 830 may be a device implemented as an on-chip type processing device according to the above embodiments, or a device including processing devices according to the above embodiments as components.

[0184] The processing unit 810 controls the overall operation of the electronic device 800. The processing unit 810 may be a central processing unit (CPU) and may include a single processor core or multiple processor cores. The processing unit 810 can process or execute programs and / or data stored in the memory 840. The processing unit 810 can control the functions of the neural network device 830 by executing programs stored in the memory 840. The processing unit 810 may be implemented using a graphics processing unit (GPU), application processor (AP), or the like instead of a CPU.

[0185] RAM 820 may temporarily store programs, data, or instructions. For example, programs and / or data stored in memory 840 may be temporarily stored in RAM 820 under the control of processing unit 810 or according to boot code. RAM 820 may be implemented by a memory device such as DRAM or SRAM.

[0186] The neural network device 830 can perform neural network operations based on received input data and can generate information signals based on the results of the operations. The neural network device 830 may include processing means according to the above embodiments (e.g., any processing means in processing means 100, 200, 300, or 700). The neural network may be, but is not limited to, a convolutional neural network (CNN), a recurrent neural network (RNN), a deep belief network, or a restricted Boltzmann machine. The neural network device 830 may correspond to a dedicated hardware accelerator for neural networks.

[0187] Information signals may include various types of recognition signals (such as voice recognition signals, object recognition signals, image recognition signals, and biometric recognition signals). For example, neural network device 830 may receive frame data included in a video stream as input data and may generate recognition signals about objects included in an image represented by the frame data. Neural network device 830 may receive various types of input data depending on the type or function of the electronic system on which electronic device 800 is installed, and may generate recognition signals based on various types of input data.

[0188] Memory 840 is a storage device for storing data and can store, for example, an operating system (OS), various types of programs, and various types of data. Memory 840 may include volatile and / or non-volatile memory. Examples of non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FeRAM). Examples of volatile memory may include DRAM, static random access memory (SRAM), synchronous DRAM (SDRAM), PRAM, MRAM, RRAM, and FeRAM. Memory 840 may include, for example, a hard disk drive (HDD), a solid-state drive (SSD), a compact flash memory (CF), a secure digital card (SD), a micro-secure digital card (Micro-SD), a mini-secure digital card (Mini-SD), an extreme digital card (xD), or a memory stick.

[0189] Sensor module 850 can collect information about the surrounding environment of the electronic system on which electronic device 800 is installed. Sensor module 850 can sense or receive signals (such as image signals, voice signals, magnetic signals, biometric signals, or touch signals) from outside the electronic device, and can convert the sensed or received signals into data. For this purpose, sensor module 850 can include any of various types of sensing devices (such as microphones, imaging devices, image sensors, light detection and ranging (LIDAR) sensors, ultrasonic sensors, infrared sensors, biometric sensors, or touch sensors).

[0190] The sensor module 850 can provide transformed data as input data to the neural network device 830. For example, the sensor module 850 may include an image sensor and can generate a video stream by capturing images of the external environment of the electronic device, and sequentially provide consecutive data frames of the video stream as input data to the neural network device 830. However, the sensor module 850 is not limited to this, and the sensor module 850 can provide various other types of data to the neural network device 830.

[0191] The Tx / Rx module 860 may include various wired or wireless interfaces capable of communicating with external devices. For example, the Tx / Rx module 860 may include a local area network (LAN), a wireless local area network (WLAN) (such as Wi-Fi), Wi-Fi, a wireless personal area network (WPAN) (such as Bluetooth), a wireless universal serial bus (USB), ZigBee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), or a communication interface capable of connecting to a mobile cellular network (such as third-generation (3G), fourth-generation (4G), long-term evolution (LTE), or fifth-generation (5G)).

[0192] Electronic device 800 may include a processor, a memory device for storing and executing program data, a permanent storage device (such as a disk drive), a communication port for handling communication with external devices, and a user interface device including a touch panel, keys, buttons, etc. For example, when software modules or algorithms are involved, these software modules may be stored as program instructions or computer-readable code executable on a processor in a computer-readable recording medium.

[0193] In this regard Figures 1 to 15The described processing devices, neural network devices, electronic devices, bit cells, bit cell lines, switches, variable resistors, layers, pinned layers, tunnel layers, free layers, active layers, metal layers, variable resistor layers, vias, bit cell arrays, controllers, row decoders, column decoders, weight drivers, current source controllers, data buffers, voltmeters, processing units, RAM, memory, sensor modules, communication (Tx / Rx) modules, processing device 200, processing device 300, processing device 700, bit cell array 710, controller 720, row decoder 730, column decoder 740, weight driver 750, current source controller 760, data buffer 770, voltmeter 780, electronic device 800, processing unit 810, RAM 820, neural network device 830, memory 840, sensor module 850, communication (Tx / Rx) module 860, and other devices, apparatuses, units, modules, and components are implemented by or represent hardware components. Examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components performing the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). The processor or computer may be implemented by one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field-programmable gate arrays, programmable logic arrays, microprocessors, or any other means or combination of means configured to respond to and execute instructions in a defined manner to achieve a desired result). In one example, the processor or computer includes or is connected to one or more memories storing instructions or software executed by the processor or computer. The hardware components implemented by the processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) for performing the operations described in this application. Hardware components can also access, manipulate, process, create, and store data in response to the execution of instructions or software. For simplicity, the singular terms "processor" or "computer" are used in the description of the examples described in this application; however, in other examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component, or two or more hardware components, may be implemented by a single processor, or two or more processors, or a processor and a controller.One or more hardware components may be implemented by one or more processors, or processors and controllers, and one or more other hardware components may be implemented by one or more other processors, or additional processors and additional controllers. One or more processors, or processors and controllers, may implement a single hardware component, or two or more hardware components. Hardware components may have any one or more different processing configurations, examples of which include: a single processor, a discrete processor, a parallel processor, Single Instruction Single Data (SISD) multiple processing, Single Instruction Multiple Data (SIMD) multiple processing, Multiple Instruction Single Data (MISD) multiple processing, and Multiple Instruction Multiple Data (MIMD) multiple processing.

[0194] Perform the operations described in this application Figures 1 to 15 The methods illustrated are executed by computing hardware (e.g., one or more processors or a computer), which is implemented to execute instructions or software as described above to perform the operations performed by the methods described in this application. For example, a single operation, or two or more operations, may be executed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be executed by one or more processors, or a processor and a controller, and one or more other operations may be executed by one or more other processors, or additional processors and additional controllers. One or more processors, or a processor and a controller, may execute a single operation, or two or more operations.

[0195] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above can be written as computer programs, code segments, instructions, or any combination thereof to individually or collectively instruct or configure one or more processors or computers to operate as a machine or special-purpose computer to perform operations performed by the hardware components and methods described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) that is directly executed by one or more processors or computers. In another example, the instructions or software include high-level code that is executed by one or more processors or computers using an interpreter. The instructions or software can be written in any programming language based on the block diagrams and flowcharts shown in the accompanying drawings and the corresponding description used herein, which disclose algorithms for performing operations performed by the hardware components and methods described above.

[0196] Instructions or software used to control computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, as well as any associated data, data files, and data structures, may be recorded, stored, or fixed in, or on, one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include: read-only memory (ROM), programmable random access read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage devices, hard disk drives (HDDs), solid-state drives (SSDs), card storage devices (such as multimedia cards or microcards (e.g., Secure Digital (SD) or Extreme Digital (XD))), magnetic tape, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state drives, and any other devices configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and to provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers, enabling one or more processors or computers to execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed across a networked computer system, such that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0197] While this disclosure includes specific examples, it will be clear upon understanding this disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered descriptive only and not for limiting purposes. The description of features or aspects in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if components in the described system, architecture, apparatus, or circuit are combined in a different manner, and / or replaced or supplemented by other components or their equivalents.

Claims

1. A bitcell circuit used in a processing device, comprising: a first variable resistor as a resistive memory device, having a resistance value set based on switching between different resistance states of the resistive memory device; a second variable resistor as another resistive memory device, connected in parallel to the first variable resistor, wherein the second variable resistor is set with a resistance value complementary to the resistance value of the first variable resistor; a first switch connected in series to the first variable resistor, and configured to switch application of a voltage or a current to the first variable resistor; and a second switch connected in series to the second variable resistor, and configured to complementarily perform a switching operation for application of a voltage or a current to the second variable resistor with the first switch, wherein the processing device is a device performing in-memory processing. 2.The bitcell circuit according to claim 1, wherein, the first variable resistor is set with either of a first resistance value and a second resistance value, and when the first variable resistor is set with the first resistance value, the second variable resistor is set with the second resistance value, and when the first variable resistor is set with the second resistance value, the second variable resistor is set with the first resistance value.

3. The bitcell circuit of claim 1, wherein, the resistance value of the first variable resistor and the resistance value of the second variable resistor are set with values corresponding to weights for a product-sum operation.

4. The bitcell circuit of claim 1, wherein, the first switch and the second switch complementarily perform on / off operations according to input values applied to the bitcell circuit to perform a product-sum operation of a neural network.

5. The bitcell circuit of claim 4, wherein, when the first switch is closed by application of a first input value, a resistance value of the bitcell circuit is equal to the resistance value of the first variable resistor, and when the second switch is closed by application of a second input value, the resistance value of the bitcell circuit is equal to the resistance value of the second variable resistor. 6.The bitcell circuit according to claim 4, wherein, when the first variable resistor is set with a first resistance value corresponding to a first weight and a first input value is applied to the bitcell circuit, a resistance value of the bitcell circuit is the first resistance value, when the second variable resistor is set with a second resistance value corresponding to a second weight and a second input value is applied to the bitcell circuit, the resistance value of the bitcell circuit is the first resistance value, when the second variable resistor is set with the second resistance value corresponding to the second weight and the first input value is applied to the bitcell circuit, the resistance value of the bitcell circuit is the second resistance value, and when the first variable resistor is set with the first resistance value corresponding to the first weight and the second input value is applied to the bitcell circuit, the resistance value of the bitcell circuit is the second resistance value.

7. The bitcell circuit of claim 4, wherein, the bitcell circuit has a resistance value corresponding to a result of an exclusive NOR operation between an input value applied to the bitcell circuit and a weight set for the bitcell circuit. 8.The bitcell circuit according to claim 1, wherein, the first variable resistor and the first switch connected in series to each other are connected in parallel to the second variable resistor and the second switch connected in series to each other, one end of the first variable resistor and one end of the second variable resistor are commonly connected to a first bit data line, and one end of the first switch and one end of the second switch are commonly connected to a second bit data line.

9. The bitcell circuit of claim 8, wherein, another bit cell circuit is connected to any one of: the one end of the first variable resistor and the one end of the second variable resistor commonly connected to the first bit data line; and the one end of the first switch and the one end of the second switch commonly connected to the second bit data line.

10. The bitcell circuit of claim 1, wherein, the first variable resistor and the second variable resistor are magnetic tunnel junction devices.

11. A processing device, comprising: a bit cell array including a plurality of bit cells including the bit cell circuit according to claim 1.

12. A bit cell circuit for use in a processing device, comprising: a pair of variable resistors as resistive memory devices, arranged to have different resistance values and connected in parallel to each other; and a pair of switches connected in series to the pair of variable resistors, respectively, and configured to complementarily switch application of a voltage or a current to the pair of variable resistors, wherein the processing device is a device that performs in-memory processing.

13. A processing device, comprising: a bit cell array including a plurality of bit cells each including a pair of variable resistors and a pair of switches, wherein at least one of the plurality of bit cells includes: a first variable resistor as a resistive memory device having a resistance value arranged based on switching of the resistive memory device between different resistance states; a second variable resistor as another resistive memory device connected in parallel to the first variable resistor, wherein the second variable resistor is arranged to have a resistance value complementary to the resistance value of the first variable resistor; a first switch connected in series to the first variable resistor and configured to switch application of a voltage or a current to the first variable resistor; and a second switch connected in series to the second variable resistor and configured to complementarily perform a switching operation for application of a voltage or a current to the second variable resistor with the first switch, wherein the processing device is a device that performs in-memory processing.

14. The processing device according to claim 13, wherein the plurality of bit cells form a bit cell array including a plurality of bit cell lines, and each of the plurality of bit cell lines includes bit cells connected in series among the plurality of bit cells.

15. The processing device according to claim 14, wherein a first bit cell line among the plurality of bit cell lines is configured to perform processing of a product-sum operation of a first node among a plurality of nodes of a neural network, and a pair of variable resistors included in each bit cell of the first bit cell line is arranged to have resistance values corresponding to weights used for the product-sum operation of the first node.

16. The processing device of claim 15, wherein, in each bit cell included in the first bit cell line, one of the pair of switches is closed and the other of the pair of switches is open based on an input value of the product-sum operation of the first node.

17. The processing device of claim 15, wherein, A result of the product-sum operation of the first node corresponds to a value of a voltage drop of the first bit cell line due to a current of a predetermined value applied to the first bit cell line, in response to a switching operation of the pair of switches corresponding to a resistance value corresponding to the weight and an input value.

18. The processing device of claim 17, wherein, The value of the voltage drop of the first bit cell line corresponds to a sum of values of voltage drops occurring in the bit cells included in the first bit cell line.

19. The processing device of claim 13, further comprising a pair of bit data lines, each of one or more of the plurality of bit cells being connected between the pair of bit data lines, and the pair of bit data lines being configured to apply a voltage or a current across each of the one or more of the plurality of bit cells to set a resistance value of a pair of variable resistors of each of the one or more bit cells.

20. A processing device comprising an array of bit cells, the processing device comprising: a plurality of bit cells; and a pair of bit data lines, each of one or more of the plurality of bit cells being connected between the pair of bit data lines, and the pair of bit data lines being configured to apply a voltage or a current across each of the one or more of the plurality of bit cells, wherein at least one of the plurality of bit cells comprises: a pair of variable resistors as resistive memory devices set to have different resistance values according to switching between different resistance states, and connected in parallel to each other; and a pair of switches respectively connected in series to the pair of variable resistors, and configured to complementarily switch application of a voltage or a current to the pair of variable resistors, wherein the processing device is a device that performs in-memory processing.

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