Memory device and method of operating a memory device

Abstract

This document provides a memory device and a method for operating a memory device. The memory device may include: a memory cell array including multiple planes; peripheral circuits that perform operations on the multiple planes; a control memory that stores control codes for controlling the peripheral circuits; and multiple independent control logics that, upon receiving commands corresponding to each plane from a memory controller, control the peripheral circuits in response to the commands and referring to the control codes corresponding to the commands. The control memory may include: a common memory that is commonly accessible to the multiple independent control logics; and a temporary storage that includes regions corresponding to the respective planes.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to memory devices, and more particularly to memory devices and methods of operating the memory devices. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores data and a memory controller that controls the memory device. Memory devices are categorized as volatile memory devices and non-volatile memory devices.

[0003] A volatile memory device is a memory device that stores data only when power is supplied and loses the stored data when power is interrupted. Examples of volatile memory devices may include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0004] A nonvolatile memory device may be a memory device that retains stored data even if power is interrupted. Examples of nonvolatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0005] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory cell array including multiple planes; a control memory storing control codes for performing a plane interleaving operation on the multiple planes; and multiple independent control logics that, upon receiving a command instructing the plane interleaving operation from a memory controller, control an operation corresponding to the command for each plane in response to the command reference control code.

[0006] The control memory may include a common memory that is commonly accessible by the independent control logics and a temporary storage that includes physically independent areas so that a plurality of independent control logics can access the areas in parallel.

[0007] Embodiments of the present disclosure may provide a method for operating a memory device. The method may include: receiving a command instructing a plane interleaving operation from a memory controller; determining whether the command is a first command of the memory controller; accessing a common memory or temporary storage commonly accessible by multiple independent control logics in response to the determination; then obtaining a control code corresponding to the command; and storing the control code in the temporary storage; and generating a control signal for the plane interleaving operation based on the control code. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1is a diagram illustrating a memory system.

[0009] Figure 2 is a diagram illustrating signals exchanged between a memory controller and a memory device.

[0010] Figure 3 This is an example Figure 1 Figure 1 is a diagram of a memory device.

[0011] Figure 4 is a diagram illustrating a multi-plane structure.

[0012] Figure 5 This is an example Figure 4 A diagram of a storage block.

[0013] Figure 6 This is an example of Figure 4 FIG2 is a diagram of an embodiment in which memory blocks are configured as a 3D structure.

[0014] Figure 7 This is an example of Figure 4 FIG2 is a diagram of an embodiment in which memory blocks are configured as a 3D structure.

[0015] Figure 8A and Figure 8B This is an example of Figure 4 A timing diagram of a plane-interleaved read operation of a multi-plane memory device.

[0016] Figure 9 FIG. 1 is a diagram illustrating a threshold voltage distribution of a memory cell in a triple-level cell format.

[0017] Figure 10 is exemplified in Figure 4 A conceptual diagram of a method for controlling memory according to a plane interleaved read operation in a multi-plane structure memory device.

[0018] Figure 11 This is an example to illustrate Figure 10 A conceptual diagram of a method of configuring a control memory in different forms and performing a plane interleaved read operation.

[0019] Figure 12 It is an example of Figure 11 A conceptual diagram of a method for performing a plane interleaved read operation when an additional command is received in a control memory configuration.

[0020] Figure 13 is an example operation with Figure 10 and Figure 11 An example flow chart of a method of controlling memory configuration of a memory device.

[0021] Figure 14 This is an example Figure 13 FIG. 1 is an example flowchart of a portion of step S110 .

[0022] Figure 15 This is an example Figure 1 Figure 1. Memory controller diagram.

[0023] Figure 16 is an example including Figure 10 and Figure 11 A diagram of an embodiment of a memory system of a memory device that controls memory configuration. DETAILED DESCRIPTION

[0024] The specific structural description or functional description of the embodiments of the present disclosure introduced in this specification or application is exemplified for the purpose of describing the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0025] Various embodiments of the present disclosure relate to a memory device capable of efficiently utilizing storage space and a method of operating the memory device. In some embodiments, the temporary storage may include physically independent areas so that multiple independent control logics can access these areas in parallel. In some embodiments, the control code may be configured to: when the command is the first command of the memory controller, access the public memory and obtain the control code from the public memory. In some embodiments, the control code may be configured to: when the command is not the first command of the memory controller, access the temporary storage instead of the public memory and obtain the control code from the temporary storage.

[0026] Figure 1 is a diagram illustrating a memory system.

[0027] Reference Figure 1 , the memory system 1000 may include a memory device 1100 that stores data, a buffer memory 1300 that temporarily stores data required for operation of the memory system 1000 , and / or a memory controller 1200 that controls the memory device 1100 and the buffer memory 1300 under the control of the host 2000 .

[0028] The host 2000 may communicate with the memory system 1000 using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI), PCI-Express (PCIe), a non-volatile memory express (NVMe), a universal flash memory (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a lightly loaded DIMM (LRDIMM) communication method.

[0029] The memory device 1100 can be implemented as a volatile memory device that loses stored data when power is interrupted, or as a non-volatile memory device that retains stored data even when power is interrupted. The memory device 1100 can perform a program operation, a read operation, or an erase operation under the control of the memory controller 1200. For example, during a program operation, the memory device 1100 can receive a command, an address, and data from the memory controller 1200, and then can perform the program operation. During a read operation, the memory device 1100 can receive a command and an address from the memory controller 1200, and can output the read data to the memory controller 1200. For this operation, the memory device 1100 may include an input / output circuit for inputting and outputting data.

[0030] The memory controller 1200 can control the overall operation of the memory system 1000 and can control data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 can program, read, or erase data by controlling the memory device 1100 in response to a request received from the host 2000. In addition, the memory controller 1200 can receive data and a logical address from the host 2000 and can convert the logical address into a physical address indicating an area in the memory device 1100 where the data is actually to be stored. In addition, the memory controller 1200 can store a logical-to-physical address mapping table in the buffer memory 1300 that configures a mapping relationship between logical addresses and physical addresses.

[0031] The memory device 1100 may include multiple planes. The memory controller 1200 may control the memory device 1100 so that, in response to a request received from the host 2000, a program operation, a read operation, or an erase operation is performed on multiple planes in parallel (or in an interleaved manner). For example, the memory controller 1200 may control the memory device 1100 so that the memory device 1100 performs a plane interleaved operation. The plane interleaved operation may include a plane interleaved read operation. The memory controller 1200 may generate a read command indicating a plane interleaved read operation in response to multiple read requests received from the host 2000, and may output the generated read command to the memory device 1100. For example, the read command may include the physical address of a plane selected from the multiple planes. The memory device 1100 may read data from the multiple planes in an interleaved manner in response to the read command, and may transmit the read data to the memory controller 1200. Hereinafter, although description will be made based on a plane interleaved read operation, the present disclosure is not limited thereto, and an embodiment in which the memory device 1100 includes a plurality of chips or dies and performs an interleaved operation on a chip or die basis may also be included in the present disclosure.

[0032] The buffer memory 1300 may be used as a working memory or cache memory of the memory controller 1200, and in addition to the above-mentioned information, may also store system data used in the memory system 1000. In embodiments, the buffer memory 1300 may include double data rate synchronous dynamic random access memory (DDR SDRAM), fourth generation DDR SDRAM (DDR4 SDRAM), low power fourth generation DDR (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, or Rambus DRAM (RDRAM).

[0033] Figure 2 is a diagram illustrating signals exchanged between a memory controller and a memory device.

[0034] Reference Figure 2 , the memory controller 1200 and the memory device 1100 may exchange commands, data, and / or addresses with each other through the input / output pads DQ.

[0035] The memory device can receive a chip enable signal through the CE# pad, a write enable signal through the WE# pad, a read enable signal through the RE# pad, an address latch enable signal through the ALE pad, a command latch enable signal through the CLE pad, and a write protect signal through the WP# pad.

[0036] In addition, the memory device 1100 may output a ready-busy signal to the memory controller 1200 through the RB pad. For example, when the memory device 110 includes multiple planes, the memory device 1100 may output multiple ready-busy signals, each of which indicates one of a ready state and a busy state of a corresponding one of the multiple planes.

[0037] Figure 3 This is an example Figure 1 Figure 1 is a diagram of a memory device.

[0038] Reference Figure 3 , the memory device 1100 may be implemented as a volatile memory device or a non-volatile memory device. Figure 3 A nonvolatile memory device is illustrated as an example of a memory device in , but this embodiment is not limited to such a nonvolatile memory device.

[0039] The memory device 1100 may include a memory cell array 100 in which data is stored. The memory device 1100 may include a peripheral circuit 200 configured to perform a program operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The memory device 1100 may include control logic 300 that controls the peripheral circuit 200 under the control of a memory controller 1200. The control logic 300 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 300 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0040] The memory cell array 100 includes a plurality of memory cells in which data is stored. For example, the memory cell array 100 may include at least one plane, and the plane may include one or more memory blocks. In an embodiment, a plane may be a unit of a memory area accessed when performing a programming operation, a read operation, or an erase operation. Each memory block may include a plurality of memory cells. A structure including a plurality of planes may be designated as a multi-plane structure. In a memory block, information and user data required for the operation of the memory device 1100 may be stored. The memory blocks may each be implemented in a two-dimensional (2D) or three-dimensional (3D) structure. Each memory block having a 2D structure may include memory cells arranged in parallel on a substrate. Each memory block having a 3D structure may include memory cells stacked vertically on a substrate.

[0041] The peripheral circuit 200 may perform a program operation, a read operation, and an erase operation under the control of the control logic 300. For example, the peripheral circuit 200 may include a voltage generation circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, a current sensing circuit 260, and a control memory 270.

[0042] The voltage generation circuit 210 may generate various operating voltages Vop to be used for program operations, read operations, and erase operations in response to an operation signal OP_CMD output from the control logic 300. For example, the voltage generation circuit 210 may generate various voltages such as a program voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage under the control of the control logic 300.

[0043] The row decoder 220 may provide an operating voltage Vop to a local line LL connected to a memory block selected from among the memory blocks of the memory cell array 100 in response to a row address RADD output from the control logic 300. The local line LL may include a local word line, a local drain select line, and / or a local source select line. In addition, the local line LL may include various lines such as a source line connected to the memory block.

[0044] The page buffer group 230 may be coupled to the bit lines BL1 to BLI coupled to the memory blocks of the memory cell array 100. The page buffer group 230 may include a plurality of page buffers PB1 to PBI coupled to the bit lines BL1 to BLI. The page buffers PB1 to PBI may operate in response to a page buffer control signal PBSIGNALS output from the control logic 300. For example, the page buffers PB1 to PBI may temporarily store data received through the bit lines BL1 to BLI during a read operation or a verify operation or may sense a voltage or current of the bit lines BL1 to BLI.

[0045] The column decoder 240 may transfer data between the input / output circuit 250 and the page buffer group 230 in response to the column address CADD output from the control logic 300. For example, the column decoder 240 may exchange data with the page buffers PB1 to PBI through the data lines DL, or may exchange data with the input / output circuit 250 through the column lines CL.

[0046] The input / output circuit 250 may receive a command CMD, an address ADD, and data from the memory controller 1200 through the input / output pad DQ, and may output read data to the memory controller 1200 through the input / output pad DQ. For example, the input / output circuit 250 may transmit the command CMD and the address ADD received from the memory controller 1200 to the control logic 300, or may exchange data with the column decoder 240.

[0047] During a read operation or a verification operation, the current sensing circuit 260 may generate a reference current in response to the enable bit VRY_BIT<#>, and may compare the sensing voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current, and output a pass signal PASS or a fail signal FAIL.

[0048] The control logic 300 may receive a command CMD and an address ADD in response to signals received via the CE#, WE#, RE#, ALE, CLE, and WP# pads. In response to receiving the command CMD and address ADD, the control logic 300 may refer to a control code CTRCODES to generate a control signal for controlling the peripheral circuit 200 and may output the generated control signal to the peripheral circuit 200. For example, the control signal may include at least one of an operation signal OP_CMD, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRY_BIT<#>. The control logic 300 may output the operation signal OP_CMD to the voltage generation circuit 210, the row address RADD to the row decoder 220, the page buffer control signal PBSIGNALS to the page buffer group 230, and the enable bit VRY_BIT<#> to the current sensing circuit 260. Furthermore, the control logic 300 may determine whether the verify operation has passed or failed in response to a pass signal PASS or a fail signal FAIL.

[0049] The control memory 270 may store control codes CTRCODES required for the control logic 300 to control the peripheral circuit 200. The control codes may include codes (or algorithms) for generating control signals related to programming operations, read operations, and erase operations, and codes for generating control signals related to plane interleaving operations. For example, the control codes may include codes for generating control signals related to plane interleaving read operations. For example, the control memory 270 may be a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or the like. Although the control memory 270 may be configured to be included in the peripheral circuit 200 according to its expression, it may be distinguished from the peripheral circuit 200 for a clear description or to clarify the target to be specified.

[0050] Figure 4 is a diagram illustrating a multi-plane structure.

[0051] Reference Figure 4 , the memory device 1100 having a multi-plane structure may include a plurality of planes P1 to P4. For example, the first plane P1 to the fourth plane P4 may be included in one memory device 1100.

[0052] The first to fourth planes P1 to P4 may be coupled to respective row decoders RD1 to RD4 and to respective page buffer groups PBG1 to PBG4 and may operate independently. For example, the first plane P1 may be operated while coupled to the first row decoder RD1 and the first page buffer group PBG1, the second plane P2 may be operated while coupled to the second row decoder RD2 and the second page buffer group PBG2, the third plane P3 may be operated while coupled to the third row decoder RD3 and the third page buffer group PBG3, and the fourth plane P4 may be operated while coupled to the fourth row decoder RD4 and the fourth page buffer group PBG4.

[0053] When describing the read operation as an example, the first row decoder RD1 to the fourth row decoder RD4 may apply a read voltage to the memory blocks selected from the first plane P1 to the fourth plane P4, respectively, in response to the received row address. The first page buffer group PBG1 to the fourth page buffer group PBG4 may temporarily store data read by sensing the voltage or current of the bit lines connected to the first plane P1 to the fourth plane P4. When all the sensing operations performed on the first plane P1 to the fourth plane P4 have been completed, the read data temporarily stored in the first page buffer group PBG1 to the fourth page buffer group PBG4 may be read by the input / output circuit (e.g., Figure 2 For example, after the read data in the first page buffer group PBG1 has been output first, the read data in the second to fourth page buffer groups PBG2 to PBG4 may be sequentially output.

[0054] like Figure 4 As shown, the memory device 1100 including multiple planes P1 to P4 can simultaneously perform a read operation, a program operation, or an erase operation on blocks or pages set in different planes. For example, the memory controller 1200 can send a command indicating a plane interleaving operation to the control logic 300. For example, the memory controller 1200 can send a command indicating a plane interleaving read operation to the control logic 300 so that blocks or pages set in different planes are read simultaneously. As used herein, the words "simultaneously" and "simultaneously" with respect to occurrences refer to occurrences occurring at overlapping time intervals. For example, if a first occurrence occurs at a first time interval and a second occurrence occurs simultaneously at a second time interval, the first interval and the second interval at least partially overlap each other, so that there is a time when both the first occurrence and the second occurrence occur.

[0055] Furthermore, to perform plane interleaving operations, the control logic 300 may include a plurality of independent control logics CL1 to CL4 corresponding to planes P1 to P4, respectively. For example, the first independent control logic CL1 may control operations performed on the first plane P1, the second independent control logic CL2 may control operations performed on the second plane PL2, the third independent control logic CL3 may control operations performed on the third plane P3, and the fourth logic CL4 may control operations performed on the fourth plane P4. Thus, the first to fourth row decoders RD1 to RD4 and the first to fourth page buffer groups PBG1 to PBG4 may be independently controlled by the first to fourth plurality of independent control logics CL1 to CL4. The independent control logic (i.e., CL1, CL2, CL3, or CL4) may be implemented as hardware, software, or a combination of hardware and software. For example, the independent control logic (i.e., CL1, CL2, CL3, or CL4) may be an independent control logic circuit operating according to an algorithm and / or a processor executing independent control logic code.

[0056] Furthermore, when multiple independent control logics CL1 to CL4 use a single control memory 270, a bottleneck may occur that interferes with the independent operations between planes P1 to P4. For example, when the first independent control logic CL1 accesses the control memory and retrieves a control code, the control memory 270 is busy, and thus the second independent control logic CL2 may be restricted from accessing the control memory 270 and retrieving the control code. To address this issue, the control memory 270 may include multiple independent control memories CM1 to CM4. For example, the first independent control logic CL1 may reference the first control memory CM1 to retrieve a control code, the second independent control logic CL2 may reference the second control memory CM2 to retrieve a control code, the third independent control logic CL3 may reference the third control memory CM3 to retrieve a control code, and the fourth independent control logic CL4 may reference the fourth control memory CM4 to retrieve a control code.

[0057] In the following, although based on Figure 4 While the description shown here assumes that multiple independent control logics CL1 to CL4 exist for respective planes P1 to P4, the present disclosure is not necessarily limited thereto. For example, embodiments may be implemented such that at least some of the multiple independent control logics CL1 to CL4 are integrated into a single control logic, and such that the single control logic controls two or more planes. Furthermore, embodiments to be described later may be implemented such that control memories CM1 to CM4 are integrated into a single control memory, and such that the single control memory stores control codes for controlling two or more planes.

[0058] Figure 5 This is an example Figure 4A diagram of a storage block.

[0059] Reference Figure 5 , as an example, Figure 4 A first memory block BLK1 among a plurality of memory blocks BLK1 to BLK6 is shown. The remaining memory blocks BLK2 to BLK6 may have the same configuration as the first memory block BLK1.

[0060] The first memory block BLK1 may include a plurality of cell strings ST coupled between bit lines BL1 to BLI and a source line SL. For example, the cell strings ST may be coupled to the bit lines BL1 to BLI, respectively, and may be coupled to the source line SL in common. Since the cell strings ST are configured in a similar manner, the description will be based on the cell string ST coupled to the first bit line BL1 by way of example.

[0061] The cell string ST may include a source select transistor SST, first to nth memory cells F1 to Fn (where n is a positive integer), and a drain select transistor DST connected in series between a source line SL and a first bit line BL1. The number of source select transistors SST and drain select transistors DST is not limited to Figure 5 The specific number shown. A source select transistor SST may be coupled between the source line SL and the first memory cell F1. The first to nth memory cells F1 to Fn may be coupled in series between the source select transistor SST and the drain select transistor DST. The drain select transistor DST may be coupled between the nth memory cell Fn and the first bit line BL1. Although not shown in the drawings, a dummy cell may be further coupled between the memory cells F1 to Fn or between the source select transistor SST and the drain select transistor DST.

[0062] The gates of the source select transistors SST included in different cell strings ST can be coupled to a source select line SSL, the gates of the first to nth memory cells F1 to Fn can be coupled to the first to nth word lines WL1 to WLn, and the gates of the drain select transistors DST can be coupled to a drain select line DSL. Here, a group of memory cells respectively coupled to the word lines WL1 to WLn is referred to as a page (PG). For example, a group of first memory cells F1 coupled to the first word line WL1 among the memory cells F1 to Fn included in different cell strings ST can be a single physical page (PPG). Programming and reading operations can be performed on a physical page (PPG) basis.

[0063] Figure 6 This is an example Figure 4 FIG2 is a diagram of an embodiment in which memory blocks are configured as a 3D structure.

[0064] Reference Figure 6 , exemplarily illustrates Figure 4 A first memory block BLK1 among a plurality of memory blocks BLK1 to BLK6 is shown in FIG. The remaining memory blocks BLK2 to BLK6 may have the same configuration as the first memory block BLK1.

[0065] The first memory block BLK1 implemented in a 3D structure may be formed in an I-shape on a substrate in a vertical direction (e.g., Z direction) and may include a plurality of cell strings ST arranged between a bit line BL and a source line SL. Alternatively, a well may be formed instead of the source line SL. This structure may be referred to as "bit cost scalable (BiCS)". For example, in the case where the source line SL is horizontally formed on top of the substrate, a cell string ST having a BiCS structure may be formed on top of the source line SL in a vertical direction (e.g., Z direction).

[0066] For example, the cell strings ST may be arranged separately in a first direction (e.g., X direction) and a second direction (e.g., Y direction). Each cell string ST may include a source select line SSL, a word line WL, and a drain select line DSL stacked apart from each other. The number of source select lines SSL, the number of word lines WL, and the number of drain select lines DSL are not limited to the number shown in the figure and may vary depending on the memory device. Each cell string ST may include a vertical channel layer CH and a bit line BL, the vertical channel layer CH vertically passing through the source select line SSL, the word line WL, and the drain select line DSL, and the bit line BL contacts the top of the vertical channel layer CH protruding upward from the drain select line DSL and extends in a second direction (e.g., Y direction). The memory cell may be formed between the word line WL and the vertical channel layer CH. A contact plug CT may be further formed between the bit line BL and the vertical channel layer CH.

[0067] Figure 7 This is an example Figure 4 FIG2 is a diagram of an embodiment in which memory blocks are configured as a 3D structure.

[0068] Reference Figure 7 , exemplarily illustrates Figure 4 A first memory block BLK1 among a plurality of memory blocks BLK1 to BLK6 is shown. The remaining memory blocks BLK2 to BLK6 may have the same configuration as the first memory block BLK1.

[0069] The first memory block BLK1 implemented in a 3D structure can be formed in a U shape on a substrate in a vertical direction (e.g., Z direction), and can include a source string ST_S and a drain string ST_D connected between a bit line BL and a source line SL to form a pair. Each source string ST_S and the corresponding drain string ST_D can be connected to each other through a pipe gate PG to form a U shape. The pipe gate PG can be formed in the pipe line PL. In more detail, the source string ST_S can be formed vertically between the source line SL and the pipe line PL. The drain string ST_D can be formed vertically between the bit line BL and the pipe line PL. This structure can also be referred to as "pipeline-shaped bit cost scalable (P-BiCS)".

[0070] For example, the drain string ST_D and the source string ST_S can be arranged separately in a first direction (e.g., X direction) and a second direction (e.g., Y direction), and the drain string ST_D and the source string ST_S can be alternately arranged along the second direction Y. Each drain string ST_D may include a word line WL and a drain select line DSL stacked apart from each other and a drain vertical channel layer D_CH vertically passing through the word line WL and the drain select line DSL. Each source string ST_S may include a word line WL and a source select line SSL stacked apart from each other and a source vertical channel layer S_CH vertically passing through the word line WL and the source select line SSL. The drain vertical channel layer D_CH and the source vertical channel layer S_CH may be coupled to each other through a pipe gate PG in a pipe line PL. The bit line BL may contact the top of the drain vertical channel layer D_CH protruding upward from the drain select line DSL and may extend in the second direction (e.g., Y direction).

[0071] Figure 8A and Figure 8B This is an example of Figure 4 A timing diagram of a plane-interleaved read operation of a multi-plane memory device.

[0072] Reference Figure 8A and Figure 8B , illustrating the Figure 2 The command CMD and address ADDR: P1 to ADDR: P4 received by the input / output pad DQ, the data DATA OUT: P1 to DATA OUT: P4 output through the input / output pad DQ, and the Figure 2 The ready-busy signals RB:P1 to RB:P4 output through the RB pads may indicate a ready state or a busy state of each of the planes P1, P2, P3, and P4 included in the memory device 1100.

[0073] At a first time t1, the memory device 1100 may receive a first page read command 00h via the input / output pad DQ. At a second time t2, the memory device 1100 may receive an address ADDR:P1 corresponding to a page of the first plane P1, which is the read target, via the input / output pad DQ. At a third time t3, the memory device 1100 may receive a second page read command 30h via the input / output pad DQ. The first page read command 00h, the address ADDR:P1 corresponding to the page of the first plane P1, and the second page read command 30h may constitute a read command for the first plane P1. With the receipt of the read command for the first plane P1, a read operation on the first plane P1 may begin. Therefore, at a fourth time t4, the ready-busy signal RB:P1 for the first plane P1 may transition from a high value indicating a ready state to a low value indicating a busy state.

[0074] During the period from the fifth time t5 to the sixth time t6, the memory device 1100 may receive a first page read command 00h, an address ADDR:P2 corresponding to a page of the second plane P2, and a second page read command 30h via the input / output pad DQ. The first page read command 00h, the address ADDR:P2 corresponding to the page of the second plane P2, and the second page read command 30h may constitute a read command for the second plane P2. With the receipt of the read command for the second plane P2, a read operation on the second plane P2 may begin. Therefore, at the sixth time t6, the ready-busy signal RB:P2 for the second plane P2 may transition from a high value indicating a ready state to a low value indicating a busy state.

[0075] During the period from the seventh time t7 to the eighth time t8, the memory device 1100 may receive a first page read command 00h, an address ADDR:P3 corresponding to a page of the third plane P3, and a second page read command 30h via the input / output pad DQ. The first page read command 00h, the address ADDR:P3 corresponding to a page of the third plane P3, and the second page read command 30h may constitute a read command for the third plane P3. With the receipt of the read command for the third plane P3, a read operation on the third plane P3 may begin. Therefore, at the eighth time t8, the ready-busy signal RB:P3 for the third plane P3 may transition from a high value indicating a ready state to a low value indicating a busy state.

[0076] During the period from the ninth time t9 to the tenth time t10, the memory device 1100 may receive a first page read command 00h, an address ADDR:P4 corresponding to a page of the fourth plane P4, and a second page read command 30h via the input / output pad DQ. The first page read command 00h, the address ADDR:P4 corresponding to a page of the fourth plane P4, and the second page read command 30h may constitute a read command for the fourth plane P4. With the receipt of the read command for the fourth plane P4, a read operation on the fourth plane P4 may begin. Therefore, at the tenth time t10, the ready-busy signal RB:P4 for the fourth plane P4 may transition from a high value indicating a ready state to a low value indicating a busy state.

[0077] Reference Figure 8B At the eleventh time t11, the read operation on the first plane P1 may be completed. Therefore, at the eleventh time t11, the ready-busy signal RB:P1 for the first plane P1 may transition from a low value to a high value. During the period from the eleventh time t11 to the twelfth time t12, the memory device 1100 may output the read data DATAOUT:P1 for the first plane P1 through the input / output pad DQ.

[0078] At the thirteenth time t13, the read operation on the second plane P2 may be completed. Therefore, at the thirteenth time t13, the ready-busy signal RB: P2 for the second plane P2 may transition from a low value to a high value. During the period from the thirteenth time t13 to the fourteenth time t14, the memory device 1100 may output the read data DATAOUT: P2 for the second plane P2 through the input / output pad DQ.

[0079] At the fifteenth time t15, the read operation on the third plane P3 may be completed. Therefore, at the fifteenth time t15, the ready-busy signal RB: P3 for the third plane P3 may transition from a low value to a high value. During the period from the fifteenth time t15 to the sixteenth time t16, the memory device 1100 may output the read data DATAOUT: P3 for the third plane P3 through the input / output pad DQ.

[0080] At the seventeenth time t17, the read operation on the fourth plane P4 may be completed. Therefore, at the seventeenth time t17, the ready-busy signal RB:P4 for the fourth plane P4 may transition from a low value to a high value. The memory device 1100 may output the read data DATAOUT:P4 for the fourth plane P4 through the input / output pad DQ starting at the seventeenth time t17.

[0081] like Figure 8A and Figure 8B As shown, the memory device 1100 having a multi-plane structure may start a read operation on any one plane, then may receive a read command for an additional plane and start a read operation on the additional plane before the read operation on the one plane ends.

[0082] As described above, an operation in which read operations on respective planes are performed overlapping with each other or in parallel during at least some time periods can be designated as a plane interleaved read operation. Since the plane interleaved read operation is performed so that read operations on multiple planes are performed overlapping with each other, the operating speed of the memory device can be increased.

[0083] Figure 9 FIG. 1 is a diagram illustrating a threshold voltage distribution of a memory cell in a triple-level cell format.

[0084] Reference Figure 9 , wherein the number of threshold voltage distributions of the memory cells in the memory device 1100 applying the multi-level cell (MLC) can be four or more. That is, a data storage method for dividing the state of the memory cell into at least four threshold voltage distributions is generally referred to as a multi-level cell (MLC) method. For example, the memory cell may have different types of data depending on the erased state, the first programmed state, the second programmed state, or the third programmed state. The data storage method for dividing the state of the memory cell into eight threshold voltage distributions is referred to as a three-level cell (TLC) method, and the data storage method for dividing the state of the memory cell into 16 threshold voltage distributions is referred to as a quad-level cell (QLC) method. This embodiment can be applied to the multi-level cell (MLC) method, the three-level cell (TLC) method, and the four-level cell (QLC) method, and can also be applied to a method for dividing the state of the memory cell into more than 16 threshold voltage distributions.

[0085] Reference Figure 9 , a threshold voltage distribution of a triple-level cell (TLC) is illustrated as an example.

[0086] In a three-level cell (TLC), a memory cell can have eight threshold voltage distributions. For example, the state of a memory cell can be divided into an erased state ER and a first programming state PV1 to a seventh programming state PV7 according to the threshold voltage distribution. A Gray code can be assigned to a memory cell according to each threshold voltage distribution, and the memory cell can be programmed and read based on the Gray code. In a three-level cell (TLC), one memory cell can be divided into three Gray codes. In a three-level cell (TLC), each Gray code can include a least significant bit (LSB), a center significant bit (CSB), and a most significant bit (MSB), and the state of the memory cell can be divided into eight states according to a combination of Gray codes.

[0087] For example, the Gray code for the erase state ER may be set to "111", the Gray code for the first program state PV1 may be set to "110", and the Gray code for the seventh program state PV7 may be set to "011". The combination of Gray codes may vary depending on the memory device 1100, so the read voltage used in the read operation may also vary depending on the Gray code. The following describes the method by way of example. Figure 9 That is, in an LSB read operation, one LSB read voltage VLSB may be used, in a CSB read operation, two CSB read voltages VCSB may be used, and in an MSB read operation, four MSB read voltages VMSB may be used.

[0088] Therefore, the corresponding read operations for the LSB, CSB, and MSB can be distinguished from each other. Hereinafter, the operation of reading the least significant bit (LSB) from a specific page is designated as an LSB page read operation, the operation of reading the center significant bit (CSB) from a specific page is designated as a CSB page read operation, and the operation of reading the most significant bit (MSB) from a specific page is designated as an MSB page read operation.

[0089] Figure 10 is exemplified in Figure 4 A conceptual diagram of a method for controlling a memory according to a plane interleaved read operation in a multi-plane structured memory device.

[0090] Reference Figure 10Each of the first to fourth control memories CM1 to CM4 may include a main area MA storing codes for overall operations such as program operations, read operations, and erase operations, and a sub-area SA storing codes for performing plane interleaving operations. For example, the sub-area SA may include an LSB code LSBC for performing an LSB page read operation, a CSB code CSBC for performing a CSB page read operation, and an MSB code MSBC for performing an MSB page read operation.

[0091] Although each of the first to fourth control memories CM1 to CM4 Figure 10 Although shown as including a main area MA and a sub-area SA, the main area MA of each of the first to fourth control memories CM1 to CM4 can be configured as a single main memory, and its sub-area SA can be configured as respective auxiliary memories. In this case, the main area MA used to configure the main memory can additionally store a code for performing a plane interleaving operation and then replace one auxiliary memory. In addition, at least one of the main memory and the auxiliary memory can be used to store a code for controlling the operation of the plane interleaving operation. Figure 4 The memory (or area) for storing the control codes of the page buffer groups PBG1 to PBG4 and the memory for storing the remaining control codes are shown, so that the plurality of independent control logics CL1 to CL4 can independently access the control codes for controlling the page buffer groups PBG1 to PBG4 separately from the other control codes. Figure 10 、 Figure 11 and Figure 12 , the control logic 300 may include independent control logic CL1 310 , independent control logic CL2 320 , independent control logic CL3 330 , and independent control logic CL4 340 .

[0092] In addition, the memory controller 1200 may transmit a read command indicating a plane interleaved read operation to the plurality of independent control logics CL1 to CL4 of the memory device 1100. For example, the read command may be one of an LSB read command indicating an LSB page read operation on a plane selected from among the plurality of planes, a CSB read command indicating a CSB page read operation on the selected plane, and an MSB read command indicating an MSB page read operation on the selected plane.

[0093] Hereinafter, the following case will be described: for a plane interleaved read operation, the memory controller 1200 sends an LSB read command for the first plane P1 to the first independent control logic CL1, sends a CSB read command for the second plane P2 to the second independent control logic CL2, sends an MSB read command for the third plane P3 to the third independent control logic CL3, and sends an LSB read command for the fourth plane P4 to the fourth independent control logic CL4. However, the present disclosure is not necessarily limited to this, and the read command to be sent and the control logic to which the corresponding read command is to be sent may be determined based on a request received by the memory controller 1200 from the host 2000.

[0094] First, the first independent control logic CL1 may retrieve an LSB code LSBC from the first control memory CM1 in response to an LSB read command, and may perform an LSB page read operation on the first plane P1 with reference to the retrieved LSB code LSBC at a first time TP1 .

[0095] The second independent control logic CL2 may retrieve a CSB code CSBC from the second control memory CM2 in response to the CSB read command, and may perform a CSB page read operation on the second plane P2 with reference to the retrieved CSB code CSBC at a second time TP2 .

[0096] The third independent control logic CL3 may retrieve the MSB code MSBC from the third control memory CM3 in response to the MSB read command, and may perform an MSB page read operation on the third plane P3 with reference to the retrieved MSB code MSBC at a third time TP3 .

[0097] The fourth independent control logic CL4 may retrieve an LSB code LSBC from the fourth control memory CM4 in response to the LSB read command and may perform an LSB page read operation on the fourth plane P4 with reference to the retrieved LSB code LSBC at a fourth time TP4 .

[0098] As described above, when the plurality of independent control logics CL1 to CL4 each use an independent control memory, the plurality of independent control logics CL1 to CL4 do not access the control memory at the same time, and thus there is an advantage that a read operation can be performed on each plane in parallel.

[0099] However, since each of the control memories CM1 to CM4 can separately store the LSB code LSBC, the CSB code CSBC, and the MSB code MSBC, and the corresponding control logic uses only one of these codes, low storage space efficiency may result. Specifically, when the storage space occupied by the control memories CM1 to CM4 increases, the size of the peripheral circuit 200 increases, and thus the area occupied by the memory cell array 100 in the memory device 1100 decreases.

[0100] Therefore, the following will describe a plane interleaving operation that can minimize and utilize storage space while ensuring the parallel operation of multiple independent control logics to the greatest extent possible.

[0101] Figure 11 is an example of a different Figure 10 A conceptual diagram of a method for configuring a control memory and performing a plane interleaved read operation in the form of a control memory.

[0102] Reference Figure 11 , for the plane interleaved read operation, the following cases will be described: Figure 10 Similarly, the memory controller 1200 sends an LSB read command for the first plane P1 to the first independent control logic CL1, sends a CSB read command for the second plane P2 to the second independent control logic CL2, sends an MSB read command for the third plane P3 to the third independent control logic CL3, and sends an LSB read command for the fourth plane P4 to the fourth independent control logic CL4.

[0103] However, with Figure 10 Depending on the configuration, the control memory 270 may include a common memory CMM and a temporary storage SR that are all accessible to multiple independent control logics CL1 to CL4. For example, the common memory CMM may be a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), etc.

[0104] With reference to above Figure 10 Similar to the first to fourth control memories CM1 to CM4 described, the common memory CMM may include: a main area MA storing codes for overall operations including programming, reading, and erasing operations; and a sub-area SA storing codes for performing plane interleaving operations.

[0105] The temporary storage SR may include areas corresponding to the respective planes P1 to P4 and physically independent of each other, so that a plurality of independent control logics CL1 to CL4 may access the temporary storage SR simultaneously. Figure 4In the example shown in FIG. 1 , when the first to fourth planes P1 to P4 are present, the temporary storage SR may include first to fourth regions AR1 to AR4. Regions AR1 to AR4 may be physically identified shift registers. For example, each of regions AR1 to AR4 may be a shift register configured to delete previously stored data when new data is input. Multiple independent control logics CL1 to CL4 may separately (or independently) access each region AR1 to AR4 to obtain a control code.

[0106] First, the first independent control logic CL1 can determine, in response to an LSB read command, whether the LSB code LSBC corresponding to the received LSB read command is stored in the temporary storage SR. If it is determined that the corresponding LSB code LSBC is not stored in the temporary storage SR, the first independent control logic CL1 can retrieve the LSB code LSBC from the common memory CMM and store the retrieved LSB code LSBC in the first area AR1 of the temporary storage SR. Next, at a first time TP1, the first independent control logic CL1 can perform an LSB page read operation on the first plane P1, referring to the LSB code LSBC stored in the common memory CMM.

[0107] The second independent control logic CL2 can determine, in response to a CSB read command, whether the CSB code CSBC corresponding to the received CSB read command is stored in the temporary storage SR. If it is determined that the corresponding CSB code CSBC is not stored in the temporary storage SR, the second independent control logic CL2 can retrieve the CSB code CSBC from the common memory CMM and store the retrieved CSB code CSBC in the second area AR2 of the temporary storage SR. Subsequently, the second independent control logic CL2 can perform a CSB page read operation on the second plane P2 starting at a second time TP2, with reference to the CSB code CSBC stored in the common memory CMM.

[0108] In response to an MSB read command, the third independent control logic CL3 can determine whether the MSB code MSBC corresponding to the received MSB read command is stored in the temporary storage SR. If it is determined that the corresponding MSB code MSBC is not stored in the temporary storage SR, the third independent control logic CL3 can retrieve the MSB code MSBC from the common memory CMM and store the retrieved MSB code MSBC in the third area AR3 of the temporary storage SR. Thereafter, the third independent control logic CL3 can perform an MSB page read operation on the third plane P3 starting at a third time TP3, with reference to the MSB code MSBC stored in the common memory CMM.

[0109] Furthermore, the fourth independent control logic CL4 can determine, in response to an LSB read command, whether the LSB code LSBC corresponding to the received LSB read command is stored in the temporary storage SR. Because the LSB code LSBC has already been stored in the first area AR1 of the temporary storage SR by the first independent control logic CL1, the fourth independent control logic CL4 can determine that the LSB code LSBC is stored in the temporary storage SR. The fourth independent control logic CL4 can access the temporary storage SR, retrieve the LSB code LSBC from the first area AR1 of the temporary storage SR, and store the retrieved LSB code LSBC in the fourth area AR4 of the temporary storage SR. Thereafter, the fourth independent control logic CL4 can perform an LSB page read operation on the fourth plane P4, starting at a fourth time TP4, with reference to the LSB code LSBC.

[0110] Therefore, even in Figure 11 In the configuration of the control memory 270 shown, similar to Figure 10 , page read operations corresponding to the read commands may be simultaneously performed on a plurality of planes (eg, the first to fourth planes P1 to P4 ) during the overlapping time.

[0111] Figure 12 It is an example of Figure 11 A conceptual diagram of a method for performing a plane interleaved read operation when receiving an additional command in a control memory configuration.

[0112] Reference Figure 12 , the control memory can be connected with Figure 11 The control memory has the same configuration. However, except Figure 11 In addition to the configuration, Figure 12 The following situation is described, in which, in order to perform a plane interleaved read operation, the memory controller 1200 sends an LSB read command for the first plane P1 to the first independent control logic CL1, sends an LSB read command for the second plane P2 to the second independent control logic CL2, sends an LSB read command for the third plane P3 to the third independent control logic CL3, and sends an LSB read command for the fourth plane P4 to the fourth independent control logic CL4.

[0113] First, the first independent control logic CL1 can determine, in response to an LSB read command, whether the LSB code LSBC corresponding to the received LSB read command is stored in the temporary storage SR. If it is determined that the corresponding LSB code LSBC is not stored in the temporary storage SR, the first independent control logic CL1 can retrieve the LSB code LSBC from the common memory CMM and store the retrieved LSB code LSBC in the first area AR1 of the temporary storage SR. Next, the first independent control logic CL1 can perform an LSB page read operation on the first plane P1 at a first time TP1, referring to the LSB code LSBC stored in the common memory CMM.

[0114] In response to an LSB read command, the second independent control logic CL2 can determine whether the LSB code LSBC corresponding to the received LSB read command is stored in the temporary storage SR. Because the LSB code LSBC has already been stored in the first area AR1 of the temporary storage SR by the first independent control logic CL1, the second independent control logic CL2 can determine that the LSB code LSBC is stored in the temporary storage SR. In this case, the second independent control logic CL2 can access the temporary storage SR, retrieve the LSB code LSBC from the first area AR1 of the temporary storage SR, and store the retrieved LSB code LSBC in the second area AR2 of the temporary storage SR. Next, the second independent control logic CL2 can refer to the LSB code LSBC stored in the first area AR1 and perform an LSB page read operation on the second plane P2 starting at the second time TP2.

[0115] In response to an LSB read command, the third independent control logic CL3 can determine whether the LSB code LSBC corresponding to the received LSB read command is stored in the temporary storage SR. Because the LSB code LSBC has already been stored in the second area AR2 of the temporary storage SR by the second independent control logic CL2, the third independent control logic CL3 can determine that the LSB code LSBC is stored in the temporary storage SR. At this time, because the second independent control logic CL2 is accessing the first area AR1 of the temporary storage SR and is currently performing an LSB page read operation, the third independent control logic CL3 cannot access the first area AR1. In this case, the third independent control logic CL3 can retrieve the LSB code LSBC from the second area AR2 of the temporary storage SR and store the retrieved LSB code LSBC in the third area AR3 of the temporary storage SR. Next, the third independent control logic CL3 can refer to the LSB code LSBC stored in the second area AR2 and perform an LSB page read operation on the third plane P3 starting at the third time TP3.

[0116] In response to an LSB read command, the fourth independent control logic CL4 can determine whether the LSB code LSBC corresponding to the received LSB read command is stored in the temporary storage SR. Because the LSB code LSBC has already been stored in the third area AR3 of the temporary storage SR by the third independent control logic CL3, the fourth independent control logic CL4 can determine that the LSB code LSBC is stored in the temporary storage SR. At this time, because the second independent control logic CL2 is accessing the first area AR1 of the temporary storage SR and currently performing an LSB page read operation, while the third independent control logic CL3 is accessing the second area AR2 of the temporary storage SR and currently performing an LSB page read operation, the fourth independent control logic CL4 cannot access the first and second areas AR1 and AR2. In this case, the fourth independent control logic CL4 can retrieve the LSB code LSBC from the third area AR3 of the temporary storage SR and store the retrieved LSB code LSBC in the fourth area AR4 of the temporary storage SR. Thereafter, the fourth independent control logic CL4 can perform an LSB page read operation on the fourth plane P4 at a fourth time TP4, referring to the LSB code LSBC stored in the third area AR3.

[0117] When integrated Figure 11 and Figure 12 , when there is no control code corresponding to the received read command in the temporary storage SR, the plurality of independent control logics CL1 to CL4 can obtain the control code (one of the LSB code, CSB code and MSB code) corresponding to the read command received from the memory controller from the common memory CMM. In addition, when the control code corresponding to the read command is stored in the temporary storage SR, the plurality of independent control logics can obtain the control code from the temporary storage SR. Here, the control code obtained from the common memory CMM or the temporary storage SR can be stored in one of the areas AR1 to AR4 of the temporary storage SR, so that another control logic can refer to the obtained control code. Thereafter, when the same read command is received by another control logic, the operation to be performed on any one plane can be controlled by referring to the control code stored in the temporary storage SR.

[0118] Therefore, even if multiple independent control logics perform read operations simultaneously (or in an interleaved manner) at regular time intervals, another control logic performing the same read operation can obtain the control code stored in the temporary storage SR by the control logic that has been previously started and performed the read operation, thereby minimizing the use of storage space while being able to smoothly perform plane interleaved read operations.

[0119] Figure 13 is an example operation with Figure 10 and Figure 11 An example of a flow chart of a method of controlling memory configuration of a memory device. Figure 14 This is an example Figure 13 An example of a flowchart of a portion of step S110.

[0120] Reference Figure 13 A method for executing a memory device including a plurality of planes may include: step S100, receiving a command instructing an operation on one of the planes from a memory controller; step S110, accessing one of a common memory and a temporary storage commonly accessible by independent control logic, and obtaining a control code corresponding to the command therefrom; and step S120, generating a control signal corresponding to the command with reference to the control code.

[0121] Reference Figure 14 , step S110 of obtaining a control code may include: step S111, determining whether a control code corresponding to the command exists in a temporary storage; and step S112, if it is determined that the control code does not exist in the temporary storage, accessing a common memory and obtaining the control code from the common memory. In an embodiment, the common memory may be accessible to all of the multiple independent control logics CL1 to CL4. In other words, the common memory can be accessed by the independent control logics to obtain the control code.

[0122] The step S110 of acquiring the control code may include: step S111, determining whether a control code corresponding to the command exists in the temporary storage; and step S113, when it is determined that the control code exists in the temporary storage, accessing the temporary storage and acquiring the control code from the temporary storage.

[0123] The method may further include: after the step S110 of acquiring the control code, a step S114 of storing the acquired control code in a temporary storage.

[0124] The temporary storage may include areas corresponding to the respective planes.

[0125] Each region can be a shift register.

[0126] The step S114 of storing the control code in the temporary storage may include storing the control code in an area other than the area from which the control code has been acquired, among the plurality of areas.

[0127] The command may include at least one of an LSB read command, a CSB read command, and an MSB read command.

[0128] The control code may include at least one of: a control code for performing an LSB page read operation corresponding to an LSB read command; a control code for performing a CSB page read operation corresponding to a CSB read command; and a control code for performing an MSB page read operation corresponding to an MSB read command.

[0129] The method may further include the step of performing an operation corresponding to the command on a second plane among the plurality of planes with reference to a control code stored in a first area among the plurality of areas before the operation on the first plane among the plurality of planes is terminated.

[0130] The control code stored in the first area may be a control code for performing the same operation on the first plane as that performed on the second plane.

[0131] The control code stored in the first area may be stored in a second area among the plurality of areas.

[0132] In addition to the above processing, it should also be understood that the above reference Figures 1 to 12 The described configuration of the memory device and the method of operating the same are applicable to a method of operating the memory device.

[0133] Figure 15 This is an example Figure 1 Figure 1. Memory controller diagram.

[0134] Reference Figure 15 , the memory controller 1200 may include an internal memory 1210 , a central processing unit (CPU) 1220 , an error correction block 1230 , a host interface 1240 , a buffer memory interface 1250 , and a memory interface 1260 .

[0135] The internal memory 1210 may store various types of information required for the operation of the memory controller 1200. For example, the internal memory 1210 may include a logical-to-physical address mapping table. The internal memory 1210 may be configured using one or more of a random access memory (RAM), a dynamic RAM (DRAM), a static RAM (SRAM), a cache, and a tightly coupled memory (TCM).

[0136] The central processing unit 1220 may perform various operations for controlling the memory device 1100 or may generate various commands. Figure 1 2000) receives a request, the central processing unit 1220 may generate a command in response to the received request and may send the generated command to the memory device 1100.

[0137] The error correction block 1230 may use an error correction code (ECC) to detect and correct errors in data received from the memory device 1100. The central processing unit 1220 may adjust a read voltage based on the result of error detection performed by the error correction block 1230 and may control the memory device 1100 to perform a reread. In example embodiments, the error correction block may be provided as an element of the memory controller 1200.

[0138] The host interface 1240 may exchange commands, addresses, and data between the memory controller 1200 and the host 2000. For example, the host interface 1240 may receive a request, address, and data from the host 2000, and may output data read from the memory device 1100 to the host 2000. The host interface 1240 may communicate with the host 2000 using a protocol such as Peripheral Component Interconnect Express (PCI-e), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), or Non-Volatile Memory Express (NVMe) protocol. The host interface 1240 is not limited to the above examples and may include various interfaces such as a Universal Serial Bus (USB), a MultiMediaCard (MMC), an Enhanced Small Disk Interface (ESDI), or an Integrated Drive Electronics (IDE) interface.

[0139] The buffer memory interface 1250 can be used between the central processing unit 1220 and the buffer memory (eg, Figure 1 When the buffer memory 1300 is included in the memory controller 1200, the buffer memory interface 1250 may be omitted.

[0140] The memory interface 1260 may exchange commands, addresses, and data between the memory controller 1200 and the memory device 1100. For example, the memory interface 1260 may transmit commands, addresses, data, etc. to the memory device 1100 through a channel, and may receive data, etc. from the memory device 1100.

[0141] Figure 16 is an example including Figure 10 and Figure 11 A diagram of an embodiment of a memory system of a memory device that controls memory configuration.

[0142] Reference Figure 16 , the memory system may include a host 2000 and a memory card 70000 .

[0143] The memory card 70000 may be implemented as a smart card. The memory card 70000 may include a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

[0144] The memory controller 1200 can control the data exchange between the memory device 1100 and the card interface 7100. In an embodiment, the card interface 7100 can be, but is not limited to, a secure digital (SD) card interface or a multimedia card (MMC) interface. In addition, the card interface 7100 can interface the data exchange between the host 2000 and the memory controller 1200 according to the protocol of the host 2000. In an embodiment, the card interface 7100 can support the universal serial bus (USB) protocol and the inter-chip (IC)-USB protocol. Here, the card interface 7100 can refer to hardware that can support the protocol used by the host 2000, software installed in the hardware, or a signal transmission scheme supported by the hardware.

[0145] The present disclosure may provide a memory device capable of efficiently utilizing storage space and a method of operating the memory device.

[0146] CROSS-REFERENCE TO RELATED APPLICATIONS

[0147] This application claims the benefit of Korean Patent Application No. 10-2020-0091955 filed on July 23, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a memory cell array, the memory cell array comprising a plurality of planes; peripheral circuitry that performs operations on the plurality of planes; a control memory storing a control code for controlling the peripheral circuit; as well as a plurality of independent control logics that, upon receiving a command corresponding to each of the plurality of planes from a memory controller, control the peripheral circuit in response to the command with reference to a control code corresponding to the command, Wherein, the control memory includes: a common memory commonly accessible by the plurality of independent control logics; and a temporary storage including a plurality of areas corresponding to the plurality of planes, respectively, and Wherein, each of the plurality of independent control logics: When the control code corresponding to the command exists in the temporary storage, accessing the temporary storage and acquiring the control code from the temporary storage; and When the control code corresponding to the command does not exist in the temporary storage, the common memory is accessed and the control code is acquired from the common memory.

2. The memory device according to claim 1, wherein Each of the plurality of independent control logics: storing the control code acquired from the public memory in one of the plurality of areas of the temporary storage, or The control code acquired from one area among the plurality of areas of the temporary storage is stored in one area among the remaining areas of the temporary storage.

3. The memory device according to claim 1, wherein The command is a command instructing a plane interleaved read operation on the plane, and The command includes at least one of a least significant bit (LSB) read command, a center significant bit (CSB) read command, and a most significant bit (MSB) read command for each of the plurality of planes.

4. The memory device according to claim 3, wherein The control code includes at least one of a control code for performing an LSB page read operation corresponding to the LSB read command, a control code for performing a CSB page read operation corresponding to the CSB read command, and a control code for performing an MSB page read operation corresponding to the MSB read command.

5. The memory device according to claim 3, wherein The public memory includes: a main area storing a control code for performing at least one of a program operation, a read operation, and an erase operation; and A sub-area stores a control code corresponding to the plane interleaving read operation. The memory device according to claim 1 , wherein: Each of the plurality of regions includes a shift register.

7. The memory device according to claim 1, wherein The plurality of independent control logics include: a first independent control logic that stores the control code acquired from the common memory in a first area among the plurality of areas and controls the peripheral circuit so that an operation on the first plane among the plurality of planes is performed with reference to the control code stored in the common memory, and A second independent control logic controls the peripheral circuit so that an operation on a second plane among the plurality of planes is performed with reference to the control code stored in the first area before the operation on the first plane is terminated.

8. The memory device according to claim 7, wherein The control code stored in the first area is a control code for performing the same operation on the first plane as that performed on the second plane.

9. A method of operating a memory device comprising a plurality of planes, the method comprising the steps of: receiving a command from a memory controller indicative of an operation on one of the plurality of planes; accessing one of a common memory and a temporary storage commonly accessible by a plurality of independent control logics and acquiring a control code corresponding to the command; as well as generating a control signal corresponding to the command with reference to the control code, The step of acquiring the control code includes: when the control code corresponding to the command does not exist in the temporary storage, accessing the public memory and acquiring the control code from the public memory.

10. The method according to claim 9, further comprising the steps of: After the control code is acquired, the acquired control code is stored in the temporary storage.

11. The method according to claim 10, wherein: The temporary storage includes a plurality of areas respectively corresponding to the plurality of planes.

12. The method according to claim 11, wherein Each of the plurality of regions includes a shift register.

13. The method according to claim 11, wherein The step of storing the acquired control code in the temporary storage comprises the following steps: The control code is stored in one of the remaining areas among the plurality of areas except for the area from which the control code was acquired.

14. The method according to claim 9, wherein The command includes at least one of a least significant bit (LSB) read command, a center significant bit (CSB) read command, and a most significant bit (MSB) read command.

15. The method according to claim 14, wherein The control code includes at least one of a control code for performing an LSB page read operation corresponding to the LSB read command, a control code for performing a CSB page read operation corresponding to the CSB read command, and a control code for performing an MSB page read operation corresponding to the MSB read command.

16. The method according to claim 11, wherein The step of obtaining the control code comprises the following steps: obtaining the control code from the public memory; and The step of generating the control signal comprises the following steps: storing the control code acquired from the public memory in a first area among a plurality of areas; performing an operation on a first plane among the plurality of planes with reference to the control code stored in the common memory; and Before the operation on the first plane is terminated, an operation is performed on a second plane among the plurality of planes with reference to the control code stored in the first area.

17. The method according to claim 16, wherein The control code stored in the first area is a control code for performing the same operation on the first plane as that performed on the second plane.

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