A high-reliability trench-gate silicon carbide MOSFET device

Abstract

This invention provides a high-reliability trench-gate silicon carbide MOSFET device, comprising: an N+ type substrate, an N- type drift region, a first P region, a P+ contact region, an N+ contact region, an N-type equivalent resistance region located between the first P region and the N+ contact region, a gate dielectric layer, a trench gate, an isolation dielectric layer, a source electrode, and a drain electrode. The SiC MOSFET device proposed in this invention adds an N-type equivalent resistance region, which acts as a series resistor. When a short circuit occurs, this reduces the saturation current of the device and improves its short-circuit capability.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, and more particularly, to a trench-gate silicon carbide MOSFET device with high reliability. BACKGROUND

[0002] Silicon carbide (SiC) material, as a kind of wide band gap semiconductor material, has the advantages of high breakdown field, high saturation electron drift rate, high thermal conductivity, etc., so that silicon carbide power semiconductor devices can realize high voltage, high power, high frequency, high temperature application, and can improve the efficiency of power electronic devices, reduce the size and weight of the device, and have more advantages than traditional silicon-based devices.

[0003] Silicon carbide MOSFET is one of the new types of wide band gap power semiconductor devices. Compared with Si MOSFET or Si IGBT, SiC MOSFET has lower on-resistance, stronger high temperature resistance and faster switching speed. However, due to its small chip area, high current density and thin gate oxide, the short circuit reliability of SiC MOSFET is tested. At present, the commercialized silicon carbide MOSFET is mainly divided into two types: planar type and trench gate type. The manufacturing process of the planar type is relatively simple, but the disadvantages are the increase of cell area and the increase of on-resistance. The traditional trench gate MOSFET structure as shown in Figure 1 , which can realize smaller cell size and higher channel mobility, thereby greatly reducing the on-resistance of the device, is an important development branch of silicon carbide MOSFET.

[0004] Compared with the planar MOSFET, the trench gate MOSFET has better channel utilization and eliminates the resistance brought by the JFET region, but its deep trench etching technology has great challenges in process. The topography of the etched surface, including etching depth, etching vertical angle, etching sidewall and etching bottom roughness, slot bottom angle, etc., have a great influence on the performance of the device.

[0005] When the silicon carbide trench gate MOSFET works in the blocking state, the high reverse bias is borne by the depletion region formed in the N-drift region. Since the silicon carbide material has a relatively high critical breakdown field, the position of the drift region trench gate bottom will have an electric field concentration effect, and will reach a very high electric field when approaching breakdown. Under the blocking state, the oxide layer electric field strength is about 2.8 times the highest electric field in the silicon carbide material, and the curvature effect makes the oxide layer corner gather extremely high electric field. Long-term work in high electric field will cause the gate oxide layer to degrade, which puts high requirements on the reliability of the gate medium.

[0006] In actual circuit, two kinds of short circuit faults can occur. The first fault is called load short circuit. When the device is working normally, the load is suddenly short circuited, and the device is rapidly switched from normal working state to high voltage and large current working state. The other fault is called hard switching short circuit. When the initial state of the device is off, the load is already short circuited, and a turn-on signal is suddenly given to the device, and the drain-source electrode still bears a high voltage. The device is rapidly switched from zero current state to large current state. When the device is short circuited, a large current will flow, and the device will generate a lot of heat. Since the trench gate MOSFET has a small area and a small on-resistance, a larger short circuit current will be generated, which poses a severe challenge to the reliability of the device. SUMMARY

[0007] The present application aims to provide a high-reliability trench gate silicon carbide MOSFET device. By adding a lower-doped N-type equivalent resistance region on the upper part of the first P region, an equivalent series resistance is added to the source region of the device when the device is turned on. When the device is short circuited, the series resistance can reduce the saturation current, thereby improving the short circuit capability of the device.

[0008] According to an embodiment of the present application, a high-reliability trench gate silicon carbide MOSFET device is provided, comprising: an N+ type substrate, a drain electrode located below the N+ type substrate, an N- type drift region located above the N+ type substrate, a trench gate region, a gate dielectric, a first P region located above the N- type drift region, an N-type equivalent resistance region located above the first P region, an N+ contact region located above the N-type equivalent resistance region, a source electrode located above the N+ contact region, an isolation dielectric region located above the trench gate region, and a P+ contact region penetrating through the N+ contact region, the N-type equivalent resistance region and extending to the first P region.

[0009] According to another embodiment of the present application, a high-reliability trench gate silicon carbide MOSFET device is provided, comprising: an N+ type substrate, a drain electrode located below the N+ type substrate, an N- type drift region located above the N+ type substrate, a trench gate region, a gate dielectric, a first P region located above the N- type drift region, an N-type equivalent resistance region located above the first P region, an N+ contact region located above the N-type equivalent resistance region, a source electrode located above the N+ contact region, an isolation dielectric region located above the trench gate region, a P+ contact region penetrating through the N+ contact region, the N-type equivalent resistance region and extending to the first P region, and a second P region formed between the gate dielectric and the N-type equivalent resistance region, wherein the doping concentration of the N-type equivalent resistance region is greater than the doping concentration of the N- type drift region and less than the doping concentration of the N+ contact region, and the doping concentration of the second P region is greater than the doping concentration of the N- type drift region.

[0010] According to another embodiment of the present application, a high-reliability trench gate silicon carbide MOSFET device is provided, comprising: an N+ substrate, a drain electrode located below the N+ substrate, an N- drift region located above the N+ substrate, a trench gate region, a gate dielectric, a first P region located above the N- drift region, an N equivalent resistance region located above the first P region, an N+ contact region located above the N equivalent resistance region, a source electrode located above the N+ contact region, an isolation dielectric region located above the trench gate region, a P+ contact region penetrating through the N+ contact region, the N equivalent resistance region and extending to the first P region, a second P region formed between the gate dielectric and the N equivalent resistance region, and an N_CSL current spreading region formed between the first P region and the N- drift region, wherein a doping concentration of the N equivalent resistance region is greater than a doping concentration of the N- drift region and less than a doping concentration of the N+ contact region, a doping concentration of the second P region is greater than the doping concentration of the N- drift region, and a doping concentration of the N_CSL current spreading region is greater than the doping concentration of the N- drift region and less than the doping concentration of the N+ contact region.

[0011] The material used in the device is SiC material, and can also be other semiconductor materials.

[0012] The beneficial effect of the present application is that when the device is short-circuited, the N equivalent resistance region functions as a series resistance, which can reduce the saturation current of the device and improve the short-circuit capability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 It is a traditional trench gate SiC MOSFET device.

[0014] Figure 2 It is a structure schematic diagram of a high-reliability trench gate silicon carbide MOSFET device according to an embodiment of the present application.

[0015] Figure 3 It is a trench gate silicon carbide MOSFET device according to an embodiment of the present application. Figure 2 It is an equivalent current path diagram when the trench gate silicon carbide MOSFET device is forwardly turned on.

[0016] Figure 4 It is a structure schematic diagram of a high-reliability trench gate silicon carbide MOSFET device according to another embodiment of the present application.

[0017] Figure 5 It is a structure schematic diagram of a high-reliability trench gate silicon carbide MOSFET device according to another embodiment of the present application.

[0018] Figure 6 It is a structure schematic diagram of a high-reliability trench gate silicon carbide MOSFET device according to another embodiment of the present application.

[0019] Figure 7 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0020] Figure 8 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0021] Figure 9 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0022] Figure 10 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0023] Figure 11 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0024] Figure 12 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0025] Figure 13 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0026] Figure 14 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application; Figure 13 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0027] Figure 15 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0028] Figure 16 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0029] Figure 17 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0030] Figure 18 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application;

[0031] Figure 19 A structure schematic diagram of a high-reliability trench gate type silicon carbide MOSFET device according to another embodiment of the present application.

[0032] 1 is N+ substrate, 2 is N- drift region, 3 is first P region, 4 is N+ contact region, 5 is P+ contact region, 6 is slot gate, 7 is gate dielectric, 8 is N_CSL current diffusion region, 9 is N equivalent resistance region, 10 is second N region, 11 is P+ shielding layer, 12 is second P region, 13 is drain electrode, 14 is source electrode, 15 is isolation dielectric region, wherein the N+ substrate 1 has a similar doping concentration to the N+ contact region 4, the N_CSL current diffusion region 8 has a similar doping concentration to the N equivalent resistance region 9 and the second N region 10, and the doping concentration order is: N+ substrate 1, N+ contact region 4 > N_CSL current diffusion region 8, N equivalent resistance region 9, second N region 10 > N- drift region; the P doping concentration order is: P+ contact region 5 > P+ shielding layer 11 > first P region 3, second P region 12. The N+ doping mentioned in the embodiment of the application can be, but is not limited to, greater than or equal to 1×1018cm-3, the N doping can be, but is not limited to, 1×1018cm-3to 1×1019cm-3, the N- doping can be, but is not limited to, 5×1018cm-3to 8×1018cm-3, the P+ doping can be, but is not limited to, greater than or equal to 1×1018cm-3, and the P doping can be, but is not limited to, 1×1018cm-3. 19 cm -3 , the N doping can be, but is not limited to, 1×1018cm-3to 1×1019cm-3, the N- doping can be, but is not limited to, 5×1018cm-3to 8×1018cm-3, the P+ doping can be, but is not limited to, greater than or equal to 1×1018cm-3, and the P doping can be, but is not limited to, 1×1018cm-3. 16 cm -3 . 17 cm -3 , the N doping can be, but is not limited to, 1×1018cm-3to 1×1019cm-3, the N- doping can be, but is not limited to, 5×1018cm-3to 8×1018cm-3, the P+ doping can be, but is not limited to, greater than or equal to 1×1018cm-3, and the P doping can be, but is not limited to, 1×1018cm-3. 15 cm -3 . 15 cm -3 , the N doping can be, but is not limited to, 1×1018cm-3to 1×1019cm-3, the N- doping can be, but is not limited to, 5×1018cm-3to 8×1018cm-3, the P+ doping can be, but is not limited to, greater than or equal to 1×1018cm-3, and the P doping can be, but is not limited to, 1×1018cm-3. 19 cm -3 . 17 cm -3 . DETAILED DESCRIPTION

[0033] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments described herein are only used for illustration and do not limit the present application. In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the present application. Each item of detail in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0034] Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in an embodiment" or "one example" or "an example" in various places in the specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments or examples. In addition, the person of ordinary skill in the art will understand that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. The same reference numbers in different drawings represent the same element. The term "and / or" as used herein means any and all combinations of one or more of the associated listed items.

[0035] As shown in Figure 2 , the high-reliability trench-gate silicon carbide MOSFET device of the present embodiment includes: an N+ substrate 1, a drain electrode 13 located below the N+ substrate 1, an N- drift region 2 located above the N+ substrate 1, a gate dielectric 7, a trench gate region 6, a first P region 3 located above the N- drift region 2, an N equivalent resistance region 9 located above the first P region 3, an N+ contact region 4 located above the N equivalent resistance region 9, a source electrode 14 located above the N+ contact region 4, an isolation dielectric region 15 located above the trench gate region 6, and a P+ contact region 5 penetrating through the N+ contact region 4, the N equivalent resistance region 9, and extending to the first P region 3. The gate dielectric 7 is located around the trench gate region 6 and in the N- drift region 2. The P+ contact region 5 penetrates through the N+ contact region 4, the N equivalent resistance region 9, the first P region 3, and extends to the N- drift region 2. The doping concentration of the N equivalent resistance region 9 is greater than the doping concentration of the N- drift region and less than the doping concentration of the N+ contact region.

[0036] The working principle of the present embodiment is as follows:

[0037] When the device is working in the on state, a positive bias is applied to the gate dielectric 7, which induces an electron inversion layer in the first P region 3. After a certain positive voltage is applied between the drain electrode 13 and the source electrode 14, a first current Ia Figure 3 flows through the N+ substrate 1, the N- drift region 2, the conductive channel in the first P region 3, the N equivalent resistance region 9, and the N+ contact region 4 to the source electrode, and the equivalent current path is as shown in Figure 3 , wherein the N equivalent resistance region 9 can be equivalent to a first resistance Ra. When the device is short-circuited, the presence of the N equivalent resistance region 9 can reduce the saturation current of the device, improve the short-circuit capability of the device, and enhance the reliability of the device.

[0038] AsFigure 4 The device structure and the working principle of the embodiment shown in Figure 2 The difference between the embodiment shown in

[0039] As shown in Figure 5 The device structure and the working principle of the embodiment shown in Figure 2 The difference between the embodiment shown in

[0040] As shown in Figure 6 The device structure and the working principle of the embodiment shown in Figure 5 The difference between the embodiment shown in

[0041] As shown in Figure 7 The device structure and the working principle of the embodiment shown in Figure 6 The difference between the embodiment shown in

[0042] As shown in Figure 8 The device structure and the working principle of the embodiment shown in Figure 5 The difference between the embodiment shown in

[0043] As shown in Figure 9 The device structure and the working principle of the embodiment shown in Figure 2 The difference between the embodiment shown in

[0044] As shown in Figure 10 The device structure and the working principle of the embodiment shown in Figure 2The difference in the illustrated embodiment is that the P+ contact region 5 penetrates the N+ contact region 4, the N-type equivalent resistance region 9, the first P region 3, and extends to the N-type drift region 2. There is an N-CSL current diffusion region 8 between the first P region 3 and the N-type drift region 2. The N-CSL current diffusion region 8 has a small area and is only distributed on the sidewall of the gate dielectric 7, not on the bottom of the gate dielectric 7. A second N region 10 is provided between the P+ contact region 5 and the N-type drift region 2.

[0045] like Figure 11 As shown, the device structure and... Figure 2 The difference in the illustrated embodiment is that a P+ shielding layer 11 is provided at the bottom of the gate dielectric 7. The P+ contact region 5 can either extend through only the N+ contact region 4, the N-type equivalent resistance region 9, and the first P region 3, or it can extend to the N-type drift region 2. The advantage of this is that, in the blocking state, the P+ shielding layer 11 can shield the electric field at the bottom of the gate dielectric 7, reducing the field strength at the corners of the gate dielectric 7 and protecting the gate dielectric 7.

[0046] like Figure 12 As shown, the device structure and... Figure 11 The difference in the embodiment shown is that there is an N-CSL current diffusion region 8 between the first P region 3 and the N-type drift region 2. The N-CSL current diffusion region 8 can be distributed only on the sidewall of the gate dielectric 7, or it can be distributed on both the sidewall and the bottom of the gate dielectric 7.

[0047] like Figure 13 As shown, the device structure and... Figure 2 The difference in the illustrated embodiment is that a second P-region 12 is added between the gate dielectric 7 and the N-type equivalent resistance region 9. The P+ contact region 5 can either extend through only the N+ contact region 4, the N-type equivalent resistance region 9, and the first P-region 3, or it can extend to the N-type drift region 2. The doping concentration of the N-type equivalent resistance region 9 is greater than that of the N-type drift region but less than that of the N+ contact region. The doping concentration of the second P-region is greater than that of the N-type drift region. The second P-region 12 is located on the vertical sidewall of the trench gate region 6 and contacts the first P-region 3. The equivalent current path of the device during forward conduction is as follows: Figure 14 As shown, the second P region 12 can be equivalent to a second resistor Rb. The advantage of this is that when a short circuit occurs, the second current Ib ( Figure 14 The line with the arrow represents the flow path of the second current Ib. It will pass through the inversion laminar flow of electrons induced in the second P region 12 to the source, reducing the saturation current of the device and improving its short-circuit capability.

[0048] like Figure 15 As shown, the device structure and... Figure 13The difference between the embodiment shown in Fig. 4 and the embodiment shown in Fig. 3 is that there is an N_CSL current spreading region 8 between the first P region 3 and the N-type drift region 2, which can be distributed only on the sidewall of the gate dielectric 7 or on the sidewall and the bottom of the gate dielectric 7.

[0049] As shown in Fig. 5, the device structure of the embodiment and the device structure of the embodiment shown in Fig. 4 are the same. Figure 16 The difference between the embodiment shown in Fig. 6 and the embodiment shown in Fig. 5 is that a P+ shielding layer 11 is arranged at the bottom of the gate dielectric 7. Figure 13 As shown in Fig. 7, the device structure of the embodiment and the device structure of the embodiment shown in Fig. 6 are the same.

[0050] The difference between the embodiment shown in Fig. 8 and the embodiment shown in Fig. 7 is that there is an N_CSL current spreading region 8 between the first P region 3 and the N-type drift region 2, which can be distributed only on the sidewall of the gate dielectric 7 or on the sidewall and the bottom of the gate dielectric 7. Figure 17 Figure 16 As shown in Fig. 9, the device structure of the embodiment and the device structure of the embodiment shown in Fig. 8 are the same. The difference between the embodiment shown in Fig. 10 and the embodiment shown in Fig. 9 is that a P+ shielding layer 11 is arranged at the bottom of the gate dielectric 7.

[0051] Figure 18 As shown in Fig. 11, the device structure of the embodiment and the device structure of the embodiment shown in Fig. 10 are the same. Figure 13 The difference between the embodiment shown in Fig. 12 and the embodiment shown in Fig. 11 is that the P+ contact region 5 penetrates the N+ contact region 4, the N-type equivalent resistance region 9, the first P region 3 and extends to the N-type drift region 2, and a second N region 10 is arranged between the P+ contact region 5 and the N-type drift region 2.

[0052] As shown in Fig. 13, the device structure of the embodiment and the device structure of the embodiment shown in Fig. 12 are the same. Figure 19 The difference between the embodiment shown in Fig. 14 and the embodiment shown in Fig. 13 is that there is an N_CSL current spreading region 8 between the first P region 3 and the N-type drift region 2, which has a small area and is distributed only on the sidewall of the gate dielectric 7 and not on the bottom of the gate dielectric 7, and the P+ contact region 5 penetrates the N+ contact region 4, the N-type equivalent resistance region 9, the first P region 3, the N_CSL current spreading region 8 and extends to the N-type drift region 2. Figure 18 In other embodiments of the present application, the above-mentioned doping types can be changed to the opposite doping, for example, the P-type doping is changed to the N-type doping while the N-type doping is changed to the P-type doping.

[0053] The present application relates to the combination structure and application of multiple different regions, which are not listed one by one in the embodiments of the present application, and those skilled in the art should know that, in other embodiments, different combinations based on the structure of the present application should also be regarded as one of the embodiments of the present application.

[0054]

[0055] ​​While the application has been described with reference to several exemplary embodiments, it is to be understood that the use of other words or terminologies used herein is intended to convey a practical, and conceptual meaning and not a limiting meaning as used in any particular exemplary embodiment. It is therefore submitted that the foregoing disclosure of exemplary embodiments of the application are intended for illustrative purposes only and not for limiting the scope of the application as contemplated by the appended claims and their equivalents.

Claims

1. A high-reliability trench-gate silicon carbide MOSFET device, comprising: The N+ type substrate, the drain electrode located below the N+ type substrate, the N- type drift region located above the N+ type substrate, the slot gate region, the gate dielectric, the first P type region located above the N- type drift region, the N type equivalent resistance region located above and in contact with the first P type region, the N+ type contact region located above and in contact with the N type equivalent resistance region, the source electrode located above the N+ type contact region and the isolation dielectric region located above the slot gate region; the second P type region formed between the gate dielectric and the N type equivalent resistance region, the second P type region located at the vertical side wall of the slot gate region and in contact with the first P type region; the N_CSL current diffusion region formed between the first P type region and the N- type drift region, and the N_CSL current diffusion region only distributed on the side wall of the gate dielectric; the second N type region formed in the N- type drift region, the second N type region spaced apart from the N_CSL current diffusion region, the P+ type contact region penetrating the N+ type contact region, the N type equivalent resistance region, the first P type region, the part of the N- type drift region located between the N_CSL current diffusion region and the second N type region, thereby extending to the second N type region; The second N type region formed between the P+ type contact region and the N- type drift region; the doping concentration of the N type equivalent resistance region is greater than the doping concentration of the N- type drift region and less than the doping concentration of the N+ type contact region, the doping concentration of the second P type region is greater than the doping concentration of the N- type drift region, the doping concentration of the N_CSL current diffusion region is greater than the doping concentration of the N- type drift region and less than the doping concentration of the N+ type contact region, and the doping concentration of the second N type region is greater than the doping concentration of the N- type drift region.

Images