Photodiode and / or PIN diode structures

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to photodiode and / or PIN diode structures and methods of manufacturing. The structure includes: a spiral fin structure including a semiconductor substrate material and a dielectric material; a photosensitive semiconductor material located on the sidewalls and top surface of the spiral fin structure, the photosensitive semiconductor material being positioned to capture incident light emitted from the side; a doped semiconductor material located above the photosensitive semiconductor material; and a contact electrically contacting the semiconductor substrate material and the doped semiconductor material from the top surface of the semiconductor substrate material and the doped semiconductor material.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly, to photodiode and / or PIN diode structures and methods of fabrication. Background Art

[0002] Avalanche photodiodes (APDs) are highly sensitive semiconductor photodiodes that use the photoelectric effect to convert light into electricity. From a functional point of view, avalanche photodiodes can be considered as the semiconductor analog of photomultiplier tubes. Typical applications for avalanche photodiodes are long-distance fiber optic components for control algorithms, telecommunications, and quantum sensing. Newer applications include positron emission tomography and particle physics.

[0003] The applicability and usefulness of an avalanche photodiode depends on many parameters. For example, two factors are quantum efficiency and total leakage. Quantum efficiency indicates the degree to which incident optical photons are absorbed and then used to generate primary charge carriers; while total leakage current is the sum of dark current, photocurrent and noise.

[0004] Photodiode sensitivity relies on the length of the path that light takes through the photosensitive material and the ability of the generated carrier pairs to reach the electrode / contact / cathode. In conventional structures, carriers travel in a two-dimensional path, for example, vertically or laterally, which results in a long path. Due to the longer path of conventional avalanche photodiodes, there is a high frequency of photon recombination within the photosensitive material, resulting in signal loss itself or attenuation of the signal. In addition, the photosensitive material itself needs to be very thick, which is expensive and time-consuming to grow, and can make integration with other circuit elements more challenging. Summary of the invention

[0005] In aspects of the present disclosure, a structure includes: a spiral fin structure including a semiconductor substrate material and a dielectric material; a photosensitive semiconductor material located on the sidewalls and top surface of the spiral fin structure, the photosensitive semiconductor material being positioned to capture incident light emitted from the side; a doped semiconductor material located above the photosensitive semiconductor material; and a contact electrically contacting the semiconductor substrate material and the doped semiconductor material from the top surface of the semiconductor substrate material and the doped semiconductor material.

[0006] In aspects of the present disclosure, a structure includes: a spiral fin structure, which includes a semiconductor substrate material in a substrate-on-insulator (SOI) technology; a shallow trench isolation region, which is located within the body of the spiral fin structure; a first semiconductor material, which lines the sidewalls and top surface of the spiral fin structure; a photosensitive semiconductor material, which is located above a doped semiconductor material and an insulator layer in the SOI technology; a doped semiconductor material, which is located above the photosensitive semiconductor material; and a contact, which electrically contacts the semiconductor substrate material and the second semiconductor material.

[0007] In aspects of the present disclosure, a method includes: forming a first shallow trench isolation structure in a spiral configuration within a semiconductor material in a substrate-on-insulator (SOI) technology; forming a second shallow trench isolation structure adjacent to the first shallow trench isolation structure; forming a spiral fin structure including the semiconductor material and the first shallow trench isolation structure, the spiral fin structure being formed above an insulator layer in the SOI technology and being defined by the second shallow trench isolation structure; lining the sidewalls and top surface of the spiral fin structure with a first semiconductor material; forming a photosensitive semiconductor material above the first semiconductor material and the insulator layer; forming a second semiconductor material above the photosensitive semiconductor material; and forming a first contact electrically contacting the semiconductor substrate material and a second contact electrically contacting the second semiconductor material on one side of the spiral fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is described in the following detailed description by way of non-limiting examples of exemplary embodiments of the present disclosure and with reference to the several accompanying drawings.

[0009] Figure 1 A substrate having shallow trench isolation regions and a corresponding fabrication process according to, among other features, aspects of the present disclosure are shown.

[0010] Figure 2 A spiral fin structure formed from a substrate and a corresponding manufacturing process are shown, among other features, in accordance with aspects of the present disclosure.

[0011] Figure 3 Photodiode materials filling spaces between spiral fin structures and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0012] Figure 4 A spiral photodiode according to aspects of the present disclosure is shown.

[0013] Figure 5 Contact formation to a spiral photodiode and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0014] Figure 6 It is along Figure 5Top view of the photodiode structure along line "A"-"A".

[0015] Figure 7 A photodiode is shown coupled to a demultiplexer / splitter in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure relates to semiconductor structures, and more specifically, to photodiode and / or PIN diode structures and methods of manufacture. More specifically, the present disclosure relates to spiral photodiode and / or pin diode structures comprised of semiconductor fin structures. Advantageously, the present disclosure provides reduced time for growth of photodiode material (e.g., Ge) by providing an increased semiconductor seed surface area, while also allowing for an overall reduction in the thinner photodiode material (e.g., Ge) region and area required to absorb light relative to a linear photodetector. In addition, the structures described herein provide an increase in detection efficiency due to a shorter path for carrier formation and a longer path for light absorption through the photodetector material (e.g., Ge).

[0017] In an embodiment, the photodiode is a spirally configured photodiode composed of a photodetector material (e.g., Ge) formed on a spiral fin structure of a substrate material. The spiral fin structure itself includes an insulator material located within the body of the fin structure and is surrounded by a shallow trench isolation region outside the spiral fin structure. The shallow trench isolation region outside the spiral fin structure guides light to the photodetector material to "trap" the incident light, thereby maximizing the chance of carrier formation. The photodiode is also integrated into a semiconductor on insulator (SOI) technology suitable for lateral illumination. In addition, the photodiode can be integrated with a waveguide structure and laterally spaced apart from the waveguide structure.

[0018] As will be described herein, the larger surface area of ​​the spiral fin structure will facilitate the growth of photodetector material (e.g., Ge). In addition, the spiral fin structure within the Ge detector region will provide improved efficiency by increasing the surface capture area. For example, the spiral capture region will have a larger surface area compared to a linear shape. Thus, a spiral photodiode can provide improved efficiency by increasing the surface area compared to a concentric circle configuration, as well as avoiding the risk of destructive interference that exists in a concentric circle or simple ring configuration.

[0019] The structure of the present disclosure can be manufactured in a variety of ways using a variety of different tools. In general, methods and tools are used to form structures with micrometer and nanometer sizes. The method for manufacturing the structure of the present disclosure, i.e., technology, has been adopted from integrated circuit (IC) technology. For example, the structure can be built on a wafer and realized with a material film patterned by a photolithography process. In particular, the manufacture of the structure uses three basic building blocks: (i) thin film material is deposited on a substrate, (ii) a patterned mask is applied on top of the film by photolithography imaging, and (iii) the film is selectively etched to the mask.

[0020] Figure 1 A substrate with shallow trench isolation regions and a corresponding manufacturing process are shown according to aspects of the present disclosure, among other features. More specifically, structure 10 includes substrate 12, which preferably includes semiconductor-on-insulator (SOI) technology. Alternatively, substrate 12 may be a bulk Si implementation.

[0021] In SOI technology, substrate 12 includes a semiconductor wafer 12a together with an insulator layer 12b and a semiconductor substrate 12c. Insulator layer 12b can be any suitable insulator material, including silicon oxide, sapphire, other suitable insulating materials and / or combinations thereof. Exemplary insulator layer 12b is a buried oxide (BOX) formed on semiconductor wafer 12a by separate implantation of oxygen (SIMOX), oxidation, deposition and / or other suitable processes. Semiconductor wafer 12a and semiconductor substrate 12c can include any suitable semiconductor material, such as single crystal Si material. By way of further example, semiconductor substrate 12c can be composed of SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. In a preferred embodiment, semiconductor substrate 12c is an n-type substrate.

[0022] In order to form the shallow isolation regions 14, 16, conventional photolithography and etching processes known to those skilled in the art are used to form trenches in the semiconductor substrate 12c. In a non-limiting example, the trenches extend to the underlying insulator layer 12b, wherein one of the trenches is a spiral pattern. When forming the trenches, the resist formed on the semiconductor substrate 12c is exposed to energy (light) to form a pattern (opening). An etching process using a selective chemistry such as reactive ion etching (RIE) will be used to form the trenches in the semiconductor substrate 12c. Post-etch cleaning such as HF will remove contaminants from the surface of the trenches, thereby ensuring a clean surface of the exposed semiconductor material of the bottom surface and sidewalls of the trenches.

[0023] After resist removal by conventional oxygen ashing process or other known strippers, an insulator material may be deposited within the trenches to form shallow trench isolation regions 14, 16. In an embodiment, the shallow trench isolation region 14 is provided in a spiral configuration; and the shallow trench isolation region 16 is formed outside (adjacent) the shallow trench isolation region 14. The insulator material may be an oxide material deposited by conventional deposition methods including, for example, a chemical vapor deposition (CVD) process. In an embodiment, the insulator material exhibits reflective properties that are designed to reflect light back into the photodiode material. After depositing the insulator material (e.g., SiO2), the pad nitride layer located on top of the semiconductor substrate 12c may be removed, resulting in shallow trench isolation regions 14, 16 extending above the surface of the semiconductor substrate 12c.

[0024] refer to Figure 2 , a hard mask 18 is deposited on the semiconductor substrate 12c. In an embodiment, the hard mask 18 may be a nitride or other hard mask material deposited by a known deposition method such as a CVD process. In an embodiment, the hard mask 18 will prevent epitaxial growth of semiconductor material on the semiconductor substrate 12c in subsequent processes.

[0025] After depositing the hard mask 18, a conventional etching process will be used to form a spiral fin structure 22 in the semiconductor substrate 12c. For example, the spiral fin structure 22 may be formed by a secondary etching process using the resist material 20 to form a spiral groove 24, thereby defining the spiral fin structure 22. Alternatively, the spiral fin structure 22 may be formed by a sidewall imaging technique (SIT) known in the art, so that further explanation is not required for a complete understanding of the present disclosure.

[0026] In an embodiment, the body of the spiral fin structure 22 includes the spiral shallow trench isolation region 14 while also being bounded by the shallow trench isolation structure 16 and the underlying insulator material 12b. After the etching process, the resist 20 may be removed by conventional oxygen ashing or use of other strippers.

[0027] exist Figure 3 In the embodiment of the present invention, the hard mask 18 located above the spiral fin structure 22 can be removed by a conventional patterning process such as a photolithography and etching process to expose the semiconductor material 12c of the spiral fin structure 22. The removal of the hard mask 18 will allow epitaxially grown semiconductor material to be deposited on all exposed surfaces of the spiral fin structure 22. For example, a photodiode material 26 (e.g., a Ge-based material) with an optional liner 28 can be grown within the spiral trench 24 (e.g., on the sidewalls and top surface of the spiral fin structure 22). The remaining hard mask 18 will prevent the growth of epitaxial semiconductor material outside the spiral fin structure 22.

[0028] In an embodiment, the liner 28 may be an epitaxially grown semiconductor material, such as a P-type semiconductor material, preferably composed of the same material as the substrate 12c (e.g., Si). The photodiode material 26 is epitaxially grown on the liner 28, or alternatively epitaxially grown directly on the semiconductor material 12c of the spiral fin structure 22. In an embodiment, the photodiode material 26 is an intrinsic photosensitive semiconductor material (non-doped), which preferably includes a Ge material that provides excellent responsiveness. In an alternative embodiment, the photodiode material 26 may be Si, SiGe, etc. In a preferred implementation, the epitaxial growth of the photodiode material 26 will not result in a pinch-off phenomenon, thereby leaving an opening 30 in the space formed between the spiral fin structures 22.

[0029] like Figure 3 As further shown in FIG. 1 , the photodiode material 26 will be bounded (e.g., surrounded) by the shallow trench isolation region 14 within the body of the spiral fin structure 22, the shallow trench isolation region 16 adjacent to the spiral fin structure 22, and the underlying insulator material 12 c. In this way, the reflective surface of the insulator material will surround (e.g., be provided on all sides) the photodiode material 26 so that light can be directed back into the photodiode material 26 to maximize carrier formation, i.e., achieve high efficiency. The photodiode material 26 will also take on a spiral shape due to its placement within the spiral trench, which provides a longer path (from one end to its center) to maximize absorption of any incident light.

[0030] exist Figure 4 In the embodiment, semiconductor material 32 is deposited in opening 30 directly on photodiode material 26 (e.g., Ge). In an embodiment, semiconductor material 32 will also grow on the upper exposed surface of photodiode material 26 (e.g., Ge). Semiconductor material 32 is preferably the same material as liner 28. For example, semiconductor material 32 is a P+ type semiconductor material (e.g., epitaxial Si or polysilicon). Figure 4 In FIG. 1 , after the growth of semiconductor material 32 , hard mask 18 is removed by a selective etching process.

[0031] In an embodiment, semiconductor material 32 is a P+ plug to provide bias for operation of avalanche photodiode 25. In this way, a NPIP photodiode 25 can be formed. More specifically, the P+ material (e.g., semiconductor material 32 and P+ material (e.g., liner 28)) located on the side and bottom of the Ge material (e.g., semiconductor material 26) creates an avalanche photodiode 25 that is biased in three dimensions, thereby increasing the probability of picking up a signal before carrier recombination.

[0032] Figure 5The contact formation to the photodiode 25 and the corresponding manufacturing process are shown, among other features. Figure 5 In the embodiment of the present invention, a silicide contact 34 is formed on the exposed surface of the semiconductor substrate 12c and the top of the photodiode 25 (e.g., on the semiconductor material 32). As is well known to those skilled in the art, the silicide process begins by depositing and patterning a thin transition metal layer (e.g., nickel, cobalt, or titanium) over the semiconductor substrate 12c and the top of the photodiode 25. After the deposition and patterning of the material, the structure is heated, allowing the transition metal to react with the exposed silicon (or other semiconductor materials described herein) to form a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving the silicide contact 34.

[0033] Still reference Figure 5 , an interlayer dielectric material (e.g., oxide) 36 is deposited on the structure. A trench is formed in the interlayer dielectric material (e.g., oxide) 36 that is aligned with and exposes the top surface of the silicide contact 34. The trench is formed by conventional photolithography and etching processes as already described herein. The trench is filled with a metallic material (e.g., tungsten) to form a contact 38. As will be appreciated by those skilled in the art, the contact 38 located on the side of the photodiode 25 will detect the current generated by the photons that strike the photodiode 25.

[0034] Although the photodiode 25 is primarily designed for side illumination, it should be appreciated that the contact 38 located above the photodiode 25 can be arranged at the edge of the photodiode 25 for frontside illumination. Such frontside illumination is possible because the contact 38 does not significantly interfere with light entering the photodiode 25 from the front side (e.g., top). The photodiode 25 can also be used for backside illumination.

[0035] Figure 6 It is along the Figure 5 The line "A"-"A" in FIG. 2 represents a top view of the planar photodiode 25. Specifically, Figure 6 A cutaway top view of a spiral fin structure 22 having a liner 28, a photodetector material 26, and a P+ plug material 32 deposited within a space 24 is shown. As shown in this view, the spiral fin structure 22 is a continuous structure defined by shallow trench isolation regions 14, 16 located above an insulator layer 12c. As further seen in this view, the body of the spiral fin structure 22 includes the shallow trench isolation region 14 along its length. In addition, the spiral fin structure 22 will be located on the insulator material 12b in SOI technology. Therefore, in this manner, the photodiode 25 will be surrounded by a reflective material that will reflect light back into the photodetector material 26.

[0036] In addition, the photodetector material 28 may include a cone or tapered portion 28a that directs light laterally into the photodiode 25 to reach the center of the spiral configuration. Incident light may be provided laterally to the photodiode 25 by a waveguide structure, optical fiber, or other laterally incident light (each indicated by an arrow) located in the same plane as the photodiode 25.

[0037] Figure 7 Photodiodes 25, 25a are shown coupled to the waveguide 100 via a demultiplexer / splitter 102. In this implementation, different photodiodes 25, 25a can detect different wavelengths using the demultiplexer / splitter 102. More specifically, light from the waveguide 100 can be separated into different wavelengths by the demultiplexer / splitter 102, and each individual wavelength can then be directed sideways to a different photodiode 25, 25a for detection. In this embodiment, different photodiodes 25, 25a detect individual wavelengths by side illumination.

[0038] This structure can be utilized in system-on-chip (SoC) technology. It should be understood by those skilled in the art that SoC is an integrated circuit (also referred to as a "chip") that integrates all components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, SoC consumes much less power and occupies much less area than multi-chip designs with equivalent functions. Therefore, SoC is becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoC is also commonly used in embedded systems and the Internet of Things.

[0039] The method as described above is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers as bare chips (i.e., as a single wafer with multiple unpackaged chips) or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier, whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier, which has one or both of surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product including an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0040] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: A spiral fin structure comprising a semiconductor substrate material and a dielectric material, wherein the semiconductor substrate material of the spiral fin structure comprises a semiconductor material in a substrate-on-insulator (SOI) technology; a photosensitive semiconductor material disposed on the sidewalls and top surface of the spiral fin structure, the photosensitive semiconductor material being positioned to capture incident light emitted from the side; a doped semiconductor material disposed above the photosensitive semiconductor material; as well as A contact electrically contacts the semiconductor substrate material and the doped semiconductor material from a top surface of the semiconductor substrate material and the doped semiconductor material.

2. The semiconductor structure according to claim 1, wherein: The photosensitive semiconductor material is in a helical configuration and is an intrinsic material different from the semiconductor substrate material.

3. The semiconductor structure according to claim 1, wherein: An insulator layer in the SOI technology is located below the photosensitive semiconductor material.

4. The semiconductor structure according to claim 3, wherein: The dielectric material is a shallow trench isolation region located within the body of the spiral fin structure.

5. The semiconductor structure according to claim 4, further comprising: A shallow trench isolation structure is adjacent to the spiral fin structure, wherein the photosensitive semiconductor material is surrounded by the shallow trench isolation region within the body of the spiral fin structure, the shallow trench isolation structure, and the insulator layer in the SOI technology.

6. The semiconductor structure according to claim 5, wherein: The shallow trench isolation region, the shallow trench isolation structure, and the insulator layer within the body of the spiral fin structure include a reflective material.

7. The semiconductor structure according to claim 6, further comprising: a semiconductor lining material lining the spiral fin structure beneath the photosensitive semiconductor material, wherein: The semiconductor substrate material is an N-type material; The semiconductor lining material is a P-type material; The photosensitive semiconductor material is an intrinsic material; and The doped semiconductor material is a P-type material.

8. The semiconductor structure according to claim 1, further comprising: A silicide is located on the top surface of the doped semiconductor material and the semiconductor substrate material, wherein a first contact and a second contact of the contacts are in contact with the silicide.

9. The semiconductor structure according to claim 1, wherein: The illumination source is at least one of a waveguide structure and a fiber optic component located in the same plane as the photosensitive semiconductor material.

10. The semiconductor structure according to claim 9, wherein: The waveguide structures are at least two waveguide structures located in the same plane as the photosensitive semiconductor material, each of the at least two waveguide structures being coupled to a demultiplexer / splitter.

11. A semiconductor structure comprising: A spiral fin structure comprising a semiconductor substrate material in a substrate-on-insulator (SOI) technology; a shallow trench isolation region located within the body of the spiral fin structure; a first semiconductor material lining sidewalls and a top surface of the spiral fin structure; a photosensitive semiconductor material located above the first semiconductor material and the insulator layer in the SOI technology; a second semiconductor material located above the photosensitive semiconductor material; as well as A contact electrically contacts the semiconductor substrate material and the second semiconductor material.

12. The semiconductor structure according to claim 11, wherein: The photosensitive semiconductor material is in a helical configuration and is an intrinsic material different from the semiconductor substrate material.

13. The semiconductor structure of claim 11, further comprising: A shallow trench isolation structure is adjacent to the spiral fin structure, wherein the photosensitive semiconductor material is surrounded by the shallow trench isolation region within the body of the spiral fin structure, the shallow trench isolation structure, and the insulator layer in the SOI technology.

14. The semiconductor structure according to claim 13, wherein:The shallow trench isolation region, the shallow trench isolation structure, and the insulator layer within the body of the spiral fin structure include a reflective material.

15. The semiconductor structure of claim 11, wherein: The semiconductor substrate material is an N-type material; The first semiconductor material is a P-type material; The photosensitive semiconductor material is an intrinsic material; as well as The second semiconductor material is a P-type material.

16. The semiconductor structure of claim 15, further comprising: A silicide is located on a top surface of the second semiconductor material and the semiconductor substrate material, wherein a first contact and a second contact of the contacts are in contact with the silicide.

17. The semiconductor structure of claim 11, further comprising: An illumination source is positioned on the same plane as the photosensitive semiconductor material so that the photosensitive semiconductor material receives light from the side of the photosensitive semiconductor material.

18. The semiconductor structure according to claim 17, wherein: The illumination source is at least a waveguide structure and a fiber optic component located in the same plane as the photosensitive semiconductor material.

19. The semiconductor structure according to claim 18, wherein: The at least one waveguide structure is at least two waveguide structures located in the same plane as the photosensitive semiconductor material, each of the at least two waveguide structures being coupled to a demultiplexer / splitter.

20. A method for manufacturing a semiconductor structure, comprising: forming a first shallow trench isolation structure in a spiral configuration within a semiconductor material in a substrate-on-insulator (SOI) technology; forming a second shallow trench isolation structure adjacent to the first shallow trench isolation structure; forming a spiral fin structure including the semiconductor material and the first shallow trench isolation structure, the spiral fin structure being formed above an insulator layer in the SOI technology and being bounded by the second shallow trench isolation structure; lining the sidewalls and top surface of the spiral fin structure with a first semiconductor material; forming a photosensitive semiconductor material over the first semiconductor material and the insulator layer; forming a second semiconductor material over the photosensitive semiconductor material; as well as A first contact electrically contacting the semiconductor substrate material and a second contact electrically contacting the second semiconductor material are formed on one side of the spiral fin structure.

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