Frequency Control Device and Frequency Control Method

Abstract

The frequency control device includes a first phase interpolator circuit, a detection circuit, and a digital controller circuit system. The first phase interpolator circuit is configured to generate a second reference frequency signal according to a first control signal and at least one first reference frequency signal. The detection circuit is configured to generate an error signal according to the difference between the receiver signal and the second reference frequency signal, where the receiver signal is the receiver frequency signal from the receiver circuit or the input signal equalized by the receiver circuit. The digital controller circuit system is configured to generate a first control signal and a second control signal according to the error signal, and update the second control signal based on the change of the first control signal, where the second control signal is used to generate the transmitter frequency signal for the transmitter circuit.

Description

Technical Field

[0001] This invention application relates to a frequency control device, and more particularly to a frequency control device and a frequency control method for a serializer / deserializer interface. Background Art

[0002] As data speeds increase, high-speed data transmission interfaces are subject to more severe input signal attenuation and increasing intersymbol interference, which can cause the receiving end to fail to receive the correct signal. In some related technologies, a re-timer is used to re-time the output signal so that the receiving end can receive the correct signal. However, in these technologies, the output signal is subject to jitter introduced by the re-timer. To reduce this jitter, a larger area loop filter needs to be used at the transmitting end for filtering, resulting in a significant increase in overall cost. Summary of the Invention

[0003] In some embodiments, the frequency control device includes a first phase interpolator circuit, a detection circuit, and a digital controller circuit system. The first phase interpolator circuit is configured to generate a second reference frequency signal based on a first control signal and at least one first reference frequency signal. The detection circuit is configured to generate an error signal based on a first difference between a receiver signal and the second reference frequency signal, where the receiver signal is a receiver frequency signal from a receiver circuit or an input signal equalized by the receiver circuit. The digital controller circuit system is configured to generate a first control signal and a second control signal based on the error signal, and update the second control signal based on a change in the first control signal, where the second control signal is used to generate a transmitter frequency signal for use by a transmitter circuit.

[0004] In some embodiments, the frequency control method includes the following operations: generating a second reference frequency signal based on a first control signal and at least one first reference frequency signal; generating an error signal based on a first difference between a receiver signal and the second reference frequency signal, where the receiver signal is a receiver frequency signal from a receiver circuit or an input signal equalized by the receiver circuit; and generating a first control signal and a second control signal based on the error signal, and updating the second control signal based on a change in the first control signal, where the second control signal is used to generate a transmitter frequency signal for use by a transmitter circuit.

[0005] The features, operations, and technical effects of this invention application will be described in detail below in conjunction with the accompanying drawings and preferred embodiments. Description of the Drawings

[0006] Figure 1 A schematic diagram of a data transmission system drawn according to some embodiments of this invention application;

[0007] Figure 2A Schematic diagrams of the intermediate frequency control device drawn in accordance with some embodiments of the present invention application Figure 1 ;

[0008] Figure 2B Schematic diagrams of the intermediate frequency control device drawn in accordance with some embodiments of the present invention application Figure 1 ;

[0009] Figure 2C Schematic diagrams drawn in accordance with some embodiments of the present invention application Figure 2A or Figure 2B schematic diagrams of the digital controller circuitry in

[0010] Figure 3A Schematic diagrams of a data transmission system drawn in accordance with some embodiments of the present invention application

[0011] Figure 3B Schematic diagrams drawn in accordance with some embodiments of the present invention application Figure 3A schematic diagrams of the intermediate frequency control device in

[0012] Figure 4A Schematic diagrams of a data transmission system drawn in accordance with some embodiments of the present invention application

[0013] Figure 4B Schematic diagrams drawn in accordance with some embodiments of the present invention application Figure 4A schematic diagrams of the phase-locked loop circuitry in

[0014] Figure 4C Schematic diagrams drawn in accordance with some embodiments of the present invention application Figure 4A schematic diagrams of the intermediate frequency control device in

[0015] Figure 4D Schematic diagrams drawn in accordance with some embodiments of the present invention application Figure 4A schematic diagrams of the phase-locked loop circuitry in; and

[0016] Figure 5 Flowcharts of a frequency control method drawn in accordance with some embodiments of the present invention application

[0017] Symbolic description:

[0018] For the above and other purposes, features, and advantages of the present invention application to be more clearly understood, the description of the attached symbols is as follows:

[0019] 100: Data transmission system

[0020] 120: Receiver circuitry

[0021] 122: Frequency data recovery circuitry

[0022] 140: First-In-First-Out circuit

[0023] 160: Transmitter circuit

[0024] 180: Frequency control device

[0025] CK R : Receiver frequency signal

[0026] CK T : Transmitter frequency signal

[0027] D R 、D T : Data signal

[0028] SIN: Input signal

[0029] SIN': Equalized input signal

[0030] SO: Output signal

[0031] S R : Receiver signal

[0032] 201: Frequency signal source

[0033] 202: Frequency division circuit

[0034] 220, 280: Phase interpolator circuit

[0035] 240: Detection circuit

[0036] 260: Digital controller circuit system

[0037] CK REF1 、CK REF2 : Reference frequency signal

[0038] PI_1, PI_2: Control signal

[0039] UP / DN: Error signal

[0040] 211~214: Frequency division circuit

[0041] S1~S4: Signal

[0042] 262, 266: Filter circuit

[0043] 264, 268: Integrator circuit

[0044] 262A, 262C, 266B: Multiplier circuit

[0045] 262B, 262E, 262G, 266D: Delta-sigma modulator circuit

[0046] 262D, 266C: Sub - integrator circuit

[0047] 262F: Adder circuit

[0048] 266A: Subtractor circuit

[0049] KP, KI, KC: Coefficients

[0050] S 21 ~S 29 、S 210 、S 211 : Signals

[0051] 300, 400: Data transmission systems

[0052] CK REF3 : Reference frequency signal

[0053] 162: Phase - locked loop circuit

[0054] 410: Detection circuit

[0055] 412: Charge pump circuit

[0056] 414: Loop filter circuit

[0057] 416: Voltage - controlled oscillator circuit

[0058] 418: Frequency division circuit

[0059] 420: Phase interpolator circuit

[0060] FREF: Reference signal Detailed implementation manners

[0061] All terms used herein have their ordinary meanings. The definitions of the above - mentioned terms in commonly used dictionaries, and examples of the use of any of the terms discussed herein in the context of the present invention application are for illustration only and should not limit the scope and meaning of the present invention application. Similarly, the present invention application is not limited to the various embodiments shown in this specification.

[0062] Regarding the use of "coupled" or "connected" herein, it can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, and can also refer to two or more components operating or acting on each other. As used herein, the term "circuitry" can be a single system formed by at least one circuit, and the term "circuit" can be a device formed by at least one transistor and / or at least one passive or active component connected in a certain way to process signals.

[0063] As used herein, the term "and / or" encompasses any combination of one or more of the listed related items. In this document, the terms first, second, third, etc. are used to describe and distinguish each component. Thus, the first component in this document may also be referred to as the second component without departing from the spirit of this patent application. For ease of understanding, similar components in the respective figures will be designated with the same reference numerals.

[0064] Figure 1 FIG. 1 is a schematic diagram of a data transmission system 100 drawn according to some embodiments of this patent application. In some embodiments, the data transmission system 100 can be applied to a serializer / deserializer (SerDes) interface. The data transmission system 100 includes a receiver circuit 120, a first in, first out (FIFO) circuit 140 (hereinafter simply referred to as the FIFO circuit 140), a transmitter circuit 160, and a frequency control device 180.

[0065] The receiver circuit 120 receives an input signal SIN according to a receiver frequency signal CK R and outputs a data signal D R and the receiver frequency signal CK R to the FIFO circuit 140. The FIFO circuit 140 receives the data signal D R according to the receiver frequency signal CK R , and outputs the received data signal D T as a data signal D R according to a transmitter frequency signal CK T . The transmitter circuit 160 outputs the data signal D T as an output signal SO.

[0066] The frequency control device 180 is coupled between the receiver circuit 120 and the transmitter circuit 160. In some embodiments, the frequency control device 180 can be used to generate a transmitter frequency signal CK R according to a receiver signal S T from the receiver circuit 120. In some embodiments, the receiver circuit 120 can output the receiver frequency signal CK R as a receiver signal S R . In some embodiments, the receiver circuit 120 can equalize the input signal SIN to an input signal SIN' and output the input signal SIN' as a receiver signal S R .

[0067] The frequency control device 180 can be operated as a re-timer circuit to retime the output signal SO to reduce the effects of signal attenuation and / or intersymbol interference. In some embodiments, the receiver frequency signal CK R can be generated by a clock and data recovery circuit 122 in the receiver circuit 120. As previously described, the receiver frequency signal CK R can be output as the receiver signal S R . Alternatively, in some embodiments, the data transmission system 100 may further include a frequency division circuit (not shown) for generating the receiver signal S R according to the receiver frequency signal CK R .

[0068] Figure 2A is a schematic diagram of the frequency control device 180 according to some embodiments of the present invention application Figure 1 . In some embodiments, the frequency control device 180 includes a phase interpolator circuit 220, a detection circuit 240, and a digital controller circuitry 260.

[0069] The phase interpolator circuit 220 is configured to generate a reference frequency signal CK REF1 based on a control signal PI_1 and at least one reference frequency signal CK REF2 . In this example, the at least one reference frequency signal CK REF1 can be a plurality of frequency signals having different phases, where the plurality of frequency signals are generated by a frequency signal source 201 and a frequency division circuit 202. The phase interpolator circuit 220 can select at least two of the at least one reference frequency signal CK REF1 for interpolation to generate the reference frequency signal CK REF2 . In some embodiments, the frequency signal source 201 can be (but is not limited to) a phase-locked loop circuit, a quartz oscillator, or an LC tank circuit. In some embodiments, the frequency signal source 201 and the frequency division circuit 202 are independent of the frequency control device 180. In other embodiments, the frequency signal source 201 and the frequency division circuit 202 can be integrated into the frequency control device 180. In still other embodiments, Figure 2A the frequency division circuit 202 in Figure 2B is optional, i.e., it can be determined whether to use it according to requirements ( 3B , the same as the embodiments of 4C).

[0070] In some embodiments, the phase interpolator circuit 220 includes a plurality of input pair circuits (not shown) and a current source circuit (not shown). The plurality of input pair circuits are coupled to the current source circuit and are selectively turned on according to at least one reference frequency signal CK REF1 The current source circuit includes a plurality of switches that are selectively turned on according to the control signal PI_1 to determine the current ratio flowing through the input pair circuits. Thus, the plurality of input pair circuits can interpolate the corresponding reference frequency signal CK according to this current ratio and at least one reference frequency signal CK REF1 REF2 . The above-described implementation of the phase interpolator circuit 220 is for illustration, and the present application is not limited thereto. Various types of phase interpolator circuits 220 fall within the scope covered by the present application.

[0071] The detection circuit 240 is used to generate an error signal UP / DN according to the difference between the aforementioned receiver signal S R and the reference frequency signal CK REF2 . In some embodiments, the detection circuit 240 can be a phase detector circuit, a frequency detector circuit, or a phase frequency detector circuit, which can be used to detect the difference between the frequency (or phase) of the receiver signal S R and the frequency (or phase) of the reference frequency signal CK REF2 and output the error signal UP / DN accordingly. The digital controller circuit system 260 is used to generate the control signal PI_1 and the control signal PI_2 according to the error signal UP / DN and update the control signal PI_2 based on the change of the control signal PI_1. In some embodiments, the digital controller circuit system 260 can be used to reduce the update rate of the transmitter frequency signal CK T to suppress the jitter on the transmitter frequency signal CK T . The detailed setting method of the digital controller circuit system 260 will be described below with reference to Figure 2C .

[0072] In this example, the frequency control device 180 further includes a phase interpolator circuit 280. The phase interpolator circuit 280 is used to generate the transmitter frequency signal CK according to the control signal PI_2 and at least one reference frequency signal CK REF1 . Similar to the phase interpolator circuit 220, the phase interpolator circuit 280 can select at least two from at least one reference frequency signal CK according to the control signal PI_2 for interpolation to generate the transmitter frequency signal CK T . REF1 T .

[0073] By updating the control signal PI_1, the reference frequency signal CK REF2 ​​may be the same as (or close to) the receiver signal S R It should be understood that if the control signal PI_2 is the same as (or close to) the control signal PI_1, and if the phase interpolator circuit 220 and the phase interpolator circuit 280 have the same circuit settings, the transmitter frequency signal CK T will also be the same as (or close to) the reference frequency signal CK REF2 Therefore, by making the control signal PI_2 follow the setting of the control signal PI_1, the transmitter frequency signal CK T can be synchronized with the receiver signal S R .

[0074] As mentioned before, the receiver signal S R can be the receiver frequency signal CK R or the equalized input signal SIN'. In some embodiments, if the receiver signal S R is set to the equalized input signal SIN', the operations of the phase interpolator circuit 220, the detection circuit 240, and the digital controller circuitry 260 are equivalent to those of the frequency data recovery circuit 122, so a reference frequency signal CK REF2 that can be used to read the input signal SIN can be generated. That is, in some other embodiments Figure 1 the frequency data recovery circuit 122 in the receiver circuit 120 is optional. For example, if the frequency data recovery circuit 122 is not selected in the receiver circuit 120, the Figure 2A reference frequency signal CK in the frequency control device 180 REF2 can be used as the receiver frequency signal CK input to the FIFO circuit 140 R (for example, transferred to the FIFO circuit 140 via the receiver circuit 120, but the present application is not limited thereto).

[0075] Figure 2B is a schematic diagram of the frequency control device 180 according to some embodiments of the present application Figure 1 . Compared with Figure 2A , the frequency control device 180 further includes a plurality of optional frequency division circuits 211 to 214. In some embodiments, at least one of the frequency division circuits 211 to 214 can be selectively used according to actual application requirements. In some embodiments, the division ratio of each of the frequency division circuits 211 to 214 is configurable. For example, the division ratio can be 1, 2, 3, etc.

[0076] The frequency division circuit 211 is used to generate a plurality of signals S1 according to at least one reference frequency signal CK REF1 Here, at least one reference frequency signal CKREF1 It can be a single - frequency signal, and these signals S1 can be multiple - frequency signals with different phases. The phase interpolator circuit 220 can generate a reference frequency signal CK according to the control signal PI_1 and these signals S1 REF2 . The frequency - division circuit 212 is used to generate a signal S2 according to the reference frequency signal CK REF2 . The detection circuit 240 can generate an error signal UP / DN according to the difference between the receiver signal S R and the signal S2. The frequency - division circuit 213 is used to generate multiple signals S3 according to at least one reference frequency signal CK REF1 . Similar to the multiple signals S1, these signals S3 are multiple - frequency signals with different phases. The phase interpolator circuit 280 can generate a signal S4 according to the control signal PI_2 and the multiple signals S3. The frequency - division circuit 214 can generate a transmitter frequency signal CK according to the signal S4 T .

[0077] It should be understood that Figure 2A and Figure 2B the multiple setting modes shown can be adjusted flexibly according to the actual application, so the present invention application is not limited to Figure 2A and Figure 2B . For example, if the frequency - division circuit 211 and the frequency - division circuit 213 are not selected, at least one reference frequency signal CK REF1 can be multiple - frequency signals with different phases and be directly input to the phase interpolator circuit 220 and the phase interpolator circuit 280. Similarly, if the frequency - division circuit 212 is not selected, the reference frequency signal CK REF2 can be directly input to the detection circuit 240. And so on, it should be understood Figure 2A and Figure 2B the various flexible adjustment modes.

[0078] Figure 2C is a schematic diagram of the digital controller circuit system 260 drawn according to some embodiments of the present invention application Figure 2A or Figure 2B . The digital controller circuit system 260 includes a filter circuit 262, an integrator circuit 264, a filter circuit 266, and an integrator circuit 268. The filter circuit 262 is used to filter the error signal UP / DN to generate a signal S 21 . The integrator circuit 264 is used to accumulate the signal S 21 to generate a control signal PI_1. The filter circuit 266 is used to filter the difference between the signal S 21 and the signal S 22 to generate a signal S 22 . The integrator circuit 268 is used to accumulate the signal S 22 to generate a control signal PI_2.

[0079] In some embodiments, filter circuit 262 includes multiplier circuit 262A, sigma delta modulator circuit 262B, multiplier circuit 262C, sub-integrator circuit 262D, sigma delta modulator circuit 262E, adder circuit 262F, and sigma delta modulator circuit 262G. Multiplier circuit 262A is configured to multiply coefficient KP and error signal UP / DN to generate signal S 23 . Sigma delta modulator circuit 262B is configured to modulate error signal UP / DN to generate signal S 24 . Multiplier circuit 262C is configured to multiply coefficient KI and signal S 24 to generate signal S 25 . Sub-integrator circuit 262D is configured to accumulate signal S 25 to generate signal S 26 . Sigma delta modulator circuit 262E is configured to modulate signal S 26 to generate signal S 27 . Adder circuit 262F is configured to add signal S 27 and signal S 23 to generate signal S 28 . Sigma delta modulator circuit 262G is configured to modulate signal S 28 to generate signal S 21 .

[0080] With the above arrangement, filter circuit 262 is a second-order circuit. The first-order signal path (which includes multiplier circuit 262A, adder circuit 262F, and sigma delta modulator circuit 262G) can track phase error, and the second-order signal path (which includes sigma delta modulator circuit 262B, multiplier circuit 262C, sub-integrator circuit 262D, and sigma delta modulator circuit 262E) can track frequency error. Furthermore, through the modulation and accumulation operations in the second-order signal path, high-frequency noise can be reduced and the update frequency of control signal PI_1 per unit time can be controlled. Thus, the update rate of transmitter frequency signal CK T can be reduced to suppress jitter on transmitter frequency signal CK T .

[0081] In some embodiments, filter circuit 266 is configured to subtract signal S 21 from signal S 22 to determine the difference between signal S 21 and signal S 22 (e.g., signal S 29 ), and update signal S 22Equivalently, the filter circuit 266 can update the control signal PI_2 based on a change in the control signal PI_1. The filter circuit 266 can include a subtractor circuit 266A, a multiplier circuit 266B, a sub-integrator circuit 266C, and a delta-sigma modulator circuit 266D. The subtractor circuit 266A subtracts the signal S 21 from the signal S 22 to generate the signal S 29 The multiplier circuit 266B multiplies the coefficient KC and the signal S 29 to generate the signal S 210 The sub-integrator circuit 266C is used to accumulate the signal S 210 to generate the signal S 211 The delta-sigma modulator circuit 266D is used to modulate the signal S 211 to generate the signal S 22 In some embodiments, the coefficients KP, KI, and KC are configurable filter coefficients that can be used to set the gain or bandwidth, etc., of the digital controller circuit system 260.

[0082] Similar to the filter circuit 262, through the modulation and accumulation operations in the filter circuit 266, high-frequency noise and the update frequency of the control signal PI_2 per unit time can be reduced. Thus, the update rate of the transmitter frequency signal CK T can be reduced to suppress jitter on the transmitter frequency signal CK T

[0083] In some embodiments, each of the integrator circuit 264, the integrator circuit 268, the sub-integrator circuit 262D, and the sub-integrator circuit 266C can be implemented by an adder circuit and a delay circuit (labeled as Z -1 )). In one or more embodiments, each of the delta-sigma modulator circuits 262B, 262E, 262G, and 266D is selectively settable. For example, if the delta-sigma modulator circuit 262B is not selected, the error signal UP / DN can be directly input to the multiplier circuit 266B, and the multiplier circuit 266B can multiply the coefficient KI and the error signal UP / DN to generate the signal S 25 . And so on, it should be understood Figure 2C the various flexible adjustment methods available.

[0084] ​Alternatively, in one or more embodiments, each of the delta-sigma modulator circuits 262B, 262E, 262G, and 266D may have a bypass mode and a modulation mode. When operating in the bypass mode, the corresponding delta-sigma modulator circuit directly outputs the input signal as the output signal. When operating in the modulation mode, the corresponding delta-sigma modulator circuit modulates the received input signal to generate the output signal. Taking the delta-sigma modulator circuit 262B as an example, when operating in the bypass mode, the delta-sigma modulator circuit 262B directly outputs the error signal UP / DN as the signal S 24 . Alternatively, when operating in the modulation mode, the delta-sigma modulator circuit 262B modulates the error signal UP / DN to generate the signal S 24 . By analogy, it should be understood Figure 2C the various flexible adjustment methods possessed

[0085] Figure 3A FIG. 300 is a schematic diagram of a data transmission system 300 drawn according to some embodiments of the present invention application. Compared with Figure 1 , the frequency control device 180 outputs a reference frequency signal CK REF3 , and the transmitter circuit 160 further includes a phase-locked loop circuit 162. The phase-locked loop circuit 162 is used to generate a transmitter frequency signal CK REF3 according to the reference frequency signal CK T . In these embodiments, the reference frequency signal CK REF3 may be a reference signal in the phase-locked loop circuit 162 (for example, the reference signal FREF of Figure 4B ). Similar to the foregoing embodiments, if the frequency data recovery circuit 122 is not selected in the receiver circuit 120 of Figure 3A , the reference frequency signal CK in the frequency control device 180 of Figure 3B can be output as the receiver frequency signal CK REF2 . R .

[0086] Figure 3B FIG. 35 is a schematic diagram of the frequency control device 180 drawn according to some embodiments of the present invention application Figure 3A . Compared with Figure 2A or Figure 2B , the phase interpolator circuit 280 is used to generate a reference frequency signal CK REF1 according to the control signal PI_2 and the reference frequency signal CK REF3 .

[0087] Figure 4A FIG. 400 is a schematic diagram of a data transmission system 400 drawn according to some embodiments of the present invention application. Compared with Figure 1For the data transmission system 100, the transmitter circuit 400 further includes a phase-locked loop circuit 162, which is used to generate a transmitter frequency signal CK according to a control signal PI_2 generated by a frequency control device 180 T . Similar to the foregoing embodiments, if a frequency data recovery circuit 122 is not selected in the Figure 4A receiver circuit 120, the reference frequency signal CK in the Figure 4C frequency control device 180 can be REF2 output as a receiver frequency signal CK R .

[0088] Figure 4B FIG. is drawn according to some embodiments of the present invention application Figure 4A FIG. is a schematic diagram of the phase-locked loop circuit 162. The phase-locked loop circuit 162 includes a detection circuit 410, a charge pump circuit 412, a loop filter circuit 414, a voltage-controlled oscillator circuit 416, and a frequency division circuit 418. The detection circuit 410 is used to detect the difference between a reference signal FREF and an output signal (not shown) of the frequency division circuit 418 to generate a corresponding error signal (not shown). The charge pump circuit 412 can be charged or discharged according to this error signal to generate a control voltage (not shown). The loop filter circuit 414 can filter this control voltage to generate an adjustment voltage (not shown). The voltage-controlled oscillator circuit 416 can generate a corresponding transmitter frequency signal CK according to this adjustment voltage T . The frequency division circuit 418 can divide the frequency of the transmitter frequency signal CK T according to the control signal PI_2 to generate an output signal (not shown) to the detection circuit 410, where the frequency division circuit 418 can set its own frequency division ratio according to the control signal PI_2

[0089] Figure 4C FIG. is drawn according to some embodiments of the present invention application Figure 4A FIG. is a schematic diagram of the frequency control device 180. Compared with Figure 2A or Figure 2B , Figure 4C the frequency control device 180 in FIG. may not use a phase interpolator circuit 280 and directly output a control signal PI_2 to the Figure 4B frequency division circuit 418 in FIG

[0090] Figure 4D FIG. is drawn according to some embodiments of the present invention application Figure 4A FIG. is a schematic diagram of the phase-locked loop circuit 162. Compared with Figure 4B, the phase-locked loop circuit 162 further includes a phase interpolator circuit 420. In this example, the voltage-controlled oscillator circuit 416 generates a plurality of frequency signals (not shown) having different phases. The phase interpolator circuit 420 generates a transmitter frequency signal CK based on the control signal PI_2 and these frequency signals T .

[0091] Figure 3B and Figure 4C The digital controller circuit system 180 in Figure 2B is used as an example, and the present application of the present invention is not limited thereto. It should be understood that similar to Figure 2B , in other embodiments, Figure 3B and Figure 4C The digital controller circuit system 180 in may also selectively provide one or more frequency division circuits (for example, at least one of the frequency division circuits 211 to 214).

[0092] Figure 5 FIG. 500 is a flowchart of a frequency control method 500 according to some embodiments of the present application. In operation S510, a second reference frequency signal is generated based on the first control signal and at least one first reference frequency signal. In operation S520, an error signal is generated based on the difference between the receiver signal and the second reference frequency signal, where the receiver signal is a receiver frequency signal from the receiver circuit or an input signal equalized by the receiver circuit. In operation S530, a first control signal and a second control signal are generated based on the error signal, and the second control signal is updated based on the change of the first control signal, where the second control signal is used to generate a transmitter frequency signal for the transmitter circuit.

[0093] The descriptions of the above operations S510, S520, and S530 can be referred to the foregoing respective embodiments, so they will not be repeated here. The multiple operations of the above frequency control method 500 are only examples, and are not limited to being executed in the order in this example. Without departing from the operation modes and scopes of the embodiments of the present application, various operations in the frequency control method 500 can be appropriately added, replaced, omitted, or executed in a different order. Alternatively, one or more operations in the frequency control method 500 can be executed simultaneously or partially simultaneously.

[0094] In summary, through the frequency control device and the frequency control method in some embodiments of the present application, the transmitter frequency signal can be synchronized with the receiver frequency signal, and the jitter on the transmitter frequency signal can be effectively reduced without using a large-area loop filter.

[0095] Although the embodiments of the present invention application are as described above, these embodiments are not used to limit the present invention application. Those of ordinary skill in the art can make changes to the technical features of the present invention application based on the express or implied content of the present invention application. All such changes may fall within the scope of protection required by the present invention application. In other words, the scope of patent protection of the present invention application shall be subject to the scope defined by the claims of the present invention application.

Claims

1. A frequency control device, characterized in that, The frequency control device includes: A first phase interpolator circuit for generating a second reference frequency signal according to a first control signal and at least one first reference frequency signal; A detection circuit for generating an error signal according to a first difference between a receiver signal and the second reference frequency signal, where the receiver signal is a receiver frequency signal from a receiver circuit or an input signal equalized by the receiver circuit; And A digital controller circuit system for generating the first control signal and a second control signal according to the error signal, and updating the second control signal based on a change in the first control signal, where the second control signal is used to generate a transmitter frequency signal for a transmitter circuit, The digital controller circuit system is used to reduce the update rate of the transmitter frequency signal to suppress jitter on the transmitter frequency signal.

2. The frequency control device according to claim 1, characterized in that, The frequency control device further includes: A second phase interpolator circuit for generating the transmitter frequency signal according to the second control signal and the at least one first reference frequency signal.

3. The frequency control device according to claim 1, wherein The frequency control device further includes: A second phase interpolator circuit for generating a third reference frequency signal according to the second control signal and the at least one first reference frequency signal, where the transmitter circuit includes a phase-locked loop circuit, and the phase-locked loop circuit is used to generate the transmitter frequency signal according to the third reference frequency signal.

4. The frequency control device according to claim 1, characterized in that The transmitter circuit includes a phase-locked loop circuit, the phase-locked loop circuit includes a frequency division circuit, and the frequency division circuit is used to set a frequency division ratio according to the second control signal to generate the transmitter frequency signal.

5. The frequency control device according to claim 1, characterized in that, The transmitter circuit includes a phase-locked loop circuit, the phase-locked loop circuit includes a second phase interpolator circuit, and the second phase interpolator circuit is used to generate the transmitter frequency signal according to the second control signal.

6. The frequency control device according to claim 1, characterized in that, The detection circuit is a phase detector circuit, a frequency detector circuit, or a phase-frequency detector circuit.

7. The frequency control device according to claim 1, characterized in that, The digital controller circuit system includes: A first filter circuit for filtering the error signal to generate a first signal; A first integrator circuit for accumulating the first signal to generate the first control signal; A second filter circuit for filtering a second difference between the first signal and a second signal to generate the second signal; And A second integrator circuit for accumulating the second signal to generate the second control signal.

8. The frequency control device according to claim 7, characterized in that, The second filter circuit is used to subtract the second signal from the first signal to determine the second difference, and update the second signal according to the second difference to update the second signal based on the change in the first control signal.

9. A frequency control method, characterized in that The frequency control method includes: Generating a second reference frequency signal according to a first control signal and at least one first reference frequency signal; Generating an error signal according to a first difference between a receiver signal and the second reference frequency signal, where the receiver signal is a receiver frequency signal from a receiver circuit or an input signal equalized by the receiver circuit; And A digital controller circuit system generates the first control signal and the second control signal according to the error signal, and updates the second control signal based on a change in the first control signal, wherein the second control signal is used to generate a transmitter frequency signal for use by a transmitter circuit, and the digital controller circuit system is configured to reduce an update rate of the transmitter frequency signal to suppress jitter on the transmitter frequency signal.

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