Bandgap reference circuit and control method

Abstract

The invention relates to a bandgap reference circuit and a control method. The bandgap reference circuit comprises: a constant current power supply module and a compensation module. The constant current power supply module comprises at least a start-up unit and a current mirror unit. The compensation module comprises at least one enhancement MOS tube and at least one depletion MOS tube. The drain of a PMOS tube MP5 is connected to the drain of a first enhancement MOS tube in the compensation module, and the source of the first enhancement MOS tube is connected to the drain of a second depletion MOS tube; or the drain of the PMOS tube MP5 is connected to the drain of a first depletion MOS tube in the compensation module, and the source of the first depletion MOS tube is connected to the drain of the second enhancement MOS tube. The problem of large circuit power consumption and complex circuit in the existing zero-temperature bandgap reference constructed by using the negative temperature characteristic of the emitter-base voltage of a BJT tube is solved, and the effect of reducing power consumption and circuit area while realizing voltage zero temperature is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply, and in particular to a bandgap reference circuit and a control method. Background Art

[0002] Bandgap reference voltage source is an indispensable component of analog integrated circuits and plays a vital role in the design of integrated circuits such as lithium battery protection chips, LED driver chips, linear regulators (LDO), power management chips, analog / digital converters (ADC), digital / analog converters (DAC), dynamic memory (DRAM), and Flash memory.

[0003] Figure 1 is a circuit diagram of a bandgap reference voltage source in the prior art, such as Figure 1 As shown, in the prior art, the bandgap reference voltage source uses the negative temperature characteristic of the emitter-base voltage of a bipolar transistor (BJT) to construct a zero-temperature bandgap reference, that is, two bipolar transistors are used to bias them at different current densities, and a positive temperature current is generated by the base-emitter voltage difference of the two transistors. The positive temperature current is allowed to flow through a certain number of resistors to generate a positive temperature voltage, and the positive temperature voltage is superimposed on the base-emitter voltage (negative temperature voltage) of the bipolar transistor, thereby obtaining a reference voltage that is independent of temperature.

[0004] In the prior art, the bandgap reference circuit uses a bipolar transistor, which has a large operating current and high power consumption. At the same time, current flows through the base of the bipolar transistor, which also causes additional loss. Summary of the invention

[0005] The present invention is intended to provide a bandgap reference circuit and a control method to solve the deficiencies in the prior art. The technical problem to be solved by the present invention is achieved through the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a bandgap reference circuit, the bandgap reference circuit comprising: a constant current power supply module and a compensation module, the constant current power supply module at least comprising a startup unit and a current mirror unit, the compensation module comprising at least one enhancement MOS tube and at least one depletion MOS tube, the enhancement MOS tube and the depletion MOS tube are connected in series, the startup unit is connected to the current mirror unit, and the source of the PMOS tube MP5 in the current mirror unit is connected to a preset voltage;

[0007] The drain of the PMOS transistor MP5 is connected to the drain of the first enhancement-mode MOS transistor in the compensation module, and the source of the first enhancement-mode MOS transistor is connected to the drain of the second depletion-mode MOS transistor;

[0008] Or the drain of the PMOS tube MP5 is connected to the drain of the first depletion-mode MOS tube in the compensation module, and the source of the first depletion-mode MOS tube is connected to the drain of the second enhancement-mode MOS tube.

[0009] Optionally, the compensation module includes an enhancement-type NMOS tube and a plurality of depletion-type NMOS tubes.

[0010] The drain of the PMOS tube MP5 is connected to the drain of the first depletion-type NMOS tube in the compensation module, the source of the first depletion-type NMOS tube is connected to the drain of the second enhancement-type NMOS tube, the source of the second enhancement-type NMOS tube is connected to the drain of the third depletion-type NMOS tube, until they are connected in series to the Nth depletion-type NMOS tube, where N is a natural number greater than 0.

[0011] Optionally, the source of the third depletion-type NMOS tube and the drain of the fourth depletion-type NMOS tube are connected in series.

[0012] The source of the fourth depletion-type NMOS tube and the drain of the fifth depletion-type NMOS tube are connected in series.

[0013] The source of the fifth depletion-type NMOS tube and the drain of the sixth depletion-type NMOS tube are connected in series.

[0014] The source of the sixth depletion-type NMOS tube and the drain of the seventh depletion-type NMOS tube are connected in series.

[0015] The source of the seventh depletion-type NMOS tube and the drain of the eighth depletion-type NMOS tube are connected in series.

[0016] The source of the eighth depletion-type NMOS tube and the drain of the ninth depletion-type NMOS tube are connected in series.

[0017] The source of the ninth depletion-type NMOS tube and the drain of the tenth depletion-type NMOS tube are connected in series.

[0018] The source of the tenth depletion-type NMOS tube and the drain of the eleventh depletion-type NMOS tube are connected in series.

[0019] The source of the eleventh NMOS tube M11 (depletion type) is grounded.

[0020] Optionally, the compensation module includes a depletion-type NMOS tube and a plurality of enhancement-type NMOS tubes.

[0021] The drain of the PMOS tube MP5 is connected to the drain of the first enhancement NMOS tube in the compensation module, the source of the first enhancement NMOS tube is connected to the drain of the second depletion NMOS tube, the source of the second depletion NMOS tube is connected to the drain of the third enhancement NMOS tube, until they are connected in series to the Mth enhancement NMOS tube, where M is a natural number greater than 0.

[0022] Optionally, the compensation module includes an enhancement-type PMOS tube and a plurality of depletion-type PMOS tubes.

[0023] The drain of the PMOS tube MP5 is connected to the drain of the first depletion-type PMOS tube in the compensation module, the source of the first depletion-type PMOS tube is connected to the drain of the second enhancement-type PMOS tube, the source of the second enhancement-type PMOS tube is connected to the drain of the third depletion-type PMOS tube, until they are connected in series to the Xth depletion-type PMOS tube, where X is a natural number greater than 0.

[0024] Optionally, the compensation module includes a depletion-type PMOS tube and a plurality of enhancement-type PMOS tubes.

[0025] The drain of the PMOS tube MP5 is connected to the drain of the first enhancement-type PMOS tube in the compensation module, the source of the first enhancement-type PMOS tube is connected to the drain of the second depletion-type PMOS tube, the source of the second depletion-type PMOS tube is connected to the drain of the third enhancement-type PMOS tube, until they are connected in series to the Yth enhancement-type PMOS tube, where Y is a natural number greater than 0.

[0026] Optionally, the current mirror unit includes a MOS tube MP1, a MOS tube MP2, a MOS tube MN1, a MOS tube MN2, a MOS tube MP3, and a MOS tube MP5, and the MOS tube MP1 and the MOS tube MP2 are in a current mirror structure, the MOS tube MN1 and the MOS tube MN2 are in a current mirror structure, and the MOS tube MP3 and the MOS tube MP5 are in a current mirror structure;

[0027] The startup unit includes a MOS transistor MP3, a MOS transistor MN3, a MOS transistor MN4, a MOS transistor MN5, a MOS transistor MP4, a MOS transistor MN6 and a MOS transistor MN7.

[0028] Optionally, a fuse is connected in parallel to the series branch of the enhancement-mode MOS tube or the series branch of the depletion-mode MOS tube.

[0029] Optionally, the compensation module includes a depletion-type NMOS tube and an enhancement-type NMOS tube, or two depletion-type NMOS tubes and one enhancement-type NMOS tube.

[0030] In a second aspect, an embodiment of the present invention provides a control method for a bandgap reference circuit, the control method comprising:

[0031] Obtain the negative temperature voltage value of the gate-source voltage of the depletion-type MOS tube and the gate-source voltage of the enhancement-type MOS tube;

[0032] Determining a positive temperature coefficient voltage according to a difference between the negative temperature voltage value and the gate-source voltage;

[0033] Determining a positive temperature current according to the positive temperature coefficient voltage and the linear region resistance of the enhancement mode MOS tube;

[0034] Determining a positive temperature voltage according to the positive temperature current and the linear region resistance of the enhancement mode MOS tube;

[0035] According to the positive temperature voltage and the negative temperature voltage of the depletion-type MOS tube gate-source voltage, the proportionality coefficient is adjusted so that the voltage zero temperature coefficient is less than a preset value.

[0036] The embodiments of the present invention include the following advantages:

[0037] The bandgap reference circuit and control method provided by the embodiment of the present invention include: the bandgap reference circuit includes: a constant current power supply module and a compensation module, the constant current power supply module includes at least a startup unit and a current mirror unit, the compensation module includes at least one enhancement MOS tube and at least one depletion MOS tube, the enhancement MOS tube and the depletion MOS tube are connected in series, the startup unit and the current mirror unit are connected, the source of the PMOS tube MP5 in the current mirror unit is connected to a preset voltage; the drain of the PMOS tube MP5 is connected to the drain of the first enhancement MOS tube in the compensation module, and the source of the first enhancement MOS tube is connected to the drain of the second depletion MOS tube; or the drain of the PMOS tube MP5 is connected to the drain of the first depletion MOS tube in the compensation module, and the source of the first depletion MOS tube is connected to the drain of the second enhancement MOS tube, so as to solve the problem of large circuit power consumption and complex circuit in the existing zero-temperature bandgap reference constructed by using the negative temperature characteristic of the emitter-base voltage of the BJT tube, and achieve the effect of reducing power consumption and circuit area while realizing voltage zero temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of a conventional bandgap reference voltage source circuit in the prior art;

[0039] Figure 2 is a schematic diagram of a bandgap reference circuit connection according to an embodiment of the present invention;

[0040] Figure 3 It is a circuit diagram of a depletion-type NMOS tube and an enhancement-type NMOS tube series branch according to an embodiment of the present invention;

[0041] Figure 4 It is a circuit diagram of a depletion-type NMOS tube and an enhancement-type NMOS tube series branch according to another embodiment of the present invention;

[0042] Figure 5 is a circuit diagram of a depletion-type NMOS tube and an enhancement-type NMOS tube series branch according to another embodiment of the present invention;

[0043] Figure 6 It is a circuit diagram of a depletion-type PMOS tube and an enhancement-type PMOS tube series branch according to an embodiment of the present invention;

[0044] Figure 7 It is a circuit diagram of a depletion-type PMOS tube and an enhancement-type PMOS tube series branch according to another embodiment of the present invention. DETAILED DESCRIPTION

[0045] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0046] Reference Figure 2 , shows a connection schematic diagram of a bandgap reference circuit according to an embodiment of the present invention, the bandgap reference circuit comprises: a constant current power supply module and a compensation module, the constant current power supply module comprises at least a startup unit and a current mirror unit, the compensation module comprises at least one enhancement MOS tube and at least one depletion MOS tube, the enhancement MOS tube and the depletion MOS tube are connected in series, the startup unit and the current mirror unit are connected, and the source of the PMOS tube MP5 in the current mirror unit is connected to a preset voltage, namely VDD;

[0047] The drain of the PMOS transistor MP5 is connected to the drain of the first enhancement-mode MOS transistor in the compensation module, and the source of the first enhancement-mode MOS transistor is connected to the drain of the second depletion-mode MOS transistor;

[0048] Or the drain of the PMOS tube MP5 is connected to the drain of the first depletion-mode MOS tube in the compensation module, and the source of the first depletion-mode MOS tube is connected to the drain of the second enhancement-mode MOS tube.

[0049] Specifically, an embodiment of the present invention provides a bandgap reference circuit, including a constant current power supply (constant gmcurrent source), that is, a constant current power supply module, which does not change with voltage, and the constant current power supply module includes a startup unit and a current mirror unit, the startup unit is connected to the current mirror unit, the current mirror unit includes a MOS tube MP1, a MOS tube MP2, a MOS tube MN1, a MOS tube MN2, a MOS tube MP3, and a MOS tube MP5, and the MOS tube MP1 and the MOS tube MP2 are current mirror structures, the MOS tube MN1 and the MOS tube MN2 are current mirror structures, and the MOS tube MP3 and the MOS tube MP5 are current mirror structures;

[0050] The start-up unit includes a MOS transistor MP3, a MOS transistor MN3, a MOS transistor MN4, a MOS transistor MN5, a MOS transistor MP4, a MOS transistor MN6 and a MOS transistor MN7.

[0051] The compensation module includes at least one enhancement MOS tube and at least one depletion MOS tube, and the enhancement MOS tube and the depletion MOS tube are connected in series. Exemplarily, the compensation module may include one enhancement MOS tube and multiple depletion MOS tubes, or may include one depletion MOS tube and multiple enhancement MOS tubes. In the embodiment of the present invention, multiple refers to two or more, and the MOS tube may be an NMOS tube or a PMOS tube, which is not specifically limited here.

[0052] As an optional implementation, the compensation module may include a depletion-mode MOS tube and multiple enhancement-mode MOS tubes, the drain of the PMOS tube MP5 is connected to the drain of the first enhancement-mode MOS tube in the compensation module, the source of the first enhancement-mode MOS tube is connected to the drain of the second depletion-mode MOS tube, the source of the second depletion-mode MOS tube is connected to the drain of the third depletion-mode MOS tube, and in this way, the multiple depletion-mode MOS tubes are connected in series;

[0053] As another optional implementation, it includes an enhancement MOS tube and multiple depletion MOS tubes, the drain of the PMOS tube MP5 is connected to the drain of the first depletion MOS tube in the compensation module, the source of the first depletion MOS tube is connected to the drain of the second enhancement MOS tube, and the source of the second enhancement MOS tube is connected to the drain of the third enhancement MOS tube. In this way, multiple enhancement MOS tubes are connected in series.

[0054] The constant current power supply module is compensated by adding a transistor group consisting of an enhancement MOS tube in series with a depletion MOS tube.

[0055] like Figure 4As shown, the depletion-type NMOS tube and the enhancement-type NMOS tube series branch of the embodiment of the present invention is composed of an enhancement-type NMOS tube (M2) connected in series with multiple depletion-type NMOS tubes (M1, M3, M4, M5, M6, M7, M8, M9, M10, M11), the gate-source voltage Vgs of the NMOS tube is superimposed, and the proportional coefficient is adjusted to achieve a voltage zero temperature coefficient.

[0056] Specifically, the compensation module includes an enhancement-type NMOS tube and a plurality of depletion-type NMOS tubes.

[0057] The drain of the PMOS tube MP5 is connected to the drain of the first depletion-type NMOS tube in the compensation module, the source of the first depletion-type NMOS tube is connected to the drain of the second enhancement-type NMOS tube, the source of the second enhancement-type NMOS tube is connected to the drain of the third depletion-type NMOS tube, until they are connected in series to the Nth depletion-type NMOS tube, where N is a natural number greater than 0.

[0058] Specifically, the source of the third depletion-type NMOS tube and the drain of the fourth depletion-type NMOS tube are connected in series.

[0059] The source of the fourth depletion-type NMOS tube and the drain of the fifth depletion-type NMOS tube are connected in series.

[0060] The source of the fifth depletion-type NMOS tube and the drain of the sixth depletion-type NMOS tube are connected in series.

[0061] The source of the sixth depletion-type NMOS tube and the drain of the seventh depletion-type NMOS tube are connected in series.

[0062] The source of the seventh depletion-type NMOS tube and the drain of the eighth depletion-type NMOS tube are connected in series.

[0063] The source of the eighth depletion-type NMOS tube and the drain of the ninth depletion-type NMOS tube are connected in series.

[0064] The source of the ninth depletion-type NMOS tube and the drain of the tenth depletion-type NMOS tube are connected in series.

[0065] The source of the tenth depletion-type NMOS tube and the drain of the eleventh depletion-type NMOS tube are connected in series.

[0066] The source of the eleventh depletion-type NMOS tube is grounded.

[0067] exist Figure 4In the embodiment, the drain of MP5 of the constant current power supply is connected to the drain of the first NMOS tube M1 (depletion type), the source of the first NMOS tube M1 (depletion type) is connected in series with the drain of the second NMOS tube M2 (enhancement type), the source of the second NMOS tube M2 (enhancement type) is connected in series with the drain of the third NMOS tube M3 (depletion type), the source of the third NMOS tube M3 (depletion type) is connected in series with the drain of the fourth NMOS tube M4 (depletion type), the source of the fourth NMOS tube M4 (depletion type) is connected in series with the drain of the fifth NMOS tube M5 (depletion type), the source of the fifth NMOS tube M5 (depletion type) is connected in series with the drain of the sixth NMOS tube M6 (depletion type), the source of the sixth NMOS tube M6 (depletion type) is connected in series with the drain of the seventh NMOS tube M7 (depletion type). The seventh NMOS tube M7 (depletion type) is connected in series with the source of the eighth NMOS tube M8 (depletion type) and the drain of the ninth NMOS tube M9 (depletion type) are connected in series, the source of the ninth NMOS tube M9 (depletion type) and the drain of the tenth NMOS tube M10 (depletion type) are connected in series, the source of the tenth NMOS tube M10 (depletion type) and the drain of the eleventh NMOS tube M11 (depletion type) are connected in series, and the source of the eleventh NMOS tube M11 (depletion type) is grounded, and the current is converted into voltage, so as to realize the superposition compensation of the positive temperature coefficient voltage generated by the enhancement type NMOS tube and the gate-source voltage with a negative temperature coefficient of the depletion type NMOS tube, so that the zero temperature coefficient voltage after superposition is output.

[0068] like Figure 5 As shown, the compensation module includes a depletion-type NMOS tube and multiple enhancement-type NMOS tubes, the drain of the PMOS tube MP5 is connected to the drain of the first enhancement-type NMOS tube in the compensation module, the source of the first enhancement-type NMOS tube is connected to the drain of the second depletion-type NMOS tube, the source of the second depletion-type NMOS tube is connected to the drain of the third enhancement-type NMOS tube, until they are connected in series to the Mth enhancement-type NMOS tube, where M is a natural number greater than 0.

[0069] That is, in the embodiment of the present invention, a depletion-type NMOS tube and an enhancement-type NMOS tube series branch is provided, which is composed of a depletion-type NMOS tube (M2) connected in series with multiple enhancement-type NMOS tubes (M1, M3, M4, M5, M6, M7, M8, M9, M10, M11), the gate-source voltage Vgs of the NMOS tube is superimposed, and the proportional coefficient is adjusted to achieve a voltage zero temperature coefficient.

[0070] like Figure 6 As shown, optionally, the compensation module includes an enhancement-type PMOS tube and a plurality of depletion-type PMOS tubes.

[0071] The drain of the PMOS tube MP5 is connected to the drain of the first depletion-type PMOS tube in the compensation module, the source of the first depletion-type PMOS tube is connected to the drain of the second enhancement-type PMOS tube, the source of the second enhancement-type PMOS tube is connected to the drain of the third depletion-type PMOS tube, until they are connected in series to the Xth depletion-type PMOS tube, where X is a natural number greater than 0.

[0072] Specifically, under a process with only a depletion-type PMOS tube, an embodiment of the present invention provides a series branch of a depletion-type PMOS tube and an enhancement-type PMOS tube, which is composed of an enhancement-type PMOS tube (M2) connected in series with multiple depletion-type PMOS tubes (M1, M3, M4, M5, M6, M7, M8, M9, M10, M11), and the gate-source voltage Vgs of the PMOS tube is superimposed and the proportional coefficient is adjusted to achieve a voltage zero temperature coefficient.

[0073] like Figure 7 As shown, the compensation module includes a depletion-type PMOS tube and multiple enhancement-type PMOS tubes, the drain of the PMOS tube MP5 is connected to the drain of the first enhancement-type PMOS tube in the compensation module, the source of the first enhancement-type PMOS tube is connected to the drain of the second depletion-type PMOS tube, the source of the second depletion-type PMOS tube is connected to the drain of the third enhancement-type PMOS tube, until they are connected in series to the Yth enhancement-type PMOS tube, where Y is a natural number greater than 0.

[0074] Specifically, under a process with only a depletion-type PMOS tube, the depletion-type PMOS tube and the enhancement-type PMOS tube series branch provided in an embodiment of the present invention is composed of a depletion-type PMOS tube (M2) connected in series with multiple enhancement-type PMOS tubes (M1, M3, M4, M5, M6, M7, M8, M9, M10, M11), and the PMOS tube gate-source voltage Vgs is superimposed and the proportional coefficient is adjusted, which can also achieve a voltage zero temperature coefficient.

[0075] Optionally, a fuse is connected in parallel to the series branch of the enhancement-mode MOS tube or the series branch of the depletion-mode MOS tube.

[0076] The embodiment of the present invention also provides a simple fuse trimming method. By using a depletion-type NMOS tube and an enhancement-type NMOS tube in series in a branch, only the size of the binary NMOS tube needs to be designed. The fuse can be easily blown by laser or power-on, and the reference voltage trimming can be easily completed.

[0077] Optionally, the compensation module includes a depletion-type NMOS tube and an enhancement-type NMOS tube, or two depletion-type NMOS tubes and one enhancement-type NMOS tube.

[0078] like Figure 3As shown, the bandgap reference circuit of the embodiment of the present invention has low power consumption and simple circuit, and can be completed with only one or two depletion-type NMOS tubes and one enhancement-type NMOS tube series branch. Therefore, it is widely used in devices such as lithium battery protection chips, LED driver chips, DC-DC converters, digital-to-analog converters, and analog-to-digital converters, and has strong practicality.

[0079] An embodiment of the present invention further provides a control method based on the above-mentioned bandgap reference circuit, the control method comprising:

[0080] Obtain the negative temperature voltage value of the gate-source voltage of the depletion-type MOS tube and the gate-source voltage of the enhancement-type MOS tube;

[0081] According to the difference between the negative temperature voltage value and the gate-source voltage, the positive temperature coefficient voltage is determined;

[0082] Determine the positive temperature current based on the positive temperature coefficient voltage and the linear region resistance of the enhancement MOS tube;

[0083] Determine the positive temperature voltage according to the positive temperature current and the linear region resistance of the enhancement MOS tube;

[0084] According to the positive temperature voltage and the negative temperature voltage of the gate-source voltage of the depletion-type MOS tube, the proportional coefficient is adjusted so that the voltage zero temperature coefficient is less than a preset value.

[0085] Specifically, Figure 2 In the circuit diagram shown, when the current in the branches of MN1, MN2, MP1, MP2, and MP5 is too low or 0, MP3 will also enter the cut-off region, which will cause the gate voltage of MN6 to drop to 0V and cut off MN6, and then increase the gate voltage of MN7 to enter the threshold region, thus lowering the gate voltage of MP1 and MP2 to enter the threshold region. Once the gate voltages of MP1 and MP2 enter the threshold region, MP3 will also enter the threshold region so that the startup circuit will not restart. The current-voltage characteristics of the constant current source circuit can be expressed as:

[0086]

[0087] Where I0 represents the reverse saturation current, ξ represents the non-ideal factor, which is greater than 1.

[0088] V GS Represents the gate-source voltage of the MOS tube, VT represents the thermal voltage, VT=KT / q, K is the Boltzmann constant, and q is the electron charge.

[0089] According to Kirchhoff's voltage law, MN1 and MN2 are two pairs of current mirror structures, which can be listed as follows:

[0090] V GS1 =V GS2 +I D2 ×R1…………(2)

[0091] Substituting the above formula (1) into formula (2), we can get the following:

[0092]

[0093] Among them I D1 : Base current flowing through MN1;

[0094] I D2 : Base current flowing through MN2;

[0095] V T1 : represents the thermal voltage of MN1;

[0096] V T2 : Indicates the thermal voltage;

[0097] μ n : electron drift rate;

[0098] C OX : Oxide layer capacitance value;

[0099] K: Boltzmann constant;

[0100] The ratio of the length to width of the MOS tube,

[0101] By rearranging formula (3), we can get

[0102] Square both sides of (4) and shift the terms to get the current that is independent of VDD,

[0103]

[0104] However, it is still related to temperature, and the voltage zero temperature coefficient can be adjusted by adding the depletion-type MOS tube and the enhancement-type MOS tube in series.

[0105] The negative temperature characteristic of the gate-source voltage of the depletion-type MOS tube connected to the drain and the gate is utilized to generate a positive temperature coefficient voltage by the difference between the gate-source voltage Vgs of the enhancement-type NMOS tube. The positive temperature coefficient voltage is divided by the resistance of the NMOS tube in the linear region to obtain a positive temperature current. The positive temperature current is multiplied by the resistance of the NMOS tube in the linear region to obtain a positive temperature voltage. The negative temperature voltage Vgs of the gate-source voltage of the depletion-type NMOS tube is superimposed, and the proportionality coefficient is adjusted to achieve a voltage zero temperature coefficient. Because no BJT is required, a large amount of area is saved. Only an enhancement-type NMOS tube and a depletion-type NMOS tube are required to make the current flowing through each branch a subthreshold current, and the power consumption is low. The existing problem of large circuit power consumption and complex circuit in constructing a zero-temperature bandgap reference using the negative temperature characteristic of the emitter-base voltage of the BJT tube is solved, and the effect of reducing power consumption and reducing circuit area while achieving voltage zero temperature is achieved.

[0106] The bandgap reference circuit and control method provided by the embodiment of the present invention include: the bandgap reference circuit includes: a constant current power supply module and a compensation module, the constant current power supply module includes at least a startup unit and a current mirror unit, the compensation module includes at least one enhancement MOS tube and at least one depletion MOS tube, the enhancement MOS tube and the depletion MOS tube are connected in series, the startup unit and the current mirror unit are connected, the source of the PMOS tube MP5 in the current mirror unit is connected to a preset voltage; the drain of the PMOS tube MP5 is connected to the drain of the first enhancement MOS tube in the compensation module, and the source of the first enhancement MOS tube is connected to the drain of the second depletion MOS tube; or the drain of the PMOS tube MP5 is connected to the drain of the first depletion MOS tube in the compensation module, and the source of the first depletion MOS tube is connected to the drain of the second enhancement MOS tube, so as to solve the problem of large circuit power consumption and complex circuit in the existing zero-temperature bandgap reference constructed by using the negative temperature characteristic of the emitter-base voltage of the BJT tube, and achieve the effect of reducing power consumption and reducing circuit area while realizing voltage zero temperature.

[0107] It should be noted that the above detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present application belongs.

[0108] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0109] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0110] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0111] For ease of description, spatially relative terms, such as "above", "above", "on the upper surface of", "above", etc., may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein are interpreted accordingly.

[0112] In the above detailed description, reference is made to the accompanying drawings, which form a part of this document. In the accompanying drawings, similar symbols typically identify similar components unless the context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.

[0113] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A bandgap reference circuit, characterized in that: The bandgap reference circuit comprises: a constant current power supply module and a compensation module, wherein the constant current power supply module at least comprises a startup unit and a current mirror unit, wherein the compensation module comprises at least one enhancement MOS tube and at least one depletion MOS tube, wherein the enhancement MOS tube and the depletion MOS tube are connected in series, wherein the startup unit is connected to the current mirror unit, and wherein the source of the PMOS tube MP5 in the current mirror unit is connected to a preset voltage; The drain of the PMOS transistor MP5 is connected to the drain of the first enhancement-mode MOS transistor in the compensation module, and the source of the first enhancement-mode MOS transistor is connected to the drain of the second depletion-mode MOS transistor; Or the drain of the PMOS tube MP5 is connected to the drain of the first depletion-mode MOS tube in the compensation module, and the source of the first depletion-mode MOS tube is connected to the drain of the second enhancement-mode MOS tube; The control method of the bandgap reference circuit comprises: Obtain the negative temperature voltage value of the gate-source voltage of the depletion-type MOS tube and the gate-source voltage of the enhancement-type MOS tube; Determining a positive temperature coefficient voltage according to a difference between the negative temperature voltage value and the gate-source voltage; Determining a positive temperature current according to the positive temperature coefficient voltage and the linear region resistance of the enhancement mode MOS tube; Determining a positive temperature voltage according to the positive temperature current and the linear region resistance of the enhancement mode MOS tube; According to the positive temperature voltage and the negative temperature voltage of the depletion-type MOS tube gate-source voltage, the proportionality coefficient is adjusted so that the voltage zero temperature coefficient is less than a preset value.

2. The bandgap reference circuit according to claim 1, characterized in that: The compensation module includes an enhancement-type NMOS tube and a plurality of depletion-type NMOS tubes. The drain of the PMOS tube MP5 is connected to the drain of the first depletion-type NMOS tube in the compensation module, the source of the first depletion-type NMOS tube is connected to the drain of the second enhancement-type NMOS tube, the source of the second enhancement-type NMOS tube is connected to the drain of the third depletion-type NMOS tube, until they are connected in series to the Nth depletion-type NMOS tube, where N is a natural number greater than 0.

3. The bandgap reference circuit according to claim 2, characterized in that: The source of the third depletion-type NMOS tube and the drain of the fourth depletion-type NMOS tube are connected in series. The source of the fourth depletion-type NMOS tube and the drain of the fifth depletion-type NMOS tube are connected in series. The source of the fifth depletion-type NMOS tube and the drain of the sixth depletion-type NMOS tube are connected in series. The source of the sixth depletion-type NMOS tube and the drain of the seventh depletion-type NMOS tube are connected in series. The source of the seventh depletion-type NMOS tube and the drain of the eighth depletion-type NMOS tube are connected in series. The source of the eighth depletion-type NMOS tube and the drain of the ninth depletion-type NMOS tube are connected in series. The source of the ninth depletion-type NMOS tube and the drain of the tenth depletion-type NMOS tube are connected in series. The source of the tenth depletion-type NMOS tube and the drain of the eleventh depletion-type NMOS tube are connected in series. The source of the eleventh NMOS tube M11 (depletion type) is grounded.

4. The bandgap reference circuit according to claim 1, characterized in that: The compensation module includes a depletion-type NMOS tube and a plurality of enhancement-type NMOS tubes. The drain of the PMOS tube MP5 is connected to the drain of the first enhancement NMOS tube in the compensation module, the source of the first enhancement NMOS tube is connected to the drain of the second depletion NMOS tube, the source of the second depletion NMOS tube is connected to the drain of the third enhancement NMOS tube, until they are connected in series to the Mth enhancement NMOS tube, where M is a natural number greater than 0.

5. The bandgap reference circuit according to claim 1, characterized in that: The compensation module includes an enhancement-type PMOS tube and a plurality of depletion-type PMOS tubes. The drain of the PMOS tube MP5 is connected to the drain of the first depletion-type PMOS tube in the compensation module, the source of the first depletion-type PMOS tube is connected to the drain of the second enhancement-type PMOS tube, the source of the second enhancement-type PMOS tube is connected to the drain of the third depletion-type PMOS tube, until they are connected in series to the Xth depletion-type PMOS tube, where X is a natural number greater than 0.

6. The bandgap reference circuit according to claim 1, characterized in that: The compensation module includes a depletion-type PMOS tube and a plurality of enhancement-type PMOS tubes. The drain of the PMOS tube MP5 is connected to the drain of the first enhancement-type PMOS tube in the compensation module, the source of the first enhancement-type PMOS tube is connected to the drain of the second depletion-type PMOS tube, the source of the second depletion-type PMOS tube is connected to the drain of the third enhancement-type PMOS tube, until they are connected in series to the Yth enhancement-type PMOS tube, where Y is a natural number greater than 0.

7. The bandgap reference circuit according to claim 1, characterized in that: The current mirror unit includes a MOS tube MP1, a MOS tube MP2, a MOS tube MN1, a MOS tube MN2, a MOS tube MP3, and a MOS tube MP5, and the MOS tube MP1 and the MOS tube MP2 are current mirror structures, the MOS tube MN1 and the MOS tube MN2 are current mirror structures, and the MOS tube MP3 and the MOS tube MP5 are current mirror structures; The startup unit includes a MOS transistor MP3, a MOS transistor MN3, a MOS transistor MN4, a MOS transistor MN5, a MOS transistor MP4, a MOS transistor MN6 and a MOS transistor MN7.

8. The bandgap reference circuit according to any one of claims 1 to 7, characterized in that: A fuse is connected in parallel to the series branch of the enhancement-mode MOS tube or the series branch of the depletion-mode MOS tube.

9. The bandgap reference circuit according to claim 1, characterized in that: The compensation module includes a depletion-type NMOS tube and an enhancement-type NMOS tube, or two depletion-type NMOS tubes and one enhancement-type NMOS tube.

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