A Debug Module Circuit for RISC-V and a Method for Reading and Writing Registers

Abstract

The present invention discloses a debugging module circuit for RISC-V and a method for reading and writing registers, belonging to the technical field of processors. The circuit includes Module 1 and Module 2; Module 1 and Module 2 are connected; Module 1 is used to transmit debugging-related control signals; Module 2 is used to implement debugging commands and store debugging results. By providing a debugging module circuit for RISC-V and a method for reading and writing its registers, the present invention solves the problem that the current high-efficiency debugging of the processor cannot be achieved. It not only realizes the rapid debugging and simulation verification of single-core and multi-core processors, but also reduces the proportion of hardware resources in the debugging system, improves the working efficiency of the system, and has important value for improving the debugging mechanism and efficiency of the debugging system.

Description

Technical Field

[0001] The present invention relates to a debugging module circuit and a method for reading and writing registers for RISC-V, belonging to the technical field of processors. Background Art

[0002] The semiconductor industry has developed rapidly. The design of integrated circuits has entered the deep sub-micron process and is developing towards high integration, high speed, and low power consumption, with increasingly powerful performance. Since the 1990s, the research and development of processors have made unprecedented progress. The rise of industries such as the Internet of Things, automotive electronics, and artificial intelligence has made people's demand for high-performance processors increasingly strong.

[0003] Inseparable from the rapid development of processors is the processor debugging system. The design of the debugging system is an inevitable part of the processor development process. The debugging system is one of the most complex parts in the design of processor chips. However, most open-source processor IPs do not have a debugging system. A convenient and efficient debugging system can improve the development efficiency of engineers and accelerate the product development progress. With the increase in the scale of integrated circuits, the difficulty of chip debugging is increasing. Now, the debugging work accounts for more than 35% in the entire chip R & D cycle. At the same time, the continuous increase in chip complexity and the growing demand for concurrent multi-threaded debugging require developers to continuously research and develop powerful debugging systems to achieve rapid debugging and simulation verification of the system. The debugging system mainly consists of a debugging module, a debugging module interface, a debugging transmission module, debugging transmission hardware, and a debugging host.

[0004] As the most critical part of the entire debugging system, the design of the debugging module determines the debugging mechanism of the entire debugging system. At the same time, as the largest part of the entire debugging system, the size of its area also directly affects the working efficiency of the entire debugging system. The RISC-V architecture has advantages such as open source, simplicity, easy portability, and modularity, and can be flexibly applied to debugging scenarios with small area and low power consumption. However, there is currently no specific implementation method and circuit structure scheme for a debugging module specifically for RISC-V, and most current research focuses on single-core debugging, and the proportion of debugging-related hardware resources is relatively high, resulting in not only low working efficiency of the debugging system, but also the inability to complete rapid debugging and simulation verification of processors, especially multi-core processors. Summary of the Invention

[0005] In order to further improve the working efficiency of the debugging system and at the same time solve the problem that the current debugging scheme cannot complete rapid debugging and simulation verification of processors, especially multi-core processors, the present invention provides a debugging module circuit and a method for reading and writing registers for RISC-V.

[0006] The first object of the present invention is to provide a debugging module circuit for RISC-V. The circuit includes: Module 1 and Module 2; Module 1 and Module 2 are connected; Module 1 is used to transfer debugging-related control signals; Module 2 is used to implement debugging commands and store debugging results.

[0007] Optionally, Module 1 includes: a DMI bus conversion module, a bus interconnection module, a DMI register node 1, and a source end of a cross-time domain module;

[0008] The DMI bus conversion module is connected to the bus interconnection module through a TileLink interface, and the bus interconnection module is respectively connected to the DMI register node 1 and the source end of the cross-time domain module through a TileLink interface;

[0009] The DMI bus conversion module is used to convert the DMI bus into a TileLink bus to enable the debugging transmission module to control and access the debugging module through the debugging module interface;

[0010] The bus interconnection module is used to establish connection and access relationships for modules with TileLink bus interfaces;

[0011] The DMI register node 1 contains multiple registers related to the debugging module and CPU cores, which are used to store information, including: reset information of the debugging module, system reset information, the number of CPU cores information, and CPU core selection information.

[0012] Optionally, the registers related to the debugging module and CPU cores in the DMI register node 1 include: control registers, etc.

[0013] Optionally, Module 2 includes: a system bus conversion module, a DMI register node 2, a TileLink register node, a custom node, and a sink end of a cross-time domain module;

[0014] The DMI register node 2 is respectively connected to the sink end of the cross-time domain module and the system bus conversion module through a TileLink bus; the system bus conversion module is respectively connected to the TileLink register node, the custom node, and the DMI register node 2 through a TileLink bus;

[0015] The system bus conversion module is used to convert the system bus into a TileLink bus to enable the debugging transmission module to control and access the debugging module through the system bus;

[0016] The DMI register node 2 contains multiple registers related to the debugging module and the CPU core, which are used to store information, including: system bus address, system bus data, abstract command address, abstract command data, and CPU core configuration information;

[0017] The TileLink register node contains instructions to be executed by the CPU core in debug mode, is connected to the bus of the CPU core, and is incorporated into the address space of the CPU core.

[0018] The custom node is used to access the CPU core.

[0019] Optionally, the registers in the DMI register node 2 related to the debugging module and the CPU core include: a command register, an abstract register, and a data register.

[0020] Optionally, the module 1 and the module 2 are connected via the cross-time domain module source end and the cross-time domain module sink end.

[0021] Optionally, within the module 1, the DMI bus conversion module and the bus interconnection module, the bus interconnection module and the DMI register node 1, and the DMI register node 1 and the cross-time domain module communicate using a VALID and READY handshake mechanism.

[0022] Optionally, within the module 2, a VALID and READY handshake mechanism is used for communication between the system bus conversion module and the DMI register node 2, between the DMI register node 2 and the TileLink register node, and between the TileLink register node and the custom node.

[0023] A second object of the present invention is to provide a register reading method for a RISC-V oriented debugging module circuit, the method being implemented based on the above-mentioned RISC-V oriented debugging module circuit, the method comprising:

[0024] Step 1: Configure the content of DMI register node 1, including: access type, access bit width, read register or write register operation, and register address to be accessed;

[0025] Step 2: Write the command to the DMI register 2 node;

[0026] Step 3: The custom node initiates a request to the arbitration module;

[0027] Step 4: The arbitration module compares the register address information and selects the corresponding CPU core;

[0028] Step 5: After receiving the response, the custom node performs a read operation on the register at the specified address in the corresponding CPU core;

[0029] Step 6: The register value returns to the DMI register node 2, and the flag bit of the DMI register node 2 is read to determine whether the read operation is successful;

[0030] Step 7: Read the register return value at the specified address.

[0031] A third object of the present invention is to provide a register writing method for a RISC-V oriented debugging module circuit, the method being implemented based on the above-mentioned RISC-V oriented debugging module circuit, the method comprising:

[0032] Step 1: Configure the contents of DMI register node 1, including: access type, access bit width, read register or write register operation, data to be written, and register address to be accessed;

[0033] Step 2: Write the command to DMI register node 2;

[0034] Step 3: The custom node initiates a request to the arbitration module;

[0035] Step 4: The arbitration module compares the register address information and selects the corresponding CPU core;

[0036] Step 5: After receiving the response, the custom node completes the write operation on the register at the specified address in the CPU core;

[0037] Step 6: Read the flag bit of DMI register node 2 to determine whether the write operation is successful.

[0038] The beneficial effects of the present invention are:

[0039] The present invention proposes a RISC-V-oriented debugging module circuit and a method for reading and writing registers thereof, thereby realizing the control and access of single-core and multi-core processors through abstract commands or system buses, and the proportion of debugging-related hardware resources is only 0.3% of the total resources. This not only realizes the rapid debugging and simulation verification of single-core and multi-core processors, but also reduces the proportion of hardware resources in the debugging system and improves debugging efficiency. It is of great value for improving the debugging mechanism of the debugging system and improving debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1It is the external logic block diagram of the RISC-V oriented debug module in an embodiment of the present invention.

[0042] Figure 2 It is the internal logic block diagram of the RISC-V oriented debug module in an embodiment of the present invention.

[0043] Figure 3 It is the overall block diagram of the RISC-V oriented debug module in an embodiment of the present invention. Detailed implementation manners

[0044] To make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0045] Embodiment 1:

[0046] This embodiment provides a RISC-V oriented debug module circuit, as Figure 3 shown. The debug module consists of Module 1 (debug module external logic) and Module 2 (debug module internal logic). Module 1 and Module 2 are interconnected through a cross-domain module, which is divided into a source end and a sink end, and the source end and the sink end are respectively arranged in Module 1 and Module 2.

[0047] As Figure 1 shown, Module 1 includes a DMI bus conversion module, a bus interconnection module, a DMI register node 1, and a cross-domain module (source end); as Figure 2 shown, Module 2 includes a system bus conversion module, a DMI register node 2, a TileLink register node, a custom node, and a cross-domain module (sink end).

[0048] Inside Module 1, the DMI bus conversion module is connected to the bus interconnection module through a TileLink interface, the bus interconnection module is respectively connected to the DMI register node 1 and the cross-domain module through a TileLink interface, and Module 1 establishes a connection with Module 2 through the cross-domain module.

[0049] Inside Module 2, the DMI register node 2 and the TileLink register node are respectively connected to the system bus conversion module through a TileLink bus, the DMI register node 2 is connected to the cross-domain module through a TileLink bus, and Module 2 establishes a connection with Module 1 through the cross-domain module.

[0050] For the debug module circuit according to the present invention, within module 1, the DMI bus conversion module is used to convert the DMI bus into a TileLink bus to enable the debug transmission module to control and access the debug module through the debug module interface. The bus interconnection module is used to establish connection and access relationships among multiple modules with TileLink bus interfaces. The DMI register node 1 contains multiple registers related to the debug module and CPU cores, such as control registers, etc. The control registers store information such as debug module reset, system reset, and the number and selection of CPU cores. The cross-time-domain module (source end) is used to establish the connection between module 1 and module 2 in the debug module, and transfer control information from module 1 to module 2 through the cross-time-domain module. The definition and related information of the control registers are shown in Table 1.

[0051] Table 1 Definition of Control Registers

[0052]

[0053] Within module 2, the system bus conversion module is used to convert the system bus into a TileLink bus to enable the debug transmission module to control and access the debug module through the system bus. The DMI register node 2 contains multiple registers related to the debug module and CPU cores, such as command registers, abstract registers, data registers, etc., which store information such as system bus address, system bus data, abstract command address, abstract command data, and CPU core configuration. The TileLink register node contains the instructions to be executed by the CPU core in the debug mode, and is connected to the bus of the CPU core and incorporated into the address space of the CPU core. The custom node is used to access the module to be debugged, i.e., the CPU core. When there are multiple cores, the custom node will first access the arbitration module, which contains the address information of multiple CPU cores, and access a specific CPU core through selection. The cross-time-domain module (sink end) is used to establish the connection between module 2 and module 1 in the debug module, and receive the control information transmitted by module 1 through the cross-time-domain module. The definition and related information of the command registers and abstract registers are shown in Table 2 and Table 3 respectively.

[0054] Table 2 Definition of Command Registers

[0055]

[0056] Taking the access to CPU core registers as an example, when cmdtype is 0, control includes fields aarsize, aarpostincrement, postexec, transfer, write, and regno. Among them, the aarsize field represents the access width, 2 means 32-bit access, 3 means 64-bit access, and 4 means 128-bit access. aarpostincrement being 1 means automatically incrementing the value of regno after successfully accessing the register. postexec being 1 means executing the instructions in the program buffer, transfer being 0 means not performing the operation specified by write, and being 1 means performing the operation specified by write. write being 0 means reading data from the register specified by regno, and being 1 means writing data to the register specified by regno. regno represents the register to be accessed.

[0057] Table 3 Abstract Register Definition

[0058]

[0059] There are 12 data registers (data0 to data11), and these 12 registers are data registers for commands. Taking the access to CPU core registers as an example, the data source for writing to the register and the value read from the register are both stored in the data registers.

[0060] According to the debugging module circuit of the present invention, within module 1, between the dmi bus conversion module and the bus interconnection module, between the bus interconnection module and the dmi register node 1, and between the dmi register and the cross-time domain module, communication is carried out using the VALID and READY handshaking mechanism. Also, within module 2, between the system bus conversion module and the dmi register node 2, between the dmi register node 2 and the TileLink register node, and between the TileLink register and the custom node, communication is carried out using the VALID and READY handshaking mechanism.

[0061] This embodiment provides a debugging module circuit for RISC-V, which realizes the control and access to the CPU core through abstract commands or the system bus. The debugging module circuit proposed in this embodiment is convenient, efficient, and has a low resource occupancy ratio, which has important value for improving the debugging mechanism of the debugging system and enhancing the debugging efficiency.

[0062] Embodiment 2

[0063] This embodiment provides a method for reading registers of a debugging module for RISC-V. When reading CPU core registers, the method includes the following steps:

[0064] Step 1: Configure the content of the DMI register node 1. Set the value of cmdtype in the command register to 0, the value of aarsize to 2, the value of transfer to 1, the value of regno to the number of the register to be read, and other values to 0.

[0065] Step 2: Write the command into the command register.

[0066] Step 3: The custom node sends a request to the arbitration module.

[0067] Step 4: The arbitration module compares the register address information and selects the corresponding CPU core.

[0068] Step 5: After the custom node receives the response, perform a read operation on the register at the specified address in the corresponding CPU core.

[0069] Step 6: Keep reading the abstract register until the busy bit of the abstract register is 0 or a timeout occurs.

[0070] Step 7: Determine whether the value of cmderr in the abstract register is 0. If it is not 0, it means that the read register fails this time. If it is 0, it means that the read register is successful.

[0071] Step 8: Read the data register to obtain the value of the register at the specified address of the CPU core.

[0072] This embodiment provides a method for reading registers, which realizes the reading of registers by the RISC-V-oriented debugging module circuit in the present invention.

[0073] Embodiment 3

[0074] This embodiment provides a method for reading registers of an RISC-V-oriented debugging module. When writing to the CPU core register, the method includes the following steps:

[0075] Step 1: Write the value to be written into the data register.

[0076] Step 2: Configure the content of the DMI register node 1. Set the value of cmdtype in the command register to 0, the value of aarsize to 2, the value of transfer to 1, the value of write to 1, the value of regno to the number of the register to be read, and other values to 0.

[0077] Step 3: Write the command into the command register.

[0078] Step 4: The custom node sends a request to the arbitration module.

[0079] Step 5: The arbitration module compares the register address information and selects the corresponding CPU core.

[0080] Step 6: After the custom node receives the response, perform a write operation on the register at the specified address in the corresponding CPU core.

[0081] Step 7: Keep reading the abstract register until the busy bit of the abstract register is 0 or a timeout occurs.

[0082] Step 8: Determine whether the value of cmderr in the abstract register is 0. If it is not 0, it means that the write register fails this time. If it is 0, it means that the write register is successful.

[0083] This embodiment provides a method for writing a register, which realizes the writing of the register by the debugging module circuit for RISC-V in the present invention.

[0084] Some steps in the embodiments of the present invention can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0085] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A debugging module circuit for RISC-V, characterized in that, The circuit includes: Module 1 and Module 2; Module 1 and Module 2 are connected; Module 1 is used to transfer debugging-related control signals; Module 2 is used to implement debugging commands and store debugging results; Module 1 includes: a DMI bus conversion module, a bus interconnection module, a DMI register node 1, and the source end of the cross-time-domain module; The DMI bus conversion module is connected to the bus interconnection module through a TileLink interface, and the bus interconnection module is respectively connected to the DMI register node 1 and the source end of the cross-time-domain module through a TileLink interface; The DMI bus conversion module is used to convert the DMI bus into a TileLink bus to enable the debugging transfer module DTM to control and access the debugging module through the debugging module interface; The bus interconnection module is used to establish connection and access relationships for modules with TileLink bus interfaces; The DMI register node 1 contains multiple registers related to the debugging module and CPU cores for storing information, including: reset information of the debugging module, system reset information, the number of CPU cores information, and CPU core selection information.

2. The circuit according to claim 1, wherein the registers related to the debug module and the CPU core in the DMI register node 1 include: Control register.

3. The circuit according to claim 1, wherein Module 2 includes: a system bus conversion module, a DMI register node 2, a TileLink register node, a custom node, and the sink end of the cross-time-domain module; The DMI register node 2 is respectively connected to the sink end of the cross-time-domain module and the system bus conversion module through a TileLink bus; the system bus conversion module is respectively connected to the TileLink register node, the custom node, and the DMI register node 2 through a TileLink bus; The system bus conversion module is used to convert the system bus into a TileLink bus to enable the debugging transfer module to control and access the debugging module through the system bus; The DMI register node 2 contains multiple registers related to the debugging module and CPU cores for storing information, including: system bus address, system bus data, abstract command address, abstract command data, and CPU core configuration information; The TileLink register node contains the instructions to be executed by the CPU core in the debugging mode, and is connected to the bus of the CPU core and incorporated into the address space of the CPU core; The custom node is used to access the CPU core.

4. The circuit according to claim 3, wherein, The registers related to the debugging module and CPU cores in the DMI register node 2 include: command register, abstract register, and data register.

5. The circuit according to claim 3, characterized in that, Module 1 and Module 2 are connected through the source end of the cross-time-domain module and the sink end of the cross-time-domain module.

6. The circuit according to claim 1, characterized in that, Inside Module 1, between the DMI bus conversion module and the bus interconnection module, between the bus interconnection module and the DMI register node 1, and between the DMI register node 1 and the cross-time-domain module, communication is carried out using the VALID, READY handshaking mechanism.

7. The circuit according to claim 3, wherein In the module 2, the system bus conversion module and the DMI register node 2, the DMI register node 2 and the TileLink register node, and the TileLink register node and the custom node communicate using the VALID and READY handshake mechanism.

8. A method for reading registers of a debug module circuit for RISC-V, characterized in that, The method is implemented based on the RISC-V-oriented debugging module circuit according to any one of claims 1 to 7, and the method includes: Step 1: Configure the content of DMI register node 1, including: access type, access bit width, read register or write register operation type, and register address to be accessed; Step 2: Write the command to DMI register node 2; Step 3: The custom node initiates a request to the arbitration module; Step 4: The arbitration module compares the register address information and selects the corresponding CPU core; Step 5: After receiving the response, the custom node performs a read operation on the register at the specified address in the corresponding CPU core; Step 6: The register value returns to the DMI register node 2, and the flag bit of the DMI register node 2 is read to determine whether the read operation is successful; Step 7: Read the register return value at the specified address.

9. A method for writing registers in a debug module circuit for RISC-V, characterized in that, The method is implemented based on the RISC-V-oriented debugging module circuit according to any one of claims 1 to 7, and the method includes: Step 1: Configure the contents of DMI register node 1, including: access type, access bit width, read register or write register operation type, data to be written, and register address to be accessed; Step 2: Write the command to DMI register node 2; Step 3: The custom node initiates a request to the arbitration module; Step 4: The arbitration module compares the register address information and selects the corresponding CPU core; Step 5: After receiving the response, the custom node completes the write operation on the register at the specified address in the CPU core; Step 6: Read the flag bit of DMI register node 2 to determine whether the write operation is successful.

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