Preparation method of silicon carbide material

Abstract

The present invention provides a method for preparing a silicon carbide material, the method comprising the following steps: performing a first annealing process on a wafer or a crystal. The conditions of the first annealing process include: using a heating rate of 10°C / min to 30°C / min, performing the first annealing process at an annealing temperature below 2000°C, and performing a constant temperature annealing time of greater than 2 minutes and less than 4 hours. After performing the first annealing process, the average resistivity of the wafer or the crystal is greater than 10 10 Ω·cm.

Description

Technical Field

[0001] The present invention relates to a method for preparing a silicon carbide material, and in particular to a method for preparing a silicon carbide material with high resistivity characteristics. Background Art

[0002] Generally speaking, to achieve high resistance in high-purity crystals, they must be annealed at temperatures between 2000°C and 2400°C, followed by a rapid annealing process at 30°C / min to 150°C / min, to create point defects and ultimately achieve the desired high resistivity. However, annealing at temperatures above 2000°C can easily degrade the quality of the crystal or wafer, or even cause it to crack.

[0003] Therefore, how to improve the resistivity of the crystal / wafer while avoiding quality degradation or cracking of the crystal / wafer is a problem that needs to be solved. Summary of the Invention

[0004] The present invention provides a method for preparing a silicon carbide material (such as a wafer or a crystal), which can improve the resistivity of the crystal / wafer while avoiding quality degradation or cracking of the crystal / wafer.

[0005] A method for preparing a silicon carbide material according to the present invention comprises the following steps: performing a first annealing process on a wafer or a crystal. The conditions of the first annealing process include: performing the first annealing process at an annealing temperature below 2000°C and a constant temperature annealing time of greater than 2 minutes and less than 4 hours using a heating rate of 10°C / min to 30°C / min. After performing the first annealing process, the average resistivity of the wafer or the crystal is greater than 10 10 Ω·cm.

[0006] In an embodiment of the present invention, the first annealing process is performed on the crystal, and the average resistivity of the wafer formed after the crystal is cut is greater than 10 10 Ω·cm.

[0007] In an embodiment of the present invention, the method further includes polishing the wafer formed after dicing and then performing a second annealing process. Conditions of the second annealing process include: using a heating rate of 10°C / min to 30°C / min, an annealing temperature below 2000°C, and a constant temperature annealing time of more than 2 minutes.

[0008] In an embodiment of the present invention, the first annealing process is performed on the wafer, and the first annealing process is performed after the wafer is polished.

[0009] In an embodiment of the present invention, the annealing temperature ranges from 1950°C to 2000°C.

[0010] In an embodiment of the present invention, the annealing temperature ranges from 1950°C to 1980°C.

[0011] In an embodiment of the present invention, the heating rate is 25°C / min to 30°C / min, and the average resistivity of the wafer or crystal is greater than 5*10 11 The Ω·cm portion occupies 100% of the area of the wafer or crystal.

[0012] In an embodiment of the present invention, the heating rate is 22°C / min to 26°C / min, and the average resistivity of the wafer or crystal is greater than 10 11 The Ω·cm portion occupies 100% of the area of the wafer or crystal.

[0013] In an embodiment of the present invention, the heating rate is 20°C / min to 24°C / min, and the average resistivity of the wafer or crystal is greater than 5*10 10 The Ω·cm portion occupies 100% of the area of the wafer or crystal.

[0014] In an embodiment of the present invention, the heating rate is 10°C / min to 20°C / min, and the average resistivity of the wafer or crystal is greater than 10 10 The Ω·cm portion occupies 100% of the area of the wafer or crystal.

[0015] The present invention further provides a silicon carbide material, wherein the silicon carbide material comprises a wafer or a crystal, and the average resistivity of the wafer or the crystal is greater than 10 10 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

[0016] In an embodiment of the present invention, the average resistivity of the wafer or the crystal is greater than 5*10 10 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

[0017] In an embodiment of the present invention, the average resistivity of the wafer or the crystal is greater than 10 11 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

[0018] In an embodiment of the present invention, the average resistivity of the wafer or the crystal is greater than 5*10 11 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

[0019] Based on the above, by using the silicon carbide material preparation method according to the embodiment of the present invention, the atoms in the silicon carbide material can be arranged more neatly, and the resistivity of the wafer / crystal can be improved. In addition, by reducing the annealing temperature and heating rate during the annealing process, the resistivity can be improved while avoiding quality degradation or cracking of the crystal / wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a flow chart of a method for preparing a silicon carbide material according to an embodiment of the present invention;

[0021] Figures 2A to 2C is a schematic cross-sectional view of a method for preparing silicon carbide material according to some embodiments of the present invention;

[0022] Figure 3 is a flow chart of a method for preparing a silicon carbide material according to another embodiment of the present invention;

[0023] Figures 4A to 4C is a schematic cross-sectional view of a method for preparing silicon carbide material according to some embodiments of the present invention;

[0024] Figures 5A to 5C is a schematic cross-sectional view of a method for preparing silicon carbide material according to some embodiments of the present invention.

[0025] Description of Reference Numerals

[0026] 100: Crystal

[0027] 100A: First surface

[0028] 100B: Second surface

[0029] 100W: Silicon carbide wafer

[0030] AN1: First annealing process

[0031] AN2: Second annealing process

[0032] D1: First direction

[0033] D2: Second direction

[0034] S10, S12, S122, S14: Steps

[0035] S20, S202, S22, S24, S26, S28: Step Ω·cm DETAILED DESCRIPTION

[0036] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0037] Figure 1 4 is a flow chart of a method for preparing silicon carbide material according to an embodiment of the present invention. Figures 2A to 2C is a cross-sectional schematic diagram of a method for preparing silicon carbide material according to some embodiments of the present invention. Figure 1 Steps in coordination Figures 2A to 2CThe cross-sectional schematic diagram of FIG is used to illustrate the method for preparing a silicon carbide wafer according to an embodiment of the present invention.

[0038] refer to Figure 1 Step S10 and Figure 2A and Figure 2B As shown in FIG, the crystal 100 obtained through the crystal growth process is cut to form a wafer. Figure 2A As shown, the crystal 100 can be a crystal 100 formed by a conventional crystal growth process. In some embodiments, the crystal 100 or the ingot can be formed by physical vapor transport (PVT) method, induction heating in a high-temperature furnace to volatilize the solid silicon carbide raw material, and then deposited on the surface of the seed crystal, growing and thickening. The crystal 100 or the ingot can have different crystal structures depending on the manufacturing method, manufacturing raw materials, and seed crystal orientation. For example, the crystal / ingot of silicon carbide includes 4H-silicon carbide, 6H-silicon carbide, etc. 4H-silicon carbide and 6H-silicon carbide belong to the hexagonal crystal system. In some embodiments, the crystal 100 includes a first surface 100A and a second surface 100B opposite to the first surface 100A. The first surface 100A is, for example, a carbon surface, and the second surface 100B is, for example, a silicon surface.

[0039] like Figure 2B As shown, after the growth of the crystal 100 is completed, the crystal 100 is cut. For example, the edges and corners of the crystal 100 are cut into equal diameter cylinders along the first direction D1, and are ground into rounded corners to prevent the edges and corners of the wafer from breaking due to collision. Next, the crystal 100 is sliced along the second direction D2 to cut and separate multiple wafers. The slicing method of the crystal 100 includes cutting with a tool or steel wire in combination with abrasive particles (abrasive particles such as diamond particles). After slicing and grinding and polishing the crystal 100, multiple wafers such as Figure 2C The silicon carbide wafer 100W is shown.

[0040] Next, refer to Figure 1 Step S12 and Figure 2C As shown, the first annealing process AN1 is performed on the silicon carbide wafer 100W. In some embodiments, the conditions of the first annealing process AN1 include performing step S122. Specifically, step S122 includes performing the first annealing process AN1 at an annealing temperature below 2000°C and a constant temperature annealing time greater than 2 minutes and less than 4 hours using a heating rate of 10°C / min to 30°C / min. Figure 1 Step S14 and Figure 2C As shown, the average resistivity of the obtained silicon carbide wafer 100W is greater than 10 10 Ω·cm.

[0041] Figure 3 FIG. 4 is a flow chart of a method for preparing a silicon carbide material according to another embodiment of the present invention. Figures 4A to 4C is a cross-sectional schematic diagram of a method for preparing silicon carbide material according to some embodiments of the present invention. Figures 5A to 5C is a cross-sectional schematic diagram of a method for preparing silicon carbide material according to some embodiments of the present invention. Figure 3 In the steps, cooperate Figures 4A to 4C A cross-sectional diagram or Figures 5A to 5C The cross-sectional schematic diagram of FIG is used to illustrate the preparation method of the silicon carbide material according to the embodiment of the present invention.

[0042] like Figure 3 Step S20 and Figure 4A and Figure 5A As shown, a first annealing process AN1 is performed on the crystal 100 obtained through the crystal growth process. Figure 4A and Figure 5A The crystal 100 shown may be used, for example, with Figure 2A The crystal 100 shown in FIG is obtained by a similar process and will not be described in detail here. In some embodiments, the conditions of the first annealing process AN1 include performing step S202. Specifically, step S202 includes performing the first annealing process AN1 at an annealing temperature below 2000°C using a heating rate of 10°C / min to 30°C / min, and a constant temperature annealing time greater than 2 minutes and less than 4 hours.

[0043] In some embodiments, after performing the first annealing process AN1, Figure 3 Step S22 shown in FIG. 1 determines whether the average resistivity of the crystal 100 is greater than 10 10 Ω·cm. If the average resistivity of the crystal 100 is greater than 10 10 Ω·cm, then Figure 4B The crystal 100 is sliced directly to separate multiple wafers. After the crystal 100 is sliced and polished, multiple wafers can be obtained. Figure 4C The silicon carbide wafer 100W is shown. Figure 3 Step S24 and Figure 4C As shown, the average resistivity of the silicon carbide wafer 100W formed after cutting will also be greater than 10 10 Ω·cm.

[0044] In some other embodiments, if it is determined in step S22 that the average resistivity of the crystal 100 after the first annealing process AN1 still cannot meet the requirement of being greater than 10 10 Ω·cm range, then Figure 3 Step S26 and Figure 5B and Figure 5CAs shown, the wafer 100W formed after cutting is ground and polished, and then the second annealing process AN2 is performed. Figure 5B As shown, the crystal 100 is sliced to separate multiple wafers. After the crystal 100 is sliced and polished, multiple wafers can be obtained. Figure 5C Next, the second annealing process AN2 is performed on the silicon carbide wafer 100W.

[0045] In some embodiments, the conditions of the second annealing process AN2 include: performing the second annealing process AN2 at an annealing temperature below 2000° C. and a constant temperature annealing time greater than 2 minutes and less than 4 hours using a heating rate of 10° C. / min to 30° C. / min. Figure 3 Step S28 and Figure 5C As shown, the average resistivity of the silicon carbide wafer 100W obtained after the second annealing process AN2 is greater than 10 10 Ω·cm.

[0046] In the above-mentioned embodiment, whether it is the first annealing process AN1 or the second annealing process AN2, the annealing temperature is below 2000°C, and for example, the annealing temperature range is 1950°C to 2000°C. In some preferred embodiments, the annealing temperature ranges from 1950°C to 1980°C. In addition, the time of constant temperature annealing is greater than 2 minutes and less than 4 hours, preferably greater than 10 minutes and less than 3 hours, and most preferably greater than 30 minutes and less than 2 hours. Accordingly, when the annealing temperature and constant temperature annealing time are controlled within the above-mentioned range, the resistivity of the crystal / wafer can be improved while avoiding the quality degradation or cracking of the crystal / wafer.

[0047] Furthermore, in the above-mentioned embodiments, the heating rate of the first annealing process AN1 or the second annealing process AN2 is controlled within a range of 10°C / min to 30°C / min. For example, in some embodiments, when the heating rate is within a range of 25°C / min to 30°C / min, the average resistivity of the resulting wafer 100W or crystal 100 is greater than 5*10 11 Ω·cm portion accounts for 100% of the area of the wafer 100W or crystal 100. In some embodiments, when the heating rate is in the range of 22°C / min to 26°C / min, the average resistivity of the obtained wafer 100W or crystal 100 is greater than 10 11 Ω·cm accounts for 100% of the area of the wafer 100W or the crystal 100. In some embodiments, when the heating rate is in the range of 20°C / min to 24°C / min, the average resistivity of the obtained wafer 100W or the crystal 100 is greater than 5*10 10The portion of Ω·cm accounts for 100% of the area of the wafer 100W or the crystal 100. In some embodiments, when the heating rate is in the range of 10°C / min to 20°C / min, the average resistivity of the obtained wafer 100W or the crystal 100 is greater than 10 10 The Ω·cm portion occupies 100% of the area of the wafer 100W or the crystal 100 .

[0048] Accordingly, when the heating rate is controlled within the above range, the resistivity of the crystal / wafer can be improved while avoiding quality degradation or cracking of the crystal / wafer.

[0049] In order to demonstrate that the method for preparing a silicon carbide wafer of the present invention can simultaneously improve the resistivity of the wafer and prevent quality degradation or cracking thereof, the following experimental examples will be used for illustration.

[0050] Experimental Example A

[0051] In the following experimental examples, the annealing process of the present invention was performed on wafers formed after dicing, and their average resistivity was determined. The annealing temperature was controlled at 1950°C, the constant-temperature annealing time was 30 minutes, and the heating rate was adjusted within a range of 10°C / min to 30°C / min. The average resistivity of the wafers, as determined by adjusting the heating rate, is shown in Table 1.

[0052] Table 1

[0053]

[0054] From the experimental examples in Table 1 above, it can be confirmed that when the annealing process of the present invention is used to prepare silicon carbide wafers, the average resistivity of the wafer can be effectively controlled to be greater than 10 10 As shown in Experimental Example A1, when the heating rate is adjusted within the range of 10°C / min to 20°C / min, the average resistivity of the silicon carbide wafer is greater than 10 10 The Ω·cm portion can account for 80% to 100% of the entire chip area. As shown in Experiment A2, when the heating rate is adjusted within the range of 20℃ / min to 24℃ / min, the average resistivity of the silicon carbide wafer is greater than 5*10 10 The Ω·cm portion can account for 80% to 100% of the entire chip area. As shown in Experiment A3, when the heating rate is adjusted within the range of 22℃ / min to 26℃ / min, the average resistivity of the silicon carbide wafer is greater than 10 11 The Ω·cm portion can account for 80% to 100% of the entire chip area. As shown in Experiment A4, when the heating rate is adjusted within the range of 25℃ / min to 30℃ / min, the average resistivity of the silicon carbide wafer is greater than 5*10 11 The Ω·cm portion can occupy 80% to 100% of the entire chip area.

[0055] Experimental Example B

[0056] To further confirm the correlation between annealing temperature and the resistivity and quality of wafers / crystals, the annealing process of the present invention was performed on the crystals in this experimental example. The annealing time was 30 minutes, the heating rate was 10°C / minute, and the annealing temperature was controlled at 1950°C, 2000°C, or 2050°C. The experimental results are shown in Table 2.

[0057] Table 2

[0058]

[0059] From the experimental results in Table 2, it can be seen that when the annealing temperature of the present invention (Experimental Examples B2 and B3) is used to perform the annealing process, the crystal can achieve a better (10 10 Ω·cm) and avoid the problem of crystal damage. As shown in Experiment B2 in Table 2, when the annealing temperature is controlled at 1950℃, the crystal is not damaged and the resistivity is good (10 10 Ω·cm or more). In addition, as shown in Experiment B3 in Table 2, when the annealing temperature is controlled at 2000°C, the crystal is slightly damaged, but the resistivity is still maintained well (10 10 Ω·cm or more).

[0060] In contrast, as shown in Experiment B1 in Table 2, when the annealing temperature is controlled at 1850°C, the crystal cannot achieve the ideal resistivity (10 10 Ω·cm or less). In addition, as shown in Experiment B4 in Table 2, when the annealing temperature is controlled at 2050°C, the higher annealing temperature increases the risk of crystal damage due to the slower heating rate than the traditional method. Therefore, the surface of the crystal will become black and damaged due to carbonization, thereby deteriorating the resistivity (10 10 Ω·cm or less).

[0061] Experimental Example C

[0062] To further confirm the correlation between the heating rate and the resistivity of the wafer / crystal, in this experimental example, the wafer was subjected to the annealing process of the present invention. The annealing temperature was controlled at 1950°C, the constant temperature annealing time was 30 minutes, and the heating rate was adjusted within a range of 10°C / min to 40°C / min. The experimental results are shown in Table 3.

[0063] Table 3

[0064] Experimental Example C1 Experimental Example C2 Experimental Example C3 Experimental Example C4 Heating rate 10℃ / min 20℃ / min 30℃ / min 40℃ / min Resistivity good good good Difference

[0065] From the experimental results in Table 3, it can be seen that when the heating rate of the present invention (experimental examples C1 to C3) is used to perform the annealing process, the wafer can achieve a better (10 10 Ω·cm or more). In contrast, as shown in Experiment C4 in Table 3, when the heating rate is controlled to a range of 40°C / min, which is outside the scope of the present invention, the resistivity becomes worse (10 10 Ω·cm or less).

[0066] In summary, the method for preparing silicon carbide materials according to embodiments of the present invention can achieve a more uniform atomic arrangement within the silicon carbide material and improve the resistivity of the wafer / crystal. Furthermore, by reducing the annealing temperature and heating rate during the annealing process and controlling the annealing temperature and heating rate within a certain range, the resistivity can be improved while preventing degradation or cracking of the crystal / wafer.

Claims

1. A method for preparing silicon carbide material, characterized in that: include: A first annealing process is performed on the wafer or crystal, wherein conditions of the first annealing process include: The first annealing process is performed at an annealing temperature of 1950° C. to 2000° C. and a constant temperature annealing time of more than 2 minutes and less than 4 hours using a heating rate of 10° C. / min to 30° C. / min, After performing the first annealing process, the average resistivity of the wafer or the crystal is greater than 10 10 Ω·cm.

2. The method according to claim 1, characterized in that The first annealing process is performed on the crystal, and the average resistivity of the wafer formed after the crystal is cut is greater than 10 10 Ω·cm.

3. The method according to claim 2, characterized in that The method further includes polishing the wafer formed after cutting and then performing a second annealing process, wherein the conditions of the second annealing process include: The second annealing process is performed at a heating rate of 10° C. / min to 30° C. / min, an annealing temperature below 2000° C., and a constant temperature annealing time greater than 2 minutes and less than 4 hours.

4. The method according to claim 1, wherein The first annealing process is performed on the wafer, and the first annealing process is performed after the wafer is polished.

5. The method according to claim 1, wherein The annealing temperature is 1950°C to 1980°C.

6. The method according to claim 1, characterized in that The heating rate is 25°C / min to 30°C / min, and the average resistivity of the wafer or the crystal is greater than 5*10 11 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

7. The method according to claim 1, characterized in that The heating rate is 22°C / min to 26°C / min, and the average resistivity of the wafer or the crystal is greater than 10 11 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

8. The method according to claim 1, characterized in that The heating rate is 20°C / min to 24°C / min, and the average resistivity of the wafer or the crystal is greater than 5*10 10 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

9. The method according to claim 1, characterized in that The heating rate is 10°C / min to 20°C / min, and the average resistivity of the wafer or the crystal is greater than 10 10 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

10. A silicon carbide material obtained by the preparation method of claim 1, wherein the silicon carbide material comprises a wafer or a crystal, and the average resistivity of the wafer or the crystal is greater than 10 10 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

11. The silicon carbide material according to claim 10, characterized in that The average resistivity of the wafer or the crystal is greater than 5*10 10 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

12. The silicon carbide material according to claim 10, characterized in that The average resistivity of the wafer or the crystal is greater than 10 11 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

13. The silicon carbide material according to claim 10, characterized in that The average resistivity of the wafer or the crystal is greater than 5*10 11 The Ω·cm portion occupies 100% of the area of the wafer or the crystal.

14. The silicon carbide material according to claim 10, characterized in that The damage rate of the wafer or the crystal is less than 5%.

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