semiconductor packaging devices

Abstract

The present disclosure relates to a semiconductor packaging device. The semiconductor packaging device includes a molding layer covering a first component and a second component, with electrical connection points between the first and second components exposed. The semiconductor packaging device utilizes a molding material instead of existing substrate materials, reducing the number of materials used in the semiconductor packaging device, lowering the inconsistency of thermal expansion coefficients, preventing warping during manufacturing, and improving product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging device. Background Art

[0002] Nowadays, miniaturization and multifunctionality of electronic devices have become a development trend, which correspondingly puts higher requirements on the miniaturization of semiconductor packaging devices.

[0003] To miniaturize semiconductor packaging devices, various electronic components are typically embedded within a substrate for packaging. This embedding method can reduce package size and, on the one hand, shorten the electrical transmission path, thereby reducing power consumption. However, these embedded semiconductor packaging devices involve multiple materials, including substrate materials, chip materials, and molding materials. These materials often have inconsistent coefficients of thermal expansion (CTE), which can cause warping of the overall structure during thermal processing, thereby reducing product yield.

[0004] Therefore, it is necessary to propose a new technical solution to solve at least one of the above technical problems. Summary of the Invention

[0005] The present disclosure provides a semiconductor packaging device.

[0006] The semiconductor packaging device provided by the present disclosure includes:

[0007] The molding layer covers the first element and the second element, and the electrical connection points of the first element and the second element are exposed.

[0008] In an optional embodiment, a conductive member is disposed in the mold layer, a first end of the conductive member is exposed from a first surface of the mold layer, and a second end of the conductive member is exposed from a second surface of the mold layer.

[0009] In an optional embodiment, the longitudinal dimension of the conductive member is the same as the thickness of the mold layer.

[0010] In an optional embodiment, the electrical connection points of the first element and the second element are exposed from the first surface of the mold layer.

[0011] In an optional embodiment, the electrical connection points of the first element and the second element are located at the same horizontal plane as the first surface of the molding layer.

[0012] In an optional embodiment, the electrical connection point between the first element and the second element is lower than the first surface of the molding layer.

[0013] In an optional embodiment, the electrical connection point of the first element includes a first electrical connector and a second electrical connector, wherein the first electrical connector is exposed from the first surface of the mold layer, and the second electrical connector is exposed from the second surface of the mold layer.

[0014] In an optional embodiment, the electrical connection point of the second component includes a third electrical connector, the third electrical connector is exposed from the first surface of the mold layer, and the third electrical connector and the first electrical connector are located at the same horizontal plane.

[0015] In an optional embodiment, the semiconductor packaging device further includes:

[0016] The first circuit layer is located on the mold layer and is electrically connected to the first element and the second element through the electrical connection points of the first element and the second element respectively.

[0017] In an optional embodiment, a vertical distance from the first circuit layer to the first component is the same as a vertical distance from the first circuit layer to the second component.

[0018] In an optional embodiment, the semiconductor packaging device further includes:

[0019] The second circuit layer is located on a side of the mold layer opposite to the first circuit layer, and is electrically connected to the first component through an electrical connection point of the first component.

[0020] In an optional embodiment, a side surface of the molding layer is located at the outermost side of the semiconductor package device.

[0021] In an optional embodiment, the side surface of the molding layer has a longitudinally extending portion, and the longitudinally extending portion at least partially covers the side surface of the first circuit layer.

[0022] In an optional embodiment, the mold layer has a laterally extending portion, and the laterally extending portion is located between the first component and the first circuit layer.

[0023] In an optional embodiment, a bottom filling material is provided between the first component and the first circuit layer.

[0024] In an optional embodiment, a protective layer is provided on the surface of the molded layer, and the longitudinally extending portion covers the protective layer.

[0025] In an optional embodiment, the electrical connection points of the first element and the second element are electrically connected to the conductive pads of the first circuit layer through solder.

[0026] In the semiconductor packaging device provided by the present invention, the first element and the second element are covered by a molding layer and the electrical connection points are exposed to the outside. The molding material is used to replace the existing substrate material, which reduces the types of materials in the semiconductor packaging device, reduces the inconsistency of the thermal expansion coefficient, and can prevent warping during the manufacturing process, which is conducive to improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present disclosure will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

[0028] Figure 1 is a schematic diagram of a semiconductor packaging device in the prior art;

[0029] Figure 2-Figure 6 are first to fifth schematic diagrams of a semiconductor package device according to an embodiment of the present disclosure;

[0030] Figure 7-12 is a schematic diagram of a method for manufacturing a semiconductor package device according to an embodiment of the present disclosure.

[0031] Explanation of symbols:

[0032] 11. Substrate; 12. Upper circuit; 13. Lower circuit; 14. Left component; 15. Right component; 16. Molding material; 100. Molding layer; 110. Conductive member; 120. Lateral extension; 130. Longitudinal extension; 140. Electrical connection; 210. First component; 211. First electrical connection; 212. Second electrical connection; 213. Third electrical connection; 220. Second component; 310. First circuit layer; 320. Second circuit layer; 321. Thick circuit layer; 322. Thin circuit layer; 329. Conductive pad; 331. First unit; 332. Second unit; 333. Third unit; 400. Solder; 500. Protective layer; 600. Bottom filling material; 910. Carrier; 920. Tape. DETAILED DESCRIPTION

[0033] The following describes specific embodiments of the present disclosure in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present disclosure and the technical effects produced by the present disclosure through the contents of this specification. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0034] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for understanding and reading by those skilled in the art, and are not used to limit the conditions for implementation of the present disclosure. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in the present disclosure without affecting the efficacy and purpose that can be achieved by the present disclosure. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present disclosure. Changes or adjustments in their relative relationships should also be regarded as the scope of implementation of the present disclosure without substantially changing the technical content.

[0035] It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0036] In addition, the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0037] Figure 1 Schematic diagram of a semiconductor packaging device in the prior art. Figure 1 As shown, the semiconductor package device includes a substrate 11, an upper circuit 12 and a lower circuit 13. The substrate 11 is located between the upper circuit 12 and the lower circuit 13. The left component 14 and the right component 15 are embedded in the substrate 11. In addition, a molding material 16 is also provided in the semiconductor package device. Figure 1 In the semiconductor package shown, the thermal expansion coefficients of various components, including substrate 11, circuitry (including upper circuitry 12 and lower circuitry 13), electronic components (including left component 14 and right component 15), and molding material 16, typically differ. During the thermal process, these components deform unevenly due to heat, causing warping of the overall structure. This warping can easily lead to structural failure and reduce product yield.

[0038] This embodiment provides a semiconductor packaging device. Figure 2-Figure 6 1 to 5 are first to fifth schematic diagrams of a semiconductor package device according to an embodiment of the present disclosure.

[0039] Figure 2 FIG1 is a first schematic diagram of a semiconductor package device according to an embodiment of the present disclosure, which shows a longitudinal cross section of the semiconductor package device. Figure 2As shown, the semiconductor package device includes a molding layer 100. The molding layer 100 covers a first component 210 and a second component 220. Electrical connection points are provided on the surface of the first component 210, including a first electrical connector 211 located on the lower surface of the first component 210 and a second electrical connector 212 located on the upper surface of the first component 210. Electrical connection points are also provided on the surface of the second component 220, including a third electrical connector 213 located on the lower surface of the second component 220. The first electrical connector 211, the second electrical connector 212, and the third electrical connector 213 are all exposed outside the molding layer 100, wherein the lower surfaces of the first electrical connector 211 and the third electrical connector 213 are directly exposed, and the upper surface of the second electrical connector 212 is directly exposed. The first component 210 and the second component 220 can be active components (such as chips) or passive components (such as resistors, inductors, or capacitors). The first electrical connector 211, the second electrical connector 212, and the third electrical connector 213 are, for example, conductive pads.

[0040] like Figure 2 As shown, the first electrical connector 211 of the first element 210 and the third electrical connector 213 of the second element 220 are exposed from the lower surface of the mold layer 100, and both are located in the same plane as the lower surface of the mold layer 100. In other embodiments, during the formation of the first electrical connector 211 and the third electrical connector 213, to prevent electrical short circuits, the surfaces of the first electrical connector 211 and the third electrical connector 213 may be micro-etched. As a result, the first electrical connector 211 and the third electrical connector 213 are not completely flush with the surface of the mold layer 100, but are slightly lower than the surface of the mold layer 100.

[0041] like Figure 2 As shown, a conductive member 110 is also disposed within the mold layer 100. The conductive member 110 extends through the mold layer 100. The upper end of the conductive member 110 is exposed from the upper surface of the mold layer 100, and the lower end of the conductive member 110 is exposed from the lower surface of the mold layer 100. The longitudinal dimension of the conductive member 110 is the same as the thickness of the mold layer 100, and its ends are flush with the upper and lower surfaces of the mold layer 100, respectively. The conductive member 110 is, for example, a conductive pillar.

[0042] Figure 6 for Figure 2 The deformation mode of semiconductor packaging device. Figure 6 As shown, the thickness of the second element 220 is less than that of the first element 210. An electrical connection portion 140 is disposed above the second element 220. The electrical connection points on the upper surface of the second element 220 are not directly exposed outside the mold layer 100, but extend to the surface of the mold layer 100 via the electrical connection portion 140.

[0043] Figure 3FIG. 1 is a second schematic diagram of a semiconductor packaging device according to an embodiment of the present disclosure. Figure 3 As shown, the semiconductor package device Figure 2 In addition to the structure shown, the device also includes a first circuit layer 310 and a second circuit layer 320. The first circuit layer 310 is located below the mold layer 100. The conductive pads 329 of the first circuit layer 310 are electrically connected to the first electrical connector 211 via solder 400, thereby electrically connecting the device to the first component 210. The conductive pads 329 of the first circuit layer 310 are also electrically connected to the third electrical connector 213 via solder 400, thereby electrically connecting the device to the second component 220. The vertical distance between the first circuit layer 310 and the first component 210 is the same as the vertical distance between the first circuit layer 310 and the second component 220. The second circuit layer 320 is located above the mold layer 100. The second circuit layer 320 is electrically connected to the second electrical connector 212 via solder 400, thereby electrically connecting the device to the first component 210. The side surfaces of the mold layer 100 are located at the outermost sides of the semiconductor package device. A protective layer 500 is provided on the surface of the mold layer 100. An underfill material 600 is disposed between the protection layer 500 and the second circuit layer 320 .

[0044] like Figure 3 As shown, the first circuit layer 310 and the second circuit layer 320 are respectively connected to the two ends of the conductive member 110 through solder 400. The conductive member 110 can serve as an electrical connection path between the first circuit layer 310 and the second circuit layer 320.

[0045] Figure 4 and Figure 5 Shown Figure 3 The deformation mode of semiconductor packaging device. Figure 4 and Figure 5 As shown, the portion between the protective layer 500 and the second circuit layer 320 is a molding material, thereby forming a transverse extension portion 120 of the molding layer 100. The side of the molding layer 100 also has a longitudinal extension portion 130, which at least partially covers the side of the first circuit layer 310. Figure 4 In the example shown, the longitudinal extension 130 is not covered with the side of the protective layer 500. Figure 5 In the example shown, the longitudinal extensions 130 partially cover the side surfaces of the protective layer 500 .

[0046] Figure 7-12 is a schematic diagram of a method for manufacturing a semiconductor package device according to an embodiment of the present disclosure.

[0047] Figure 7 FIG. 1 shows a manufacturing process of the molding layer 100. Figure 7As shown, first, tape 920 is placed on the surface of carrier 910, and first component 210, second component 220, and conductive member 110 are placed on tape 920. Next, molding is performed on carrier 910 to form mold layer 100, wherein mold layer 100 covers first component 210, second component 220, and conductive member 110. Finally, tape 920 and carrier 910 are removed to obtain mold layer 100.

[0048] Figure 8 and Figure 9 The first method for manufacturing a semiconductor package device in this embodiment is shown. Figure 8 As shown in the upper part, the rough circuit layer 321, the mold layer 100 and the first circuit layer 310 are manufactured respectively. Figure 8 As shown in the middle, the rough circuit layer 321, the mold layer 100 and the first circuit layer 310 are connected to each other in a stacked manner. Figure 8 As shown in the lower part, bottom filling material 600 is respectively provided between the molding layer 100 and the rough circuit layer 321 and between the molding layer 100 and the first circuit layer 310. Figure 9 As shown, a fine circuit layer 322 is formed on the coarse circuit layer 321, wherein the coarse circuit layer 321 and the fine circuit layer 322 together form a second circuit layer 320. Figure 9 The structure shown in the figure is cut into pieces to obtain Figure 3 In addition, electronic components can be further arranged on the fine circuit layer 322.

[0049] Figure 10 The second method for manufacturing the semiconductor package device in this embodiment is shown. Figure 10 As shown in the upper part, the rough circuit layer 321 is divided into a plurality of first units 331, and the plurality of first units 331 are arranged above the mold layer 100. Figure 10 As shown in the middle, molding is performed on the molding layer 100 to form a transverse extension portion 120 and a longitudinal extension portion 130, wherein the transverse extension portion 120 is located between the molding layer 100 and the first unit 331, and the longitudinal extension portion 130 covers the sidewall of the rough circuit layer 321. Figure 10 As shown in the lower part, a plurality of second units 332 (divided by the second circuit layer 320) are arranged under the molding layer 100 and molded. Finally, a fine circuit layer 322 can be formed on the coarse circuit layer 321 and singulated to obtain the following: Figure 4 The semiconductor package device shown.

[0050] Figure 11 The third method for manufacturing the semiconductor package device in this embodiment is shown. Figure 11 As shown in the upper part, the first unit 331 (divided by the thick circuit layer 321), the second unit 332 (divided by the second circuit layer 320) and the third unit 333 (divided by the mold layer 100) are stacked and arranged on the fine circuit layer 322. Figure 11 As shown in the lower part, molding is performed on the fine line layer 322 to form the longitudinal extension 130 and the lateral extension 120. Finally, the Figure 11 The structure shown in the lower part is cut into pieces to obtain Figure 5 The semiconductor package device shown.

[0051] Figure 12 Another method for manufacturing a semiconductor package device according to the present embodiment is shown. Figure 11 The difference between the methods shown is that Figure 12 The method shown is to stack the coarse circuit layer 321, the molding layer 100 and the coarse circuit layer 321 and then separate them. Therefore, the first unit 331, the second unit 332 and the third unit 333 are an integral structure. The above integral structure is placed on the fine circuit layer 322 and molded and cut into pieces. Figure 5 The semiconductor package device shown.

[0052] In the semiconductor packaging device provided by the present disclosure, the first element 210 and the second element 220 are covered by the molding layer 100 and the electrical connection points are exposed to the outside. The molding material is used to replace the existing substrate material, which reduces the types of materials in the semiconductor packaging device, reduces the inconsistency of the thermal expansion coefficient, and can prevent warping during the manufacturing process, which is conducive to improving product yield.

[0053] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A semiconductor packaging device, comprising: a molding layer covering the first element and the second element, wherein electrical connection points of the first element and the second element are exposed; The electrical connection points of the first element and the second element are exposed from the first surface of the mold layer and are lower than the first surface of the mold layer; The electrical connection point of the first component includes a first electrical connection member and a second electrical connection member, wherein the first electrical connection member is exposed from the first surface of the mold layer, and the second electrical connection member is exposed from the second surface of the mold layer; The semiconductor package device further includes: a first circuit layer, located on the mold layer and electrically connected to the first element and the second element through electrical connection points of the first element and the second element respectively; The side surface of the molding layer has a longitudinal extension portion, and the longitudinal extension portion at least partially covers the side surface of the first circuit layer; The molding layer has a lateral extension portion, and the lateral extension portion is located between the first component and the first circuit layer.

2. The semiconductor package device according to claim 1, wherein A conductive element is disposed in the mold layer, a first end of the conductive element is exposed from a first surface of the mold layer, and a second end of the conductive element is exposed from a second surface of the mold layer.

3. The semiconductor package device according to claim 1, wherein The semiconductor packaging device further includes: The second circuit layer is located on a side of the mold layer opposite to the first circuit layer, and is electrically connected to the first component through an electrical connection point of the first component.

4. The semiconductor package device according to claim 1, wherein The side surface of the molding layer is located at the outermost side of the semiconductor package device.

5. The semiconductor package device according to claim 1, wherein A protective layer is provided on the surface of the molding layer, and the longitudinally extending portion covers the protective layer.

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