Semiconductor device and power conversion device

Abstract

The present invention provides a semiconductor device and a power conversion device with improved moisture resistance reliability. The semiconductor device (100) of the present invention comprises: a metal base substrate (11), a first insulating layer (41) provided on a metal base (21), a carrier conductor (31) provided on the first insulating layer (41), and a second insulating layer (51) provided on the side of the carrier conductor (31); a semiconductor element (71) bonded to the carrier conductor (31); a housing (61) provided outside the second insulating layer (51); an external terminal (74) mounted on the housing (61); and a sealing member (77) filling a region surrounded by the carrier conductor (31), the second insulating layer (51), and the housing (61).

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a housing and a power conversion device using the semiconductor device. Background Art

[0002] Conventional semiconductor devices include a metal base substrate and a housing mounted on the metal base substrate, the housing being fixed to the metal base substrate. The metal base substrate comprises a metal plate; a heat transfer layer comprising a thermosetting resin and an inorganic filler, mounted on the metal plate; and a lead frame embedded in the heat transfer layer to form a plurality of electrodes (see, for example, Patent Document 1). The heat transfer layer herein includes a portion disposed in contact with a side surface of the lead frame and contributing to electrical insulation between the electrodes; and a portion disposed between the lead frame and the metal plate and contributing to heat dissipation and electrical insulation.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2009-224445 Summary of the Invention

[0006] However, in these conventional semiconductor devices, a housing is provided over the heat transfer layer of the metal base substrate. This means that the heat transfer layer, which is in contact with the side surfaces of the lead frame, exposes the portion electrically insulating the electrodes to the outside air. Because the heat transfer layer contains a thermosetting resin and an inorganic filler, moisture can intrude through the portion exposed to the outside air. This moisture and electric field can cause corrosion of the metal components at the semiconductor element terminals, potentially damaging the semiconductor element and reducing the reliability of the semiconductor device.

[0007] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device having a housing provided on a metal base substrate, which reduces the amount of moisture reaching the semiconductor element and improves moisture resistance reliability.

[0008] The semiconductor device of the present invention comprises: a metal base substrate having a metal base, a first insulating layer arranged on a surface of the metal base, a carrying conductor arranged on a surface of the first insulating layer opposite to the surface on which the metal base is arranged, and a second insulating layer arranged on a side surface of the carrying conductor so as to expose a surface of the carrying conductor opposite to a surface in contact with the first insulating layer; a semiconductor element bonded to the carrying conductor; a housing arranged on an outer side compared to the second insulating layer; an external terminal mounted on the housing; and a sealing component filling an area surrounded by the carrying conductor, the second insulating layer and the housing.

[0009] The semiconductor device of the present invention can suppress moisture from penetrating through the second insulating layer and reaching the semiconductor element even if the housing is provided on the metal base substrate by arranging the housing outside the second insulating layer, thereby improving moisture resistance reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 1 of the present invention.

[0011] Figure 2 It is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention.

[0012] Figure 3 This is a cross-sectional view showing the structure of a first modified example of the semiconductor device according to the first embodiment of the present invention.

[0013] Figure 4 This is a cross-sectional view showing the structure of a second modified example of the semiconductor device according to the first embodiment of the present invention.

[0014] Figure 5 This is a cross-sectional view showing the structure of a third modified example of the semiconductor device according to the first embodiment of the present invention.

[0015] Figure 6 This is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

[0016] Figure 7 This is a cross-sectional view showing the structure of a modified example of the semiconductor device according to the second embodiment of the present invention.

[0017] Figure 8 This is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

[0018] Figure 9 This is a block diagram showing the configuration of a power conversion system to which a power conversion device according to Embodiment 4 of the present invention is applied.

[0019] (Explanation of Reference Numerals)

[0020] 11, 12, 13, 14, 15: Metal base substrate; 21: Metal base; 31, 32: Carrying conductor; 31A, 32A: First carrying conductor; 31B, 32B: Second carrying conductor; 32C: Upper surface; 41, 42, 43, 44: First insulating layer; 50: Boundary surface; 51, 52, 53: Second insulating layer; 53A: Upper surface; 61, 62, 63: Housing; 62A, 63A: Protrusion; 71: Semiconductor element; 74: External terminal; 77: Sealing component; 81: Solder; 84: Wire; 91: Barrier layer; 100, 101, 102, 103, 200, 201, 300, 402: Semiconductor device; 400: Power conversion device; 401: Main conversion circuit; 403: Control circuit; 410: Power supply; 420: Load. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following drawings, identical or corresponding parts are denoted by identical reference numerals, and their description will not be repeated.

[0022] Implementation method 1.

[0023] use Figure 1 A semiconductor device according to Embodiment 1 of the present invention will be described. Figure 1 is a cross-sectional view showing the structure of the semiconductor device 100 of this embodiment. Figure 2 1 is a top view of the semiconductor device 100. A first insulating layer 41 is provided on the surface of the metal base 21. A carrier conductor 31 is provided on the surface of the first insulating layer 41 opposite to the surface on which the metal base 21 is provided. In this embodiment, the carrier conductor 31 includes a first carrier conductor 31A and a second carrier conductor 31B. Figure 1 In the figure, the case where the carrier conductor 31 includes two, namely the first carrier conductor 31A and the second carrier conductor 31B, is shown, but of course there are cases where there are multiple carrier conductors including more than three. On the side of the carrier conductor 31, the second insulating layer 51 is provided so that the opposite side of the surface of the carrier conductor 31 in contact with the first insulating layer 41 is exposed. The metal base substrate 11 has the above-mentioned metal base 21, the first insulating layer 41, the carrier conductor 31 and the second insulating layer 51. The semiconductor element 71 is placed on the carrier conductor 31 and joined via the solder 81 as a conductive bonding component. In addition, in this embodiment, the case where the semiconductor element 71 is formed of silicon (Si) as a semiconductor material is described as an example. In addition, as a conductive bonding component, a sintered metal bonding component formed by sintering silver particles, copper particles, etc. can also be used. The housing 61 is configured as follows. Figure 1 As shown in the cross-sectional view, on the upper side of the first insulating layer 41, as shown in FIG. Figure 2As shown, the outer side of the second insulating layer 51 is completely surrounded by the outer side of the second insulating layer 51 when viewed from above. Specifically, the housing 61 is provided on the metal base substrate 11. The external terminals 74 are embedded in the housing 61 except for their ends. The area surrounded by the bottom surface formed by the first carrier conductor 31A, the second carrier conductor 31B, and the second insulating layer 51, and the housing 61, is filled with a sealing member 77 to protect the semiconductor element 71 mounted on the carrier conductor 31 from moisture intrusion from the outside air. The semiconductor device 100 further includes a wire 84 serving as a wiring member.

[0024] The metal base 21 and the carrier conductor 31 are not particularly limited and can be formed of a metal material such as copper (Cu) or aluminum (Al), or an alloy such as an aluminum-silicon carbide (AlSiC) alloy or a copper-molybdenum (CuMo) alloy. The metal base 21 and the carrier conductor 31 can be formed of the same material or different materials. Furthermore, the metal base 21 can be mounted with a heat sink made of a metal material such as copper (Cu) or aluminum (Al), or with a heat sink.

[0025] In the semiconductor device 100, the first insulating layer 41 and the second insulating layer 51 are independent components made of different materials. The first insulating layer 41 is provided for the purpose of electrical insulation between the first carrier conductor 31A and the metal base 21, electrical insulation between the second carrier conductor 31B and the metal base 21, heat dissipation from the first carrier conductor 31A to the metal base 21, and heat dissipation from the second carrier conductor 31B to the metal base 21. In other words, the first insulating layer 41 is provided for both electrical insulation and heat dissipation. In contrast, the second insulating layer 51 is provided primarily for the purpose of electrical insulation between the first carrier conductor 31A and the second carrier conductor 31B. Therefore, in the semiconductor device 100 of this embodiment, different materials can be used for the first insulating layer 41 and the second insulating layer 51 to meet the above-mentioned purposes.

[0026] The first insulating layer 41 has high electrical insulation and thermal conductivity and is mainly formed by filling a resin composition with a filler. As the resin composition, thermosetting resins such as epoxy resin, phenolic resin, silicone rubber, etc. are used. In addition, polyethylene, polyimide, acrylic thermoplastic resins, etc. can also be used. As fillers, it is best to use aluminum oxide (Al2O3), boron nitride (BN), aluminum nitride (AlN), diamond (C), silicon carbide (SiC), silicon nitride (Si3N4), boron oxide (B2O3), etc. with high thermal conductivity. In addition, when the thermal conductivity requirement is low, silicon dioxide (SiO2) can be used, or it can be formed with a resin material such as silicone resin or acrylic resin. The filler can be one type or two or more types.

[0027] The second insulating layer 51 has high electrical insulation and is mainly formed by filling a filler in a resin composition. As the resin composition, thermosetting resins such as epoxy resin, phenolic resin, silicone rubber, etc. are used. In addition, polyethylene, polyimide, acrylic thermoplastic resins, etc. can also be used. As fillers, inorganic ceramic materials such as aluminum oxide (Al2O3), boron nitride (BN), aluminum nitride (AlN), diamond (C), silicon carbide (SiC), silicon nitride (Si3N4), silicon dioxide (SiO2), and boron oxide (B2O3) can be used, or resin materials such as silicone resin or acrylic resin can be used. The filler can be one type or two or more types.

[0028] In the metal base substrate 11, the metal base 21, the first insulating layer 41, the carrier conductor 31, and the second insulating layer 51 are integrally formed. In the semiconductor device 100, the thickness of the carrier conductor 31 and the thickness of the second insulating layer 51 are the same. Therefore, it is easy to form by stamping, molding, etc. The forming method is not particularly limited, and for example, the forming process described below can also be used.

[0029] The first example of the forming process is described below. The metal base 21 and the first insulating layer 41 are integrally formed by stamping. A flat plate material, such as a thick copper plate, used as a carrier conductor 31 is patterned by etching or punching to form the carrier conductor 31. In addition, etching can be either single-sided etching or double-sided etching. The carrier conductor 31 is molded integrally with the material constituting the second insulating layer 51. The metal base 21 and the first insulating layer 41, and the integrated carrier conductor 31 and the second insulating layer 51 as described above are integrally formed by stamping to form the metal base substrate 11.

[0030] A second example of the forming process will be described. Similar to the first example, the metal base 21 and the first insulating layer 41 are integrally formed, and a thick copper plate, for example, is patterned to form the carrier conductor 31. Using a mold and through molding, the integrated metal base 21, the first insulating layer 41, the carrier conductor 31, and the material constituting the second insulating layer 51 are integrally formed to form the metal base substrate 11.

[0031] The third example of the forming process is described. Similar to the first example, the metal base 21 and the first insulating layer 41 are integrally formed. The integrated metal base 21 and the first insulating layer 41 are integrally formed by stamping, along with, for example, a thick copper plate, which serves as a flat plate material for the conductor 31. After the thick copper plate, the metal base 21, and the first insulating layer 41 are integrated, the thick copper plate is patterned by etching to form the conductor 31. The material constituting the second insulating layer 51 is poured between the patterns of the conductor 31 and hardened, thereby forming the metal base substrate 11.

[0032] The type of semiconductor element 71 can be an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), or a free wheeling diode (FWD) or other power semiconductor element, or it can be an IC chip or a diode or other control semiconductor element for driving and controlling the power semiconductor element. In this embodiment, the semiconductor element 71 is described as an example of a semiconductor material formed of silicon (Si), but it can also be formed of a wide bandgap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN) or diamond (C). There are multiple semiconductor elements 71, and they can be the same or different in at least one aspect of type and material.

[0033] The housing 61 is formed of a material with low permeability to water. For example, the housing 61 is preferably formed of a thermoplastic resin such as polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), or polyetheretherketone (PEEK). In addition, by ensuring the thickness of the housing 61, a thermosetting resin with relatively high permeability to water can be used. In addition, a fluorine-based resin such as polytetrafluoroethylene (PTFE), a ceramic material, a glass material, or a mixture thereof can also be used. The housing 61 is arranged on the metal base substrate 11. The housing 61 and the metal base substrate 11 are not particularly limited and can also be joined using, for example, an adhesive.

[0034] The external terminal 74 is not particularly limited and may also include a metal material such as copper (Cu) or aluminum (Al). In addition, the wire 84 as a wiring component electrically connects the external terminal 74 and the semiconductor element 71 and is made of a metal material such as copper (Cu) or aluminum (Al). Here, it is also possible to set a lead frame structure in which a wire is not used in the wiring component, but a portion of the carrier conductor is extended to the outside of the insulating layer and bent to serve as the external terminal. However, the external terminal is exposed to the outside air, so when moisture invades from the interface between the external terminal and the housing, a path is formed for moisture to reach the interface between the carrier conductor and the sealing resin in front of the bend of the external terminal, and there is a concern that moisture can easily reach the semiconductor element mounted on the carrier conductor. In contrast, in the semiconductor device 100 of this embodiment, the external terminal 74 and the wire 84 as a wiring component are independently provided and electrically coupled. Generally speaking, the surface area of ​​the wire 84 is smaller than the surface area of ​​the portion of the carrier conductor corresponding to the wire extended in the lead frame structure. That is, by providing the lead 84, the area of ​​the moisture absorption path at the interface with the sealing member 77 is smaller than that of the lead frame structure. Therefore, even if moisture intrudes from the interface between the external terminal and the housing, the intrusion of moisture at the interface between the lead 84 and the sealing member is reduced.

[0035] Sealing member 77 is formed of, for example, an electrically insulating resin such as epoxy resin, silicone resin, urethane resin, polyimide resin, polyamide resin, or acrylic resin. Sealing member 77 may also be formed of an insulating composite material in which a filler is dispersed to improve the mechanical strength and thermal conductivity of sealing member 77. The filler that improves the mechanical strength and thermal conductivity of sealing member 77 may also be formed of, for example, an inorganic ceramic material such as silicon dioxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AlN), boron nitride (BN), silicon nitride (Si3N4), diamond (C), silicon carbide (SiC), or boron oxide (B2O3).

[0036] Next, the effects of the semiconductor device 100 of this embodiment configured as described above will be described. Figure 1In the semiconductor device 100 shown, the carrier conductor 31 is thicker than the first insulating layer 41. Furthermore, the carrier conductor 31 has an area larger than that of the semiconductor element 71 to facilitate areal heat dissipation. The first insulating layer 41 is formed from a composite material, such as epoxy resin, mixed with fillers to enhance thermal conductivity. However, such a composite material has lower thermal conductivity than the metal material or alloy forming the carrier conductor 31, resulting in poorer heat dissipation. Therefore, by making the carrier conductor 31, which has better heat dissipation properties, thicker than the first insulating layer 41, which has relatively poorer heat dissipation properties, heat generated in the semiconductor element 71 is diffused across the thick carrier conductor 31. Heat can be dissipated over a wider area through the first insulating layer 41 to the metal base 21, thereby improving the heat dissipation properties of the semiconductor device. To ensure electrical insulation between the first carrier conductor 31A and the second carrier conductor 31B, the second insulating layer 51, disposed on the side of the carrier conductor 31, becomes thicker as the thickness of the first and second carrier conductors 31A and 31B increases. Therefore, according to the structure of this embodiment, semiconductor device 100, by providing housing 61 outside second insulating layer 51, can suppress moisture intrusion from the sides of second insulating layer 51, thereby preventing degradation of the semiconductor element, even when housing 61 is provided on metal base substrate 11. Consequently, a semiconductor device with improved reliability can be obtained. Furthermore, while the semiconductor device 100 has been described as having a larger area than semiconductor element 71 for heat dissipation, a configuration in which the conductor 31 and semiconductor element 71 have equal areas is also possible. In this case, the semiconductor device can be miniaturized.

[0037] In semiconductor device 100, metal base 21 has an area larger than the sum of the area of ​​carrier conductor 31 and the area of ​​second insulating layer 51. In semiconductor device 100 constructed in this manner, metal base substrate 11 has a stepped structure in the outer peripheral region. Due to this structure, when heat is generated by semiconductor element 71 during operation in semiconductor device 100, the heat is dissipated in the vertical direction via solder 81, carrier conductor 31, first insulating layer 41, and metal base 21, and heat dissipation is also promoted in the area direction. Therefore, semiconductor device 100 has enhanced heat dissipation due to the stepped structure of metal base substrate 11, resulting in a semiconductor device with improved reliability.

[0038] Furthermore, in the semiconductor device 100, the thickness of the carrier conductor 31 is greater than the thickness of the metal base 21. In the semiconductor device 100 of this embodiment, rather than injecting a composite material, such as a filler-filled resin material, between the first carrier conductor 31A and the second carrier conductor 31B as a sealing member, a second insulating layer 51 is provided to form the metal base substrate 11 that integrates the two materials. To miniaturize the semiconductor device, it is desirable to keep the gap between the first carrier conductor 31A and the second carrier conductor 31B as narrow as possible while ensuring electrical insulation. Therefore, in conventional semiconductor devices, when the first carrier conductor 31A and the second carrier conductor 31B are thicker than before, injecting the sealing member into the gap between the first carrier conductor 31A and the second carrier conductor 31B without creating voids has been a problem. In contrast, in the semiconductor device 100 of this embodiment, the increased thickness of the carrier conductor 31 improves heat dissipation across the surface. Furthermore, the integral molding of the metal base substrate 11 minimizes the area between the first carrier conductor 31A and the second carrier conductor 31B, allowing the second insulating layer 51 to be filled without voids, ensuring electrical insulation and enabling miniaturization. Consequently, a miniaturized semiconductor device can be achieved, while achieving improved heat dissipation and reliability.

[0039] Furthermore, the metal base substrate 11 provided in the semiconductor device 100 includes a metal base 21, a first insulating layer 41, a carrier conductor 31, and a second insulating layer 51. Rigidity is primarily ensured by the carrier conductor 31 and the metal base 21. In conventional semiconductor devices, rigidity is maintained for the entire metal base substrate by making the carrier conductor relatively thin and the metal base relatively thick. In such conventional semiconductor devices, when a thin metal base is provided with a heat sink or the like to improve heat dissipation, both the carrier conductor and the metal base are thin, resulting in reduced rigidity for the entire metal base substrate. Therefore, in this embodiment, by making the carrier conductor 31 relatively thick and the metal base 21 relatively thin—that is, making the carrier conductor 31 thicker than the metal base 21—this ensures rigidity for the entire metal base substrate 11 and improves heat dissipation. Furthermore, the thinness of the metal base 21 reduces material costs compared to a configuration where both the carrier conductor 31 and the metal base 21 are thick.

[0040] While the thicknesses of the metal base 21, first insulating layer 41, and carrier conductor 31 are not particularly specified, a metal base substrate 11 with high heat dissipation and rigidity can be obtained by setting the metal base 21 to 500-1000 μm, the first insulating layer 41 to 150-175 μm, and the carrier conductor 31 to 1000-2000 μm. Therefore, with respect to the thicknesses of the metal base 21, first insulating layer 41, and carrier conductor 31, the carrier conductor 31 is the thickest, the metal base 21 is the second thickest, and the first insulating layer 41 is the thinnest, thereby achieving a structure that ensures both heat dissipation and rigidity of the metal base substrate 11.

[0041] Figure 3 FIG. 1 is a cross-sectional view showing the structure of a semiconductor device 101 as a first modification of the semiconductor device of this embodiment. Figure 3 As shown, a convex portion 62A is provided on the outer periphery of the lower surface of the housing 62, and a portion of the housing 62 covers at least a portion of the outer periphery of the first insulating layer 41. According to such a structure, in the semiconductor device 101, it is possible to prevent the position of the housing 62 from being offset relative to the metal base substrate 11. Therefore, it is further suppressed that moisture enters through the gap at the interface due to the positional offset of the housing 62, and it is possible to obtain a semiconductor device with improved reliability. In addition, Figure 3 In the figure, the structure of the semiconductor device 101 is illustrated as a first variant of the semiconductor device 100 of this embodiment, but since the characteristic of this structure lies in the shape of the shell, the shell 62 with the protrusion 62A described here can also be applied to the structure described elsewhere in this embodiment, and can also be applied to other embodiments as long as there is no contradiction.

[0042] Figure 4 FIG2 is a cross-sectional view showing the structure of a semiconductor device 102 as a second modification of the semiconductor device of this embodiment. Figure 4 As shown, the first insulating layer 42 and the second insulating layer 52 may be made of the same material and have an integrated structure without an interface at the boundary surface 50. The semiconductor device 102 constructed in this way can also be formed by stacking the composite material constituting the first insulating layer 42 and the second insulating layer 52 on the metal base 21 during the forming process of the metal base substrate 12, burying the patterned carrier conductor 31 and hardening it. According to such a structure, since the semiconductor device 102 does not have an interface at the boundary surface 50 between the first insulating layer 42 and the second insulating layer 52, the intrusion of moisture from the interface is further suppressed, thereby achieving the effect of obtaining a semiconductor device with improved reliability. In addition, in Figure 4In the figure, as a second variant of the semiconductor device 100 of this embodiment, the structure of the semiconductor device 102 is illustrated and described, but this structure has the characteristic of integrally constituting the first insulating layer 42 and the second insulating layer 52 without having an interface in the boundary surface 50, so the structure of the first insulating layer 42 and the second insulating layer 52 described here can also be applied to the structure described elsewhere in this embodiment, and can also be applied to other embodiments as long as there is no contradiction.

[0043] Figure 5 FIG. 1 is a cross-sectional view showing the structure of a semiconductor device 103 as a third modification of the semiconductor device of this embodiment. Figure 5 As shown, the second insulating layer 53 is thicker than the carrier conductor 32, that is, the upper surface 53A of the second insulating layer 53 is arranged on the upper side than the upper surface 32C of the carrier conductor 32. The second insulating layer 53 is provided for the purpose of electrical insulation between the first carrier conductor 32A and the second carrier conductor 32B. In the semiconductor device 103 constructed in this way, by setting the creepage distance between the first carrier conductor 32A and the second carrier conductor 32B to be longer, the electrical insulation can be further improved, which has the effect of obtaining a semiconductor device with further improved reliability. In addition, in Figure 5 In the figure, as a third variant of the semiconductor device 100 of this embodiment, the structure of the semiconductor device 103 is illustrated and described, but this structure has the characteristic that the second insulating layer 53 is thicker than the carrying conductor 32, so the structure in which the second insulating layer 53 is thicker than the carrying conductor 32 described here can also be applied to the structure described elsewhere in this embodiment, and can also be applied to other embodiments as long as there is no contradiction.

[0044] Implementation method 2.

[0045] use Figure 6 A semiconductor device according to a second embodiment of the present invention will be described. Figure 6 This is a cross-sectional view showing the structure of a semiconductor device 200 according to this embodiment. The semiconductor device 200 according to this embodiment includes a metal base substrate 14 having a metal base 21, a first insulating layer 43, a carrier conductor 31, and a second insulating layer 51; a semiconductor element 71; a housing 61; an external terminal 74; and a sealing member 77. While the housing 61 is disposed outside the second insulating layer 51, this is similar to the first embodiment. However, this difference from the semiconductor device 100 according to the first embodiment is that the housing 61 is disposed outside the first insulating layer 43.

[0046] The first insulating layer 43 has an area equal to the sum of the area of ​​the carrier conductor 31 and the area of ​​the second insulating layer 51. In the semiconductor device 200, the metal base 21 is not particularly limited and may be bonded to the housing 61 using an adhesive or the like.

[0047] In the metal base substrate 14, the metal base 21, the first insulating layer 43, the mounted conductor 31, and the second insulating layer 51 are integrally formed. The forming method is not particularly limited and may be the same as the forming process described in the first embodiment or the method described below.

[0048] An example of the forming process is described below. A thick copper plate, for example, a flat plate material used as the carrier conductor 31, is patterned by etching or punching to form the carrier conductor 31. Etching can be performed on either one or both sides. The carrier conductor 31 is molded integrally with the material forming the second insulating layer 51. The integrated carrier conductor 31, second insulating layer 51, metal base 21, and material forming the first insulating layer 43 are integrally formed by stamping or molding to form the metal base substrate 14.

[0049] Even the semiconductor device 200 shown in the second embodiment, constructed in this manner, can suppress moisture intrusion from the side surfaces of the second insulating layer 51, thereby preventing degradation of the semiconductor element and achieving a semiconductor device with improved reliability. Furthermore, by providing a housing outside the first insulating layer 43, moisture intrusion from the side surfaces of the first insulating layer 43 is also suppressed, preventing degradation of the semiconductor element and achieving a semiconductor device with further improved reliability.

[0050] Figure 7 2 is a cross-sectional view showing the structure of a semiconductor device 201 as a modified example of the semiconductor device of this embodiment. Figure 7 As shown, the first insulating layer 44 may be configured to have an area larger than the sum of the area of ​​the carrier conductor 31 and the area of ​​the second insulating layer 51. In the semiconductor device 201, the metal base 21 and the first insulating layer 44 are not particularly limited, and at least one of them may be bonded to the housing 63 using an adhesive or the like.

[0051] Even with a semiconductor device 201 constructed in this manner, by providing a shell on the outside of the first insulating layer 44 and the second insulating layer 51, it is possible to suppress the intrusion of moisture from the side surfaces of the first insulating layer 44 and the second insulating layer 51, thereby preventing the degradation of the semiconductor elements and achieving a semiconductor device with further improved reliability.

[0052] Furthermore, in the semiconductor device 201, regarding the areas of the metal base 21, the first insulating layer 44, the carrier conductor 31, and the second insulating layer 51, the metal base 21 has the largest area, the first insulating layer 44 has a smaller area than the metal base 21, and the sum of the area of ​​the carrier conductor 31 and the area of ​​the second insulating layer 51 is smaller than the area of ​​the metal base 21 and the area of ​​the first insulating layer 44. Therefore, as Figure 7 As shown, the metal base substrate 15 has a gradually expanding stepped structure. In the semiconductor device 201 thus constructed, when heat is generated by the semiconductor element 71 during operation, the heat is dissipated in the vertical direction via the solder 81, the mounting conductor 31, the first insulating layer 44, and the metal base 21, and heat dissipation is also promoted in the area direction. Therefore, the semiconductor device 201 has a further improved heat dissipation due to the gradually expanding stepped structure of the metal base substrate 15, resulting in a semiconductor device with further improved reliability.

[0053] In addition, according to Figure 7 In the structure shown, the housing 63 can be configured to, for example, provide a convex portion 63A so that a portion of the housing 63 covers the outer peripheral area of ​​the first insulating layer 44, so that the semiconductor device 201 can prevent the position of the housing 63 from being offset relative to the metal base substrate 15. Therefore, the intrusion of moisture from the gap at the interface is further suppressed, and the semiconductor device with improved reliability can be obtained. In addition, Figure 7 In the figure, the structure of the semiconductor device 201 is illustrated as a variation of the semiconductor device 200 involved in this embodiment, but the structure has the characteristic that the metal base substrate 15 has a gradually unfolding step structure, so the structure of the metal base substrate 15 with a gradually unfolding step structure can also be applied to other embodiments as long as there is no contradiction.

[0054] Implementation method 3.

[0055] use Figure 8 A semiconductor device according to a third embodiment of the present invention will be described. Figure 8 : is a cross-sectional view showing the structure of the semiconductor device 300 of the present embodiment. The semiconductor device 300 of the present embodiment includes a metal base substrate 11 having a metal base 21, a first insulating layer 41, a carrier conductor 31 and a second insulating layer 51, a semiconductor element 71, a housing 61, an external terminal 74, and a sealing member 77. The housing 61 is provided on the outside of the first insulating layer 41, which is the same as in the first embodiment. However, the barrier layer 91 is provided on the side opposite to the metal base substrate 11 relative to the semiconductor element 71 and is provided on the inner side of the housing 61 on the sealing member 77, which is different from the semiconductor device 100 of the first embodiment. Here, Figure 8 The semiconductor device 300 is a semiconductor device in which the barrier layer 91 is provided in the semiconductor device 100 described in the first embodiment. However, the semiconductor device 300 may be a semiconductor device in which the barrier layer 91 is provided in a modification of the semiconductor device 100 described in the first embodiment, or may be a semiconductor device in which the barrier layer 91 is provided in the semiconductor device 200 described in the second embodiment or a modification thereof. Figure 8, the barrier layer 91 is provided in a region inside the housing 61 . However, the present invention is not limited thereto, and at least a portion of the barrier layer 91 may be provided in a region outside the housing 61 .

[0056] Barrier layer 91 is formed from a material with low water permeability. Barrier layer 91 is preferably formed from a thermoplastic resin such as polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), or polyetheretherketone (PEEK). Alternatively, by ensuring the thickness of barrier layer 91, a thermosetting resin with relatively high water permeability, a fluorine-based resin such as polytetrafluoroethylene (PTFE), a ceramic material, a glass material, or a mixture thereof can also be used. Barrier layer 91 and housing 61 are not particularly limited and can be bonded together using, for example, an adhesive, or barrier layer 91 and sealing member 77 can be bonded together.

[0057] Even in the semiconductor device 300 shown in the third embodiment, which is constructed in this manner, moisture intrusion from the side surfaces of the second insulating layer 51 is suppressed, thereby preventing degradation of the semiconductor element and achieving a semiconductor device with improved reliability. Furthermore, by providing the barrier layer 91 in the region of the sealing member 77 that is located inward of the housing 61, moisture intrusion from the upper portion of the sealing member 77 is suppressed, preventing degradation of the semiconductor element and achieving a semiconductor device with further improved reliability.

[0058] Implementation method 4.

[0059] use Figure 9 A power conversion device according to a fourth embodiment of the present invention, in which the semiconductor device according to any one of the first to third embodiments is mounted, will be described. Figure 9 is a block diagram for explaining the power conversion device of this embodiment. Figure 9 The entirety of FIG. 1 shows a power conversion system to which the power conversion device of this embodiment is applied. Hereinafter, a case where the fourth embodiment is a three-phase inverter will be specifically described.

[0060] Figure 9 The illustrated power conversion system includes a power supply 410, a power conversion device 400 according to this embodiment, and a load 420. Power supply 410 is a DC power supply that supplies DC power to power conversion device 400. Power supply 410 can include various examples, such as a DC system, a solar cell, a battery, a rectifier circuit connected to an AC system, or an AC / DC converter. Power supply 410 may also include a DC / DC converter that converts DC power output from the DC system into a predetermined power level.

[0061] The power conversion device 400 is a three-phase inverter connected between the power source 410 and the load 420, which converts the DC power supplied from the power source 410 into AC power and supplies the AC power to the load 420. Figure 9 The main converter circuit 401 is provided with a main converter circuit 401 for converting input DC power into AC power and outputting the AC power; and a control circuit 403 for outputting a control signal for controlling the main converter circuit 401 to the main converter circuit 401 .

[0062] Load 420 is a three-phase electric motor driven by the AC power supplied from power conversion device 400. Load 420 is not limited to a specific application and may be a motor mounted on various electrical devices, such as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0063] The power conversion device 400 of this embodiment is described in detail below. The main conversion circuit 401 includes switching elements and freewheeling diodes (not shown). The switching elements are used to convert DC power supplied from the power supply 410 into AC power, which is then supplied to the load 420. While there are various examples of the specific circuit structure of the main conversion circuit 401, the main conversion circuit 401 of this embodiment is a two-level three-phase full-bridge circuit, which can include six switching elements and six freewheeling diodes connected in anti-parallel with each switching element. The semiconductor device 402 described in any one of the above-described embodiments 1 to 3 is applied to at least one of the switching elements and freewheeling diodes of the main conversion circuit 401. The six switching elements are connected in series, with each pair forming an upper and lower branch. Each upper and lower branch constitutes a phase (U phase, V phase, and W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower branch, i.e., the three output terminals of the main conversion circuit 401, are connected to the load 420.

[0064] In addition, the main conversion circuit 401 includes a drive circuit (not shown) for driving each switching element, and the drive circuit may be built into the semiconductor device 402 or may be a structure that includes the drive circuit independently of the semiconductor device 402. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 401 and provides it to the control electrode of the switching element of the main conversion circuit 401. Specifically, according to the control signal from the control circuit 403 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) greater than the threshold voltage of the switching element. When the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) less than the threshold voltage of the switching element.

[0065] The control circuit 403 controls the switching elements of the main conversion circuit 401 so that the desired power is supplied to the load 420. Specifically, the control circuit 403 calculates the time (on-time) for each switching element of the main conversion circuit 401 to be in the on state based on the power to be supplied to the load 420. For example, the main conversion circuit 401 can be controlled using PWM control, which modulates the on-time of the switching elements according to the voltage to be output. Furthermore, a control instruction (control signal) is output to the drive circuit of the main conversion circuit 401 so that, at each point in time, an on signal is output to the switching element to be in the on state and an off signal is output to the switching element to be in the off state. In accordance with the control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0066] In the power conversion device of this embodiment, the semiconductor device according to any one of Embodiments 1 to 3 is applied to at least one of the switching element and the freewheeling diode of the main conversion circuit 401 , thereby achieving an effect of improving reliability.

[0067] Furthermore, this embodiment describes an example of application to a two-level, three-phase inverter, but the present invention is not limited thereto and can be applied to various power conversion devices. While this embodiment uses a two-level power conversion device, a three-level or multi-level power conversion device is also possible, and it can also be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, when supplying power to a DC load, etc., this embodiment can also be applied to a DC / DC converter or an AC / DC converter.

[0068] In addition, the power conversion device of this embodiment is not limited to the case where the above-mentioned load is an electric motor. For example, it can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

Claims

1. A semiconductor device comprising: A metal base substrate comprising a metal base, a first insulating layer provided on a surface of the metal base for electrical insulation and heat dissipation, a carrier conductor provided on a surface of the first insulating layer opposite to the surface on which the metal base is provided, and a second insulating layer for electrical insulation provided so that a surface of the carrier conductor opposite to the surface in contact with the first insulating layer is exposed and in contact with a surface of the first insulating layer opposite to the surface on which the metal base is provided and a side surface of the carrier conductor. a semiconductor element joined to the carrier conductor; a housing, wherein the housing is disposed on an upper side of the first insulating layer in a cross-sectional view, the first insulating layer being exposed to the outside air, and the housing is disposed outside the second insulating layer in a plan view, the housing being in contact with a side surface of the second insulating layer; external terminals mounted on the housing; as well as a sealing member filling the area surrounded by the carrier conductor, the second insulating layer, and the outer shell, The first insulating layer and the second insulating layer are integrally formed of the same material.

2. The semiconductor device according to claim 1, wherein The carrier conductor is thicker than the first insulating layer.

3. The semiconductor device according to claim 1 or 2, wherein: The mounting conductor has an area larger than that of the semiconductor element.

4. The semiconductor device according to claim 1 or 2, wherein: The metal base has an area larger than the sum of the area of ​​the mounting conductor and the area of ​​the second insulating layer.

5. The semiconductor device according to claim 1 or 2, wherein: The carrier conductor is thicker than the metal base.

6. The semiconductor device according to claim 1 or 2, wherein: The second insulating layer has the same thickness as that of the mounting conductor.

7. The semiconductor device according to claim 1 or 2, wherein: The second insulating layer is thicker than the mounting conductor.

8. The semiconductor device according to claim 1 or 2, wherein: A barrier layer is provided. The barrier layer is arranged on the side opposite to the metal base substrate with respect to the semiconductor element and is provided on the sealing member.

9. A power conversion device comprising: A main conversion circuit comprising the semiconductor device according to any one of claims 1 to 8, the main conversion circuit converting input power and outputting the converted power; and The control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

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