Bilateral embedded trace substrate

Abstract

Some features relate to a substrate, which includes: a first portion of the substrate including a first plurality of metal layers; a second portion of the substrate including a second plurality of metal layers; and a plurality of insulating layers configured to separate the first plurality of metal layers and the second plurality of metal layers. A first plurality of pillars and a plurality of interconnects are coupled together such that the first plurality of pillars and the plurality of interconnects couple the first portion of the substrate to the second portion of the substrate.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to provisional application No. 62 / 859,233 entitled “DOUBLE SIDED EMBEDDED TRACESUBSTRATE” filed on June 10, 2019, and non-provisional application No. 16 / 946,104 entitled “DOUBLE SIDE DEMBEDDED TRACE” filed on June 5, 2020, which has been assigned to their assignees and is hereby expressly incorporated by reference. Technical Field

[0003] Various features involve dual-sided embedded trace substrates. Background Technology

[0004] Integrated circuits, integrated circuit packages, and electronic devices are being driven to smaller form factors. Correspondingly, the connections between such devices are being driven to have smaller widths and finer pitches to increase input / output while still maintaining a smaller form factor.

[0005] Surface mount devices, such as surface mount dies, are electrically coupled to electrical wiring boards. Surface mount devices are being driven to have smaller widths and finer pitches, as well as electrical wiring boards.

[0006] One way to achieve devices with smaller widths and finer pitches is by embedding traces in a substrate, such as a packaging substrate. Summary of the Invention

[0007] Various features involve dual-sided embedded trace substrates.

[0008] A first example provides a substrate comprising: a first portion of the substrate including a first plurality of metal layers; and a second portion of the substrate including a second plurality of metal layers. The substrate includes a plurality of insulating layers configured to separate the first and second plurality of metal layers. The substrate also includes a first plurality of pillars and a plurality of interconnects coupled together, such that the first plurality of pillars and the plurality of interconnects couple the first plurality of pillars to the second portion of the substrate. The plurality of interconnects may be solder interconnects or may be the second plurality of pillars.

[0009] The first multiple pillars are not limited to columnar shapes.

[0010] A second example provides a method of manufacturing a substrate, the method comprising: forming a first portion of the substrate, including forming a first plurality of metal layers; forming a second portion of the substrate, including forming a second plurality of metal layers; and forming a plurality of insulating layers configured to separate the first plurality of metal layers and the second plurality of metal layers. The method of manufacturing the substrate further comprises forming a first plurality of pillars and a plurality of interconnects, and coupling the first plurality of pillars to the plurality of interconnects such that the first portion of the substrate and the second portion of the substrate are coupled together. Attached Figure Description

[0011] Various features, properties and advantages will become apparent when viewed in conjunction with the accompanying drawings, in which the same reference numerals are correspondingly identified throughout the text.

[0012] Figure 1 The illustration shows several surface-mount packaged integrated circuits.

[0013] Figure 2 The illustration shows a cross-section of an exemplary dual-sided embedded trace substrate.

[0014] Figure 3 The illustration shows a cross-section of an exemplary dual-sided embedded trace substrate.

[0015] Figure 4 A simplified view of multiple integrated circuits mounted on the surface of an exemplary dual-sided embedded trace substrate is illustrated.

[0016] Figures 5A-5F The diagram illustrates the pair Figure 2 and Figure 3 The sequence of common manufacturing process steps for the dual-sided embedded trace substrate.

[0017] Figures 6A-6D The illustration depicts a substrate used for fabricating dual-sided embedded traces (such as...). Figure 2 The remaining sequence of manufacturing process steps for the double-sided embedded trace substrate.

[0018] Figures 7A-7D The illustration depicts a substrate used for fabricating dual-sided embedded traces (such as...). Figure 3 The remaining sequence of manufacturing process steps for the double-sided embedded trace substrate.

[0019] Figure 8 An exemplary flowchart of a method 800 for providing or manufacturing a double-sided embedded trace substrate is illustrated.

[0020] Figure 9 The illustrations depict various electronic devices, which may include the various substrates, integrated devices, integrated device packages, semiconductor devices, dies, integrated circuits and / or packages described herein. Detailed Implementation

[0021] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid confusing various aspects of this disclosure.

[0022] Overview

[0023] Some features relate to a dual-sided embedded trace substrate. The dual-sided embedded trace substrate includes a first portion having a first plurality of metal layers and a second portion having a second plurality of metal layers. A plurality of insulating layers separate and insulate each of the first and second plurality of metal layers. A first plurality of pillars and a plurality of interconnects are coupled together such that the first plurality of pillars and the plurality of interconnects couple the first plurality of pillars to the second portion of the substrate.

[0024] Dual-sided embedded trace substrates allow surface-mount circuit components to be directly and electrically coupled to the embedded trace substrate without the need for separate packaging. Therefore, dual-sided embedded trace substrates save on the cost of separate packaging. For example, dual-sided embedded trace substrates eliminate the cost of the packaging substrate used to package surface-mount circuits. Furthermore, dual-sided embedded trace substrates have a reduced overall height. The overall height is reduced by omitting the packaging substrate.

[0025] The dual-sided embedded trace substrate includes a first portion and a second portion. The first portion includes embedded traces in a top metal layer and the second portion includes embedded traces in a bottom metal layer.

[0026] The first part includes multiple metal layers, multiple pads, multiple embedded traces (in the top metal layer), and multiple vias for electrically coupling the multiple metal layers. The second part also includes multiple metal layers, multiple pads, multiple embedded traces (in the top metal layer), and multiple vias for electrically coupling the multiple metal layers.

[0027] The first and second portions of the substrate are coupled together (e.g., conductively coupled) via a plurality of pillars and a plurality of interconnects.

[0028] In the first example, the multiple interconnects are multiple solder interconnects. The multiple solder interconnects are at least partially surrounded by photoresist. The multiple solder interconnects are reflowed, such that the first plurality of pillars and the multiple interconnects (e.g., the multiple solder interconnects) are electrically and physically coupled. The gap between the first and second portions of the substrate is filled with molding compound.

[0029] In the second example, the interconnects are a second set of pillars. The first and second sets of pillars are electrically and physically coupled together by a conductive film. The gap between the first and second portions of the substrate is filled with molding compound.

[0030] Terms and Definitions

[0031] In some implementations, an interconnect is a component or assembly that allows or facilitates an electrical connection between two points, i.e., between a component and / or an assembly. In some implementations, an interconnect may include traces, vias, pads, pillars, redistributed metal layers, under-bump metallization (UBM) layers, and solder (e.g., solder balls). In some implementations, an interconnect is a conductive material that can be configured to provide an electrical path for signals (e.g., data signals, ground signals, power signals). An interconnect may be a device, electronic component, substrate, interposer, printed circuit board (PCB), die, die interconnect, or part of a circuit. In some implementations, an interconnect may include more than one component or assembly.

[0032] A trace is a form of interconnect that provides an electrical path in a horizontal or near-horizontal direction within a device. In some implementations, traces can be formed in or on a substrate. In some implementations, traces formed in the substrate are embedded traces. An embedded trace includes a case where at least two sides of the trace are covered by an insulating material of the substrate (such as a dielectric or prepreg laminate), and the top side of the trace is not covered by the insulating material of the substrate. However, a trace does not have to be an embedded trace; for example, a trace can be formed on or on the substrate. Traces can pass through insulating material.

[0033] A via is a form of interconnect that provides an electrical path in a vertical or near-vertical direction within an integrated device. In some implementations, vias can be formed in a substrate (e.g., substrate vias). In some implementations, vias can be formed in an encapsulation layer (e.g., molding compound). In some implementations, vias can have vertical walls, or they can have tapered or sloping walls, or other orientations.

[0034] A pad is a form of interconnect that provides an electrical path in an integrated device. In some implementations, a pad is a component or assembly that provides a coupling interface for interconnects made of different materials. For example, a pad can be configured to provide an interface for solder (e.g., solder balls).

[0035] The term “embedded” as used throughout this disclosure includes a situation where at least two sides of an object A are covered by an object B or material B.

[0036] The term "spacing" can be defined as the distance between the midpoints of two objects. For example, spacing can be the distance from the midpoint of interconnect A to the midpoint of interconnect B.

[0037] The term "width" can be defined as the lateral or horizontal measurement of an object when viewed in a cross-sectional view. For example, the width of an interconnect (e.g., 204) is the lateral or horizontal measurement of the interconnect from its first sidewall (or first side) to its second sidewall (or second side).

[0038] The term "thickness" can be defined as a vertical measurement of an object. In other words, thickness can be defined as the measurement from the bottom to the top of an object.

[0039] Unless otherwise stated, the term "coupled" means conductive coupling. Furthermore, an object, component, or device A can be coupled to device C even if one or more intermediate components exist between them.

[0040] Multiple surface mount packaged integrated circuits

[0041] Figure 1 The illustration shows multiple surface-mount packaged integrated circuits (ICs) 100. Specifically, Figure 1 The illustration shows multiple surface-mount packaged ICs 112a-d, including a first packaged IC 112a, a second packaged IC 112b, a third packaged IC 112c, and a fourth packaged IC 112d. The first packaged IC 112a includes an IC (e.g., a die) 102, an IC interconnect 104, a package substrate 106, a molding compound 110, and a package interconnect 114. Figure 1 The printed circuit board (PCB) 116 is further illustrated. Multiple surface-mount packaged ICs 112a-d are surface-mounted (i.e., mounted to the surface) onto the PCB 116.

[0042] IC 102 includes various interconnects (not shown) with smaller width and finer pitch compared to other technologies. Package substrate 106 includes a first side facing IC 102 and a second side facing PCB 116. Multiple embedded traces (not shown) are located within package substrate 106 and on the first side of package substrate 106. With the aid of multiple embedded traces (not shown), package substrate 106 is configured to accommodate the smaller width and finer pitch of IC 102. IC 102 is coupled to IC interconnects 104, and IC interconnects 104 are coupled to package substrate 106.

[0043] The second side of the package substrate 106 is coupled to the PCB 116 via the package interconnect 114. The PCB 116 is not suitable for the smaller width and finer pitch of the IC 102; therefore, the IC 102 is packaged in the package substrate 106 using embedded traces (not shown).

[0044] Due to the size of the packaging substrate 106 and PCB 116, multiple surface-mount packaged integrated circuits (ICs) 200 occupy a significant amount of space. Furthermore, the multiple surface-mount packaged integrated circuits (ICs) 100 increase the cost of both the packaging substrate 106 and PCB 116.

[0045] Exemplary dual-sided embedded trace substrate

[0046] Figure 2 The illustration shows a cross-section of an exemplary dual-sided embedded trace substrate 200 (substrate 200). Specifically, Figure 2 The diagram illustrates a first portion 210 and a second portion 250 of substrate 200. The first portion 210 and the second portion 250 of substrate 200 are coupled together. The first portion 210 of substrate 200 is an embedded trace substrate, and the second portion 250 of substrate 200 is also an embedded trace substrate. Together, the first portion 210 and the second portion 250 of substrate 200 constitute a single substrate 200, which is a dual-sided embedded trace substrate.

[0047] The substrate 200 may be a packaging substrate, an interposer, or an embedded trace substrate. The substrate 200 may include a core (not shown) or may be coreless.

[0048] The first portion 210 of the substrate 200 includes a first plurality of metal layers 214, which include a first metal layer 214a, a second metal layer 214b, a third metal layer 214c, and a fourth metal layer 214d. The first metal layer 214a is the top layer, and the fourth metal layer 214d is the bottom layer of the first portion 210 of the substrate 200. The second metal layer 214b and the third metal layer 214c are inner layers of the substrate 200. Because the fourth metal layer 214d of the first plurality of metal layers 214 is coupled to the fourth metal layer 254d of the second plurality of metal layers (as discussed later), the fourth metal layer 214d and the fourth metal layer 254d are also inner metal layers of the substrate 200.

[0049] Although Figure 2 The first portion 210 of the substrate 200 is illustrated as having four metal layers (i.e., a first plurality of metal layers 214a-d), but this disclosure is not limited thereto. The first portion 210 of the substrate 200 may have fewer than four metal layers or more than four metal layers.

[0050] The first portion 210 of the substrate 200 includes a plurality of insulating layers 216 configured to separate and insulate each of the first plurality of metal layers 214. The plurality of insulating layers 216 may include one or more materials. The plurality of insulating layers may be dielectric layers or prepreg laminates.

[0051] The first portion 210 of the substrate 200, particularly the first plurality of metal layers 214, includes a first plurality of pads 220, a first plurality of traces 222, and a first plurality of vias 224. A first metal layer 214a of the first plurality of metal layers 214 includes the first plurality of traces 222 embedded in the first portion 210 of the substrate 200. The first plurality of traces 222 embedded in the first portion 210 of the substrate 200 are located on top of the substrate 200 (i.e., in the first metal layer 214a) and are configured such that surface mount circuit assemblies (e.g., dies, ICs, passive devices) can be coupled to the first portion 210 of the substrate 200. The first plurality of traces 222 embedded in the substrate 200 allow for smaller widths and finer spacing compared to unembedded traces.

[0052] The first plurality of pads 220 are configured to receive, for example, IC interconnects 104. Figure 1 Interconnects, such as IC interconnects 104, are coupled to surface mount circuit assemblies (e.g., dies, ICs, or passive devices). Photoresist 218 is placed over at least some of the first plurality of traces 222 such that when the interconnects (e.g., Figure 1 When the IC interconnect 104 is formed, the interconnect is not electrically short-circuited with any of the first plurality of traces 222.

[0053] The first plurality of pads 220 are coupled to the first plurality of vias 224 perpendicularly through the substrate 200. The first plurality of vias 224 allow surface mount circuit assemblies (not shown) to be electrically (or conductively) coupled to any metal layer of the first plurality of metal layers 214 or to a second portion of the substrate 200 (i.e., any metal layer of the second plurality of metal layers 254).

[0054] Figure 2 The illustration further illustrates a second portion 250 of the substrate 200, comprising a second plurality of metal layers 254, which includes a first metal layer 254a, a second metal layer 254b, a third metal layer 254c, and a fourth metal layer 254d. The first metal layer 254a is the bottom layer, and the fourth metal layer 254d is the top layer of the second portion 250 of the substrate 200. The second metal layer 254b and the third metal layer 254c are internal metal layers. Because the fourth metal layer 254d of the second plurality of metal layers is coupled to the fourth metal layer 214d of the first plurality of metal layers 214, the fourth metal layer 214d and the fourth metal layer 254d are also internal metal layers of the substrate 200.

[0055] Although Figure 2 The second portion 250 of the substrate 200 is illustrated as having four metal layers (i.e., multiple metal layers 254a-d), but this disclosure is not limited thereto. The second portion 250 of the substrate 200 may have fewer than four metal layers or more than four metal layers.

[0056] The second portion 250 of the substrate 200 includes a plurality of insulating layers 256 configured to separate and insulate the second plurality of metal layers 254. The plurality of insulating layers 256 may include one or more materials. The plurality of insulating layers 256 may be dielectric layers or prepreg laminates.

[0057] The second portion 250 of the substrate 200, particularly the second plurality of metal layers 254, includes a second plurality of pads 260, a second plurality of traces 262, and a second plurality of vias 264. A first metal layer 254a of the second plurality of metal layers 254 includes the second plurality of traces 262 embedded in the second portion 250 of the substrate 200. The second plurality of traces 262 embedded in the second portion 250 of the substrate 200 are located at the bottom of the substrate 200 (i.e., in the first metal layer 254a) and are configured such that another surface-mount circuit assembly (e.g., die, IC, passive device) can be coupled to the second portion 250 of the substrate 200.

[0058] The second plurality of pads 260 located on the first metal layer 3541 of the second plurality of metal layers 354 are configured to receive, for example, IC interconnects 104. Figure 1 Interconnects, such as IC interconnect 104, are coupled to another surface mount circuit assembly (e.g., die, IC, passive device). Photoresist 258 is placed on at least some of the second plurality of traces 262 such that when the interconnect (e.g., Figure 1 When the IC interconnect 104 is formed, the interconnect is not electrically short-circuited with any of the second plurality of traces 262.

[0059] The second plurality of pads 260 are coupled to the second plurality of vias 264 perpendicularly through the substrate 200. The second plurality of vias 264 allow another surface mount circuit assembly (not shown) to be electrically (or conductively) coupled to any metal layer of the second plurality of metal layers 254 or to the first portion 210 of the substrate 200 (i.e., any metal layer of the first plurality of metal layers 214).

[0060] The substrate 200 also includes a first plurality of pillars 230 located on a fourth metal layer 214d of the first plurality of metal layers 214, wherein the fourth metal layer 214d is an inner or inner metal layer of the substrate 200. Specifically, the first plurality of pillars 230 are located on a first plurality of pads 220 located on the fourth metal layer 214d. The width of the first plurality of pillars 230 (i.e., a lateral or horizontal measurement when viewed in a cross-sectional view) is in the range of 10-100 μm. The thickness of the first plurality of pillars 230 (i.e., a vertical measurement when viewed in a cross-sectional view) is in the range of 10-30 μm. The first plurality of pillars 230 may be made of any one or a combination of materials, but not limited to: copper, or copper with a surface treatment (such as nickel gold or an organic solderable corrosion inhibitor), or copper with solder. The first plurality of pillars 230 may be cylindrical, but is not limited to. The first plurality of pillars 230 may be rectangular, square, or elliptical.

[0061] The substrate 200 includes a plurality of interconnects 234 located on a fourth metal layer 254d of a second plurality of metal layers 254, wherein the fourth metal layer 254d is an inner or inner metal layer of the substrate 200. Specifically, the plurality of interconnects 234 are located on another pad of a first plurality of pads 220 located on the fourth metal layer 254d (of the second plurality of metal layers 254). Figure 2 As shown, the plurality of interconnects 234 include a plurality of solder interconnects. The plurality of interconnects 234 and the fourth metal layer 214d (e.g., pad 220) are at least partially surrounded by photoresist 268.

[0062] The first plurality of pillars 230 and the plurality of interconnects 234 are coupled together such that the first plurality of pillars 230 and the plurality of interconnects 234 couple a first portion 210 of substrate 200 to a second portion 250 of substrate 200. The first portion 210 of substrate 210 is coupled (i.e., electrically coupled) to the second portion 250 of substrate 200 as follows: the first plurality of pillars 230 are electrically coupled to a fourth metal layer 214d, and the first plurality of pillars 230 are coupled (i.e., electrically coupled) to the plurality of interconnects 234. The thickness from the first metal layer 214d to the photoresist 268 (i.e., the vertical measurement when viewed in a cross-sectional view) is in the range of 20-60 μm.

[0063] The substrate 200 includes a gap 298 between a first portion 210 and a second portion 250 of the substrate 200. The gap 298 includes a gap between each of the first plurality of pads 220 on the fourth metal layer 254d, a gap between the lowest insulating layer and the photoresist 268 of the plurality of insulating layers 216 of the first portion 210 of the substrate 200, a gap between each of the first plurality of pillars 230, or a combination thereof.

[0064] Molding material 232 is configured to fill the gap 298 between the first portion 210 and the second portion 250 of substrate 200. The molding material can be, but is not limited to, molding compounds, non-conductive pastes, or non-conductive films. Alternatively, a dielectric or insulating material can be used instead of molding material 232. Molding material 232 is also configured to fill the gap 298 located between a first plurality of pads 220 situated on a fourth metal layer 214d of a first plurality of metal layers 214.

[0065] Figure 3 The illustration shows a cross-section of an exemplary dual-sided embedded trace substrate 300 (substrate 300). Specifically, Figure 3 The illustration shows a first portion 310 and a second portion 350 of substrate 300. The first portion 310 and the second portion 350 of substrate 300 are coupled together (e.g., conductive coupling and physical coupling). The first portion 310 of substrate 300 is an embedded trace substrate, and the second portion 350 of substrate 300 is also an embedded trace substrate. Together, the first portion 310 and the second portion 350 of substrate 300 constitute a single substrate 300, which is a dual-sided embedded trace substrate.

[0066] The substrate 300 may be a packaging substrate, an interposer, or an embedded trace substrate. The substrate 300 may include a core (not shown) or may be coreless.

[0067] The first portion 310 of the substrate 300 includes a first plurality of metal layers 314, which include a first metal layer 314a, a second metal layer 314b, a third metal layer 314c, and a fourth metal layer 314d. The first metal layer 314a is the top layer, while the fourth metal layer 314d is the bottom layer of the first portion 310 of the substrate 300. The fourth metal layer 314d is also an inner layer of the substrate 200. The second metal layer 314b and the third metal layer 315b are inner layers of the first portion 310 of the substrate 200.

[0068] Although Figure 3 The first portion 310 of the substrate 300 is illustrated as having four metal layers (i.e., multiple metal layers 314a-d), but this disclosure is not limited thereto. The first portion 310 of the substrate 300 may have fewer than four metal layers or more than four metal layers.

[0069] The first portion 310 of the substrate 300 includes a plurality of insulating layers 316 configured to separate and insulate the first plurality of metal layers 314. The plurality of insulating layers 316 may comprise one or more materials. The plurality of insulating layers may be dielectric layers or prepreg laminates.

[0070] The first portion 310 of the substrate 300, particularly the first plurality of metal layers 314, includes a first plurality of pads 320, a first plurality of traces 322, and a first plurality of vias 324. The first metal layer 314a of the first plurality of metal layers 314 includes the first plurality of traces 322 embedded in the first portion 310 of the substrate 300. The first plurality of traces 322 embedded in the first portion 310 of the substrate 300 are on the top of the substrate 300 (e.g., on an outer portion of the substrate 300) (i.e., in the first metal layer 314a) and are configured such that surface mount circuit assemblies (e.g., dies, ICs, passive devices) can be coupled to the first portion 310 of the substrate 300.

[0071] The first plurality of pads 320 are configured to receive, for example, IC interconnects 104. Figure 1 Interconnects, such as IC interconnects 104, are coupled to surface mount circuit assemblies (e.g., dies, ICs, passive devices). Photoresist 318 is placed over at least some of the first plurality of traces 322 such that when the interconnects (e.g., Figure 1 When the IC interconnect 104 is formed, the interconnect is not electrically short-circuited with any of the first plurality of traces 322.

[0072] The first plurality of pads 320 are coupled to the first plurality of vias 324 perpendicularly through the substrate 300. The first plurality of vias 324 allow surface mount circuit assemblies (not shown) to be electrically (or conductively) coupled to any metal layer of the first plurality of metal layers 314 or to the second portion 350 of the substrate 300 (i.e., any metal layer of the second plurality of metal layers 354).

[0073] Figure 3 The illustration further illustrates that the second portion 350 of the substrate 300 includes a first plurality of metal layers 354, which include a first metal layer 354a, a second metal layer 354b, a third metal layer 354c, and a fourth metal layer 354d. The first metal layer 354a is the bottom layer, and the fourth metal layer 354d is the top layer of the second portion 350 of the substrate 300. The second metal layer 354b and the third metal layer 354c are internal metal layers of the second portion 350 of the substrate 300.

[0074] Although Figure 3 The second portion 350 of the substrate 300 is illustrated as having four metal layers (i.e., multiple metal layers 354a-d), but this disclosure is not limited thereto. The second portion 350 of the substrate 300 may have fewer than four metal layers or more than four metal layers.

[0075] The second portion 350 of the substrate 300 includes a plurality of insulating layers 356 configured to separate and insulate the second plurality of metal layers 354. The plurality of insulating layers 356 may comprise one or more materials. The plurality of insulating layers 356 may be dielectric layers or prepreg laminates.

[0076] The second portion 350 of the substrate 300, particularly the second plurality of metal layers 354, includes a second plurality of pads 360, a second plurality of traces 362, and a second plurality of vias 364. A first metal layer 354a of the second plurality of metal layers 354 includes the second plurality of traces 362 embedded in the second portion 350 of the substrate 300. The second plurality of traces 362 embedded in the second portion 350 of the substrate 300 are located on the bottom of the substrate 300 (i.e., in the first metal layer 354a) and are configured such that another surface-mount circuit assembly (e.g., die, IC, passive device) can be coupled to the second portion 350 of the substrate 300.

[0077] The second plurality of pads 360 located on the first metal layer 354a of the second plurality of metal layers 354 are configured to receive, for example, IC interconnects 104. Figure 1 Interconnects, such as IC interconnects 104, are coupled to another surface-mount circuit assembly (e.g., die, IC, passive device). Photoresist 358 is placed on at least some of the second plurality of traces 362, such that when the interconnects (e.g., Figure 1 When the IC interconnect 104 is formed, the interconnect is not electrically short-circuited with any of the second plurality of traces 362.

[0078] The second plurality of pads 360 are coupled to the second plurality of vias 364 perpendicularly through the substrate 300. The second plurality of vias 364 allow another surface mount circuit assembly (not shown) to be electrically (or conductively) coupled to any metal layer of the second plurality of metal layers 354 or to the first portion 310 of the substrate 300 (i.e., any metal layer of the first plurality of metal layers 314).

[0079] The substrate 300 also includes a first plurality of pillars 330 located on a fourth metal layer 314d of the first plurality of metal layers 314, wherein the fourth metal layer 314d is an inner or inner metal layer of the substrate 300. Specifically, the first plurality of pillars 330 are located on a first plurality of pads 320, which are located on the fourth metal layer 314d. The width of the first plurality of pillars 330 (i.e., a lateral or horizontal measurement when viewed in a cross-sectional view) is in the range of 10-100 μm. The thickness of the first plurality of pillars 330 (i.e., a vertical measurement when viewed in a cross-sectional view) is in the range of 10-30 μm. The first plurality of pillars 330 may be made of any one or a combination of materials, but not limited to: copper, or copper with a surface treatment (such as nickel gold) or an organic solderable corrosion inhibitor, or copper with solder. The first plurality of pillars 330 may be cylindrical, but is not limited to. The first plurality of pillars 330 may be rectangular, square, or elliptical.

[0080] The substrate 300 includes a plurality of interconnects 334 located on a fourth metal layer 354d of a second plurality of metal layers 354. The fourth metal layer 354d is an internal or inner metal layer of the substrate 300. Specifically, the plurality of interconnects 334 are located on a second plurality of pads 320 located on the fourth metal layer 354d (of the second plurality of metal layers 354). The plurality of interconnects 334 includes a second plurality of pillars 334. The width of the second plurality of pillars 334 (i.e., the lateral or horizontal dimension when viewed in a cross-sectional view) is in the range of 10-100 μm. The thickness of the second plurality of pillars 334 (i.e., the vertical measurement when viewed in a cross-sectional view) is in the range of 10-30 μm. The second plurality of pillars 334 may be cylindrical, but is not limited thereto. The second plurality of pillars 334 may be rectangular, square, or elliptical.

[0081] First plurality of pillars 330 and plurality of interconnects 334 (e.g., second plurality of pillars) are coupled together such that the first plurality of pillars 330 and plurality of interconnects 334 (e.g., second plurality of pillars) electrically and physically couple a first portion 310 of substrate 300 to a second portion 350 of substrate 300. The first portion of substrate 310 is coupled (i.e., electrically coupled) to the second portion 350 of substrate 300 such that the first plurality of pillars 330 are electrically coupled to the plurality of interconnects 334 (e.g., second plurality of pillars). Alternatively, a conductive film 368 comprising an anisotropic conductive film or a solder cap may be used to couple the first plurality of pillars 330 to the plurality of interconnects 334 (e.g., multiple pillars). The conductive film 368 may be used as an adhesive such that the first plurality of pillars 330 are adhered to the plurality of interconnects 334.

[0082] The substrate 300 includes a gap 398 between a first portion 310 and a second portion 350 of the substrate 300. The gap 398 may include a gap between each of a first plurality of pads 220 on a fourth metal layer 314d, a gap between each of a second plurality of pads 360 on a fourth metal layer 354d, a gap between the lowest insulating layer of a plurality of insulating layers 316 of the first portion 210 of the substrate 200 and the lowest insulating layer of a plurality of insulating layers 356 of the second portion 350 of the substrate 200, a gap between each of a first plurality of pillars 230, a gap between each of a plurality of interconnects (e.g., a second plurality of pillars), or a combination thereof.

[0083] Molding material 332 is configured to fill the gap 398 between the first portion 310 and the second portion 350 of substrate 300. The molding material can be, but is not limited to, molding compounds, non-conductive pastes, or non-conductive films. Alternatively, dielectric or insulating materials can be used instead of molding material 332.

[0084] Integrated circuit mounted on the surface of an exemplary dual-sided embedded trace substrate

[0085] Figure 4 A simplified view is illustrated of multiple integrated circuits mounted on the surface of an exemplary dual-sided embedded trace substrate. Specifically, Figure 4 The illustration shows a packaged integrated circuit (IC) 402, which includes a plurality of ICs 404a-d surface-mounted to a dual-sided embedded trace substrate 400. The dual-sided embedded trace substrate 400 can be similar to... Figure 2 and Figure 3 The dual-sided embedded trace substrates 200 and 300 are shown respectively. The dual-sided embedded trace substrate 400 includes a first portion (unmarked), such as the top, and a second portion (unmarked), such as the bottom, of the substrate 400.

[0086] ICs 404a and 404b are surface-mounted to a first portion (e.g., the top) of a dual-sided embedded trace substrate 400. ICs 404c and 404d are surface-mounted to a second portion (e.g., the bottom) of the dual-sided embedded trace substrate 400. Each of ICs 404a-d has a plurality of fine-pitch interconnects 406 (not drawn to scale) configured to electrically couple each of ICs 404a, 404b and 404c, 404d to the dual-sided embedded trace substrate 400. The dual-sided embedded trace substrate 400 includes components similar to... Figure 2 and Figure 3 The first and second plurality of embedded traces shown (not shown) and similar Figure 2 and Figure 3The first and second plurality of pads shown are not shown.

[0087] The first and second plurality of traces and the first and second plurality of pads allow the dual-sided embedded trace substrate 400 to have fine lines and spatial interconnects. Because the exemplary dual-sided embedded trace substrate 400 has these fine lines and spatial interconnects, a plurality of ICs 404a-d having fine-pitch interconnects 406 can be directly coupled to the dual-sided embedded trace substrate 400. Furthermore, the plurality of ICs 404a-d do not require separate package substrates, such as... Figure 1 The packaging substrate 106 shown in the figure reduces costs.

[0088] This is similar to Figure 1 The multiple surface-mount packaged ICs 112a-d shown are in contrast. These surface-mount packaged ICs 112a-d have fine-pitch IC interconnects 104, therefore they cannot be directly coupled to a PCB 116 with wider-pitch interconnects (not shown). Instead, the multiple surface-mount packaged ICs 112a-d must be coupled to... Figure 1 The packaging substrate 106 shown is packaged separately.

[0089] Due to the size of both the package substrate 106 and the PCB 116, multiple surface-mount packaged integrated circuits (ICs) 200 occupy a significant amount of space. Furthermore, the multiple surface-mount packaged integrated circuits (ICs) 100 increase the cost of the package substrate 106 and the PCB 116, which is expensive. In contrast, the packaged integrated circuit (IC) 402 coupled to the exemplary dual-sided embedded trace substrate 400 has a lower cost. Moreover, the packaged integrated IC 402 is smaller, at least in the Z-direction (vertical direction), thus saving valuable space.

[0090] Exemplary sequence of steps for fabricating a double-sided embedded trace substrate

[0091] In some implementations, fabricating a double-sided embedded trace substrate involves several processes. Figures 5A-5F The diagram illustrates the pair Figure 2 (where multiple interconnects 234 include multiple solder interconnects) and Figure 3 A sequence of common manufacturing process steps for a dual-sided embedded trace substrate (where multiple interconnects 334 include a second plurality of pillars). Manufacturing Figure 2 and Figure 3 The remaining sequence of fabrication process steps for the dual-sided embedded trace substrate will be discussed later. Figures 6A-6D and Figures 7A-7D Let's discuss them separately.

[0092] The following will now be described in the context of fabricating a dual-sided embedded trace substrate comprising multiple interconnects 234. Figures 5A-5FMultiple interconnects 234 include Figure 2 Multiple solder interconnects. Note that... Figures 5A-5F The sequence can be simplified and / or clarified by combining one or more stages. In some implementations, the order of processes can be changed or modified.

[0093] Figure 5A The illustration shows a removable carrier foil. The removable carrier foil 503 can be supplied or manufactured by a vendor. The removable carrier foil has a first side (e.g., a top side) which forms the basis for a first portion (e.g., 210) of the substrate 500. Furthermore, the removable carrier foil 503 has a second side (e.g., a bottom side) which forms the basis for a second portion (e.g., 550) of the substrate 500. That is, any layer formed over the first side of the removable carrier foil is part of the first portion of the substrate, and any layer formed over the second side of the removable carrier foil is part of the second portion of the substrate.

[0094] Seed layer 502a is formed on a first surface (e.g., top surface) of removable carrier foil 503. Seed layer 502b is formed on a second surface (e.g., bottom surface) of removable carrier foil 503. Seed layers 502a and 502b are used to form other metal layers on seed layers 502a and 502b.

[0095] Figure 5B The illustration shows a first metal layer 514a patterned or formed on a first portion 510 of a substrate 500. The first metal layer 514a includes a first plurality of pads 520a and a first plurality of traces 522a formed on the first metal layer 514a of the first portion 510 of the substrate 500.

[0096] Another first metal layer 554a is patterned or formed on a second portion 554 of the substrate 500. The first metal layer 554a includes a second plurality of pads 560a and a second plurality of traces 562b formed on the first metal layer 554a of the second portion 550 of the substrate 500.

[0097] Figure 5CThe illustration shows an insulating layer 516a, one of a plurality of insulating layers 516 formed over a first metal layer 514a of a first portion 510 of a substrate 500. A plurality of first vias 524a are formed in the insulating layer 516a and configured to electrically couple the first metal layer 514a to a second metal layer 514b (the first portion 510 of the substrate 500). The second metal layer 514b is patterned or formed on the insulating layer 516a. The second metal layer 514b includes a plurality of first pads 520b and a plurality of first traces 522b. Some of the first pads 520b may be coupled to the first vias 524a. The plurality of insulating layers 516 may comprise one or more materials. The plurality of insulating layers 516 may be a dielectric layer or a prepreg laminate.

[0098] Figure 5C An insulating layer 556a is illustrated above a first metal layer 554a on a second portion 550 of substrate 500. A second plurality of vias 564a are formed in the insulating layer 556a and configured to electrically couple the first metal layer 554a to a second metal layer 554b (the second portion 550 of substrate 500). The second metal layer 554b is patterned or formed on the insulating layer 556a. The second metal layer 554b includes a second plurality of pads 560b and a second plurality of traces 562b. Some of the second plurality of pads 560b may be coupled to the second plurality of vias 564a. The second plurality of insulating layers 556a may comprise one or more materials. The second plurality of insulating layers 556a may be a dielectric layer or a prepreg laminate.

[0099] Figure 5D An insulating layer 516b is illustrated above a second metal layer 514b on a first portion 510 of substrate 500. A plurality of first vias 524b are formed in the insulating layer 516b and configured to electrically couple the second metal layer 514b to a third metal layer 514c (the first portion 510 of substrate 500). The third metal layer 514c is patterned or formed on the insulating layer 516b. The third metal layer 514c includes a plurality of first pads 520c and a plurality of first traces 522c. Some of the first plurality of pads 520c may be coupled to the first plurality of vias 524b.

[0100] Figure 5DAn insulating layer 556b is illustrated above a second metal layer 554b on a second portion 550 of substrate 500. A second plurality of vias 564b are formed in the insulating layer 556b and configured to electrically couple the second metal layer 554b to a third metal layer 554c (the second portion 550 of substrate 500). The third metal layer 554c is patterned or formed on the insulating layer 556b. The third metal layer 554c includes a second plurality of pads 560c and a second plurality of traces 562c. Some of the second plurality of pads 560c may be coupled to the second plurality of vias 564b.

[0101] Figure 5E The illustration shows an insulating layer 516c above a third metal layer 514c of a first portion 510 of substrate 500. A plurality of first vias 524c are formed in the insulating layer 516c and configured to electrically couple the third metal layer 514c to a fourth metal layer 514d (the first portion 510 of substrate 500). The fourth metal layer 514d is patterned or formed on the insulating layer 516c. The fourth metal layer 514d includes a plurality of first pads 520d and a plurality of first traces 522d. Some of the first plurality of pads 520d may be coupled to the first plurality of vias 524c.

[0102] Figure 5E The illustration shows an insulating layer 556c above a third metal layer 554c of a second portion 550 of substrate 500. A second plurality of vias 564c are formed in the insulating layer 556c and configured to electrically couple the third metal layer 554c to a fourth metal layer 554c (the second portion 550 of substrate 500). The fourth metal layer 554d is patterned or formed on the insulating layer 556c. The fourth metal layer 554d includes a second plurality of pads 560d and a second plurality of traces 562d. Some of the second plurality of pads 560d may be coupled to the second plurality of vias 564c.

[0103] Figure 5F The illustration shows the first portion 510 of substrate 500 separated from the second portion 550 of substrate 500, and the removable carrier foil 503 removed. The first portion 510 is rotated or flipped such that the first metal layer 514a of the first portion 510 of substrate 500 faces upward. The second portion 550 of substrate 500 remains as shown.

[0104] Figures 6A-6D The illustration depicts a substrate used for fabricating dual-sided embedded traces (such as...). Figure 2 The remaining sequence of manufacturing process steps for the dual-sided embedded trace substrate (where multiple interconnects 234 include multiple solder interconnects). Figures 6A-6D The remaining sequence of manufacturing process steps shown is from Figure 5F continue.

[0105] Figure 6A The illustration shows a first portion (e.g., the top) of a substrate 610. The first portion of the substrate 610 includes a first plurality of metal layers 614. The first plurality of metal layers 614 includes a first metal layer 614a, a second metal layer 614b, a third metal layer 614c, and a fourth metal layer 614d separated by a first plurality of insulating layers 616, the first plurality of insulating layers 616 being configured such that the first plurality of metal layers 614 are electrically insulated from each other.

[0106] Figure 6A The illustration shows a first plurality of pillars 630 coupled to a first plurality of pads 620. The first plurality of pads 620 are formed on a fourth metal layer 614d. Photoresist 618 is placed on at least some of the first plurality of traces 622 to prevent electrical short circuits when other interconnects (not shown, such as die interconnects) are coupled to the first plurality of traces 622.

[0107] Figure 6B The illustration shows a second portion (e.g., the bottom) of a substrate 650. The second portion of the substrate 650 includes a second plurality of metal layers 564. The second plurality of metal layers 564 includes a first metal layer 654a, a second metal layer 654b, a third metal layer 654c, and a fourth metal layer 654d, separated by a second plurality of insulating layers 656, which are configured such that the first plurality of metal layers 654 are electrically insulated from each other.

[0108] The second portion of the substrate 650 includes a photoresist 658 placed on at least some of the second plurality of traces 662 of the first metal layer 654a to prevent electrical short circuits when other interconnects (not shown, such as die interconnects) are coupled to the second plurality of traces 662.

[0109] Multiple interconnects 634 are located on multiple pads 620 on the fourth metal layer 654d. The multiple interconnects 634 include multiple solder interconnects. A photoresist 668 is also placed on and between the fourth metal layer 654d. Specifically, the photoresist 668 is placed on and between the multiple pads 620 on the fourth metal layer 654d. The photoresist 668 is also placed between each of the multiple interconnects 634 to prevent short circuits in the multiple interconnects 634.

[0110] Figure 6CThe illustration shows a dual-sided embedded trace substrate 600 (or, for simplicity, substrate 600), which includes a first portion 610 and a second portion 650. First plurality of pillars 630 are coupled to a plurality of interconnects 634 (e.g., a plurality of solder interconnects). Specifically, the first plurality of pillars 630 are coupled to a plurality of solder interconnects 634. The first portion 610 and the second portion 650 are electrically coupled together via the first plurality of pillars 630, which are coupled to the plurality of interconnects 634.

[0111] Figure 6D The illustration shows a dual-sided embedded trace substrate 600 after multiple interconnects 634, including multiple solder interconnects, have been reflowed (e.g., melted, such that the solder interconnects 634 operate to attach a first portion 610 to a second portion 650 of a substrate 600), such that the first portion 610 and the second portion 650 are electrically coupled together and physically attached. A molding compound 632 is configured to fill any gaps between any of the first plurality of insulating layers 616 and the photoresist 668, and to fill any gaps between any of the first plurality of pillars 630. The molding compound 632 can be, but is not limited to, molding compounds, non-conductive pastes, and non-conductive films. Alternatively, a dielectric or insulating material can be used instead of the molding compound 632. Figure 6D Similar to Figure 2 .

[0112] Although not shown, but Figure 4 Any one or more of the multiple ICs 404 shown in the diagram can be coupled to the dual-sided embedded trace substrate 600. That is, ICs such as 404a and 404b can be mounted to a first portion 610 (e.g., top) of the dual-sided embedded trace substrate 600 via a first plurality of pads 620. ICs such as 404c and 404d can be mounted to a second portion 650 (e.g., bottom) of the dual-sided embedded trace substrate 600 via a second plurality of pads 660.

[0113] Figures 7A-7D The illustration depicts a substrate used for fabricating dual-sided embedded traces (such as...). Figure 3 The remaining sequence of manufacturing process steps for the dual-sided embedded trace substrate (where multiple interconnects 334 include a second plurality of pillars). Figures 7A-7D The remaining sequence of manufacturing process steps shown is from Figure 5F continue.

[0114] Figure 7AThe illustration shows a first portion of substrate 710. The first portion of substrate 710 includes a first plurality of metal layers 714. The first plurality of metal layers 714 includes a first metal layer 714a, a second metal layer 714b, a third metal layer 714c, and a fourth metal layer 714d separated by a first plurality of insulating layers 716, the first plurality of insulating layers 716 being configured such that the first plurality of metal layers 714 are electrically insulated from each other. A first plurality of pillars 730 are coupled to a first plurality of pads 720 on the fourth metal layer 714d. The first plurality of pads 720 are formed on the fourth metal layer 714d. A photoresist 718 is placed over at least some of the first plurality of traces 722 to prevent electrical short circuits when other interconnects (not shown, such as die interconnects) are coupled to the first plurality of traces 722.

[0115] Figure 7B The second portion of substrate 750 is illustrated. The second portion of substrate 750 includes a second plurality of metal layers 754. The second plurality of metal layers 754 includes a first metal layer 754a, a second metal layer 754b, a third metal layer 754c, and a fourth metal layer 754d separated by a second plurality of insulating layers 756, the second plurality of insulating layers 756 being configured such that the first plurality of metal layers 754 are electrically insulated from each other.

[0116] A second portion of substrate 750 includes photoresist 758, which is placed over at least some of the second plurality of traces 762 of the first metal layer 754a to prevent electrical short circuits when other interconnects (not shown, such as die interconnects) are coupled to the second plurality of traces 762. A plurality of interconnects 734 are located on a plurality of pads 750 on the fourth metal layer 754d. The plurality of interconnects 734 include a second plurality of pillars.

[0117] Figure 7C The illustration shows a double-sided embedded trace substrate 700 (or, for simplicity, substrate 700) comprising a first portion 710 of substrate 700 and a second portion 750 of substrate 700. First plurality of pillars 730 are coupled to a plurality of interconnects 734 (e.g., second plurality of pillars) via a conductive film 768. The conductive film 768 is conductive and enables electrical connections between the first plurality of pillars 730 and the plurality of interconnects 734.

[0118] Figure 7D The illustration shows a double-sided embedded trace substrate 700 after the molding compound 732 is configured to fill any gap between one of the first plurality of insulating layers 716 of the first portion 710 and one of the second plurality of insulating layers 756 of the second portion 750, in order to fill any gap between any of the first plurality of pillars 730 and any of the second plurality of pillars 734 (e.g., multiple interconnects). Figure 7D Similar to Figure 3 .

[0119] Although not shown, but Figure 4 Any one or more of the plurality of ICs 404 shown may be coupled to the dual-sided embedded trace substrate 700. That is, ICs such as 404a and 404b may be mounted to a first portion 710 (e.g., top) of the dual-sided embedded trace substrate 700 via a first plurality of pads 720. ICs such as 404c and 404d may be mounted to a second portion 750 (e.g., bottom) of the dual-sided embedded trace substrate 700 via a second plurality of pads 760.

[0120] Exemplary flowchart of a method for fabricating a double-sided embedded trace substrate

[0121] In some implementations, fabricating a double-sided embedded trace substrate involves several processes. Figure 8 An exemplary flowchart of a method 800 for providing or manufacturing a double-sided embedded trace substrate is illustrated. In some implementations, Figure 8 Method 800 can be used to manufacture as described in this disclosure. Figure 2 , Figure 3 , Figure 4 The double-sided embedded trace substrates shown in Figures 5, 6 and 7.

[0122] It should be noted that Figure 8 The sequence can combine one or more processes to simplify and / or clarify the methods used to provide or manufacture dies. In some implementations, the order of processes can be changed or modified.

[0123] The method at 802 includes forming a first portion of a substrate, including forming a first plurality of metal layers.

[0124] The method at 804 includes forming a second portion of the substrate, including forming a second plurality of metal layers.

[0125] The method at 806 includes forming a plurality of insulating layers, the plurality of insulating layers being configured to separate a first plurality of metal layers from a second plurality of metal layers.

[0126] The method at 808 includes forming a first plurality of pillars and a plurality of interconnects, and coupling the first plurality of pillars to the plurality of interconnects such that a first portion of the substrate and a second portion of the substrate are coupled together.

[0127] Exemplary electronic devices

[0128] Figure 9The illustrations depict various electronic devices that can be integrated with any of the aforementioned dual-sided embedded trace substrates. For example, mobile phone device 902, laptop computer device 904, fixed-location terminal device 906, and wearable device 908 may include the integrated device 900 as described herein. The integrated device 900 may be, for example, any of the substrates, integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and multilayer packaged devices described herein. Figure 9 The devices 902, 904, 906, and 908 shown are merely exemplary. Other electronic devices may also feature integrated device 900, including but not limited to groups of devices (e.g., electronic devices), including mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices supporting Global Positioning System (GPS), navigation devices, set-top boxes, music players, video players, entertainment devices, fixed location data units such as meter reading devices, communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0129] Figure 2 One or more components, processes, features, and / or functions shown in Figure 7 (where Figure 7 includes 7A-7d) can be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figure 2 Figures 7 (including 7A-7d) and their corresponding descriptions in this disclosure are not limited to dual-sided embedded trace substrates. In some implementations, Figure 2 Figures 7 (including 7A-7d) and their corresponding descriptions can be used to manufacture, create, provide, and / or produce integrated devices. In some implementations, the device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a multi-package (PoP) device, and / or an interposer.

[0130] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. As used herein, the term “crossing” means traversing and includes traversing through or partially traversing an object.

[0131] Furthermore, it should be noted that the various disclosures contained herein can be described as processes depicted as flowcharts, diagrams, block diagrams, or sectional diagrams. While flowcharts may describe operations as sequential processes, many operations can be executed in parallel or concurrently. Additionally, the order of operations can be rearranged. A process terminates when its operations are completed.

[0132] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of various aspects of this disclosure is intended to be illustrative and not to limit the scope of the claims. Therefore, this teaching can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A substrate comprising: a first portion of the substrate comprising a first plurality of metal layers, the first plurality of metal layers comprising a first metal layer located on a first surface of the first portion of the substrate; a second portion of the substrate comprising a second plurality of metal layers, the second plurality of metal layers comprising a second metal layer located on a second surface of the second portion of the substrate; a plurality of insulating layers configured to separate the first plurality of metal layers from the second plurality of metal layers; a first plurality of pads located on the first metal layer and a second plurality of pads located on the second metal layer; and a first plurality of pillars located on the first plurality of pads and a plurality of solder interconnects located on the second plurality of pads, wherein the first plurality of pillars are coupled to the plurality of solder interconnects such that (i) the first portion of the substrate and the second portion of the substrate are coupled together and (ii) the first surface of the first portion of the substrate faces the second surface of the second portion of the substrate, wherein the first plurality of pillars are coupled to the plurality of solder interconnects such that a gap between the first portion of the substrate and the second portion of the substrate is formed; and a molding compound configured to fill the gap when the first plurality of pillars are coupled to the plurality of solder interconnects such that the molding compound fills the gap between the first plurality of pads and between the first plurality of pillars.

2. The substrate of claim 1, further comprising: a first metal layer of the first plurality of metal layers comprises a first plurality of traces embedded in the first portion of the substrate; and a second metal layer of the second plurality of metal layers comprises a second plurality of traces embedded in the second portion of the substrate.

3. The substrate of claim 2: wherein the first metal layer is a top layer of the substrate and the first plurality of traces are configured to be coupled to a surface mount circuit component; and wherein the second metal layer is a bottom layer of the substrate and the second plurality of traces are configured to be coupled to another surface mount circuit component.

4. The substrate of claim 2: wherein the first plurality of pillars are located on an internal metal layer of the substrate; and wherein the substrate further comprises a second plurality of pillars located on another internal metal layer of the substrate.

5. The substrate of claim 1, wherein the plurality of solder interconnects are encapsulated by the molding compound.

6. The substrate of claim 1, wherein the molding compound comprises a non-conductive paste and / or a non-conductive film.

7. The substrate of claim 1, wherein the plurality of solder interconnects are located internally to the substrate.

8. The substrate of claim 7, wherein the plurality of solder interconnects are located between the first portion of the substrate and the second portion of the substrate.

9. The substrate of claim 7, wherein the plurality of solder interconnects are at least partially surrounded by a solder resist, wherein the solder resist is located internally to the substrate.

10. The substrate of claim 9, ​ ​ wherein the first plurality of metal layers from the first portion of the substrate comprises three or more layers; and wherein the second plurality of metal layers from the second portion of the substrate comprises three or more layers.

11. The substrate of claim 9, further comprising a second plurality of pillars, wherein the first plurality of pillars is coupled to the second plurality of pillars through the plurality of solder interconnects.

12. The substrate of claim 1, wherein the substrate is incorporated into a device selected from a group consisting of: an entertainment unit, a navigation device, a mobile device, a fixed location terminal, a wearable device, a server, an Internet of Things (IoT) device.

13. The substrate of claim 1, wherein the substrate is incorporated into a device selected from a group consisting of: a smartphone.

14. The substrate of claim 1, wherein the substrate is incorporated into a device selected from a group consisting of: a computer, a personal digital assistant.

15. The substrate of claim 1, wherein the substrate is incorporated into a device selected from a group consisting of: a music player, a video player, a mobile phone, a tablet computer, a laptop computer, a device in an automobile.

16. A method of manufacturing a substrate, comprising: forming a first portion of the substrate, including forming a first plurality of metal layers, the first plurality of metal layers including a first metal layer located on a first surface of the first portion of the substrate; forming a second portion of the substrate, including forming a second plurality of metal layers, the second plurality of metal layers including a second metal layer located on a second surface of the second portion of the substrate; forming a plurality of insulating layers configured to separate the first plurality of metal layers from the second plurality of metal layers; and forming a first plurality of pads located on the first metal layer and a second plurality of pads located on the second metal layer; forming a first plurality of pillars located on the first plurality of pads and a plurality of solder interconnects located on the second plurality of pads; coupling the first plurality of pillars to the plurality of solder interconnects such that (i) the first portion of the substrate and the second portion of the substrate are coupled together and (ii) the first surface of the first portion of the substrate faces the second surface of the second portion of the substrate, wherein coupling the first plurality of pillars to the plurality of solder interconnects forms a gap between the first portion of the substrate and the second portion of the substrate; and after coupling the first plurality of pillars to the plurality of solder interconnects, filling the gap with a molding compound such that the molding compound fills gaps between the first plurality of pads and between the first plurality of pillars.

17. The method of claim 16, further comprising: forming a first plurality of traces embedded in the first portion of the substrate, the first plurality of traces formed in the first metal layer of the first plurality of metal layers; and forming a second plurality of traces embedded in the second portion of the substrate, the second plurality of traces formed in the second metal layer of the second plurality of metal layers.

18. The method of claim 17: wherein the first metal layer is a top layer of the substrate and the first plurality of traces are configured to be coupled to a surface mount circuit component; and wherein the second metal layer is a bottom layer of the substrate and the second plurality of traces are configured to be coupled to another surface mount circuit component.

19. The method of claim 16, wherein the molding compound includes a non-conductive paste and / or a non-conductive film.

20. The method of claim 16, wherein the plurality of solder interconnects are located inside the substrate.

21. The method of claim 20, further comprising: at least partially surrounding the plurality of solder interconnects with a solder resist.

22. The method of claim 20, wherein coupling the first plurality of pillars to the plurality of solder interconnects includes coupling the first plurality of pillars to a second plurality of pillars through the plurality of solder interconnects, wherein the first plurality of pillars are located above the second plurality of pillars.

23. The method of claim 20, wherein the first portion of the substrate and the second portion of the substrate are manufactured using an embedded trace substrate process.

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