Co-packaged optical device and transceiver

Abstract

A component. In some embodiments, the component includes: a photonic integrated circuit (PIC, 105); and an electronic integrated circuit (IC, 110). The front surface of the photonic integrated circuit abuts the front surface of the electronic integrated circuit in an overlapping region (135). A first portion (125) of the photonic integrated circuit protrudes beyond a first edge (130) of the electronic integrated circuit, and a first portion (115) of the electronic integrated circuit protrudes beyond a first edge (120) of the photonic integrated circuit. Conductors on the front surface of the electronic integrated circuit are connected to conductors on the front surface of the photonic integrated circuit in the overlapping region.

Description

Technical Field

[0001] One or more aspects according to embodiments of the present disclosure relate to optoelectronic systems, and more particularly to systems and methods for co-packaging optical devices and transceiver components. Background Art

[0002] Some systems for packaging photonic integrated circuits and electronic integrated circuits (such as, fan-out wafer-level packaging (FOWLP)) may include redistribution layers (RDLs) on one or both surfaces of the electronic integrated circuit and vias (through the electronic integrated circuit) for routing signals from the front surface of the electronic integrated circuit to the back surface. Such systems may have certain disadvantages. For example, the thickness of the RDL can increase the interconnect path length between the photonic integrated circuit and the electronic integrated circuit. This increased length increases the inductance of the connection and reduces the bandwidth of the circuits (e.g., the circuit of a photodetector on the photonic integrated circuit and the circuit of a transimpedance amplifier on the electronic integrated circuit). This limits the data rate that can be achieved when using RDLs. Also, if the back surface of the electronic integrated circuit is used for electrical interconnection, the presence of this interconnection may be an obstacle to directly placing a heat sink on the electronic integrated circuit, and heat may instead flow through the photonic integrated circuit to the heat sink, resulting in an increase in terms of thermal resistance and potentially a higher operating temperature for temperature-sensitive devices in the photonic integrated circuit.

[0003] Thus, there is a need for improved systems and methods for co-packaging optical devices and transceiver components. Summary of the Invention

[0004] According to an embodiment of the present invention, there is provided a component including: a photonic integrated circuit; and an electronic integrated circuit, the front surface of the photonic integrated circuit abuts against the front surface of the electronic integrated circuit in an overlapping region, a first portion of the photonic integrated circuit protrudes beyond a first edge of the electronic integrated circuit, and a first portion of the electronic integrated circuit protrudes beyond a first edge of the photonic integrated circuit, and conductors on the front surface of the electronic integrated circuit are connected to conductors on the front surface of the photonic integrated circuit in the overlapping region.

[0005] In some embodiments, the first edge of the electronic integrated circuit is opposite to the first portion of the electronic integrated circuit, and the first edge of the photonic integrated circuit is opposite to the first portion of the photonic integrated circuit.

[0006] In some embodiments, the conductors on the front surface of the electronic integrated circuit are connected to the conductors on the front surface of the photonic integrated circuit in the overlapping region by metal bumps, the metal bump is one of a plurality of metal bumps, the metal bumps are arranged on a grid of a rectangular array, and the metal bumps do not exist at the grid points at the corners of the rectangular array.

[0007] In some embodiments, in the overlapping region: there is no redistribution layer on the electronic integrated circuit, and there is no redistribution layer on the photonic integrated circuit.

[0008] In some embodiments, the assembly further includes a printed circuit board adjacent to a first portion of the electronic integrated circuit.

[0009] In some embodiments, the assembly further includes a compressible membrane connector between the first portion of the electronic integrated circuit and the printed circuit board, and conductors on the first portion of the electronic integrated circuit are connected to conductors on the printed circuit board through conductors in the compressible membrane connector.

[0010] In some embodiments, the assembly further includes a digital integrated circuit on the printed circuit board, and the digital integrated circuit is connected to the electronic integrated circuit through conductors on the printed circuit board and conductors in the compressible membrane connector.

[0011] In some embodiments, the assembly further includes: a heat sink on the digital integrated circuit; and a heat sink on the electronic integrated circuit.

[0012] In some embodiments, the assembly is configured to allow replacement of: the photonic integrated circuit and the electronic integrated circuit without removing the heat sink from the digital integrated circuit.

[0013] In some embodiments: the photonic integrated circuit includes a photodetector, and the electronic integrated circuit includes an amplifier connected to the photodetector through a conduction path having a length less than 500 micrometers.

[0014] In some embodiments, the length of the conduction path is less than 200 micrometers.

[0015] In some embodiments, the length of the conduction path is less than 100 micrometers.

[0016] In some embodiments: the photonic integrated circuit includes a photodetector, and the electronic integrated circuit includes an amplifier connected to the photodetector; and wherein the signal path from the optical input carrying amplitude-modulated light to the photodetector to the output from the amplifier of the electrical signal corresponding to the amplitude modulation has a 3 dB bandwidth of at least 10 GHz.

[0017] In some embodiments, the signal path has a 3 dB bandwidth of at least 60 GHz.

[0018] In some embodiments: the photonic integrated circuit includes a modulator, and the electronic integrated circuit includes an amplifier connected to the modulator through a conduction path having a length less than 500 micrometers.

[0019] In some embodiments, the length of the conduction path is less than 200 micrometers.

[0020] In some embodiments, the length of the conduction path is less than 100 microns.

[0021] In some embodiments: a photonic integrated circuit includes a modulator, and an electronic integrated circuit includes an amplifier connected to the modulator; and wherein a signal path from an input of an electrical signal to the amplifier to an output from the modulator that carries light having an amplitude modulation corresponding to the electrical signal has a 3 dB bandwidth of at least 10 GHz.

[0022] In some embodiments, the signal path has a 3 dB bandwidth of at least 40 GHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] These and other features and advantages of the present disclosure will be recognized and understood with reference to the specification, claims, and drawings, in which:

[0024] Figure 1A is a side view of a flip chip assembly according to an embodiment of the present disclosure;

[0025] Figure 1B is a bottom view of a flip chip assembly according to an embodiment of the present disclosure;

[0026] Figure 2A is a top view of a flip chip assembly according to an embodiment of the present disclosure;

[0027] Figure 2B is a pinout diagram according to an embodiment of the present disclosure;

[0028] Figure 3 is a side view of a component according to an embodiment of the present disclosure;

[0029] Figure 4 is an assembly flow chart according to an embodiment of the present disclosure;

[0030] Figure 5 is a side view of a component according to an embodiment of the present disclosure; and

[0031] Figure 6 is a perspective view of a component according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The detailed description set forth below in connection with the accompanying drawings is intended as a description of exemplary embodiments of systems and methods for co-packaging optical devices and transceiver components in accordance with the present disclosure and is not intended to represent the only form in which the present disclosure may be constructed or utilized. The description sets forth the features of the present disclosure in connection with the illustrated embodiments. However, it will be understood that the same or equivalent functions and structures may be accomplished by different embodiments that are also intended to be encompassed within the scope of the present disclosure. As referred to elsewhere herein, like element numbers are intended to indicate like elements or features.

[0033] Referring Figure 1A to Figure 1B and Figure 1A , in some embodiments, a short electrical connection between (i) components (e.g., photodetectors and / or modulators) on a photonic integrated circuit 105 (PIC) and (ii) components or circuits (e.g., transimpedance amplifiers and / or modulator drivers) on an electronic integrated circuit 110 can be formed by flip-chip bonding the photonic integrated circuit 105 to the electronic integrated circuit 110 to form a flip-chip assembly. The photonic integrated circuit may include a substrate (e.g., a silicon substrate) having a front surface (in the Figure 1A orientation, the upper surface of the photonic integrated circuit 105), on or in which may be V-grooves (not shown for ease of illustration) for passive alignment with optical fibers, optical waveguides, optoelectronic devices (e.g., photodetectors and modulators), and one or more metal layers forming conductive traces for routing electrical signals to and from the optoelectronic devices. The optical waveguides may include mode converters (e.g., tapered sections) for converting, for example, between a mode that may propagate in a 3-micron-wide waveguide and (i) a mode that may propagate in a single-mode optical fiber or (ii) a mode that may produce a useful intensity distribution in an optoelectronic device. The electronic integrated circuit 110 may have a length between 5 mm and 15 mm (e.g., a length of 10.2 mm) and a width between 2 mm and 9 mm (e.g., a width of 4.4 mm), and the photonic integrated circuit 105 may have a length between 7 mm and 30 mm (e.g., a length of 15 mm) and a width between 3 mm and 11 mm (e.g., a width of 5.5 mm).

[0034] The electronic integrated circuit 110 may be a silicon integrated circuit, and the front surface of the electronic integrated circuit 110 (in the Figure 1AIn the orientation of, the lower surface) may include interface circuits for docking with optoelectronic devices (e.g., a transimpedance amplifier for amplifying the photocurrent generated by a photodetector on the photonic integrated circuit 105 and a modulator driver for driving a modulator (e.g., an electro-absorption (EA) modulator) on the photonic integrated circuit 105). Each of these interface circuits may be part of a corresponding high-speed channel on the front surface of the electronic integrated circuit 110. Each high-speed channel may include (in addition to the interface circuit) a serial receiver circuit (for the high-speed channel connected to the modulator) or a serial transmitter circuit (for the high-speed channel connected to the photodetector). These serial receiver circuits and serial transmitter circuits may be, for example, XSR or USR receiver or transmitter circuits, and they may be used to exchange data with digital electronic circuits (e.g., an application-specific integrated circuit (ASIC) for switches) as discussed in more detail below. Each high-speed channel may also include circuitry for connecting the interface circuit to the serial receiver circuit or the serial transmitter circuit (e.g., in the case of the high-speed channel connected to the photodetector, a clock and data recovery circuit connected to the transimpedance amplifier). The circuitry on the electronic integrated circuit 110 may occupy a relatively small fraction (e.g., less than half or less than a quarter) of the area of the electronic integrated circuit 110, and in some embodiments, for example, additional area may be used to fabricate a microcontroller on the first portion 115 of the electronic integrated circuit 110.

[0035] In some embodiments, the electrical connection between the optoelectronic device on the photonic integrated circuit 105 and the corresponding interface circuit (e.g., an amplifier) on the electronic integrated circuit 110 can have a length less than 500 microns, or less than 200 microns, or less than 100 microns. In some embodiments, the length can be almost as small as the height of the metal bumps 140 (e.g., copper pillar bumps, which are discussed in more detail below) that form the connection between the photonic integrated circuit 105 and the electronic integrated circuit 110. In some embodiments, the analog portion of the receive channel (e.g., a photodetector and a transimpedance amplifier connected to the photodetector) can have a bandwidth of at least 10 GHz, or at least 20 GHz, or at least 60 GHz (e.g., 3 dB bandwidth), where the bandwidth is defined according to the transfer function from the amplitude modulation of the light received by the photodetector to the corresponding signal at the output of the transimpedance amplifier. The bandwidth can be a relatively sensitive function of the interconnect length between the PIC 140 and the IC 110 mentioned above. For example, a relatively small increase in the interconnect length can result in a significant decrease in the bandwidth. Similarly, the analog portion of the transmit channel (e.g., a modulator and a drive amplifier in the modulator driver connected to the modulator) can have a bandwidth of at least 10 GHz, or at least 20 GHz, or at least 60 GHz (e.g., 3 dB bandwidth), where the bandwidth is defined according to the transfer function from the electrical signal at the input of the drive amplifier to the corresponding amplitude modulation generated by the modulator. The bandwidth can be a relatively sensitive function of the interconnect length between the PIC 140 and the IC 110 mentioned above. For example, a relatively small increase in the interconnect length can result in a significant decrease in the bandwidth. In some embodiments, Figure 1A and Figure 1B configured such that it is not necessary for the electronic integrated circuit 110 (or the photonic integrated circuit 105) to have a redistribution layer on either surface; instead, a relatively small number of patterned metal layers (e.g., 10 or fewer metal layers) on one or both of the electronic integrated circuit 110 and the photonic integrated circuit 105 may be sufficient.

[0036] The photonic integrated circuit 105 and the electronic integrated circuit 110 can be offset from each other such that Figure 1A each of the photonic integrated circuit 105 and the electronic integrated circuit 110 protrudes outside the other as shown. In particular, a first portion 115 of the electronic integrated circuit 110 can protrude outside a first edge 120 of the photonic integrated circuit 105, and a first portion 125 of the photonic integrated circuit 105 can protrude outside a first edge 130 of the electronic integrated circuit 110. Refer to Figure 1B, the photonic integrated circuit 105 and the electronic integrated circuit 110 may overlap in the overlapping region 135. In some embodiments, the first portion 125 of the photonic integrated circuit 105 and the first portion 115 of the electronic integrated circuit 110 are located on opposite sides of the overlapping region 135 (as shown, for example, in Figure 1B ), and the overlapping region 135 is generally located between the first portion 115 of the electronic integrated circuit 110 and the first portion 125 of the photonic integrated circuit 105. In other embodiments, the relative positions may be different; for example, the first portion 115 of the electronic integrated circuit 110 may extend away from the overlapping region 135 in a first direction, and the first portion 125 of the photonic integrated circuit 105 may extend away from the overlapping region 135 in a second direction perpendicular to the first direction.

[0037] In the overlapping region 135, the photonic integrated circuit 105 and the electronic integrated circuit 110 may be fastened together and electrically connected by a plurality of metal bumps. For example, a plurality of solder-topped copper pillar bumps 140 (e.g., Cu / Ni / SnAg bumps) may be formed on the front surface of the photonic integrated circuit 105, and a corresponding plurality of pads 145 (e.g., Ni / Au pads) may be formed on the front surface of the electronic integrated circuit 110; then, the photonic integrated circuit 105 may be soldered to the electronic integrated circuit 110, where each solder-topped copper pillar bump 140 of the photonic integrated circuit 105 in the overlapping region is soldered to the corresponding pad on the electronic integrated circuit 110. The soldering may be performed, for example, using thermocompression bonding.

[0038] Each of the copper pillar bumps 140 may have a diameter between 25 um (micrometers) and 100 um and a height between 25 um and 100 um. Each of the copper pillar bumps 140 may be formed on a pad opening (e.g., an opening in an insulating (e.g., silicon dioxide) layer on the front surface of the photonic integrated circuit 105) having a diameter between 10 um and 70 um.

[0039] Reference Figure 2A, the copper pillar bumps 140 in the overlapping region 135 can be located on a grid that substantially fills the overlapping region 135 (e.g., a grid with a pitch between 50 um and 150 um). As shown, the overlapping region 135 can be rectangular. In some embodiments, as shown, corner bumps can be omitted for stress relief. The pads 145 (e.g., Ni / Au pads) on the electronic integrated circuit 110 can have a diameter of more than 100 um (in embodiments where the pitch of the grid exceeds 100 um). The pitch of the copper pillar bumps 140 can be selected based on the design channel count and density. For example, reducing the bump pitch (and correspondingly reducing the channel pitch) reduces the width of the PIC 105 and the electronic integrated circuit 110. The reduction in chip width increases the bandwidth density and reduces the overall product form factor within high-volume manufacturing limitations. For example, in some embodiments, the optical engines discussed herein are filled on the edge of the printed circuit board 310, and the printed circuit board 310 can form the substrate of the switch ASIC package ( Figure 5 ). The substrate form factor is ultimately determined by the widths of the PIC 105 and the electronic integrated circuit 110, which depend on the bump pitch. Additionally, reducing the substrate form factor improves the aforementioned serializer-deserializer performance and reduces the cost for high volumes. This is discussed in more detail below. Each of the high-speed channels 150 can be connected to a corresponding pair of pads, or "connector bumps" (e.g., Ni / Au pads), in the first portion 115 of the front surface of the electronic integrated circuit 110 through a pair of conductive traces on the front surface of the electronic integrated circuit 110, as part of a connection (e.g., XSR or USR connection, or other suitable serial electrical connection) to, for example, a switch ASIC, as discussed in more detail below. The pads in the first portion 115 of the front surface of the electronic integrated circuit 110 can be similar to the pads on the front surface of the electronic integrated circuit 110 in the overlapping region 135, although the pads in the first portion 115 of the front surface of the electronic integrated circuit 110 may have different sizes from the pads on the front surface of the electronic integrated circuit 110 in the overlapping region 135. Figure 2B An example of a candidate pin assignment for the connector bumps is shown. Corner connector bumps may not be present (as Figure 2A shown) or may be present (as Figure 2B shown).

[0040] The optoelectronic devices can be located in rows approximately 700 um from the first edge 120 (the lower edge in the Figure 2A orientation) of the photonic integrated circuit 105, and each of the high-speed channels 150 can extend from the corresponding optoelectronic device in the overlapping region 135 to the first portion 115 of the electronic integrated circuit 110, as Figure 2Aas shown in. For ease of illustration, not shown in Figure 2A a V-groove.

[0041] In some embodiments, Figure 1A , Figure 1B and Figure 2A components are made as part of a larger component as shown in Figure 3 . The compressible membrane connector 305 forms a plurality of conductive paths, for example, between pads 145 on the front surface of the first portion 115 of the electronic integrated circuit 110 and corresponding pads on the printed circuit board 310, which may form a connection to the switch ASIC, as discussed in more detail below. The carrier 315 may be fastened to the rear surface of the electronic integrated circuit 110 (the rear surface being the surface opposite the front surface of the electronic integrated circuit 110). The carrier 315 may have one or more alignment ridges 320, which may be used to align the electronic integrated circuit 110 with the carrier 315 during assembly. The carrier 315 may provide mechanical reinforcement to the electronic integrated circuit 110 and to the photonic integrated circuit 105 to reduce the risk of damage during assembly, and in operation, the carrier 315 may provide a heat flow path for conducting heat dissipated in the electronic integrated circuit 110 out. The carrier 315 may be made of copper or another thermally conductive material.

[0042] In some embodiments, all optoelectronic devices on the photonic integrated circuit 105 are the same. For example, on a photonic integrated circuit 105 that may be referred to as a receive PIC (Rx PIC), all optoelectronic devices are photodetectors, and on an electronic integrated circuit 110 connected to the PIC (which may be referred to as an Rx IC), the interface circuits are all transimpedance amplifiers. Similarly, on a photonic integrated circuit 105 that may be referred to as a transmit PIC (Tx PIC), all optoelectronic devices may be modulators, and on an electronic integrated circuit 110 connected to the PIC (which may be referred to as a Tx IC), the interface circuits are all modulator drivers.

[0043] Figure 4Shows a manufacturing process in some embodiments. The Tx IC is prepared using steps including bumping (using Ni / Au pads 145), wafer backgrinding, and dicing, and the Rx IC is similarly prepared using steps including bumping (using Ni / Au pads 145), wafer backgrinding, and dicing. Wafer backgrinding can be employed to reduce the total thickness of the Tx IC or Rx IC while also reducing the case-to-junction thermal resistance between the IC and the ASIC heat sink, which is discussed in more detail below. The Tx PIC is prepared using steps including III-V microtransfer printing (to place a modulator, which can be a III-V device, on the PIC), bumping (using copper pillar bumps 140), and dicing, and the Rx PIC is prepared using steps including bumping (using copper pillar bumps 140), and dicing. The Tx IC is then soldered to the Tx PIC to form a component that can be referred to as the "Tx subassembly", and the Rx IC is then soldered to the Rx PIC to form a component that can be referred to as the "Rx subassembly". The Tx subassembly and Rx subassembly are then fastened to a carrier 315, and fiber optic pigtails are attached to the PIC to form a component that can be referred to as an optical engine. In these subassemblies, particularly in cases where the IC undergoes wafer backgrinding during wafer fabrication, the PIC can be substantially thicker than the IC. The thicker PIC reduces warping to support fine-pitch bump assembly in 135 and improves component rigidity after fiber optic pigtail assembly. In some embodiments, the photonic integrated circuit 105 has a thickness between 500 microns and 1000 microns, e.g., approximately 680 microns, and the electronic integrated circuit 110 has a thickness between 100 microns and 700 microns, e.g., 580 microns.

[0044] One or more optical engines can be used to provide an optical interface to a digital integrated circuit 505 (e.g., a switch ASIC) as shown in Figure 5 The ASIC heat sink 510 conducts heat away from the digital integrated circuit 505 (e.g., to a heat pipe-based cooling system). The top clamp 515 (along with the bottom portion 517) fastens the optical engine and the compressible membrane connector 305 to the printed circuit board 310 and conducts heat away from the optical engine that flows through the carrier 315; the top clamp is thermally connected to the removable heat sink section 520 through a layer of compliant thermal interface material 525. In Figure 5 embodiments, the carrier 315 lacks the Figure 3 alignment ridges 320 shown in Figure 5 ; in other embodiments, however, there can be one or more alignment ridges 320, and the structure can otherwise be similar to the structure shown in Figure 5 The printed circuit board 310 can form a substrate of the package, which includes Figure 5The components shown in the figure, the substrate can be fastened and connected to another printed circuit board (e.g., a motherboard) by an array of conductors 530 located on the lower surface of the printed circuit board 310. Such a motherboard may have holes or cutouts for receiving the bottom portion 517 of the fixture. The second beachfront 540 can be used to accommodate another optical engine (not shown) or, for example, an edge connector for making a serial electrical connection with the digital integrated circuit 505 (as discussed in more detail below).

[0045] Figure 5 Not drawn to scale. In some embodiments, the digital integrated circuit 505 is rectangular (e.g., square) and large enough to accommodate one or more optical engines on each of its four edges, thereby providing multiple optical interfaces to the digital integrated circuit 505. In some embodiments, the digital integrated circuit 505 has multiple electrical serial transmitters and receivers, and the package provides a direct electrical connection (e.g., at the second beachfront 540) to the first plurality of electrical serial transmitters and receivers of the digital integrated circuit 505 and (as shown on the right side of Figure 5 an optical connection to a second plurality of high-speed channels of the digital integrated circuit 505 through one or more optical engines. In embodiments having multiple optical engines, it may be advantageous to be able to replace any one of the optical engines without, for example, removing the ASIC heat sink 510 from the digital integrated circuit 505 (e.g., to install a different version of the optical engine or to replace a faulty optical engine). By Figure 5 the configuration enables such replacement of the optical engine to be possible. Figure 6 is a perspective view of an optical engine in which optical fibers are installed. The optical engine includes a Tx PIC 605, a Tx IC 610, an Rx PIC 615, and an Rx IC 620. An exemplary implementation is an embodiment providing up to 1.6T throughput. If FR4 is used, the maximum number of optical fibers can be 20 Tx fibers and 4 Rx fibers.

[0046] As used herein, the word "or" is inclusive, such that for example "A or B" means (i) A, (ii) B, and (iii) either A and B. As used herein, the term "rectangle" includes a square as a special case, i.e., a square is an example of a rectangle. It will be understood that when an element or layer is referred to as being "on another element or layer", "connected to" another element or layer, "coupled to" another element or layer, "adjacent to" another element or layer, or "next to" another element or layer, it can be directly on, connected to, coupled to, adjacent to, or next to another element or layer, or there can be one or more intervening elements or layers. In contrast, when an element or layer is referred to as being "directly on another element or layer", "directly connected to" another element or layer, "directly coupled to" another element or layer, "immediately adjacent to" another element or layer, or "immediately next to" another element or layer, there are no intervening elements or layers.

[0047] Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision that are subsumed within the recited range. For example, a range of "1.0 to 10.0" or "between 1.0 and 10.0" is intended to include all sub-ranges between the recited minimum value of 1.0 and the recited maximum value of 10.0 (and including the recited minimum value of 1.0 and the recited maximum value of 10.0), i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.

[0048] Although exemplary embodiments of systems and methods for co-packaging optical devices and transceiver components have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it will be understood that the systems and methods for co-packaging optical devices and transceiver components constructed in accordance with the principles of the present disclosure may be embodied in a manner different from that specifically described herein. The invention is also defined in the following claims and their equivalents.

Claims

1. A component, comprising: A printed circuit board; A compressible film connector; A photonic integrated circuit; And An electronic integrated circuit, A front surface of the photonic integrated circuit abuts a front surface of the electronic integrated circuit in an overlapping region, A first portion of the photonic integrated circuit protrudes beyond a first edge of the electronic integrated circuit, and a first portion of the electronic integrated circuit protrudes beyond a first edge of the photonic integrated circuit, Conductors on the front surface of the electronic integrated circuit are connected to conductors on the front surface of the photonic integrated circuit in the overlapping region, The printed circuit board abuts the first portion of the electronic integrated circuit, The compressible film connector is between the first portion of the electronic integrated circuit and the printed circuit board, and conductors on the first portion of the electronic integrated circuit are connected to conductors on the printed circuit board through conductors in the compressible film connector.

2. The component according to claim 1, wherein the first edge of the electronic integrated circuit is opposite to the first portion of the electronic integrated circuit, and the first edge of the photonic integrated circuit is opposite to the first portion of the photonic integrated circuit.

3. The component according to claim 1 or claim 2, wherein the conductors on the front surface of the electronic integrated circuit are connected to the conductors on the front surface of the photonic integrated circuit in the overlapping region through metal bumps, the metal bumps are one of a plurality of metal bumps, the metal bumps are arranged on a grid of a rectangular array, and no metal bumps exist at grid points at corners of the rectangular array.

4. The component according to claim 1, wherein in the overlapping region: There is no redistribution layer on the electronic integrated circuit, and There is no redistribution layer on the photonic integrated circuit.

5. The component according to claim 1, further comprising a digital integrated circuit on the printed circuit board, the digital integrated circuit is connected to the electronic integrated circuit through: Conductors on the printed circuit board, and Conductors in the compressible film connector.

6. The component according to claim 5, further comprising: A heat sink on the digital integrated circuit; And A heat sink on the electronic integrated circuit.

7. The component according to claim 6, wherein the component is configured to allow replacement of: The photonic integrated circuit, and The electronic integrated circuit without removing the heat sink from the digital integrated circuit.

8. The component according to claim 1, wherein: The photonic integrated circuit includes a photodetector, and The electronic integrated circuit includes an amplifier connected to the photodetector through a conduction path having a length less than 500 microns.

9. The component according to claim 8, wherein the length of the conduction path is less than 200 microns.

10. The component according to claim 8, wherein the length of the conduction path is less than 100 microns.

11. The component according to claim 1, wherein: The photonic integrated circuit includes a photodetector, and The electronic integrated circuit includes an amplifier connected to the photodetector; and wherein a signal path from an optical input carrying amplitude-modulated light to the photodetector to an output from the amplifier of an electrical signal corresponding to the amplitude modulation has a 3 dB bandwidth of at least 10 GHz.

12. The component according to claim 11, wherein the signal path has a 3 dB bandwidth of at least 60 GHz.

13. The component according to claim 1, wherein: the photonic integrated circuit includes a modulator, and the electronic integrated circuit includes an amplifier connected to the modulator by a conduction path having a length less than 500 microns.

14. The component according to claim 13, wherein the length of the conduction path is less than 200 microns.

15. The component according to claim 13, wherein the length of the conduction path is less than 100 microns.

16. The component according to claim 1, wherein: the photonic integrated circuit includes a modulator, and the electronic integrated circuit includes an amplifier connected to the modulator; and wherein a signal path from an input of an electrical signal to the amplifier to an output from the modulator carrying amplitude-modulated light corresponding to the electrical signal has a 3 dB bandwidth of at least 10 GHz.

17. The component according to claim 16, wherein the signal path has a 3 dB bandwidth of at least 40 GHz.

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