A dummy-based instruction execution method, computing device and storage medium

Abstract

The present invention discloses an instruction execution method based on dummy variables, a computing device and a storage medium. The method comprises the steps of: submitting a first storage instruction for storing data in an internal memory to the processor; generating a second storage instruction according to a data storage exception message generated by the processor; writing a dummy variable according to the storage address of the data stored in the second storage instruction; executing the second storage instruction by the processor to store data in the internal memory and replace the stored dummy variable; when receiving a first read instruction for reading data in the internal memory after writing the dummy variable, executing the first read instruction by the processor to determine whether the dummy variable is read; if the dummy variable is read, prompting that the read data is invalid, then executing the first read instruction by the processor again; if the dummy variable is not read, reading the data by the first read instruction. The present invention can prevent the atomicity of data access from being lost and avoid abnormal operation of certain special applications.

Description

Technical Field

[0001] The present invention relates to the field of computer instruction execution, and in particular to an instruction execution method based on dummy variables, a computing device and a storage medium. Background Art

[0002] With the continuous development of computer technology, more and more applications have been developed. Correspondingly, the application data is increasing, and the data structure is becoming more and more complex. Therefore, the system's memory access performance for complex data structures in memory is becoming more and more important, directly affecting the running speed of key applications. When storing data, special storage situations often occur. When the application accesses these stored data, the processor does not support special memory access instructions for the data, and an error will occur. The processor cannot directly process this type of memory access instruction to operate the data.

[0003] Therefore, in the prior art, in order to access these stored data, the data access instructions are changed so that the instructions for application accessing these data become normal instructions, and the processor can execute the data access. One of the solutions is to convert the original cross-border access instructions into two cross-border access instructions. By executing the two cross-border access instructions, the complete data can be successfully stored or read.

[0004] However, this method converts one memory access into multiple memory accesses, which essentially changes the memory access model of the application. For some special application scenarios, the atomicity of one memory access is destroyed by multiple memory accesses. If the application relies on the atomicity of memory access, in this case, the destruction of atomicity will cause data errors or errors, which may cause the application to run abnormally in severe cases.

[0005] To this end, a new instruction execution method is needed. Summary of the invention

[0006] To this end, the present invention provides an instruction execution method based on dummy variables, in an effort to solve or at least alleviate the above problems.

[0007] According to one aspect of the present invention, there is provided an instruction execution method based on dummy variables, which is suitable for execution in a computing device, wherein the computing device includes a processor, an internal memory, and runs one or more applications, wherein a storage area of ​​the internal memory is mapped to a storage space, and the application uses a storage address in the storage space to read and write data in the internal memory, and the method includes the steps of: submitting a first storage instruction for storing data in the internal memory to the processor; when the processor cannot normally execute the first storage instruction due to the storage address of the data stored in the first storage instruction, generating a second storage instruction according to a data storage exception message generated by the processor, wherein the second storage instruction is suitable for storing the first storage instruction; The instruction is to store data, and the processor will not generate a data storage exception message when executing the second storage instruction; a dummy word is written according to the storage address of the data stored in the second storage instruction, and the dummy word is suitable for prompting that the read data is invalid when being read; the processor executes the second storage instruction to store data in the internal memory and replaces the stored dummy word; when the first read instruction for reading data in the internal memory is received after writing the dummy word, the processor executes the first read instruction to determine whether the dummy word is read; if the dummy word is read, it is prompted that the read data is invalid, and the first read instruction is executed again by the processor; if the dummy word is not read, the data is read by the first read instruction.

[0008] Optionally, in the method according to the present invention, generating a second storage instruction according to a data storage exception message generated by a processor includes the steps of: generating a first half storage instruction and a second half storage instruction according to the storage address of the first storage instruction, the first half storage instruction and the second half storage instruction being suitable for storing data according to the first half address and the half address, respectively; and using the first half storage instruction and the second half storage instruction as the second storage instruction.

[0009] Optionally, in the method according to the present invention, writing a dummy word in the storage address of the data stored by the second storage instruction comprises the step of: writing a dummy word according to the second half address of the data stored by the second half storage instruction.

[0010] Optionally, in the method according to the present invention, the data is stored in the internal memory by executing the second storage instruction by the processor, and the stored dummy word is replaced, including the steps of: generating the first half data and the second half data according to the data; executing the first half storage instruction by the processor, storing the first half data according to the first half address; executing the second half storage instruction by the processor, storing the second half data according to the second half address, and replacing the stored dummy word.

[0011] Optionally, in the method according to the present invention, the first read instruction includes a second half read instruction, and the first read instruction is executed by the processor, and determining whether a dummy word is read includes the steps of: executing the second half read instruction by the processor, and reading the stored data according to the second half address to determine whether a dummy word is stored.

[0012] Optionally, in the method according to the present invention, executing the first read instruction again by the processor includes the steps of: executing the second half read instruction by the processor, reading the stored data according to the second half address to determine whether a dummy variable is stored.

[0013] Optionally, in the method according to the present invention, the first read instruction includes a first half read instruction, and reading data through the first read instruction includes the steps of: executing the first half read instruction through a processor, and reading the stored first half data according to the first half address; combining the first half data read from the first half address with the second half data read from the second half address to obtain data.

[0014] Optionally, the method according to the present invention also includes the steps of: if a second read instruction is received, submitting the second read instruction to the processor; when the processor cannot execute the second read instruction normally due to the address of the data read by the second read instruction, generating a first read instruction according to the data access exception message generated by the processor, the first read instruction is suitable for reading the data to be read by the second read instruction, and the processor will not generate a data read exception message when executing the first read instruction.

[0015] Optionally, in the method according to the present invention, generating a first read instruction based on a data access exception message generated by a processor includes the steps of: generating a first half read instruction and a second half read instruction based on a storage address of a second read instruction, the first half read instruction and the second half read instruction being suitable for reading data according to the first half address and the second half address, respectively; and using the first half read instruction and the second half read instruction as the first read instruction.

[0016] Optionally, in the method according to the present invention, the first storage instruction includes a non-boundary storage instruction, and the first half storage instruction and the second half storage instruction include bounded storage instructions.

[0017] Optionally, in the method according to the present invention, the second read instruction includes a non-boundary read instruction, and the first half read instruction and the second half read instruction include bounded read instructions.

[0018] According to another aspect of the present invention, a computing device is provided, comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing a dummy-based instruction execution method according to the present invention.

[0019] According to another aspect of the present invention, there is provided a computer-readable storage medium storing one or more programs, wherein the one or more programs include instructions which, when executed by a computing device, cause the computing device to execute a method in a dummy-based instruction execution method according to the present invention.

[0020] The dummy-based instruction execution method of the present invention is suitable for execution in a computing device, the computing device includes a processor, an internal memory, and runs one or more applications, including the steps of: submitting a first storage instruction for storing data in the internal memory of the application to the processor, when the processor cannot normally execute the first storage instruction due to the storage address of the data stored in the first storage instruction, generating a second storage instruction according to the data storage exception message generated by the processor, the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor will not generate a data storage exception message when executing the second storage instruction. In order to avoid that when storing data, threads of other cores of the processor execute data reading instructions, and incomplete data is read from a location where data storage has not been completed, causing an error in the application operation, firstly, a dummy is written according to the storage address of the data stored in the second storage instruction, and the dummy is suitable for prompting that the read data is invalid when being read; then the processor executes the second storage instruction to store data in the internal memory, replaces the stored dummy, and completes the storage of data by replacing the dummy. When the first read instruction for reading data in the internal memory is received after the dummy word is written, the processor executes the first read instruction to determine whether the dummy word is read. If the dummy word is read, it is prompted that the read data is invalid, indicating that the data storage is not completed at this time and the data cannot be read normally. The first read instruction needs to be executed again by the processor. If the dummy word is not read, the data is read through the first read instruction, indicating that the data storage is completed at this time and the data can be read normally. The present invention can constrain the edge effects caused by the change of the memory access model of the application, so that the atomicity of data access is not lost, thereby avoiding the abnormal operation of some special applications due to such edge effects, thereby improving the stability of the application and the compatibility of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. By reading the following detailed description in conjunction with the accompanying drawings, the above and other purposes, features and advantages disclosed by the present invention will become more apparent. Throughout the present disclosure, the same reference numerals generally refer to the same parts or elements.

[0022] Figure 1A schematic diagram showing a structure of a processor and an internal memory deployed in a computing device according to an exemplary embodiment of the present invention is shown;

[0023] Figure 2 shows a block diagram of a computing device 200 according to an exemplary embodiment of the present invention;

[0024] Figure 3 A schematic flow chart of a dummy-based instruction execution method 300 according to an exemplary embodiment of the present invention is shown;

[0025] Figure 4 A schematic diagram showing generating a second storage instruction according to an exemplary embodiment of the present invention; and

[0026] Figure 5 A schematic diagram of destroying instruction atomicity according to an exemplary embodiment of the present invention is shown. DETAILED DESCRIPTION

[0027] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to enable the scope of the present disclosure to be fully conveyed to those skilled in the art. The same reference numerals generally refer to the same components or elements.

[0028] Figure 1 FIG. 1 shows a schematic diagram of a structure in which a processor and an internal memory are deployed in a computing device according to an exemplary embodiment of the present invention. Figure 1 As shown, the computing device 200 includes a processor 204 and an internal memory 140. An operating system 220 is also installed in the computing device 200, and the application 110 runs on the operating system 220. The present invention does not limit the specific type of the operating system 220. Figure 1 The number of applications shown is only exemplary. There is no limit to the number and type of applications running on the operating system 220. The internal memory 140 is suitable for storing the operating data of the operating system 220 and the applications 110, and the processor 204 is suitable for processing the operating data.

[0029] Figure 1 The specific structure of the computing device 200 is as follows: Figure 2 Provide detailed explanation. Figure 2 FIG. 2 shows a block diagram of a computing device 200 according to an exemplary embodiment of the present invention. Figure 2As shown, in a basic configuration 202, computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 may be used for communication between processor 204 and system memory 206.

[0030] Depending on the desired configuration, the processor 204 can be any type of processor, including but not limited to: a microprocessor (μP), a microcontroller (μC), a digital information processor (DSP), or any combination thereof. The processor 204 can include one or more levels of cache such as a primary cache 210 and a secondary cache 212, a processor core 214, and registers 216. An example processor core 214 can include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP core), or any combination thereof. An example memory controller 218 can be used with the processor 204, or in some implementations, the memory controller 218 can be an internal part of the processor 204.

[0031] Depending on the desired configuration, the system memory 206 may be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. The system memory 206 may include an operating system 220, one or more programs 222, and program data 228. In some embodiments, the program 222 may be arranged to be executed by one or more processors 204 on the operating system using the program data 228 to execute the instructions 223 of the method 300 according to the present invention.

[0032] The computing device 200 may also include a storage interface bus 234. The storage interface bus 234 enables communication from storage devices 232 (e.g., removable storage 236 and non-removable storage 238) to the basic configuration 202 via the bus / interface controller 230. At least a portion of the operating system 220, the program 222, and the data 224 may be stored on the removable storage 236 and / or the non-removable storage 238, and when the computing device 200 is powered on or the program 222 is to be executed, it is loaded into the system memory 206 via the storage interface bus 234 and executed by the one or more processors 204.

[0033] The computing device 200 may also include an interface bus 240 that facilitates communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to the basic configuration 202 via the bus / interface controller 230. Example output devices 242 include a graphics processing unit 248 and an audio processing unit 250. They can be configured to facilitate communication with various external devices such as a display or speakers via one or more A / V ports 252. Example peripheral interfaces 244 may include a serial interface controller 254 and a parallel interface controller 256, which may be configured to facilitate communication with external devices such as input devices (e.g., keyboards, mice, pens, voice input devices, touch input devices) or other peripherals (e.g., printers, scanners, etc.) via one or more I / O ports 258. Example communication devices 246 may include a network controller 260, which may be arranged to communicate with one or more other computing devices 262 via a network communication link via one or more communication ports 264.

[0034] A network communication link can be an example of a communication medium. Communication media can generally be embodied as computer-readable instructions, data structures, program modules in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium. A "modulated data signal" can be a signal in which one or more of its data sets or its changes can be carried out in a manner that encodes information in the signal. As non-limiting examples, communication media can include wired media such as a wired network or a dedicated line network, and various wireless media such as sound, radio frequency (RF), microwave, infrared (IR) or other wireless media. The term computer-readable medium used herein can include both storage media and communication media.

[0035] In the computing device 200 according to the present invention, the program 222 includes multiple program instructions of the dummy-based instruction execution method 300, which can instruct the processor 204 to execute some steps in running the dummy-based instruction execution method 300 in the computing device 200 of the present invention, so that each part in the computing device 200 executes instructions by executing the dummy-based instruction execution method 300.

[0036] The computing device 200 can be implemented as a server, such as a file server 240, a database 250, a server, an application server, etc. These electronic devices can be such as personal digital assistants (PDAs), wireless network browsing devices, application-specific devices, or hybrid devices that can include any of the above functions. It can be implemented as a personal computer including desktop computers and notebook computer configurations. In some embodiments, the computing device 200 is configured to execute the instruction execution method 300 based on dummy variables.

[0037] Figure 3 FIG. 3 is a flow chart of a dummy-based instruction execution method 300 according to an exemplary embodiment of the present invention. The dummy-based instruction execution method 300 of the present invention is suitable for execution in a computing device, and is further suitable for execution by Figure 1 The operating system 220 shown in FIG. Figure 3 As shown, the dummy-based instruction execution method 300 begins at step S310, submitting a first storage instruction of the application 110 to store data in the internal memory 140 to the processor 204. When the application 110 needs to store data in the internal memory 140, it needs to submit the first storage instruction of the storage data to the processor 204 for execution via the operating system 220. The storage area of ​​the internal memory 140 is mapped to a storage space, and the application 110 stores data in the internal memory 140 using a storage address in the storage space.

[0038] Subsequently, step S320 is executed. When the processor 204 cannot normally execute the first storage instruction due to the storage address of the data stored in the first storage instruction, a second storage instruction is generated according to the data storage exception message generated by the processor 204. The second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor 204 does not generate a data storage exception message when executing the second storage instruction.

[0039] According to one embodiment of the present invention, when the storage address is not bounded in the internal memory 140, the processor 204 cannot execute the special operation instruction, and a data storage exception message will be generated. The first storage instruction includes a non-bounded storage instruction. When the data to be read by the application 110 is not stored in the internal memory 140, the first operation instruction is a non-bounded memory access instruction, and the data storage exception message is a non-bounded memory storage exception. Non-bounded means that the starting position of the data stored in the memory is not aligned with the natural boundary of the data of this type stored sequentially in the memory. For example, a 32-bit register, when storing data normally, the register stores a complete 32-bit data, and the first address of the data storage is the first address of the register. However, when the storage is not bounded, the calculator only stores a part of the 32-bit data, and the first address of the 32-bit data is offset from the first address of the register, and the first address of the data is at a certain address in the middle of the register. The other part of the 32-bit data is stored in the next register. Or for a 32-bit register, the processor 204 supports reading 16 bits of data at a time. When the first address of the 16-bit data is in the middle of the 32-bit register, that is, cross-border storage of the 16-bit data occurs, the processor 204 cannot read the data normally. The processor 204 cannot completely retrieve the 16-bit data stored separately according to one instruction, so the processor 204 will throw an exception. The non-bounded memory storage exception means that on a processor 204 that does not support direct storage of non-bounded data, directly storing non-bounded data will cause the processor 204 to throw an exception.

[0040] Figure 4 FIG. 4 is a schematic diagram showing a method of generating a second storage instruction according to an exemplary embodiment of the present invention. Figure 4 As shown, when converting the out-of-bounds memory access instruction, the instruction decomposition calculation sequence is first executed, and the first half storage instruction and the second half storage instruction are generated according to the storage address of the first storage instruction. The first half storage instruction and the second half storage instruction are respectively suitable for storing data according to the first half address and the half address, and finally the first half storage instruction and the second half storage instruction are used as the second storage instruction. The first half storage instruction and the second half storage instruction include the in-bounds storage instruction.

[0041] In the above instruction conversion process, the memory access model of application 110 is changed, and one memory operation is split into multiple operations, which leads to edge effects, especially changes in the atomicity of memory access. When the correctness of the running logic of application 110 depends on the assumption of atomicity, the lack of atomicity will cause the application 110 to run abnormally.

[0042] Figure 5 FIG. 2 shows a schematic diagram of destroying instruction atomicity according to an exemplary embodiment of the present invention. Figure 5As shown, since the first half memory access instruction and the second half memory access instruction are two independent operations, there is no atomicity, and there is a horizon gap between them, and other horizons can be inserted. If a thread of another processing core performs a memory access and write operation in its horizon, the integrity of the data will be destroyed, which may cause the application 110 to run abnormally.

[0043] Therefore, it is necessary to execute step S330, and write a dummy word according to the storage address of the data stored by the second storage instruction. The dummy word is suitable for prompting that the read data is invalid when being read. When starting to store data, writing a dummy word represents the beginning of data storage, and data cannot be read from the storage segment at this time. The dummy word is a preset data. When the processor 204 reads the dummy word, it represents that the read data is invalid. The dummy word is written at the location where the first storage instruction stores the data. Specifically: the complete data space stored by the first storage instruction is [0, n), and the data space for storing the dummy word is [i, j], where 0≤i<n, 0≤j<n, i≤j. Inserting a dummy word can replace an additional locking mechanism, solve the problem of atomicity loss caused by the conversion of out-of-bounds memory access instructions, and improve the overall performance of data access. Specifically, when writing a dummy word, the dummy word is written according to the second half address of the data stored by the second half storage instruction.

[0044] Then, step S340 is executed, and the processor executes the second storage instruction to store data in the internal memory 140, and the stored dummy word is replaced. The completion of the dummy word replacement means that the data is stored in the internal memory 140. Specifically, the first half of the data and the second half of the data are first generated according to the data, and then the processor 204 executes the first half storage instruction, and the first half of the data is stored according to the first half address. Finally, the processor 204 executes the second half storage instruction, and the second half of the data is stored according to the second half address, and the stored dummy word is replaced.

[0045] In the process of storing data, if a thread executes an instruction to access data and needs to operate in the storage segment currently writing data, step S350 is executed to protect the atomicity of the data writing process. When a first read instruction to read data in the internal memory 140 is received after writing the dummy, the processor 204 executes the first read instruction to determine whether the dummy is read. The first read instruction includes a second half read instruction and a first half read instruction, and the first half read instruction and the second half read instruction include a boundary read instruction. Since the dummy is written in the second half address when writing the dummy, the processor 204 executes the second half read instruction to read the stored data according to the second half address to determine whether the dummy is stored.

[0046] If no dummy character is read, it means that the storage segment has completed data storage and data can be read normally.

[0047] Then, step S360 is executed. If a dummy word is read, it indicates that the read data is invalid, and the first read instruction is executed again by the processor 204. If a dummy word is read, it indicates that the storage segment is storing data. If data is read at this time, wrong and incomplete data will be read. The first read instruction is executed again, that is, it is determined again whether the data is stored. When the first read instruction is executed again. The second half read instruction is still executed by the processor 204, and the stored data is read according to the second half address to determine whether a dummy word is stored.

[0048] If a dummy word is still read at this time, the first read instruction is continued to be executed to continue to determine whether the data storage is complete, until the data storage is complete, and the first read instruction is continued until no dummy word is read. In the process of repeated reading, data is also written. When the data writing is completed, the data can be read normally and the loop can be exited, thereby preventing the reading of wrong data.

[0049] Finally, step S370 is executed. If no dummy word is read, data is read through the first read instruction. When the data storage is completed, step S360 is executed at this time, and the stored second half data can be read according to the second half address. When reading data through the first read instruction, the processor 204 executes the first half read instruction, reads the stored first half data according to the first half address, and combines the first half data read from the first half address with the second half data read from the second half address to obtain data. When the first half data and the second half data are combined and sorted, according to the data structure of the first half data and the second half data, the obtained first half data and the second half data are subjected to logical bit operations such as shift, AND, OR, and the required data is intercepted and aligned from the data obtained by the boundary access instruction.

[0050] According to one embodiment of the present invention, when performing instruction conversion, when a certain instruction in the execution instruction stream is a non-bounded memory access instruction, it will be converted to an in-bounded memory access instruction. And all instructions after the instruction stream are traversed, and subsequent non-bounded memory access instructions are converted to in-bounded memory access instructions. Non-bounded memory access instructions include non-bounded read instructions and non-bounded store instructions, and in-bounded memory access instructions include in-bounded read instructions and in-bounded store instructions.

[0051] If a second read instruction is received in the instruction stream, and the second read instruction includes an out-of-bounds read instruction that has not been converted, the second read instruction is first submitted to the processor 204. When the processor 204 cannot normally execute the second read instruction due to the address of the data read by the second read instruction, a first read instruction is generated according to the data access exception message generated by the processor 204, and the first read instruction is suitable for reading the data to be read by the second read instruction, and the processor 204 does not generate a data read exception message when executing the first read instruction.

[0052] When the first read instruction is generated according to the data access exception message generated by the processor 204, the instruction decomposition sequence is executed first, and the first half read instruction and the second half read instruction are generated according to the storage address of the second read instruction. The first half read instruction and the second half read instruction are suitable for reading data according to the first half address and the second half address, respectively. The first half read instruction and the second half read instruction are used as the first read instruction.

[0053] The dummy-based instruction execution method of the present invention is suitable for execution in a computing device, the computing device includes a processor, an internal memory, and runs one or more applications, including the steps of: submitting a first storage instruction for storing data in the internal memory of the application to the processor, when the processor cannot normally execute the first storage instruction due to the storage address of the data stored in the first storage instruction, generating a second storage instruction according to the data storage exception message generated by the processor, the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor will not generate a data storage exception message when executing the second storage instruction. In order to avoid that when storing data, threads of other cores of the processor execute data reading instructions, and incomplete data is read from a location where data storage has not been completed, causing an error in the application operation, firstly, a dummy is written according to the storage address of the data stored in the second storage instruction, and the dummy is suitable for prompting that the read data is invalid when being read; then the processor executes the second storage instruction to store data in the internal memory, replaces the stored dummy, and completes the storage of data by replacing the dummy. When the first read instruction for reading data in the internal memory is received after the dummy word is written, the processor executes the first read instruction to determine whether the dummy word is read. If the dummy word is read, it is prompted that the read data is invalid, indicating that the data storage is not completed at this time and the data cannot be read normally. The first read instruction needs to be executed again by the processor. If the dummy word is not read, the data is read through the first read instruction, indicating that the data storage is completed at this time and the data can be read normally. The present invention can constrain the edge effects caused by the change of the memory access model of the application, so that the atomicity of data access is not lost, thereby avoiding the abnormal operation of some special applications due to such edge effects, thereby improving the stability of the application and the compatibility of the entire system.

[0054] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0055] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim.

[0056] Those skilled in the art will appreciate that the modules or units or groups of the devices in the examples disclosed herein may be arranged in the device as described in the embodiment, or alternatively may be located in one or more devices different from the devices in the example. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0057] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or groups in the embodiments may be combined into one module or unit or group, and in addition they may be divided into a plurality of submodules or subunits or subgroups. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0058] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present invention and to form different embodiments.

[0059] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0060] The various techniques described herein may be implemented in combination with hardware or software, or a combination thereof. Thus, the method and apparatus of the present invention, or some aspects or portions of the method and apparatus of the present invention may be in the form of program codes (i.e., instructions) embedded in a tangible medium, such as a floppy disk, a CD-ROM, a hard disk drive, or any other machine-readable storage medium, wherein when the program is loaded into a machine such as a computer and executed by the machine, the machine becomes a device for practicing the present invention.

[0061] In the case where the program code is executed on a programmable computer, the computing device generally includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store the program code; the processor is configured to execute the dummy-based instruction execution method of the present invention according to the instructions in the program code stored in the memory.

[0062] By way of example and not limitation, computer readable media include computer storage media and communication media. Computer readable media include computer storage media and communication media. Computer storage media stores information such as computer readable instructions, data structures, program modules or other data. Communication media generally embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and includes any information delivery medium. Any combination of the above is also included within the scope of computer readable media.

[0063] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0064] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and didactic purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative, not restrictive, with respect to the scope of the present invention, which is defined by the appended claims.

Claims

1. A dummy variable-based instruction execution method, suitable for execution in a computing device, the computing device comprising a processor, an internal memory, and running one or more applications, the storage area of ​​the internal memory is mapped as a storage space, and the application reads and writes data in the internal memory with a storage address in the storage space, the method comprising the steps of: submitting a first storage instruction of the application to store data in the internal memory to the processor; When the processor cannot normally execute the first storage instruction due to the storage address of the data stored by the first storage instruction, a second storage instruction is generated according to the data storage exception message generated by the processor, the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor does not generate a data storage exception message when executing the second storage instruction; Writing a dummy word according to the storage address of the data stored by the second storage instruction, wherein the dummy word is a preset data segment suitable for prompting that the read data is invalid when being read; Executing the second storage instruction by the processor to store data in the internal memory, and replacing the stored dummy variable; When a first read instruction to read data in the internal memory is received after the dummy word is written, the processor executes the first read instruction to determine whether the dummy word is read; If a dummy word is read, indicating that the read data is invalid, the processor executes the first read instruction again; If no dummy word is read, reading data through the first read instruction; Wherein, generating a second storage instruction according to the data storage exception message generated by the processor comprises the steps of: Generate a first half storage instruction and a second half storage instruction according to the storage address of the first storage instruction, wherein the first half storage instruction and the second half storage instruction are respectively suitable for storing data according to the first half address and the second half address, wherein the first storage instruction includes a non-boundary storage instruction, and the first half storage instruction and the second half storage instruction include a bounded storage instruction; Using the first half storage instruction and the second half storage instruction as the second storage instruction; The method further includes: if a second read instruction is received, submitting the second read instruction to the processor; When the processor cannot normally execute the second read instruction due to the address of the data to be read by the second read instruction, generating a first read instruction according to the data access exception message generated by the processor, the first read instruction is suitable for reading the data to be read by the second read instruction, and the processor does not generate a data read exception message when executing the first read instruction, and the second read instruction includes an out-of-bounds read instruction; The step of generating a first read instruction according to the data access exception message generated by the processor comprises the following steps: Generate a first half read instruction and a second half read instruction according to the storage address of the second read instruction, wherein the first half read instruction and the second half read instruction include a boundary read instruction, and the first half read instruction and the second half read instruction are respectively suitable for reading data according to the first half address and the second half address; Using the first half read instruction and the second half read instruction as the first read instruction; The step of writing a dummy variable into the storage address of the data stored according to the second storage instruction comprises the following steps: A dummy word is written according to the second half address of the data stored by the second half storage instruction.

2. The method of claim 1, wherein: The step of executing the second storage instruction by the processor to store data in the internal memory and replacing the stored dummy variable comprises the following steps: Generate the first half of the data and the second half of the data according to the data to be stored; Executing the first half storage instruction by the processor, storing the first half data according to the first half address; The processor executes the second half storage instruction, stores the second half data according to the second half address, and replaces the stored dummy variable.

3. The method of claim 2, wherein: The first read instruction includes a second half read instruction, and the processor executes the first read instruction to determine whether a dummy variable is read, including the steps of: The processor executes the second half read instruction and reads the stored data according to the second half address to determine whether a dummy variable is stored.

4. The method of claim 3, wherein: The executing the first read instruction again by the processor comprises the steps of: The processor executes the second half read instruction and reads the stored data according to the second half address to determine whether a dummy variable is stored.

5. The method of claim 4, wherein: The first read instruction includes a first half read instruction, and reading data through the first read instruction includes the steps of: Executing the first half read instruction by the processor to read the first half data stored according to the first half address; The first half data read from the first half address and the second half data read from the second half address are combined to obtain data.

6. A computing device comprising: one or more processors; Memory; as well as One or more devices comprising instructions for executing the method according to any one of claims 1-5.

7. A computer-readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device cause the computing device to perform the method according to any one of claims 1 to 5.

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