Storage life calculation method and flash memory

Abstract

The present invention provides a storage life calculation method and a flash memory. The calculation method includes: respectively obtaining distribution curves of data retention performance parameters of multiple identical devices under test placed in multiple test environments over operating time, wherein the operating temperature of each test environment is different, and the device under test has a preset data retention performance standard line; then, based on the multiple distribution curves and the preset data retention performance standard line, obtaining the storage life of each device under test at the corresponding operating temperature, and taking each operating temperature and the corresponding storage life as a target array; finally, fitting a linear function of the storage life varying with the operating temperature based on the multiple target arrays, and calculating an empirical relationship between the storage life of the device under test and the operating temperature. The empirical relationship can be used to accurately calculate the storage life of the device under test at any operating temperature.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a method for calculating storage life and a flash memory. Background Art

[0002] Whether the data retention (DR) lifespan (TTF) of the memory at the target operating temperature can meet the specification requirements is one of the reliability evaluation items of 3D NAND flash memory.

[0003] Existing evaluation methods often employ a "high-temperature acceleration" approach to save evaluation time. The target operating temperature and target data retention life at the target operating temperature are entered into a preset conversion formula to calculate the memory's test data retention life at the test temperature. The memory is then tested in a test environment at the test operating temperature for the duration of the test data retention life. If the relevant parameters of the memory after testing meet the evaluation criteria, the target data retention life at the target operating temperature is considered to have passed.

[0004] However, existing evaluation methods cannot accurately calculate the data retention life of the memory at any temperature. Summary of the Invention

[0005] The present invention provides a storage life calculation method and a flash memory, which effectively solves the problem that the data storage life of the memory at any temperature cannot be accurately calculated.

[0006] In order to solve the above problem, the present invention provides a method for calculating storage life, which includes:

[0007] Obtaining distribution curves of data retention performance parameters of a plurality of identical devices under test placed in a plurality of test environments over operating time, wherein each of the test environments has a different operating temperature and the devices under test have a preset data retention performance standard line;

[0008] Obtaining the storage life of each device under test at the corresponding operating temperature according to the plurality of distribution curves and the preset data retention performance standard line, and taking each operating temperature and the corresponding storage life as a target array;

[0009] A linear function of the storage life varying with the operating temperature is fitted based on a plurality of target arrays, and an empirical relationship between the storage life of the device under test and the operating temperature is calculated based on the linear function.

[0010] Further preferably, the data retention performance parameter is the sum of the voltage distribution intervals of the device under test, the preset data retention performance standard line is the sum of the lowest voltage distribution intervals of the device under test, and the distribution curve is the relationship between the sum of the voltage distribution intervals of the device under test and the operation time at different operating temperatures.

[0011] Further preferably, the step of obtaining the storage life of each of the devices under test at the corresponding operating temperature based on the plurality of distribution curves and the preset data retention performance standard line specifically includes:

[0012] Obtaining a direct intersection point between the distribution curve and the preset data retention performance standard line; or,

[0013] Obtaining a first extrapolated intersection point of an extrapolated line of the distribution curve and the preset data retention performance standard line;

[0014] The direct intersection point and the first extrapolated intersection point represent the storage life of the device under test at the corresponding operating temperature.

[0015] Further preferably, the data retention performance parameter is the maximum value of the error code that can be corrected in the sector of the device under test, the preset data retention performance standard line is the maximum value of the error correction code memory of the device under test, and the distribution curve is the relationship between the maximum value of the error code that can be corrected in the sector of the device under test and the operation time at different operating temperatures.

[0016] Further preferably, the device under test has a standard line for error correction success probability, and before the step of fitting a distribution curve of the data retention performance parameter of each device under test over time, the method further includes:

[0017] sampling and counting the number of bit errors of each device under test in sectors at a plurality of the operating times, to obtain a statistical curve of the number of sectors with target value bit errors in each device under test at different operating temperatures;

[0018] According to the plurality of statistical curves and the standard line of error correction success probability, the maximum value of the correctable error codes of the sector of each device under test in the corresponding operation time is obtained.

[0019] Further preferably, the step of obtaining the maximum value of correctable error codes of the sector of each device under test at the corresponding operation time based on the plurality of statistical curves and the error correction success probability standard line specifically includes:

[0020] A second extrapolated intersection point between the extrapolated line of the statistical curve and the standard line of error correction success probability is obtained, wherein the second extrapolated intersection point represents the maximum value of the correctable error code of the sector of the device under test under the corresponding operating time.

[0021] Further preferably, the step of fitting a linear function of the storage life varying with the operating temperature based on the plurality of target arrays specifically includes:

[0022] An Arrhenius model is applied to the plurality of target arrays to fit a linear function of the storage life after the model is applied and the operating temperature after the model is applied.

[0023] Further preferably, the step of applying the Arrhenius model to the plurality of target arrays specifically includes:

[0024] performing a logarithmic transformation on the storage lifetimes in the plurality of target arrays; and

[0025] Performing a reciprocal transformation on the operating temperatures in a plurality of the target arrays.

[0026] Further preferably, the device under test has an operating time critical value, and before the device under test operates to the operating time critical value, the distribution curve has a first change rate, and after the device under test operates to the operating time critical value, the distribution curve has a second change rate, wherein the first change rate is greater than the second change rate.

[0027] Further preferably, the operating temperatures in the multiple test environments include the highest operating temperature and the lowest operating temperature of the device under test.

[0028] On the other hand, the present invention further provides a flash memory, comprising:

[0029] a memory cell array; and

[0030] The peripheral circuit is electrically connected to the memory cell array and is provided with a controller, wherein the controller is configured to calculate the storage life of the memory cell array using any of the above-mentioned empirical relationships.

[0031] The beneficial effects of the present invention are as follows: the present invention provides a storage life calculation method, comprising: obtaining distribution curves of data retention performance parameters of multiple identical devices under test placed in multiple test environments over operating time, wherein each test environment has a different operating temperature and the devices under test have a preset data retention performance standard line; then, obtaining the storage life of each device under test at the corresponding operating temperature based on the multiple distribution curves and the preset data retention performance standard line, and taking each operating temperature and the corresponding storage life as a target array; finally, fitting a linear function of the storage life as a inverse of the operating temperature based on the multiple target arrays, and calculating an empirical relationship between the storage life of the device under test and the operating temperature based on the linear function. The storage life calculation method provided by the present invention tests the multiple devices under test in test environments with different operating temperatures, obtains data retention performance parameters of the devices under test at different operating temperatures at different sampling time points, and performs corresponding calculations and transformations using the preset data retention performance standard line of the devices under test, ultimately obtaining an empirical relationship between the storage life of the device under test and the operating temperature. The empirical relationship can then be used to accurately calculate the storage life of the device under test at any operating temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in describing the various embodiments according to the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 FIG. 1 is a flow chart of a storage life calculation method provided in a first embodiment according to the present invention.

[0034] Figure 2 1 is a further flowchart of the storage life calculation method provided in the first embodiment of the present invention.

[0035] Figures 3a to 3d 2 is a schematic diagram of an application scenario of the storage life calculation method provided by the first embodiment of the present invention.

[0036] Figure 4 FIG. 1 is a flow chart of a storage life calculation method provided in a second embodiment of the present invention.

[0037] Figures 5a to 5c 2 is a schematic diagram of an application scenario of the storage life calculation method provided in the second embodiment of the present invention.

[0038] Figure 6FIG. 1 is a schematic structural diagram of a flash memory provided in an embodiment according to the present invention. DETAILED DESCRIPTION

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0040] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of the specified features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0041] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or mutual communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0042] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0043] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0044] The present invention addresses the problem that existing methods for evaluating memory lifespan cannot accurately calculate the data retention lifespan of the memory at any temperature. Embodiments according to the present invention are used to solve this problem.

[0045] See also Figure 1 , Figure 1 A flow chart of a storage life calculation method provided in accordance with a first embodiment of the present invention is shown. The storage life calculation method specifically includes: a testing step S101, a point-taking step S102, and a calculation step S103. Next, each step is described in detail.

[0046] Test step S101: obtaining distribution curves of data retention performance parameters of multiple identical devices under test placed in multiple test environments over operating time, wherein the operating temperature of each test environment is different and the devices under test have a preset data retention performance standard line.

[0047] See also Figure 3a It is easy to understand that in this embodiment, multiple identical DUTs are divided into six groups, and these six groups of DUTs are placed in six test environments with different operating temperatures (T1 to T6) for testing. Then, the data retention performance (Data Retention) parameters of each group of DUTs are collected at multiple sampling time points, and the distribution curve of the data retention performance parameters of the DUTs over the operating time (Bake Time) is fitted, as shown in FIG. Figure 3b shown.

[0048] Specifically, the operating temperatures in the multiple test environments include the maximum operating temperature and the minimum operating temperature of the device under test. That is, in this embodiment, the above six operating temperatures (T1 to T6) cover the maximum operating temperature and the minimum operating temperature of the device under test.

[0049] It should be noted that, in this embodiment, the data retention performance parameter used to indicate that the performance of the device under test gradually degrades with increasing operating time at different operating temperatures is the voltage distribution interval sum (Edge sum, Esum). The preset data retention performance standard line used to determine that the performance of the device under test has degraded to the failure point when the voltage distribution interval sum is used as the reference standard for its performance degradation is the minimum voltage distribution interval sum (Final Esum Criterion) of the device under test. At this time, the above-mentioned distribution curve indicates the relationship between the voltage distribution interval sum of the device under test and the operating time at different operating temperatures.

[0050] Specifically, the device under test has an operating time threshold. Before the device under test reaches the operating time threshold, the distribution curve has a first rate of change. After the device under test reaches the operating time threshold, the distribution curve has a second rate of change, where the first rate of change is greater than the second rate of change. That is, the performance degradation rate of the device under test before reaching the operating time threshold is faster than the performance degradation rate after reaching the operating time threshold. Therefore, data storage performance parameters are typically collected more times for the device under test before reaching the operating time threshold. Specifically, an exemplary value for the operating time threshold is 168 hours.

[0051] Point selection step S102: according to the plurality of distribution curves and the preset data retention performance standard line, the storage life of each device under test at the corresponding operating temperature is obtained, and each operating temperature and the corresponding storage life are used as a target array.

[0052] It is easy to understand that if Figure 3b As shown, among the multiple distribution curves obtained in the test step S101, some distribution curves have intersections with the preset data retention performance standard line, indicating that the performance of the device under test at the operating temperature corresponding to the distribution curve has degraded to failure at a certain time point at the end of the test (in this embodiment, that is, the sum of the voltage distribution intervals of the device under test at the operating temperature corresponding to the distribution curve has decreased to the minimum voltage distribution interval sum at a certain time point). In addition, some distribution curves have no intersections with the preset data retention performance standard line, indicating that the performance of the device under test at the operating temperature corresponding to the distribution curve has not yet degraded to failure at the end of the test. For the device under test whose performance has not yet degraded to failure at the end of the test, it is necessary to perform linear extrapolation on its corresponding distribution curve, as shown in FIG. Figure 3c As shown, the time required for the performance of the device under test to degrade to failure at the operating temperature corresponding to the distribution curve is calculated, and this time is used as the storage life (TTF@Tn) of the device under test at the corresponding operating temperature.

[0053] Therefore, see Figure 2 , Figure 2 FIG. 1 shows a further flow chart of the storage life calculation method provided by the first embodiment of the present invention, as shown in FIG. Figure 2 As shown, in the point selection step S102, the step of "obtaining the storage life of each device under test at the corresponding operating temperature according to the multiple distribution curves and the preset data retention performance standard line" may specifically include:

[0054] Obtain the direct intersection of the distribution curve and the preset data retention performance standard line; or,

[0055] Obtaining a first extrapolated intersection point of an extrapolated line of the distribution curve and a preset data retention performance standard line;

[0056] The direct intersection point and the first extrapolated intersection point represent the storage life of the device under test at the corresponding operating temperature.

[0057] Preferably, when performing linear extrapolation on the distribution curve, the last preset number of points on the distribution curve are taken as the extrapolation line of the distribution curve, and an exemplary value of the preset number is 3.

[0058] Calculation step S103: fitting a linear function of the storage life versus operating temperature based on multiple target arrays, and calculating an empirical relationship between the storage life and operating temperature of the device under test based on the linear function.

[0059] Furthermore, the “fitting a linear function of storage life versus operating temperature according to multiple target arrays” in the calculation step S103 may specifically include:

[0060] An Arrhenius model is applied to multiple target arrays to fit a linear function of the storage life after the model is applied as a function of the operating temperature after the model is applied.

[0061] It should be noted that, because the storage life curves over the operating temperature for the multiple target arrays obtained in the point selection step S102, the relationship between the storage life and the operating temperature cannot be calculated directly from this curve-shaped trend chart. However, the Arrhenius model is the most typical and widely used acceleration model for temperature stress testing. Applying the Arrhenius model to the multiple target arrays above yields a linear relationship between the variable and the dependent variable. That is, the storage life after applying the model is a linear function of the operating temperature after applying the model. Using this linear function, an empirical relationship between the storage life and the operating temperature of the device under test can be calculated.

[0062] Therefore, please continue to see Figure 2 ,like Figure 2As shown, the above steps of "applying the Arrhenius model to multiple target arrays" may specifically include:

[0063] The storage life in the plurality of target arrays is logarithmically transformed, and the operating temperature in the plurality of target arrays is reciprocally transformed.

[0064] It should be noted that, in this embodiment, the storage life is recorded as TTF (Time to Failure, also known as lifetime), and the operating temperature is recorded as T. The storage life after applying the model (i.e., taking the logarithm of TTF) is Ln (lifetime), and the operating temperature after applying the model (i.e., taking the inverse of T) is 1 / K*T, where K is the Boltzmann constant (K=8.62×10 –5 eV / K). Figure 3d It can be seen that the storage life Ln(lifetime) after applying the model is a linear function of the operating temperature after applying the model, which is 1 / K*T.

[0065] Furthermore, the empirical relationship between the storage life of the device under test and the operating temperature can be expressed as TTF=Ae B(1 / K*T) , where A and B are constant coefficients calculated by the above linear function.

[0066] It is easy to understand that by substituting the target temperature of a semiconductor device into the empirical relationship, the storage life of the semiconductor device operating at the target temperature can be calculated.

[0067] Different from the prior art, the first embodiment according to the present invention provides a method for calculating storage life, including: a test step S101: respectively obtaining distribution curves of data retention performance parameters of multiple identical devices under test placed in multiple test environments over operating time, wherein the operating temperature of each test environment is different, the device under test has a preset data retention performance standard line, and the data retention performance parameter is the sum of the voltage distribution intervals of the device under test, and the preset data retention performance standard line is the sum of the lowest voltage distribution intervals of the device under test; a point selection step S102: obtaining the storage life of each device under test at the corresponding operating temperature based on the multiple distribution curves and the preset data retention performance standard line, and taking each operating temperature and the corresponding storage life as A target array; and a calculation step S103: fitting a linear function of the storage life changing with the operating temperature based on the multiple target arrays, and calculating the empirical relationship between the storage life of the device under test and the operating temperature based on the linear function. The storage life calculation method provided in this embodiment is carried out by placing multiple devices under test in test environments with different operating temperatures for testing, obtaining the sum of the voltage distribution intervals of the devices under test at different operating temperatures at different sampling time points, and using the sum of the lowest voltage distribution intervals of the devices under test to perform corresponding calculations and transformations, and finally obtaining the empirical relationship between the storage life of the device under test and the operating temperature. Therefore, by using this empirical relationship, the storage life of the device under test at any operating temperature can be accurately calculated.

[0068] See also Figure 4 , Figure 4 FIG. 1 is a flow chart showing a method for calculating storage life provided by a second embodiment of the present invention. Figure 4 As shown, the process of the second embodiment is substantially the same as that of the first embodiment. The difference is that in this embodiment, the data retention performance parameter used to indicate the gradual degradation of the performance of the device under test with increasing operating time at different operating temperatures is the maximum value of the Fail Bit Count by Sector (FBC by Sector) of the device under test. The preset data retention performance standard line used to determine whether the performance of the device under test has degraded to the failure point when the maximum value of the sector error-correcting code is used as the reference standard for performance degradation is the maximum value of the error correcting code (ECC) of the device under test. In this case, the distribution curve described above shows the relationship between the maximum value of the sector error-correcting code of the device under test and the operating time at different operating temperatures. Furthermore, the memory generally includes multiple blocks, each of which may include multiple sectors as mentioned above, and each sector includes a certain number of storage cells.

[0069] The storage life calculation method provided in this embodiment may specifically include the following steps:

[0070] Testing step S201: Obtaining distribution curves of maximum error-correctable codes in sectors of a plurality of identical devices under test placed in a plurality of test environments over operating time, wherein the operating temperature of each test environment is different and the devices under test have a maximum error-correcting code memory value;

[0071] Point selection step S202: obtaining the storage life of each device under test at the corresponding operating temperature based on the multiple distribution curves and the maximum value of the error correction code memory, and taking each operating temperature and the corresponding storage life as a target array;

[0072] Calculation step S203: fitting a linear function of the storage life versus operating temperature based on multiple target arrays, and calculating an empirical relationship between the storage life and operating temperature of the device under test based on the linear function.

[0073] It should be noted that the device under test has a standard line of error correction success probability related to its uncorrectable bit error rate (Uber), where the uncorrectable bit error rate refers to the probability that error correction cannot be successfully performed after applying any specific error correction mechanism. Therefore, in the distribution curve mentioned in test step S201, the maximum correctable error bit of the sector of the device under test at each operating temperature at each sampling time point needs to be calculated by first counting the number of bit errors in the sector, such as Figure 5a As shown, it is obtained by combining the standard line of the error correction success probability.

[0074] Therefore, before the above-mentioned test step S201, the following steps are also included:

[0075] Sampling and counting the number of bit errors in each device under test in sectors at multiple operating times, and fitting a statistical curve of the number of sectors with target value bit errors in each device under test at different operating temperatures;

[0076] According to the multiple statistical curves and the standard line of error correction success probability, the maximum value of the correctable error code of the sector of each device under test in the corresponding operation time is obtained.

[0077] For example, if the device under test has five sectors and the error correction success probability standard line is 1, then this means that there will always be one sector in the five sectors of the device under test that cannot be successfully corrected. If at sampling time t1, the number of bit errors (fail bit count) in the five sectors is 1, 1, 2, 3, and 4 respectively, then at sampling time t1, the maximum number of correctable error bits in the sector is 3. Since the number of bit errors in each sector increases with the increase in operation time, at sampling time t2 (t2>t1), the number of bit errors in the five sectors becomes 2, 2, 3, 4, and 5. Therefore, at sampling time t2, the maximum number of correctable error bits in the sector is 4.

[0078] Furthermore, the error correction success probability standard line is a value obtained by statistically analyzing a large number of samples. In actual testing, the total number of samples of the device under test may be less than the number of samples used to calculate the error correction success probability standard line. Therefore, at a certain sampling time point, the multiple statistical curves obtained by sampling and counting the number of bit errors of each device under test in units of sectors do not intersect with the error correction success probability standard line. For example, Figure 5a Therefore, it is necessary to linearly extrapolate the above statistical curves, as shown in Figure 5b As shown, the maximum value of the correctable sector error code (FBC@Tn) that can be allowed to appear in the device under test at the corresponding operating temperature at the sampling time point is calculated.

[0079] Therefore, the above step of "obtaining the maximum value of correctable error codes of the sector of each device under test under corresponding operation time based on multiple statistical curves and the standard line of error correction success probability" may specifically include:

[0080] A second extrapolated intersection point between the extrapolated line of the statistical curve and the standard line of error correction success probability is obtained, wherein the second extrapolated intersection point represents the maximum value of correctable error codes in the sector of the device under test under corresponding operation time.

[0081] It should be noted that the maximum value of the correctable error code of the above-mentioned sector will increase with the increase of operation time. However, the maximum value of the error correction code memory of the device under test is fixed. That is, if the maximum value of the correctable error code of the sector of the device under test exceeds the maximum value of its error correction code memory, the device under test will fail. Figure 5c As shown, in the point-taking step S202, the time required for the sector of the device under test to be increased by the maximum error correction code to the maximum error correction code memory at a certain operating temperature is used to represent the storage life of the device under test at the operating temperature.

[0082] Different from the prior art, the second embodiment according to the present invention provides a method for calculating storage life, including: a testing step S201: obtaining distribution curves of the maximum error-correctable codes of sectors of multiple identical devices under test placed in multiple test environments over the operating time, wherein the operating temperature of each test environment is different and the device under test has a maximum error-correcting code memory; a point-taking step S202: obtaining the storage life of each device under test at the corresponding operating temperature based on the multiple distribution curves and the maximum error-correcting code memory, and taking each operating temperature and the corresponding storage life as a target array; and a calculation step S203: fitting the multiple target arrays A linear function of the storage life varying with the operating temperature is obtained, and an empirical relationship between the storage life of the device under test and the operating temperature is calculated based on the linear function. The storage life calculation method provided in this embodiment is carried out by placing multiple devices under test in test environments with different operating temperatures for testing, thereby obtaining the maximum value of the correctable error code of the sector of the device under test at different sampling time points at different operating temperatures, and using the maximum value of the error correction code memory of the device under test to perform corresponding calculations and transformations, and finally obtaining an empirical relationship between the storage life of the device under test and the operating temperature. Therefore, the storage life of the device under test at any operating temperature can be accurately calculated by using this empirical relationship.

[0083] See also Figure 6 , Figure 6 A schematic structural diagram of a flash memory 100 provided in accordance with an embodiment of the present invention is shown. From the diagram, the various components of the embodiment of the present invention and the relative positional relationships of the various components can be intuitively seen.

[0084] like Figure 6 As shown, the flash memory 100 includes: a memory cell array 110 and a peripheral circuit 120 electrically connected to the memory cell array 110, wherein a controller 121 is provided in the peripheral circuit 120, and the controller 121 is configured to calculate the storage life of the memory cell array 110 using the empirical relationship described in the first embodiment and the second embodiment above.

[0085] Different from the prior art, the present invention provides a flash memory 100, comprising: a memory cell array 110 and a peripheral circuit 120, wherein the peripheral circuit 120 is electrically connected to the memory cell array 110 and is provided with a controller 121 configured to calculate the storage life of the memory cell array 110 using the empirical relationship described in the above embodiment. The storage life of the flash memory 100 provided by the present invention at any operating temperature can be accurately calculated using the empirical relationship.

[0086] In addition to the above embodiments, the present invention may also have other implementations. Any technical solution formed by equivalent replacement or equivalent replacement falls within the scope of protection required by the present invention.

[0087] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

Claims

1. A method for calculating storage life, characterized in that: The calculation method includes: Obtaining distribution curves of data retention performance parameters over operating time for a plurality of identical devices under test placed in a plurality of test environments, wherein each of the test environments has a different operating temperature and the devices under test have a preset data retention performance standard line; the data retention performance parameter is the sum of voltage distribution intervals of the devices under test, the preset data retention performance standard line is the sum of minimum voltage distribution intervals of the devices under test, and the distribution curve is a relationship between the sum of voltage distribution intervals of the devices under test and the operating time at different operating temperatures; Obtaining the storage life of each device under test at the corresponding operating temperature according to the plurality of distribution curves and the preset data retention performance standard line, and taking each operating temperature and the corresponding storage life as a target array; A linear function of the storage life varying with the operating temperature is fitted based on a plurality of target arrays, and an empirical relationship between the storage life of the device under test and the operating temperature is calculated based on the linear function.

2. The calculation method according to claim 1, characterized in that The step of obtaining the storage life of each of the devices under test at the corresponding operating temperature based on the plurality of distribution curves and the preset data retention performance standard line specifically includes: Obtaining a direct intersection point between the distribution curve and the preset data retention performance standard line; or, Obtaining a first extrapolated intersection point of an extrapolated line of the distribution curve and the preset data retention performance standard line; The direct intersection point and the first extrapolated intersection point represent the storage life of the device under test at the corresponding operating temperature.

3. The calculation method according to claim 1, characterized in that The data retention performance parameter is the maximum value of the correctable error code of the sector of the device under test, the preset data retention performance standard line is the maximum value of the error correction code memory of the device under test, and the distribution curve is the relationship between the maximum value of the correctable error code of the sector of the device under test and the operation time at different operating temperatures.

4. The calculation method according to claim 3, characterized in that The device under test has a standard line for error correction success probability, and before the step of fitting a distribution curve of the data retention performance parameter of each device under test over time, the method further includes: sampling and counting the number of bit errors of each device under test in sectors at a plurality of the operating times, to obtain a statistical curve of the number of sectors with target value bit errors in each device under test at different operating temperatures; According to the plurality of statistical curves and the standard line of error correction success probability, the maximum value of the correctable error codes of the sector of each device under test in the corresponding operation time is obtained.

5. The calculation method according to claim 4, characterized in that The step of obtaining the maximum value of the correctable error codes of the sector of each device under test at the corresponding operation time based on the plurality of statistical curves and the error correction success probability standard line specifically includes: A second extrapolated intersection point between the extrapolated line of the statistical curve and the standard line of error correction success probability is obtained, wherein the second extrapolated intersection point represents the maximum value of the correctable error code of the sector of the device under test under the corresponding operating time.

6. The calculation method according to claim 1, characterized in that The step of fitting a linear function of the storage life varying with the operating temperature based on the plurality of target arrays specifically includes: An Arrhenius model is applied to the plurality of target arrays to fit a linear function of the storage life after the model is applied and the operating temperature after the model is applied.

7. The calculation method according to claim 6, characterized in that: The step of applying the Arrhenius model to the plurality of target arrays specifically includes: performing a logarithmic transformation on the storage lifetimes in the plurality of target arrays; and Performing a reciprocal transformation on the operating temperatures in a plurality of the target arrays.

8. The calculation method according to claim 1, characterized in that The device under test has an operation time critical value. Before the device under test operates to the operation time critical value, the distribution curve has a first change rate. After the device under test operates to the operation time critical value, the distribution curve has a second change rate, wherein the first change rate is greater than the second change rate.

9. The calculation method according to claim 1, characterized in that: The operating temperatures in the multiple test environments include a maximum operating temperature and a minimum operating temperature of the device under test.

10. A flash memory, characterized in that: The flash memory comprises: a memory cell array; and A peripheral circuit is electrically connected to the memory cell array and is provided with a controller, wherein the controller is configured to calculate the storage life of the memory cell array using the empirical relationship according to any one of claims 1 to 9.

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