Method of forming a thin film transistor

Abstract

Embodiments disclosed herein generally relate to methods of forming thin film transistors (TFTs). The methods include forming one or more metal oxide layers and / or polysilicon layers. A gate interface (GI) layer is deposited over the one or more metal oxide layers and / or polysilicon layers using a high-density plasma chemical vapor deposition (HDP-CVD) process with inductively coupled plasma (ICP). Depositing the GI layer using HDP-CVD layer deposition unexpectedly increases the mobility of the metal oxide layer deposited thereon.

Description

Technical Field

[0001]

[0014] Embodiments of the present disclosure relate generally to methods, and more particularly, to methods of forming thin film transistors. Background Art

[0002] A thin film transistor (TFT) is a type of metal oxide semiconductor field effect transistor (MOSFET) made by depositing a thin film of active semiconductor layers, along with dielectric layers and metal contacts, on a supporting substrate. A common substrate is glass, as one application of TFTs is in liquid crystal displays (LCDs).

[0003] TFTs have attracted significant attention in display applications due to their high resolution, low power consumption, and high-speed operation for LCD and organic light-emitting diode (OLED) displays. TFTs are embedded within the display panel. Data and gate line voltage signals from the display module in the display system are transmitted to TFTs in the pixel circuits and / or gate driver circuits in the peripheral display panel area to control the displayed image by turning the TFTs on and off. Image distortion is reduced by improving the response of TFTs with higher mobility and / or by reducing crosstalk between pixels. Most display products, including LCD televisions (TVs) and monitors, include TFTs in their panels. Many modern high-resolution and high-quality electronic visual display devices use active-matrix displays with a large number of TFTs. One beneficial aspect of TFT technology is that it uses a separate TFT for each pixel on the display. By controlling the voltage and current passing through the data and gate signal lines, each TFT acts as a switch or current source in the pixel circuit or gate driver circuit, increasing control over the displayed image. The higher on-current from high-mobility TFTs minimizes distortion in the data and gate signal voltages, allowing for faster refresh rates and better image quality.

[0004] One drawback of TFTs in the art is that they can have unacceptably low mobility in the conductive channel. Furthermore, the methods used to form TFTs can provide poor control over channel mobility. Finally, it can be difficult to alter the channel's mobility after it has been deposited.

[0005] Therefore, there is a need in the art for a method of forming a TFT that allows for enhanced channel mobility. Summary of the Invention

[0006] Embodiments disclosed herein generally relate to methods of forming a TFT. The methods include depositing a layer that modifies the mobility of an underlying channel.

[0007] An exemplary method of forming a thin film transistor device includes forming a metal oxide layer over a first portion of a substrate; forming a gate insulating (GI) layer over the first portion of the substrate; forming a gate electrode over the GI layer; and etching one or more remaining portions of the GI layer. Forming the GI layer includes depositing a silicon-containing layer by a high-density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP). The HDP-CVD process has a power density of approximately 2.3 W / cm 2 to about 5.3W / cm 2 ICP power density and ICP frequency of about 2 MHz to about 13.56 MHz.

[0008] Another exemplary method of forming a thin film transistor device includes: forming a first metal oxide layer over a first portion of a substrate, the first portion of the substrate corresponding to a first thin film transistor (TFT); forming an interfacial gate insulating (GI) layer of the first TFT over the first portion of the substrate and in contact with the first metal oxide layer; forming a lower layer over a second portion of the substrate, the second portion of the substrate corresponding to a second TFT, and the lower layer contacting a bottom surface of the second metal oxide layer of the second TFT, wherein forming the interfacial GI layer and the lower layer includes depositing a first silicon-containing layer over the first portion and the second portion, wherein the first silicon-containing layer is deposited by a high-density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP), the HDP-CVD process having a power density of approximately 2.3 W / cm 2 to about 5.3W / cm 2an ICP power density of about 2 MHz to about 13.56 MHz and an ICP frequency of about 2 MHz to about 13.56 MHz; forming the second metal oxide layer of the second TFT so that its bottom surface contacts the lower layer; forming a bulk GI layer of the first TFT in contact with the interface layer, and forming a GI layer of the second TFT in contact with the top surface of the second metal oxide layer, the forming of the bulk GI layer and the GI layer comprising depositing a second silicon-containing layer over the first portion and the second portion by a chemical vapor deposition (CVD) process using a capacitively coupled plasma (CCP); forming a first gate electrode of the first TFT over the second silicon-containing layer over the first portion and forming a second gate electrode of the second TFT over the second silicon-containing layer over the second portion; removing one or more residual portions of the second silicon-containing layer from the first portion and the second portion to form the interface GI layer of the first TFT, the bulk GI layer of the first TFT, the GI layer of the second TFT, and the lower layer of the second TFT; and depositing an interlayer dielectric (ILD) layer over the substrate.

[0009] Another exemplary method of forming a thin film transistor device includes: forming a polysilicon layer over a first portion of a substrate, the first portion of the substrate corresponding to a polysilicon thin film transistor (TFT); depositing a first gate insulating (GI) layer over the polysilicon layer of the first portion and over a second portion of the substrate, the second portion of the substrate corresponding to a metal oxide (MOx) TFT; forming a first gate electrode of the polysilicon TFT over the first GI layer, and forming a shielding metal of the MOx TFT; forming a first interlayer dielectric (ILD) layer over the first GI layer, the first gate electrode, and the shielding metal; forming a metal oxide layer of the MOx TFT over the first ILD layer on the second portion of the substrate; and forming a second GI layer on the metal oxide layer, the forming of the second GI layer including depositing a silicon-containing layer by a high-density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP), the HDP-CVD process having a power of about 2.3 W / cm 2 to about 5.3W / cm 2 forming a second gate electrode over the second GI layer; and forming a second ILD layer over the first ILD layer, the metal oxide layer, and the second gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to understand in detail the manner in which the above-mentioned features of the present disclosure can be understood, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the various embodiments (some of which are depicted in the accompanying drawings). It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments.

[0011] Figure 1 A schematic cross-sectional view of a chamber according to one embodiment is shown.

[0012] Figures 2A-2H A schematic cross-sectional view of a TFT according to an embodiment is shown.

[0013] Figure 3 is a flowchart of a method of forming a TFT according to one embodiment.

[0014] Figures 4A-4J A schematic cross-sectional view of a dual transistor structure according to one embodiment is shown.

[0015] Figure 5 is a flow chart of a method of forming a dual transistor structure according to one embodiment.

[0016] Figure 6 A schematic cross-sectional view of a dual transistor structure according to one embodiment is shown.

[0017] Figure 7 A schematic cross-sectional view of a dual transistor structure according to one embodiment is shown.

[0018] Figure 8 A schematic cross-sectional view of a dual transistor structure according to one embodiment is shown.

[0019] Figures 9A-9N A schematic cross-sectional view of a dual transistor structure according to one embodiment is shown.

[0020] Figure 10 is a flow chart of a method of forming a dual transistor structure according to one embodiment.

[0021] Figure 11 A schematic cross-sectional view of a dual transistor structure according to one embodiment is shown.

[0022] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0023] Embodiments disclosed herein generally relate to methods of forming a TFT. The method includes depositing one or more metal oxide layers and / or polysilicon layers. A GI layer is deposited over the one or more metal oxide layers and / or polysilicon layers. Depositing the GI layer using HDP-CVD results in an unexpected increase in the mobility of the metal oxide layer and / or polysilicon layer deposited thereon. Depending on whether the GI layer is deposited by HDP-CVD or a CVD process using CCP, the selective placement of the GI layer results in control of the mobility of the underlying layer. Depositing the GI layer allows the mobility of the underlying layer to be controlled after the layer is deposited; that is, the mobility can be improved after deposition in addition to during deposition. Embodiments disclosed herein can be used for, but are not limited to, forming a TFT including a channel with improved mobility.

[0024] As used herein, the term "about" refers to a variation of + / - 10% from the nominal value. It should be understood that such variations can be included in any value provided herein.

[0025] In various embodiments of the present disclosure, layers or other materials are referred to as being etched. It will be appreciated that the etching of these materials can be carried out using any conventional method used in semiconductor manufacturing, such as, but not limited to, reactive ion etching (RIE), dry etching, wet etching, plasma etching, micro-loading, the selective etching of any of the above methods, a combination of the above methods, and any other suitable method. It will be appreciated that when the method operation is described herein as etching two or more types of materials, or two or more parts of the same material, etching can occur simultaneously with the same etching process, or different etching processes can be used to perform etching in separate sub-operations. For example, the operation of etching metal and dielectric includes a first etching sub-operation using a first etching process for etching metal, and the operation further includes a second etching sub-operation using a second etching process for etching dielectric.

[0026] Figure 1 A schematic cross-sectional view of a chamber 100 according to one embodiment is shown. Suitable chambers are available from Applied Materials, Inc., located in Santa Clara, California. It should be understood that the system described below is an exemplary chamber and that other chambers, including those from other manufacturers, may be used or modified to implement various aspects of the present disclosure. Chamber 100 is configured to produce HDP.

[0027] As shown, the chamber 100 includes a chamber body 104, a lid assembly 106, and a substrate support assembly 108. The lid assembly 106 is disposed at an upper end of the chamber body 104. The substrate support assembly 108 is at least partially disposed within an interior volume of the chamber body 104. The substrate support assembly 108 includes a substrate support 110 and a shaft 112. The substrate support 110 has a support surface 114 for supporting at least one substrate 102.

[0028] In one embodiment, which may be combined with other embodiments described herein, the substrate 102 is a large area substrate, such as a substrate having a surface area of ​​typically about 1 m 2 or larger substrates. However, substrate 102 is not limited to any particular size or shape. For example, the term "substrate" refers to any polygonal, square, rectangular, curved or other non-circular workpiece, such as a glass or polymer substrate used to manufacture flat panel displays. Substrate 102 may include any suitable material, such as a silicon-based substrate, a semiconductor-based substrate, an insulating-based substrate, a germanium-based substrate, and one or more common layers typically found in complementary metal oxide semiconductor (CMOS) device structures. Substrate 102 may include a transparent material, such as rigid glass or flexible polyimide (PI), which may be useful if the substrate is used for LCD or OLED display applications, such as TVs, tablets, laptops, mobile phones, or other displays. Substrate 102 may have any number of metal layers, semiconductor layers, or insulating layers thereon.

[0029] The lid assembly 106 includes a diffuser 116 located at an upper end of the chamber body 104. The diffuser 116 includes one or more diffuser inlets 118 that can be coupled to at least one gas source 120. The diffuser 116 provides one or more gases from the gas source 120 to a processing region 124 between the diffuser 116 and the substrate support 110. The one or more gases are provided to the processing region 124 through a plurality of holes (not shown) in the diffuser 116. A flow controller 122, such as a mass flow control (MFC) device, is disposed between each diffuser inlet 118 and the gas source 120 to control the flow rate of the gas from the gas source 120 to the diffuser 116. A pump 126 is in fluid communication with the processing region 124. The pump 126 is operable to control the pressure within the processing region 124 and to exhaust gases and byproducts from the processing region 124.

[0030] The lid assembly 106 includes at least one cavity 128 having one or more inductively coupled plasma generating components (or coils) 130 formed therein. The coils 130 are supported by at least one dielectric plate 132. Each dielectric plate 132 provides a physical barrier with structural strength to withstand the structural loads generated by the atmospheric pressure present within the cavity 128 and the vacuum pressure present within the interior volume of the chamber body 104. Each coil 130 is connected to a power supply 134 and a ground 138. In one embodiment, which may be combined with other embodiments described herein, each coil 130 is connected to the power supply 134 via a matching box 136 having a matching circuit for adjusting the electrical characteristics (such as impedance) of the coils 130. In some embodiments, a first capacitor 137 is electrically connected between the coil 130 and the matching box 136. In some embodiments, a terminal capacitor 139 is electrically connected between the coil 130 and the ground 138. Each coil 130 is configured to generate an electromagnetic field that excites the gas in the processing region 124 to generate a high-density plasma (HDP).

[0031] In one embodiment, the electron density generated in the chamber is greater than about 1E11 / cm 3 In one embodiment, the ion plasma density generated in the chamber is greater than about 1E11 / cm 3 In one embodiment, the ICP power density used to generate the HDP is about 5.3 W / cm 2 In one embodiment, the ICP frequency used to generate the HDP is from about 2 MHz to about 13.56 MHz.

[0032] Controller 190 is coupled to chamber 100 and is configured to control various aspects of chamber 100 during processing. As shown, controller 190 includes a central processing unit (CPU) 191, memory 192, and support circuitry (or I / O) 193. CPU 191 is one of any form of computer processor used in industrial environments to control various processes and hardware (e.g., pattern generators, motors, and other hardware) and monitor processes (e.g., processing time and substrate positioning or location). Memory 192 is connected to CPU 191 and can be one or more readily available memory devices, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. Software instructions and data can be encoded and stored within memory 192 for directing CPU 191. Support circuitry 193 is also connected to CPU 191 for supporting the CPU in a conventional manner. Support circuitry 193 includes conventional cache memory, power supplies, clock circuitry, input / output circuitry, subsystems, and the like. A program (or computer instructions) readable by the controller 190 determines which tasks are performed on the substrate 102. The program may be software readable by the controller 190 and may include code for monitoring and controlling, for example, processing parameters (e.g., pressure, temperature, gas flow rates) in the chamber 100.

[0033] Figures 2A-2H A schematic cross-sectional view illustrating a method of forming a TFT 200 according to one embodiment is shown. Figure 3 is a flow chart of a method 300 for forming a TFT 200 according to the same embodiment. Figure 1 The chamber 100 is described Figures 2A-2H 、 Figure 3 、 Figure 8 and Figure 11 However, it should be noted that ICP-CVD chambers other than chamber 100 may also be used in conjunction with method 300. Method 300 may be stored on or accessible to controller 190 as a computer-readable medium containing instructions that, when executed by CPU 191, cause chamber 100 to perform method 300.

[0034] As shown in the figure, a TFT 200 ( Figure 2A ).

[0035] Method 300 begins at operation 310, where a metal oxide layer 204 is formed, such as Figure 2B2B. The metal oxide layer 204 is formed by any conventional method used in the art. In some embodiments, the metal oxide layer 204 is deposited on the substrate 102. In one embodiment, which may be combined with other embodiments described herein, the metal oxide layer 204 includes oxygen (O) and at least one of the following: indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and hafnium (Hf). Examples of the metal oxide layer 204 include, but are not limited to, In-Ga-Zn-O, In-Zn-O, In-Ga-Sn-O, In-Zn-Sn-O, In-Ga-Zn-Sn-O, In-Sn-O, Hf-In-Zn-O, Ga-Zn-O, In-O, Al-Sn-Zn-O, Zn-O, Zn-Sn-O, Al-Zn-O, Al-Zn-Sn-O, Hf-Zn-O, Sn-O, and Al-Sn-Zn-In-O. Operation 310 may include doping the metal oxide layer 204 with an n-type or p-type dopant, such as boron (B) or nitrogen (N). The metal oxide layer 204 may have a thickness of about 30 nm to about 50 nm. The metal oxide layer film may be formed in a first sub-operation and etched in a second sub-operation to produce the metal oxide layer 204. In other embodiments, the metal oxide layer 204 is deposited using selective deposition to produce a metal oxide layer 204 having a desired shape.

[0036] At operation 340, the GI layer 206 is deposited, as Figure 2C As shown. GI layer 206 is deposited on at least a portion of metal oxide layer 204. GI layer 206 is in direct contact with metal oxide layer 204. GI layer 206 includes insulating materials such as silicon, silicon oxide (Si x O y ), silicon nitride (SiN x ), other insulating materials, or a combination thereof. The GI layer 206 may have a thickness of about to about Operation 340 is performed using high density plasma chemical vapor deposition (HDP-CVD).

[0037] Operation 340 includes flowing a gas having a flow rate of about 0.40 sccm / cm for a period of about 20 seconds to about 900 seconds. 2 to about 0.60 sccm / cm 2 of nitrous oxide (N2O) and a flow rate of about 0.01 sccm / cm 2 to about 0.01 sccm / cm 2Silane (SiH4), a ratio of N2O to SiH4 is about 5 to about 40, the chamber pressure is at a pressure of about 75 mTorr to about 150 mTorr, the chamber temperature is about 70°C to about 350°C, and the substrate temperature is about 80°C to about 160°C. Operation 340 is performed using HDP-CVD, and the ICP power density is about 2 W / cm 2 to about 6W / cm 2 , such as about 2.3 W / cm 2 to about 5.3W / cm 2 The ICP frequency is about 1 MHz to about 15 MHz, such as about 2 MHz to about 13.56 MHz, the applied bias power is about 0 W to about 200 W, and the ICP power is about 4000 W to about 10000 W. In some embodiments, silicon tetrafluoride (SiF4), disilane (Si2H6), oxygen (O2), ozone (O3), Ar, nitrogen (N2), ammonia (NH3), He, or a mixture thereof is co-flowed. The distance between the substrate and the gas source may be about 7000 mm to about 8000 mm.

[0038] The GI layer 206 may be formed at about to about The GI layer may be deposited at a rate of about 1.8 to about 2.0. The refractive index of the GI layer may be about 1.8 to about 2.0. The percentage of silicon-hydrogen (Si-H) bonds may be about 0.1% to about 12%. The percentage of silicon-nitrogen (Si-N) bonds may be about 10% to about 25%. The peak position of silicon-oxygen bonds (Si-O) measured in spectroscopy may be about 10501 / cm to about 11001 / cm. The stress of the GI layer 206 is about -450MPa to about 700MPa. The stress of the GI layer 206 including Si is given in Table 1. x N y Example process variables for operation 340 are given in Table 2 where the GI layer 206 includes Si x O y Example process variables for operation 340 are shown.

[0039]

[0040] Table 1: For including Si x N y Example process variables for operation 340 of the GI layer of FIG. A blank cell indicates that the variable is not applicable.

[0041]

[0042] Table 2: For including Si x O y Example process variables for operation 340 of the GI layer of FIG. A blank cell indicates that the variable is not applicable.

[0043] In a capacitively coupled plasma chemical vapor deposition (CCP-CVD) process, a pair of electrodes, such as parallel plate electrodes, are provided, with one electrode coupled to ground and the other to a power source. A gas is introduced between them, effectively forming a capacitor. By powering the powered electrode with electricity, electrical energy is capacitively coupled into the gas to form a plasma of the gas. The ion density of the plasma is a function of the power delivered to the gas. In contrast, in an ICP, a coil surrounds or is positioned above the gas region where the plasma will form, and electrical energy flowing through the coil is electromagnetically coupled into the gas to ionize or otherwise excite the gas atoms or molecules. Similarly, the plasma ion density is a function of the energy coupled into the gas. In a CCP system, one of the electrodes is typically also the substrate support, so the power that can be coupled into the gas is limited by its potential negative impact on the substrate. In contrast, with an ICP arrangement, the power for ionizing gas atoms and molecules is separated from the circuit components that hold the substrate, allowing higher power to be delivered into the plasma, thereby achieving higher ion densities in the plasma without adversely affecting the substrate. Therefore, HDP can be generated from an ICP source (ie, HDP-CVD process).

[0044] It has been found that HDP-CVD deposition of SiO x The GI layer 206 unexpectedly results in an increase in the mobility of the underlying metal oxide layer 204. The mobility of the metal oxide layer 204 (eg, InGaZnO4) can be increased from less than 15 cm 2 / V s increases to greater than about 150 cm 2 / V s, e.g. up to about 450cm 2 / V s or even greater. In addition, the mobility of the metal oxide layer 204 at saturation can be greater than about 3000 cm 2 / V s. When SiO is deposited on the same metal oxide layer 204 using a CVD process using CCP x When the GI layer 206 is deposited at saturation, there is no such increase in mobility or mobility at saturation. It is believed that the use of HDP-CVD to deposit the GI layer 206 causes a chemical transformation of the underlying metal oxide layer 204, thereby resulting in an increase in mobility. The interface between the metal oxide layer 204 and the GI layer 206 may have an increased carrier density, which increases the mobility of the metal oxide layer. In the metal oxide layer 204 including indium (In), the diffusion of In atoms from the metal oxide layer to the GI layer 206 may result in increased carrier generation and, therefore, an increase in mobility. In addition, the metal oxide layer 204 may undergo structural changes that further increase mobility, such as atomic diffusion to repair atomic defects.

[0045] At operation 350, the gate electrode 208 is formed, as shown in FIG. Figure 2D As shown. In some embodiments, the gate electrode 208 is formed on the GI layer 206. The gate electrode 208 includes molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals including MoW, a combination of conductive materials including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, any conductive material, such as including conductive metal oxides such as indium tin oxide (InSnO) (ITO) and indium zinc oxide (InZnO) (IZO), or any combination thereof. In some embodiments, the gate electrode 208 is deposited in a single operation. In other embodiments, the material of the gate electrode 208 is deposited in a first sub-operation to form a metal layer, and one or more remaining portions of the metal layer are etched to form the gate electrode 208. The gate electrode 208 is configured to be connected to a gate line signal as a power supply (not shown) to provide a voltage across the various layers of the TFT 200.

[0046] At operation 360, one or more remaining portions 206* of the GI layer 206 are etched. Figure 2D ),like Figure 2E In some embodiments, the gate electrode 208 acts as a mask to etch the GI layer 206 into a desired size and shape. In some embodiments, the wet etch rate (WER) of the GI layer 206 is about to about Operation 360 may include dry etching.

[0047] At operation 370, an interlayer dielectric (ILD) layer 210 is formed, such as Figure 2F In some embodiments, an ILD layer 210 is formed on the gate electrode 208 and the metal oxide layer 204. The ILD layer 210 includes, for example, single silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), insulating materials such as silicon oxynitride (SiON), other insulating materials, or combinations thereof. In some embodiments, the ILD layer 210 is deposited using the same process parameters as operation 330. The ILD layer 210 can be planarized, such as by chemical mechanical polishing (CMP). The ILD layer 210 can be deposited using HDP-CVD or a CVD process using CCP.

[0048] As a result of sequence 380 , source electrode 212 , drain electrode 214 , source electrode via 216 , and drain electrode via 218 are formed in ILD layer 210 . Figure 2G As shown. Sequence 380 may include any conventional method used in the art for forming gate and drain electrode structures. In some embodiments, in a first operation, portions of the ILD layer 210 are etched to expose a portion of the metal oxide layer 204. In a second operation, portions of the ILD that expose a portion of the metal oxide layer 204 are filled with a conductive material to form the source electrode 212, the drain electrode 214, the source electrode via 216, and the drain electrode via 218. Conductive materials include Mo, Cr, Cu, Ti, Ta, W, alloy metals including MoW, combinations of conductive materials including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, any conductive material, such as a conductive metal oxide such as ITO or IZO, or any combination thereof.

[0049] At operation 390, a passivation layer 220 is formed, such as Figure 2H As shown. In some embodiments, a passivation layer 220 is formed over the ILD layer 210, the source electrode 212, and the drain electrode 214. The passivation layer 220 may include any material used in the ILD layer 210 or the buffer layer 202. The passivation layer 220 may be deposited using HDP-CVD or a CVD process using CCP. In some embodiments, the passivation layer 220 is deposited using the same process parameters as operation 330. The passivation layer 220 may be planarized, such as by chemical mechanical polishing (CMP).

[0050] In some embodiments, a buffer layer (not shown) is disposed on the substrate 102 and below the metal oxide layer 204. The buffer layer includes an insulating material such as silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or a combination thereof.

[0051] In some embodiments, the TFT 200 further includes a secondary buffer layer (not shown) disposed above the buffer layer and below the metal oxide layer 204. A shielding metal (not shown) is disposed above the buffer layer, within the secondary buffer layer, and below the metal oxide layer 204. The secondary buffer layer can include any of the materials described above for the buffer layer. The shielding metal can include any of the materials described above for the gate electrode 208. The shielding metal reduces the exposure of the TFT 200 to undesirable electromagnetic radiation.

[0052] Figures 4A-4J A schematic cross-sectional view of a dual-transistor structure 400 is shown according to one embodiment. Figure 5is a flow chart of a method 500 for forming a dual transistor structure 400 according to the same embodiment. Figure 1 The chamber 100 is described Figures 4A-4J 、 Figure 5 、 Figure 6 and Figure 7 However, it should be noted that ICP-CVD chambers other than chamber 100 may also be used in conjunction with method 500. Method 500 may be stored on or accessible to controller 190 as a computer-readable medium containing instructions that, when executed by CPU 191, cause chamber 100 to perform method 500.

[0053] As shown in the figure, the dual transistor structure 400 includes a substrate 102 ( Figure 4A ).

[0054] The method 500 begins at operation 510, where a first metal oxide layer 204A is formed, such as Figure 4B In some embodiments, the first metal oxide layer 204A is formed on the first portion 491 of the substrate 102 (or on the buffer layer 202 , if present). Operation 510 may be performed similarly to operation 310 .

[0055] At operation 540, a GI layer 206 (or interfacial GI layer) is deposited, such as Figure 4C As shown, a GI layer is deposited on at least a portion of the first metal oxide layer 204A. The GI layer 206 is in direct contact with the metal oxide layer 204A. Operation 540 may be performed similarly to operation 340.

[0056] At operation 550, a second metal oxide layer 204B is formed, such as Figure 4D In some embodiments, the second metal oxide layer 204B is formed on the GI layer 206 over the second portion 492 of the substrate 102. Operation 550 may be performed similarly to operation 510.

[0057] At operation 555, a secondary GI layer (or bulk layer) 406 is deposited, such as Figure 4E As shown. A secondary GI layer 406 is deposited over the GI layer 206 and the second metal oxide layer 204B. The secondary GI layer 406 is in direct contact with the second metal oxide layer 204B. The secondary GI layer 406 may include any material included in the GI layer 206. The deposition of the secondary GI layer includes a CVD process using CCP. Operation 555 may be performed similarly to operation 340.

[0058] At operation 560, a first gate electrode 208A and a second gate electrode 208B are formed, as shown in FIG. Figure 4FIn some embodiments, a first gate electrode 208A and a second gate electrode 208B are formed on the secondary GI layer 406. The first gate electrode 208A is formed on the first metal oxide layer 204A, and the second gate electrode 208B is formed on the second metal oxide layer 204B. Operation 560 can be performed similarly to operation 350.

[0059] At operation 570, one or more remaining portions 206* of the GI layer 206 and one or more remaining portions 406* of the secondary GI layer 406 are etched. Figure 4F ),like Figure 4G As shown. In some embodiments, the first gate electrode 208A and the second gate electrode 208B act as masks to etch the GI layer 206 into a desired size and shape, thereby forming a first GI layer portion (or interface GI layer) 206A, a first secondary GI portion (or bulk GI layer) 406A, a lower side layer 206B, and a GI layer 406B. Similarly, in some embodiments, the first gate electrode 208A and the second gate electrode 208B act as masks to etch the secondary GI layer 406 into a desired size and shape, thereby forming a first GI layer portion 206A, a first secondary GI portion 406A, a lower side layer 206B, and a GI layer 406B. Forming the lower side layer 206B and the first GI layer portion 206A in a single operation 570 reduces the total number of masking and etching operations. In addition, the reduction in masking and etching operations improves yield and reduces the operator's cost of ownership (CoO). Furthermore, operation 570 reduces the size of the two-transistor structure 400, thereby reducing the space in a display including the two-transistor structure 400. Operation 570 may be performed similarly to operation 360.

[0060] At operation 580, an ILD layer 210 is formed, such as Figure 4H In some embodiments, an ILD layer is formed over the first gate electrode 208A and the second gate electrode 208B. Operation 580 may be performed similarly to operation 370 .

[0061] As a result of sequence 590, first source electrode 212A, second source electrode 212B, first drain electrode 214A, second drain electrode 214B, first source electrode via 216A, second source electrode via 216B, first drain electrode via 218A, and second drain electrode via 218B are formed in ILD layer 210, as shown in FIG. Figure 4IAs shown. Sequence 590 may include any conventional method used in the art for forming gate and drain electrode structures. In some embodiments, in a first operation, portions of the ILD layer 210 are etched to expose a portion of the first metal oxide layer 204A and a portion of the second metal oxide layer 204B. In a second operation, portions of the ILD layer that expose the first metal oxide layer 204A are filled with a conductive material to form source electrodes 212A, 212B, drain electrodes 214A, 214B, source electrode vias 216A, 216B, and drain electrode vias 218A, 218B. Sequence 590 may be performed similarly to sequence 380.

[0062] At operation 595, a passivation layer 220 is formed, such as Figure 4J As shown. In some embodiments, a passivation layer 220 is formed over the ILD layer 210, the source electrodes 212A, 212B, and the drain electrodes 214A, 214B. Operation 595 can be performed similarly to operation 390. Thus, two TFTs 401A, 401B are formed in the dual-transistor structure 400. The two TFTs 401A, 401B can be connected in series or in parallel. The two TFTs 401A, 401B can receive the same input voltage signal or different voltage signals.

[0063] In some embodiments, a buffer layer (not shown) is disposed on the substrate 102 and below the metal oxide layer 204A. The buffer layer includes a silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), insulating materials such as silicon oxynitride (SiON), other insulating materials, or combinations thereof.

[0064] In some embodiments, the dual-transistor structure 400 further includes a secondary buffer layer (not shown) disposed above the buffer layer and below the metal oxide layer 204A and the lower layer 206B. One or more barrier metals (not shown) are disposed above the buffer layer, within the secondary buffer layer, and below one or both of the metal oxide layers 204A, 204B.

[0065] Figure 6 A dual transistor structure 600 is shown according to one embodiment. The method 500 can also be used to form the dual transistor structure 600, as will be described in more detail below.

[0066] As shown, the dual-transistor structure 600 includes a first TFT 601A and a second TFT 601B. The first TFT 601A may be similar to the first TFT 401A ( Figure 4J). However, the first TFT 601A does not include a secondary GI layer, and thus operation 555 may be omitted.

[0067] The second TFT 601B may be similar to the second TFT 401B ( Figure 4J However, the second metal oxide layer 204B is disposed over the ILD layer 210, so operation 550 is performed after operation 560. In addition, the second source electrode 212B and the second drain electrode 214B are in direct contact with the second metal oxide layer 204B and do not include a source electrode through hole or a drain electrode through hole.

[0068] In some embodiments, the dual transistor structure 600 further includes a secondary buffer layer (not shown) disposed on the buffer layer. One or more barrier metals (not shown) are disposed on the buffer layer, within the secondary buffer layer, and below one or both of the metal oxide layers 204A, 204B.

[0069] The two TFTs 601A and 601B may be connected in series or in parallel. The two TFTs 601A and 601B may receive the same input voltage signal or different voltage signals.

[0070] In some embodiments, a buffer layer (not shown) is disposed on the substrate 102 and below the metal oxide layer 204A. The buffer layer includes a silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), insulating materials such as silicon oxynitride (SiON), other insulating materials, or combinations thereof.

[0071] Figure 7 A dual transistor structure 700 is shown according to one embodiment. The method 500 can also be used to form the dual transistor structure 700, as will be described in more detail below.

[0072] As shown, the dual-transistor structure 700 includes a first TFT 701A and a second TFT 701B. The first TFT 701A is similar to the first TFT 401A ( Figure 4J). However, the first TFT 701A does not include a secondary GI layer, so operation 555 can be omitted. The dual-transistor structure 700 also includes an etch stop layer (ESL) 710 disposed above the ILD layer 210 and below the passivation layer 220. The ESL 710 can be formed in an operation after operation 550. The formation of the ESL 710 can be performed similarly to operation 370. The ESL 710 can include any material included in the ILD layer 210. The first source electrode 212A and the first drain electrode 214A are disposed above the ESL 710. The first source electrode via 216A and the first drain electrode via 218A are disposed in the ESL 710 and the ILD layer 210.

[0073] The second TFT 701B is similar to the second TFT 401B ( Figure 4J However, the second metal oxide layer 204B is disposed on the ESL 710, so operation 550 is performed after operation 560. The second source electrode 212B and the second drain electrode 214B are disposed on the ESL 710. The second source electrode via 216B and the second drain electrode via 218B are disposed in the ESL 710.

[0074] In some embodiments, a buffer layer (not shown) is disposed on the substrate 102 and below the metal oxide layer 204A. The buffer layer includes a silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), insulating materials such as silicon oxynitride (SiON), other insulating materials, or combinations thereof.

[0075] In some embodiments, the dual-transistor structure 700 further includes a secondary buffer layer (not shown) disposed above the buffer layer. One or more barrier metals (not shown) are disposed above the buffer layer, within the secondary buffer layer, and below one or both of the second metal oxide layers 204A, 204B.

[0076] The two TFTs 701A and 701B may be connected in series or in parallel. The two TFTs 701A and 701B may receive the same input voltage signal or different voltage signals.

[0077] Figure 8 A dual transistor structure 800 is shown according to one embodiment. The method 300 can also be used to form the dual transistor structure 800, as will be described in more detail below.

[0078] As shown, the dual-transistor structure 800 includes a first TFT 801A and a second TFT 801B. The first TFT 801A may be similar to the TFT 200 ( Figure 2H The second TFT 801B may be similar to the TFT 200 ( Figure 2H ). However, the GI layer and the gate electrode are not included. The dual transistor structure 800 can be formed using the method 300, wherein operation 310 further includes depositing the second metal oxide layer 204B.

[0079] In some embodiments, a buffer layer (not shown) is disposed on the substrate 102 and below the metal oxide layer 204A. The buffer layer includes a silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), insulating materials such as silicon oxynitride (SiON), other insulating materials, or combinations thereof.

[0080] The dual transistor structure 800 further includes a buffer layer 202 disposed on the substrate 102. The buffer layer 202 includes silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), insulating materials such as silicon oxynitride (SiON), other insulating materials, or combinations thereof. A secondary buffer layer 203 is disposed on the buffer layer 202. The secondary buffer layer 203 includes any material included in the buffer layer 202. A shield metal 808B is disposed on the buffer layer 202, within the secondary buffer layer 203, and below the metal oxide layer 204B. The shield metal 908B is configured to be connected to a gate line signal as a power source (not shown) to provide a voltage across the layers of the TFT 801B.

[0081] In some embodiments, the dual-transistor structure 800 further includes an additional barrier metal disposed above the buffer layer 202 , within the secondary buffer layer 203 , and below the first metal oxide layer 204A.

[0082] The two TFTs 801A and 801B can be connected in series or in parallel. The two TFTs 801A and 801B can receive the same input voltage signal or different voltage signals.

[0083] Figures 9A-9N A schematic cross-sectional view of a dual-transistor structure 900 is illustrated according to one embodiment. Figure 10is a flow chart of a method 1000 for forming a dual transistor structure 900 according to the same embodiment. Figure 1 、 Figures 9A-9N and Figure 10 The method operations are described, but those skilled in the art will understand that any system configured to perform the operations of method 1000 in any order falls within the scope of the embodiments described herein. Figure 1 The chamber 100 is described Figures 9A-9N and Figure 10 However, it should be noted that ICP-CVD chambers other than chamber 100 may also be used in conjunction with method 1000. Method 1000 may be stored on or accessible to controller 190 as a computer-readable medium containing instructions that, when executed by CPU 191, cause chamber 100 to perform method 1000.

[0084] As shown, the dual transistor structure 900 includes a substrate 102 ( Figure 9A ).

[0085] Method 1000 begins at operation 1005, where a polysilicon layer 904A is deposited. Figure 9B As shown. In some embodiments, a polysilicon layer 904A is deposited on the substrate 102 (or on the buffer layer 202, if present). The polysilicon layer 904A can be deposited using any desired method. Operation 1005 includes doping the polysilicon layer 904A with an n-type or p-type dopant (e.g., B or N), such as by ion implantation.

[0086] At operation 1010, a first GI layer 206 is deposited, such as Figure 9C In some embodiments, a first GI layer is deposited over at least a portion of the polysilicon layer 904A. Operation 1010 may be performed similarly to operation 340.

[0087] At operation 1020, a first gate electrode 208A and a shield metal 908B are formed, as shown in FIG. Figure 9D As shown. In some embodiments, a first gate electrode 208A and a shield metal 908B are formed on the first GI layer 206. The first gate electrode 208A is formed above the polysilicon layer 904A. In some embodiments, a metal layer is deposited in a first sub-operation, and one or more remaining portions of the metal layer are removed in a second sub-operation to form the first gate electrode 208A and the shield metal 908B. Operation 1020 can be performed similarly to operation 350.

[0088] At operation 1025, a secondary ILD layer 910 is formed, such as Figure 9EIn some embodiments, a secondary ILD layer 910 is formed over the first gate electrode 208A and the shield metal 908B. The secondary ILD layer 910 includes any material of the ILD layer 210. Operation 1025 may be performed similarly to operation 370.

[0089] As a result of sequence 1030, a secondary source electrode 912A, a secondary drain electrode 914A, a secondary source electrode via 916A, and a secondary drain electrode via 918A are formed in the secondary ILD layer 910. Figure 9F As shown. Sequence 1030 may include any conventional method used in the art for forming gate and drain electrode structures. In some embodiments, in a first operation, portions of secondary ILD layer 910 are etched to expose a portion of polysilicon layer 904A. In a second operation, portions of secondary ILD layer 910 are filled with a conductive material to form secondary source electrode 912A, secondary drain electrode 914A, secondary source electrode via 916A, and secondary drain electrode via 918A. Secondary source electrode 912A, secondary drain electrode 914A, secondary source electrode via 916A, and secondary drain electrode via 918A may include any material included in first source electrode 212A, first drain electrode 214A, first source electrode via 216A, and first drain electrode via 218A. Sequence 1030 may be performed similarly to sequence 380.

[0090] At operation 1035, a secondary buffer layer 203 is formed, as shown in FIG. Figure 9G In some embodiments, secondary buffer layer 203 is deposited over secondary source electrode 912A, secondary drain electrode 914A, secondary source electrode via 916A, and secondary drain electrode via 918A. Secondary buffer layer 203 may be deposited using HDP-CVD or a CVD process using CCP.

[0091] At operation 1040, a second metal oxide layer 204B is formed, such as Figure 9H In some embodiments, a second metal oxide layer 204B is formed on the secondary buffer layer 203. Operation 1040 may be performed similarly to operation 510.

[0092] At operation 1050, a secondary GI layer 406 is deposited, such as Figure 9I As shown, the secondary GI layer 406 is deposited on the second metal oxide layer 204B. The secondary GI layer 406 is in direct contact with the second metal oxide layer 204B. Operation 1050 may be performed similarly to operation 555.

[0093] At operation 1060, a second gate electrode 208B is formed, as shown in FIG. Figure 9JIn some embodiments, the second gate electrode 208B is formed on the secondary GI layer 406. The second gate electrode 208B is formed on the second metal oxide layer 204B. Operation 1060 may be performed similarly to operation 350.

[0094] At operation 1065, one or more remaining portions 406* of the secondary GI layer 406 are etched. Figure 9J ),like Figure 9K In some embodiments, the second gate electrode 208B acts as a mask to etch the secondary GI layer 406 into a desired size and shape. Operation 1065 may be performed similarly to operation 360 .

[0095] At operation 1070, an ILD layer 210 is formed, such as Figure 9L In some embodiments, an ILD layer 210 is formed over the second gate electrode 208B and the metal oxide layer 206B. Operation 1070 may be performed similarly to operation 370 .

[0096] As a result of sequence 1075, source electrodes 212A, 212B, drain electrodes 214A, 214B, source electrode vias 216A, 216B, and drain electrode vias 218A, 218B are formed in the ILD layer 210. Figure 9M As shown. Sequence 1075 may include any conventional method used in the art to form gate and drain electrode structures. First source electrode via 216A and first drain electrode via 218A are in electrical contact with secondary source electrode 912A and secondary drain electrode 914A, respectively. Sequence 1075 may be performed similarly to sequence 380.

[0097] At operation 1080, a passivation layer 220 is formed, such as Figure 9N As shown. In some embodiments, a passivation layer 220 is deposited over the ILD layer 210, the source electrodes 212A, 212B, and the drain electrodes 214A, 214B. Operation 1080 can be performed similarly to operation 390. Thus, a first TFT (or polysilicon TFT) 901A and a second TFT (or metal oxide (MOx) TFT) 901B are formed in the dual-transistor structure 400.

[0098] In some embodiments, the shield metal 908B is formed over the secondary ILD layer 910. In these embodiments, operation 1020 is divided into two sub-operations, and the sub-operation of forming the shield metal 908B is performed after operation 1025.

[0099] In some embodiments, sequence 1030 is not performed, and thus, the secondary source electrode, secondary source electrode via, secondary drain electrode, and secondary drain electrode via are not formed. In these embodiments, the first source electrode via 216A and the first drain electrode via 218A are further disposed in the secondary ILD layer 910 and the secondary buffer layer 203. Therefore, the first source electrode via 216A and the first drain electrode via 218A are in direct electrical contact with the polysilicon layer 904A.

[0100] In some embodiments, the polysilicon layer 904 is p-type doped (eg, with B) and the metal oxide layer 204B is n-type doped (eg, with N).

[0101] The two TFTs 901A and 901B can be connected in series or in parallel. The two TFTs 901A and 901B can receive the same input voltage signal or different voltage signals.

[0102] Figure 11 A dual transistor structure 1100 is shown according to one embodiment. The method 300 can also be used to form the dual transistor structure 1100, as will be described in more detail below.

[0103] As shown, the dual transistor structure 1100 includes a first TFT 1101A and a second TFT 1101B. The first TFT 1101A may be similar to the TFT 200 ( Figure 2H ). However, instead of the first metal layer, a polysilicon layer 904A is included. Therefore, operation 310 forms only the second metal oxide layer 904B. Operation 1005 is also included. The second TFT 1101B is similar to TFT 200 ( Figure 2H The dual-transistor structure 1100 further includes a buffer layer 202 disposed above the substrate 102 and below the ILD layer 210. The dual-transistor structure 1100 further includes a shield metal 908B. The shield metal 908B is disposed above the substrate 102, within the buffer layer 202, and below the metal oxide layer 904B. The GI layer 206A does not increase the mobility of the polysilicon layer 904A below the GI layer 206A.

[0104] In some embodiments, the GI layer 206 is etched in operation 360 such that the GI layer exists over the entire surface 904S of the polysilicon layer 904A and over the metal oxide layer 204B.

[0105] In some embodiments, the GI layer 206 is not etched, and thus the GI layer 206 is disposed as a layer over the polysilicon layer 904A and the metal oxide layer 204B.

[0106] The two TFTs 1101A and 1101B may be connected in series or in parallel. The two TFTs 1101A and 1101B may receive the same input voltage signal or different voltage signals.

[0107] The two TFTs in each of the above-described dual-transistor structures (e.g., dual-transistor structures 400, 600, 700, 800, 900, 1100) are used as a liquid crystal display (LCD) or organic light-emitting diode (OLED) display pixel circuit, or in a gate driver (GIP) circuit in a panel. For example, each TFT in the dual-transistor structure can be used as a switch or driver TFT in an OLED pixel circuit. Each dual-transistor structure includes a first TFT (e.g., TFT 401A, 601A, 701A, 801A, 901B, 1101B) having a higher mobility than a second TFT (e.g., TFT 401B, 601B, 701B, 801B, 901A, 1101A). Because the GI layer is deposited on top of the metal oxide layer in the first TFT and the GI layer is deposited by HDP-CVD, the first TFT has a higher mobility than the second TFT. The GI layer in direct contact with the metal oxide layer (the GI layer deposited by HDP-CVD) increases the mobility of the underlying metal oxide layer, as described in detail above in the discussion of method 300. According to one embodiment, the first TFT has a mobility greater than about 30 cm2 / V s and the second TFT has a mobility less than about 30 cm2 / V s.

[0108] In any of the above methods 300, 500, and 1000, one or more optional operations may be included. Optionally, any of the disclosed metal oxide layers may be pretreated. The pretreatment comprises flowing a gas at a temperature of about 25°C to about 400°C for a period of about 1 second to about 600 seconds, wherein the gas comprises nitrous oxide (N2O) at a flow rate of about 0.40 sccm / cm2 to about 0.60 sccm / cm2, and the gas comprises argon (Ar) at a flow rate of about 0 sccm / cm2 (i.e., no Ar co-flow) to about 0.60 sccm / cm2, with the chamber pressure being about 1 mTorr to about 300 mTorr. In one example, the pretreatment includes flowing a gas comprising nitrous oxide (NO) at a flow rate of about 0.40 sccm / cm2 to about 0.60 sccm / cm2 and argon (Ar) at a flow rate of about 0 sccm / cm2 (i.e., no Ar co-flow) to about 0.60 sccm / cm2 at a temperature of about 50°C to about 300°C for a period of about 1 second to about 45 seconds, with a chamber pressure of about 10 mTorr to about 150 mTorr. In some embodiments, nitrogen dioxide (NO), neon (Ne), helium (He), or a mixture of the foregoing gases may also co-flow. The pretreatment may increase the mobility of the pretreated metal oxide layer. The pretreatment may be performed in a static chamber or by a linear source in a dynamic chamber (such as chamber 100 described above).

[0109] Optionally, a seed layer may be deposited on top of any metal oxide layer disclosed herein. The seed layer is deposited on at least a portion of the metal oxide layer. The seed layer improves the adhesion of the layer deposited thereon (e.g., the GI layer). The seed layer may have a thickness of about 1 nm to about 100 nm. The deposition of the seed layer may include a CVD process using a CCP. For example, the deposition of the seed layer may include a CVD process using a CCP, followed by deposition of a GI layer on the interface seed layer, and deposition of the GI layer by an HDP-CVD process. Since the seed layer is thin, the metal oxide layer below the seed layer is still affected by the HDP-CVD process, and the mobility of the metal oxide layer is advantageously improved. In any of the above embodiments, one or more residual portions of the seed GI layer may also be removed.

[0110] The formation of the metal oxide layer, the optional pretreatment of the metal oxide layer, the optional deposition of the seed layer, and the deposition of the GI layer (hereinafter collectively referred to as MO / GI operations) can be performed in a single chamber (e.g., chamber 100) without breaking vacuum. In another embodiment, the MO / GI operations can be performed in an integrated system having multiple chambers without breaking vacuum, and each MO / GI operation can be performed in any chamber. Alternatively, any of the MO / GI operations can be performed in any number of chambers, with vacuum breaks included between MO / GI operations.

[0111] In one example, the metal oxide layer is formed in a first chamber, the substrate is transferred to a second chamber under vacuum, and the GI layer is deposited in the second chamber. In another example, the metal oxide layer is formed in a first chamber, the substrate is transferred to a second chamber with vacuum broken, and the GI layer is deposited in the second chamber.

[0112] As described above, methods for forming a TFT and a method for forming a dual-transistor structure are provided. These methods include depositing one or more metal oxide layers and / or polysilicon layers. A GI layer is deposited on top of the one or more metal oxide layers using a HDP-CVD process.

[0113] Depositing the GI layer using HDP-CVD results in an unexpected increase in the mobility of the metal oxide layer and / or polysilicon layer deposited thereon. Depending on whether the GI layer is deposited by HDP-CVD or a CVD process using CCP, the selective placement of the GI layer results in mobility control of the underlying layers. Depositing the GI layer allows for control of the mobility of the underlying layers after the layer is deposited; that is, mobility can be increased after deposition, in addition to during deposition.

[0114] While the foregoing is directed to examples of the present disclosure, other and further examples of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A method for forming a thin film transistor, comprising: forming a metal oxide layer over the first portion of the substrate; Depositing a gate insulating (GI) layer over the metal oxide layer, forming the GI layer includes depositing a silicon-containing layer by a high-density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP), the HDP-CVD process having: 2.3W / cm 2 Up to 5.3W / cm 2 ICP power density; and ICP frequencies from 2MHz to 13.56MHz; depositing a bulk GI layer over the GI layer, wherein depositing the bulk GI layer comprises a chemical vapor deposition (CVD) process using a capacitively coupled plasma (CCP); forming a gate electrode on the bulk GI layer; and The GI layer and one or more remaining portions of the bulk GI layer are etched.

2. The method according to claim 1, further comprising: Prior to depositing the GI layer, the metal oxide layer is pretreated, wherein pretreating the metal oxide layer comprises exposing the metal oxide layer to a pretreatment ICP.

3. The method of claim 2, wherein the pretreatment ICP is formed from nitrous oxide (N2O), argon (Ar), or a combination thereof.

4. The method according to claim 1, further comprising: Before depositing the GI layer, a seed layer is deposited on the metal oxide layer, wherein depositing the seed layer includes a CVD process using CCP, and the seed layer has a thickness of less than 100 nm. The method of claim 1 , wherein depositing the GI layer comprises heating the substrate to a temperature of 70° C. to 350° C.

6. The method according to claim 1, further comprising: forming an interlayer dielectric (ILD) layer over the gate electrode; forming a source electrode, a source electrode through-hole, a drain electrode, and a drain electrode through-hole in the ILD layer; and A passivation layer is formed over the source electrode, the drain electrode, and the ILD layer.

7. The method according to claim 1, further comprising: A polysilicon layer or an additional metal oxide layer is formed over the second portion of the substrate.

8. A method of forming a thin film transistor device, comprising: forming a first metal oxide layer over a first portion of a substrate, the first portion of the substrate corresponding to a first thin film transistor (TFT); depositing an interfacial gate insulating (GI) layer of the first TFT over the first portion of the substrate in contact with the first metal oxide layer; forming a lower layer on a second portion of the substrate, the second portion of the substrate corresponding to the second TFT, and the lower layer contacting a bottom surface of the second metal oxide layer of the second TFT, and forming the interface GI layer and the lower layer comprising: Depositing a first silicon-containing layer over the first portion and the second portion, the first silicon-containing layer being deposited by a high-density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP), the HDP-CVD process having: 5.3W / cm 2 ICP power density; and ICP frequencies from 2MHz to 13.56MHz; forming the second metal oxide layer of the second TFT so that the bottom surface contacts the lower layer; depositing a bulk GI layer of the first TFT in contact with the interface GI layer, and forming a GI layer of the second TFT in contact with a top surface of the second metal oxide layer, wherein forming the bulk GI layer and the GI layer comprises depositing a second silicon-containing layer over the first portion and the second portion by a chemical deposition process (CVD) using capacitively coupled plasma (CCP); forming a first gate electrode of the first TFT over the first portion and forming a second gate electrode of the second TFT over the second portion; removing one or more remaining portions of the second silicon-containing layer from the first portion and the second portion to form the interfacial GI layer of the first TFT, the bulk GI layer of the first TFT, the GI layer of the second TFT, and the underside layer of the second TFT; and An interlayer dielectric (ILD) layer is formed over the substrate.

9. The method of claim 8, wherein depositing the interface GI layer and forming the underside layer are included in the same operation. 10 . The method of claim 8 , wherein the first gate electrode and the second gate electrode include molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), or alloys thereof.

11. The method according to claim 8, wherein the bulk GI layer comprises silicon oxide (Si x O y ) and the first metal oxide layer includes In-Ga-Zn-O. 12 . The method of claim 8 , wherein the bulk GI layer has a higher atomic percentage of indium (In) atoms than the interface GI layer.

13. A method of forming a thin film transistor device, comprising: forming a polysilicon layer over a first portion of a substrate, the first portion of the substrate corresponding to a polysilicon thin film transistor (TFT); depositing a first gate insulating (GI) layer over the polysilicon layer in the first portion and over a second portion of the substrate, the second portion of the substrate corresponding to a metal oxide (MOx) TFT; forming a first gate electrode on the first GI layer of the polysilicon TFT and forming a shielding metal of the MOx TFT; forming a first interlayer dielectric (ILD) layer over the first GI layer, the first gate electrode, and the shield metal; forming a metal oxide layer of the MOx TFT over the first ILD layer on the second portion of the substrate; forming a second GI layer on the metal oxide layer, wherein forming the second GI layer includes depositing a silicon-containing layer by a high-density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP), wherein the HDP-CVD process has: 2.3W / cm 2 Up to 5.3W / cm 2 ICP power density; and ICP frequencies from 2MHz to 13.56MHz; forming a second gate electrode on the second GI layer; and A second ILD layer is formed over the first ILD layer, the metal oxide layer, and the second gate electrode.

14. The method of claim 13, wherein the barrier metal comprises molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), or alloys thereof. The method of claim 13 , wherein forming the first ILD layer comprises a HDP-CVD process. The method of claim 13 , further comprising forming a passivation layer over the second ILD layer. The method of claim 13 , further comprising forming a buffer layer over the first ILD layer.

18. The method according to claim 13, wherein the MOx TFT has a thermal conductivity greater than 30 cm 2 / Vs mobility. The method of claim 13 , wherein depositing the first GI layer comprises the HDP-CVD process.

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