An integrated circuit layout simulation method, computer device, and storage medium

Abstract

The present invention is applicable to the field of PCB layout simulation, and provides an integrated circuit layout simulation method, a computer device, and a storage medium. The simulation method includes: obtaining a plurality of integrated circuit layouts and connection relationships, where the connection relationships are the connection relationships between the integrated layouts and the connection relationships within the integrated circuit layouts; dividing the plurality of integrated circuit layouts into a plurality of subsystems according to the connection relationships; and performing excitation simulation on the plurality of subsystems. By treating different layouts as a whole based on their connection relationships and then dividing them into different subsystems, on the one hand, it can directly reduce the scale of the sparse matrix in the finite element excitation simulation calculation, thereby improving the calculation efficiency. On the other hand, the ports connected between the layouts can be used as the internal connection relationships of the subsystems, which also reduces the number of elements in the right-hand side term, and thus reduces the number of unknowns to be solved in the finite element excitation simulation calculation; improving the overall calculation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of PCB layout simulation, and particularly to an integrated circuit layout simulation method, a computer device, and a storage medium. Background Art

[0002] A printed circuit board (PCB) is an important electronic component, a support for electronic components, and a carrier for electrical connections between electronic components. Almost every electronic device, from small electronic watches and calculators to large computers, communication electronic devices, and military weapon systems, as long as there are electronic components such as integrated circuits, a circuit board is used for their electrical interconnection. In the development process of larger electronic products, the most basic success factor is the design, documentation, and manufacturing of the circuit board of the product.

[0003] Since a PCB is made by electronic printing technology, it is called a "printed" circuit board. Printed boards have developed from single-layer to double-sided, multi-layer, and flexible, and still maintain their respective development trends. Due to continuous development towards high precision, high density, and high reliability, continuously reducing volume, cost, and improving performance, printed boards still maintain strong vitality in the development of future electronic devices. The function of a PCB is to provide a substrate for bonding components that complete the first-level packaging and other necessary electronic circuit parts to form a module or finished product with a specific function. Therefore, a PCB plays a leading role in the entire electronic product.

[0004] Although there are existing simulation tools for multiple PCB integrated circuit layouts in current products, they simply simulate multiple PCB integrated circuit layouts simultaneously. In essence, multiple simulation tools are started simultaneously, and the simulated models are superimposed to achieve the simulation of multiple PCB integrated circuit layouts.

[0005] Although the existing technology can expand the scale of integrated circuit layout simulation, it still requires a large amount of computing resources and has low computing efficiency. Summary of the Invention

[0006] Based on this, it is necessary to provide an integrated circuit layout simulation method, a computer device, and a storage medium for the above problems.

[0007] The simulation method includes:

[0008] Obtain a plurality of integrated circuit layouts and connection relationships, where the connection relationships are the connection relationships between integrated layouts and the connection relationships within the integrated circuit layouts;

[0009] Divide the plurality of integrated circuit layouts into a plurality of subsystems according to the connection relationships;

[0010] Perform excitation simulation on the several subsystems.

[0011] In one embodiment, an integrated circuit layout simulation device is provided, which may specifically include:

[0012] A layout acquisition module, configured to acquire several integrated circuit layouts and connection relationships.

[0013] A subsystem division module, configured to divide the several integrated circuit layouts into several subsystems according to the connection relationships;

[0014] A simulation module, configured to perform excitation simulation on the several subsystems.

[0015] In one embodiment, a computer device is provided, including a memory and a processor. When the computer program stored in the memory is executed by the processor, the processor is caused to execute the steps of the above-mentioned integrated circuit layout simulation method.

[0016] In one embodiment, a computer-readable storage medium is provided. When the computer program stored on the computer-readable storage medium is executed by a processor, the processor is caused to execute the steps of the above-mentioned integrated circuit layout simulation method.

[0017] In the above-mentioned integrated circuit layout simulation method, device, computer device, and storage medium, different layouts are regarded as a whole according to their connection relationships and then divided into different subsystems; when the connection relationships between the layouts are relatively complex, by dividing them into different subsystems, on the one hand, it can directly reduce the scale of the sparse matrix in the finite element excitation simulation calculation, thereby improving the calculation efficiency. On the other hand, the ports connected between the layouts do not have to be used as external nodes during mesh division, but as internal connection relationships of the subsystems, which reduces the number of elements in the right-hand side term and thus reduces the number of unknowns to be solved in the finite element excitation simulation calculation; the overall calculation efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flowchart of the integrated circuit layout simulation method provided in one embodiment;

[0019] Figure 2 It is a flowchart of the integrated circuit layout simulation method provided in another embodiment;

[0020] Figure 3 It is a flowchart of the integrated circuit layout simulation method provided in another embodiment;

[0021] Figure 4 It is a flowchart of the integrated circuit layout simulation method provided in another embodiment;

[0022] Figure 5 It is a flowchart of an integrated circuit layout simulation method provided in another embodiment;

[0023] Figure 6 It is a flowchart of an integrated circuit layout simulation method provided in another embodiment;

[0024] Figure 7 It is a flowchart of an integrated circuit layout simulation method provided in another embodiment;

[0025] Figure 8 It is a structural block diagram of an integrated circuit layout simulation device in one embodiment;

[0026] Figure 9 It is an internal structural block diagram of a computer device in one embodiment. Detailed implementation manners

[0027] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0028] It can be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various elements, but unless otherwise specified, these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of the present application, the first xx script may be referred to as the second xx script, and similarly, the second xx script may be referred to as the first xx script.

[0029] As Figure 1 shown, in one embodiment, an integrated circuit layout simulation method is proposed. In this embodiment, it is mainly illustrated by applying this method to a computer device. Specifically, it may include the following steps:

[0030] Step S102, obtain a plurality of integrated circuit layouts and connection relationships, where the connection relationships are the connection relationships between integrated layouts and the connection relationships inside the integrated circuit layout;

[0031] Step S104, divide the plurality of integrated circuit layouts into a plurality of subsystems according to the connection relationships;

[0032] Step S106, perform excitation simulation on the plurality of subsystems.

[0033] In one embodiment, the computer device can be an independent physical server or terminal, or a server cluster composed of multiple physical servers, and can be a cloud server that provides basic cloud computing services such as cloud servers, cloud databases, cloud storage, and CDN.

[0034] In one embodiment, the integrated circuit layout can be manually imported by the user into the simulation software of the computer device, and the computer device recognizes the integrated circuit layout; for the internal connection relationship of the integrated circuit layout, the computer device can recognize it, which is determined by the layout's own structure. For the connection relationship between integrated circuit layouts, it can be manually added and defined by the user, and can be recognized by the computer device after the user adds it. The connection relationship can refer to the wire connection, via connection, port connection between integrated circuit layouts, or the wire connection, via connection between layers inside the integrated circuit layout, and the wires, vias, etc. within the integrated circuit layout layer; the layers of the integrated circuit layout can be power layers, signal layers.

[0035] In one embodiment, the integrated circuit layout is divided into several relatively independent subsystems, and the points or regions with connection relationships between the divided subsystems are retained. These points or regions are equivalent to the ports connected to other subsystems, and the ports are equivalent to the external nodes during mesh generation. During the division, it can be divided in a way that reduces the number of external nodes of each subsystem, so as to improve the overall calculation efficiency.

[0036] Generally, when simulating without dividing the integrated circuit layout into subsystems, first perform mesh generation on the integrated circuit layout to generate an impedance network corresponding to the integrated circuit layout, and then input excitation conditions to the impedance network for finite element excitation simulation, such as voltage excitation, so as to obtain the voltage drop and current density distribution in the field domain within the impedance network.

[0037] Therefore, when several integrated circuit layouts are divided into several subsystems, during the finite element simulation of the subsystems, mesh generation can be first performed on the subsystems to generate the impedance networks of the subsystems. Excitation conditions can be input to the impedance networks of each subsystem to obtain the voltage and current distributions in each subsystem, or the impedance networks of the subsystems can be cascaded to obtain a complete impedance network, and then excitation simulation can be performed.

[0038] It is understandable that for a certain subsystem i, the sparse matrix equation generated by its finite element excitation simulation calculation is Ai*xi = bi, where Ai is the subsystem impedance network matrix of the finite element mesh division, bi is the excitation vector, that is, the right-hand side term, and xi is the solution vector corresponding to the excitation vector bi, which corresponds to the voltage value at each node in the finite element mesh division. If the number of internal nodes in the subsystem i is Ni, then the dimension of the subsystem impedance network matrix Ai is Ni×Ni. If the number of external nodes of the subsystem connected to other subsystems is Mi, then the dimensions of the excitation vectors xi and bi are Ni×Mi. When there are more external nodes, there are more elements in the right-hand side term, the sparse matrix equation needs to calculate more unknowns, and the scale of the sparse matrix equation is also larger. When performing calculations, the more computing resources are consumed. Therefore, the fewer external nodes of the subsystem, the shorter the calculation time.

[0039] In this embodiment, different layout diagrams are regarded as a whole according to their connection relationships and then divided into different subsystems; when the connection relationships between the layout diagrams are relatively complex, by dividing them into different subsystems, on the one hand, it can directly reduce the scale of the sparse matrix during the finite element excitation simulation calculation, thereby improving the calculation efficiency. On the other hand, the ports connected between the layout diagrams do not have to be external nodes during grid division, but can be regarded as the internal connection relationships of the subsystems, which reduces the number of elements in the right-hand side term, and thus reduces the number of unknowns to be solved during the finite element excitation simulation calculation; the overall calculation efficiency is improved.

[0040] In one embodiment, as Figure 2 shown, step S104, that is, the step of dividing the plurality of integrated circuit layout diagrams into a plurality of subsystems according to the connection relationship, may specifically include the following steps:

[0041] Step S202, confirm the optimal subsystem division scheme for the plurality of integrated circuit layout diagrams. The optimal subsystem division scheme is the division scheme with the highest calculation efficiency when performing finite element excitation simulation calculation;

[0042] Step S202, divide the plurality of integrated circuit layout diagrams into a plurality of subsystems according to the optimal subsystem division scheme.

[0043] In one embodiment, generally speaking, the integrated circuit layout diagram is relatively complex. Therefore, there can be many situations for the division method of the subsystem. Therefore, when dividing the subsystem, the division scheme of the subsystem can be planned to find the division scheme with the shortest total calculation duration or the highest calculation efficiency.

[0044] One possible way is to directly divide a number of integrated circuit layouts through a preset division method. If multiple division schemes can be obtained, the division scheme with the fewest external nodes in all subsystems is the preset division method, which is the division scheme with the highest calculation efficiency; if only one division scheme can be obtained, then this division scheme is the optimal division scheme. The division scheme can be based on different layers of the integrated circuit layout.

[0045] After determining the optimal division scheme, the number of integrated circuit layouts can be divided according to the optimal division scheme.

[0046] In one embodiment, such as Figure 3 , step S202, the steps for confirming the optimal subsystem division scheme for a number of integrated circuit layouts include:

[0047] Step S302, exhaust all subsystem division schemes according to the preset division method;

[0048] Step S304, calculate the finite element first simulation time corresponding to each division scheme in all the subsystem division schemes;

[0049] Step S306, select the division scheme with the shortest finite element first simulation time as the optimal division scheme.

[0050] In one embodiment, all subsystem division schemes can be exhausted. The preset division method is the actual division method when the computer device divides the subsystem of a number of integrated circuit layouts. Therefore, when planning the division scheme, it is also planned according to the preset division method. When actually dividing the subsystem, the computer device can identify its internal entities in the integrated circuit layout, such as layers, vias, traces, resistors, etc., and then divide the integrated circuit layout into different subsystems according to these entities. Several different division methods can be preset in the computer device. When planning the division scheme, one division scheme can be obtained corresponding to each division method; or several different division methods can be combined for division within the same division scheme. Since the division methods are limited, the number of division schemes is also limited, which can be several to dozens.

[0051] Then calculate the finite element first simulation time of the divided subsystems corresponding to the obtained division scheme. The finite element first simulation time is the calculation duration required by the computer device when performing finite element excitation simulation for all subsystems after dividing the subsystem and performing mesh generation. It can be understood that the first simulation time is an estimated value after calculation, which is approximate to the actual duration required for finite element excitation simulation, or there can be a reasonable deviation.

[0052] After the first simulation time corresponding to all partitioning schemes is calculated, the partitioning scheme with the shortest first simulation time is the optimal partitioning scheme.

[0053] In this embodiment, by calculating the first simulation time of the finite element corresponding to the partitioning scheme, the optimal partitioning scheme for a number of integrated circuits is confirmed. Therefore, in subsequent steps, the partitioning can be carried out through the optimal partitioning scheme, thereby improving the simulation time of the current layout of a number of integrated circuits as a whole and enhancing the processing efficiency.

[0054] In one embodiment, the preset partitioning method includes:

[0055] Dividing according to the interconnection structure between integrated circuit layouts;

[0056] Dividing according to the via connections between integrated circuit layout layers;

[0057] Dividing according to the traces within the integrated circuit layout layer.

[0058] In a possible embodiment, when planning the partitioning scheme, the units obtained by directly dividing a number of integrated circuit layouts can be directly used as subsystems. For example, in one partitioning scheme, first divide according to the interconnection structure between the integrated circuit layouts, and then divide according to the connections between the layers inside the integrated circuit layout to form a number of subsystems; in another partitioning scheme, first divide according to the interconnection structure between the integrated circuit layouts, then divide according to the connections between the layers inside the integrated circuit layout, and then divide according to the traces within the layer to form a number of subsystems; in yet another partitioning scheme, first divide a number of circuit layouts of several layers by layer, and then divide according to the traces within the layer to form a number of subsystems.

[0059] In a possible embodiment, after dividing a number of integrated circuit layouts according to the interconnection structure between the integrated circuit layouts, according to the via connections between the integrated circuit layout layers, and according to the traces within the integrated circuit layout layer, the units obtained by division can also be merged according to the connection relationship and used as subsystems, and then the subsequent optimal partitioning scheme can be determined. For example, first divide according to the interconnection structure between the integrated circuit layouts to obtain Figure 1 version Figure 2 , and then divide according to the via connections between the integrated circuit layout layers, that is, divide version Figure 1 to obtain layer 1 and layer 2, and divide version Figure 3Layers 3 and 4 are obtained by splitting; according to the connection relationships between the layers for merging, and by exhaustively listing the merging methods, several different partitioning schemes can be obtained. Exemplarily, one partitioning scheme is that layers 1 and 2 are merged as a subsystem, layer 3 is a subsystem, and layer 4 is a subsystem; another partitioning scheme is that layer 1 is a subsystem, layer 2 is a subsystem, and layers 3 and 4 are merged as a subsystem; yet another partitioning scheme is that layer 1 is a subsystem, layers 2 and 3 are merged as a subsystem, and layer 4 is a subsystem; still another partitioning scheme is that layers 1, 2, 3, and 4 are each a subsystem.

[0060] In one embodiment, as Figure 4 , step S304, the step of calculating the first finite element simulation time corresponding to each partitioning scheme among all the subsystem partitioning schemes includes:

[0061] Step S402, confirm that the partitioning scheme for which the first simulation time is to be calculated is the target partitioning scheme;

[0062] Step S402, calculate the second finite element simulation time of each subsystem in the target partitioning scheme;

[0063] Step S402, sum up the second finite element calculation times of each subsystem to generate the first simulation time.

[0064] In one embodiment, during planning, each partitioning scheme needs to be calculated one by one to select the optimal partitioning scheme. A calculation model can be used to input the partitioning scheme for which the first simulation time is to be calculated as the target partitioning scheme into the calculation model. After the calculation of the calculation model, the first simulation duration of the target partitioning scheme is output. When the calculation model calculates, it sums up the second finite element simulation times of each subsystem in the target partitioning scheme after calculation. The second simulation time is the duration required for the computer device to calculate the simulation result of the subsystem when performing finite element excitation simulation after mesh division. It can be understood that the second simulation time is a pre-estimated value after calculation and is approximate to or can have a reasonable deviation from the actual duration required for finite element excitation simulation.

[0065] In one embodiment, as Figure 5 , step S402, the step of calculating the second finite element simulation time of each subsystem in the target partitioning scheme includes:

[0066] Step S502, determine the number of internal nodes and external nodes of the subsystem for which the second simulation time is to be calculated. The internal nodes and external nodes are points or regions that serve as finite element simulation mesh division nodes;

[0067] Step S504: Calculate the third simulation time according to the number of internal nodes. The third simulation time is the time required for matrix reordering and numerical decomposition of the sparse matrix equation.

[0068] Step S506: Calculate the fourth simulation time according to the number of internal nodes and the number of external nodes. The fourth simulation time is the time required for solving the right-hand side term of the sparse matrix equation.

[0069] Step S508: Sum the third simulation time and the fourth simulation time to generate the second simulation time.

[0070] Wherein, the sparse matrix equation is the matrix equation generated during the finite element excitation simulation.

[0071] In one embodiment, for the target partitioning scheme, for several subsystems partitioned according to this scheme, each subsystem includes several internal nodes and external nodes after grid meshing, and the number of these internal nodes and external nodes will directly affect the duration of the finite element excitation simulation calculation. Therefore, it is necessary to determine the number of external nodes and internal nodes of each subsystem, and calculate the second simulation time of this subsystem accordingly.

[0072] For the subsystem whose second simulation time needs to be calculated, the calculation of its second simulation time is mainly divided into two parts. One is to calculate the fourth simulation time according to the number of internal nodes and the number of external nodes, and the other is to calculate the fourth simulation time according to the number of internal nodes and the number of external nodes; summing the two can obtain the second simulation time of this subsystem.

[0073] Exemplarily, for the sparse matrix equation of the i-th subsystem, the LU factorization-based method can be used for solving. For the two parts of the solution, one is matrix reordering and numerical LU factorization, and the second is forward substitution and backward substitution solution for each right-hand side term. The calculation time of LU factorization can be written as the function L(N), and the calculation time for each of its right-hand side terms can be written as K(N); then for the subsystem with Mi external nodes and Ni internal nodes, the third simulation time is L(Ni), and the fourth simulation time is Mi * K(Ni); and the calculation time for the finite element excitation simulation solution of this subsystem can be written as:

[0074] L(Ni) + Mi * K(Ni)

[0075] Furthermore, for the partitioning scheme with T subsystems, the calculation time for its finite element excitation simulation solution can be written as:

[0076]

[0077] It is understandable that for any two subsystems i and j in the partitioning scheme, the computational time for finite element excitation simulation can be written as:

[0078] L(Ni)+Mi*K(Ni)+L(Nj)+Mj*K(Nj)

[0079] If in another partitioning scheme, subsystems i and j are merged into one subsystem, then the computational time for finite element excitation simulation of the merged subsystem can be written as:

[0080] L(Ni+Nj)+(Mi+Mj-2Mcommon)*K(Ni+Nj)

[0081] Where Mcommon is the number of connection ports or the number of external nodes between subsystem i and subsystem j. When the number of Mcommon is large, the efficiency of combined solution is significantly better than that of independent solution for each subsystem.

[0082] Therefore, an optimal partitioning scheme with the shortest computational time can be determined by calculating the finite element simulation time corresponding to the partitioning scheme. This scheme is the optimal partitioning scheme. By planning the partitioning scheme and dividing the subsystems through the optimal partitioning scheme, the computational time of the computer device is reduced and the efficiency of finite element simulation is improved.

[0083] In one embodiment, such as Figure 6 , after step S104 of dividing the plurality of integrated circuit layouts into a plurality of subsystems according to the connection relationship, the steps include:

[0084] Step S602, performing mesh generation on the plurality of subsystems and retaining the mesh generation nodes.

[0085] In this embodiment, mesh generation is performed on a plurality of subsystems for simulation, and the external nodes and internal nodes of the mesh generation of each subsystem are numbered in sequence.

[0086] In one embodiment, such as Figure 7 , before step S106 of performing excitation simulation on the plurality of subsystems, the steps include:

[0087] Step S702, performing finite element solution on each subsystem to generate a plurality of subsystem impedance networks;

[0088] Step S704, cascading the plurality of subsystem impedance networks to generate a complete simulation model;

[0089] Step S706, performing excitation simulation on the simulation model.

[0090] In one embodiment, after mesh generation, it is necessary to write a finite element equation set for DC voltage drop analysis based on the information of each mesh generation node in the subsystem, and generate a subsystem impedance network matrix. The subsystem network matrix corresponds to the subsystem impedance network entity model. Then, cascade the impedance networks corresponding to all subsystems with the corresponding connection relationships to generate an abstract circuit impedance network corresponding to the problem, and perform circuit simulation according to the simulation parameters set by the user to obtain the voltage values of the external nodes of each subsystem.

[0091] Then, substitute the voltage values of the external nodes of each subsystem into the finite element boundary conditions corresponding to their external nodes to obtain the final voltage and current distributions on each subsystem.

[0092] As Figure 8 shown, in one embodiment, an integrated circuit layout simulation device is provided. This integrated circuit layout simulation device can be integrated into the above computer device, and specifically can include:

[0093] A layout acquisition module, configured to acquire a plurality of integrated circuit layouts and connection relationships.

[0094] A subsystem division module, which divides the plurality of integrated circuit layouts into a plurality of subsystems according to the connection relationships;

[0095] A simulation module, configured to perform excitation simulation on the plurality of subsystems.

[0096] In one embodiment, a computer device is provided. Figure 9 The internal structure diagram of the computer device in one embodiment is shown. This computer device can specifically be the computer device described in any of the above embodiments. As Figure 9 shown, this computer device includes a processor, a memory, a network interface, an input device, and a display screen connected through a system bus. Among them, the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of this computer device stores an operating system and can also store a computer program. When the computer program is executed by the processor, the processor can implement the integrated circuit layout simulation method. The internal memory can also store a computer program. When the computer program is executed by the processor, the processor can execute the integrated circuit layout simulation method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the computer device housing, or an external keyboard, touchpad, or mouse, etc.

[0097] Those skilled in the art can understand. Figure 9The structure shown is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0098] In one embodiment, the integrated circuit layout simulation device provided by this application can be implemented in the form of a computer program, and the computer program can run on a computer device as shown in Figure 9 . In the memory of the computer device, each program module that makes up the integrated circuit layout simulation device can be stored. For example, Figure 8 the layout acquisition module, subsystem division module, and simulation module shown. The computer program composed of each program module enables the processor to execute the steps in the integrated circuit layout simulation method of each embodiment of this application described in this specification.

[0099] For example, Figure 9 the computer device shown can execute step S102 through the layout acquisition module in the integrated circuit layout simulation device as shown in Figure 8 . The computer device can execute step S104 through the subsystem division module. The computer device can execute step S106 through the simulation module.

[0100] In one embodiment, a computer device is proposed. The computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented:

[0101] Step S102, obtaining a plurality of integrated circuit layouts and connection relationships, where the connection relationships are the connection relationships between integrated layouts and the connection relationships inside the integrated board layout;

[0102] Step S104, dividing the plurality of integrated circuit layouts into a plurality of subsystems according to the connection relationships;

[0103] Step S106, performing excitation simulation on the plurality of subsystems.

[0104] In one embodiment, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the processor is caused to execute the following steps:

[0105] Step S102, obtaining a plurality of integrated circuit layouts and connection relationships, where the connection relationships are the connection relationships between integrated layouts and the connection relationships inside the integrated circuit layouts;

[0106] Step S104: Divide the plurality of integrated circuit layouts into a plurality of subsystems according to the connection relationship;

[0107] Step S106: Perform excitation simulation on the plurality of subsystems.

[0108] It should be understood that although the steps in the flowcharts of the embodiments of the present invention are shown sequentially according to the indication of the arrows, these steps do not necessarily need to be executed sequentially according to the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in each embodiment may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be executed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages does not necessarily need to be sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0109] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0110] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0111] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention shall be subject to the appended claims.

Claims

1. An integrated circuit layout simulation method, the simulation method comprises: Obtaining a plurality of integrated circuit layouts and connection relationships, where the connection relationships are the connection relationships between integrated layouts and the connection relationships inside the integrated circuit layout; Dividing the plurality of integrated circuit layouts into a plurality of subsystems according to the connection relationships; Performing excitation simulation on the plurality of subsystems; The step of dividing the plurality of integrated circuit layouts into a plurality of subsystems according to the connection relationships includes: Confirming an optimal subsystem division scheme for the plurality of integrated circuit layouts, where the optimal subsystem division scheme is the division scheme with the highest calculation efficiency when performing finite element excitation simulation calculation; Dividing the plurality of integrated circuit layouts into a plurality of subsystems according to the optimal subsystem division scheme; The step of confirming the optimal way to divide the subsystems of the plurality of integrated circuit layouts includes: Enumerating all subsystem division schemes according to a preset division method; Calculating the finite element first simulation time corresponding to each division scheme among all the subsystem division schemes; Selecting the division scheme with the shortest finite element first simulation time as the optimal division scheme; The preset division methods include: Dividing according to the interconnection structure between integrated circuit layouts; Dividing according to the via connections between integrated circuit layout layers; Dividing according to the traces within the integrated circuit layout layer.

2. The simulation method according to claim 1, wherein, The step of calculating the finite element first simulation time corresponding to each division scheme among all the subsystem division schemes includes: Confirming the division scheme for which the first simulation time is to be calculated as the target division scheme; Calculating the finite element second simulation time of each subsystem in the target division scheme; Summing up the finite element second calculation times of each subsystem to generate the first simulation time.

3. The simulation method according to claim 2, wherein, The step of calculating the finite element second simulation time of each subsystem in the target division scheme includes: Determining the number of internal nodes and external nodes of the subsystem for which the second simulation time is to be calculated, where the internal nodes and external nodes are points or regions serving as finite element simulation mesh subdivision nodes; Calculating the third simulation time according to the number of internal nodes, where the third simulation time is the time required for sparse matrix equation matrix reordering and numerical decomposition; Calculating the fourth simulation time according to the number of internal nodes and external nodes, where the fourth simulation time is the time required for solving the right - hand side term of the sparse matrix equation; Summing up the third simulation time and the fourth simulation time to generate the second simulation time; wherein, the sparse matrix equation is the matrix equation generated during the finite element excitation simulation process.

4. The simulation method according to claim 1, wherein, The steps after dividing the plurality of integrated circuit layouts into a plurality of subsystems include: Performing mesh subdivision on the plurality of subsystems and retaining the mesh subdivision nodes.

5. The simulation method according to claim 1, wherein, The steps before performing excitation simulation on the plurality of subsystems include: Performing finite element solution on each subsystem to correspondingly generate a plurality of subsystem impedance networks; Cascade the impedance networks of the several subsystems to generate a complete simulation model; Perform excitation simulation on the simulation model.

6. A computer device, characterized in that, it includes a memory and a processor, and a computer program is stored in the memory. When the computer program is executed by the processor, the processor executes the steps of the simulation method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that, a computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the processor executes the steps of the simulation method according to any one of claims 1 to 5.

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