Memory management method, memory storage device, and memory controller

Abstract

The present invention provides a memory management method, a memory storage device, and a memory controller. The method includes: performing bad block handling on a first physical unit and suspending the use of the first physical unit; after performing the bad block handling on the first physical unit and after a preset time, performing a read detection on the first physical unit; and in response to the first physical unit passing the read detection, resuming the use of the first physical unit. Thereby, a balance can be achieved between the reliability and the device performance of the memory module.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and more particularly to a memory management method, a memory storage device, and a memory controller. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, flash memory continues to evolve towards smaller size and larger capacity. However, smaller memory cells and more memory bits are accompanied by a reduction in the maximum number of write / erase cycles of the memory cells and / or a decrease in the number of available physical blocks. These adverse factors may lead to a shortened service life of flash memory. In addition, most of the flash memories on the market currently support bad block management technology. When the bit error rate of a specific physical block in the flash memory is too high, the data cannot be read, the data cannot be restored, and / or the number of read / write cycles is too high, this physical block may be marked as a bad block and permanently disabled to avoid affecting the reliability of the entire flash memory. However, over time, the above bad block management technology will also cause the number of available physical blocks in the flash memory to continuously decrease, thereby affecting the device performance and durability of the flash memory. Summary of the Invention

[0003] The present invention provides a memory management method, a memory storage device, and a memory controller, which can recycle eligible bad blocks to improve the above problems.

[0004] An embodiment of the present invention provides a memory management method for a memory module. The memory module includes a plurality of physical units, and the memory management method includes: performing bad block handling on a first physical unit among the plurality of physical units and suspending the use of the first physical unit; performing a read detection on the first physical unit after performing the bad block handling on the first physical unit and after a preset time; and resuming the use of the first physical unit in response to the first physical unit passing the read detection.

[0005] Another embodiment of the present invention provides a memory storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory module includes a plurality of physical units. The memory controller is connected to the connection interface and the memory module. The memory controller is configured to: perform bad block handling on a first physical unit among the plurality of physical units and suspend the use of the first physical unit; perform a read detection on the first physical unit after performing the bad block handling on the first physical unit and after a preset time; and resuming the use of the first physical unit in response to the first physical unit passing the read detection.

[0006] An embodiment of the present invention further provides a memory controller, which includes a host interface, a memory interface, and a memory control circuit. The host interface is used to connect to a host system. The memory interface is used to connect to a memory module. The memory module includes a plurality of physical units. The memory control circuit is connected to the host interface and the memory interface. The memory control circuit is configured to: perform bad block handling on a first physical unit among the plurality of physical units and suspend using the first physical unit; perform a read detection on the first physical unit after performing the bad block handling on the first physical unit and after a preset time; and in response to the first physical unit passing the read detection, resume using the first physical unit.

[0007] Based on the above, after performing the bad block handling on the first physical unit and after a preset time, a read detection can be performed on the first physical unit. In response to the first physical unit passing the read detection, the first physical unit can be resumed for use. By recycling eligible bad blocks, a balance can be achieved between the reliability of the memory module and the device performance (and the durability of the memory module). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a memory storage device shown according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of a preset read voltage level shown according to an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of a preset read voltage level and an optimal read voltage level shown according to an embodiment of the present invention;

[0013] Figure 6 is a schematic diagram of a soft decision read voltage level shown according to an embodiment of the present invention;

[0014] Figure 7 is a flowchart of a memory management method shown according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 is a schematic diagram of a memory storage device shown according to an embodiment of the present invention. Please refer to Figure 1 , the memory storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 can be any type of computer system. For example. The host system 11 can be various electronic systems such as a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, a digital camera, etc. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 can include a solid state drive, a USB flash drive, a memory card or other types of non-volatile storage devices. The host system 11 can be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express), a Universal Serial Bus (USB) or other types of connection interfaces. Therefore, the host system 11 can store data to the memory storage device 12 and / or read data from the memory storage device 12.

[0017] The memory storage device 12 can include a connection interface 121, a memory module 122 and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 can support connection interface standards such as SATA, PCI Express or USB. The memory storage device 12 can communicate with the host system 11 via the connection interface 121.

[0018] The memory module 122 is used to store data. The memory module 122 can include a rewritable non-volatile memory module. The memory module 122 includes a memory cell array. The memory cells in the memory module 122 store data in the form of voltage. For example, the memory module 122 can include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module or other memory modules with similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be used to control the memory storage device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 to perform data access and data management. For example, the memory controller 123 can include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices, or a combination of these devices.

[0020] In one embodiment, the memory controller 123 is also referred to as a flash memory controller. In one embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 can receive an instruction sequence from the memory controller 123 and execute writing, reading, and erasing of data on the storage units in the memory module 122 according to this instruction sequence.

[0021] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 is responsible for the overall or partial operation of the memory storage device 12. The memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. In one embodiment, the memory control circuit 23 can also be regarded as the control core of the memory controller 123. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 further includes a decoding circuit 24. The decoding circuit 24 is connected to the memory control circuit 23 and is used to perform encoding and decoding of data. For example, the decoding circuit 24 can support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc.

[0024] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention. Please refer to Figures 1 to 3 As shown, the memory module 122 includes a plurality of physical units 301(1) to 301(C). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely. For example, a physical unit can include one or more physical blocks. Each physical block can include a plurality of physical programming units. A physical programming unit can include one or more physical pages. The plurality of memory cells in a physical programming unit can be programmed simultaneously to store data. In addition, all the memory cells in a physical block can be erased simultaneously.

[0025] In one embodiment, the physical units 301(1) to 301(A) and 301(A + 1) to 301(B) in the memory module 122 can be respectively divided into a data area 31 and a spare area 32. The physical units 301(1) to 301(A) in the data area 31 store data (also called user data) from the host system 11. The physical units 301(A + 1) to 301(B) in the spare area 32 do not store valid data.

[0026] In one embodiment, when there is new data from the host system 11 that needs to be stored, one or more physical units in the spare area 32 are selected and used to store this new data. The physical units in the spare area 32 that are used to store data can be divided into the data area 31.

[0027] In one embodiment, the memory control circuit 23 can configure a plurality of logical units 302(1) to 302(D) to map the physical units in the data area 31. For example, a logical unit can be composed of one or more logical addresses. The mapping relationship between the logical unit and the physical unit can be recorded in the logical-to-physical mapping table. When receiving an access instruction from the host system 11, the memory control circuit 23 can access the physical units in the data area 31 according to the corresponding logical-to-physical mapping table.

[0028] In one embodiment, if a certain physical unit is currently mapped by a certain logical unit, it means that valid data is stored in this physical unit. However, if a certain physical unit is not currently mapped by any logical unit, it means that no valid data is stored in this physical unit. In one embodiment, the physical units that do not store valid data can be reallocated to the idle area 32.

[0029] In one embodiment, the physical units 301(B + 1) to 301(C) in the memory module 122 can be allocated to the bad block handling area 33. The physical units in the bad block handling area 33 can be marked as bad blocks and will not be used to store data (i.e., user data) from the host system 11. In other words, the bad block handling area 33 is similar to an isolation area for damaged physical units (i.e., bad blocks) in the memory module 122.

[0030] In one embodiment, the memory control circuit 23 can continuously detect the usage status of each physical unit in the data area 31 and the idle area 32. In response to a certain physical unit (also referred to as the first physical unit) in the data area 31 or the idle area 32 meeting the condition of being determined as a bad block, the memory control circuit 23 can mark the first physical unit as a bad block and perform bad block handling on the first physical unit. For example, the memory control circuit 23 can add the first physical unit marked as a bad block to the bad block handling area 33 and suspend the use of the first physical unit. For example, in the operation of marking the first physical unit as a bad block, the memory control circuit 23 can add identification information such as the number and / or physical address of the first physical unit to the bad block management table. The bad block management table can be used to record the identification information of each physical unit in the bad block handling area 33.

[0031] In one embodiment, after performing the bad block handling on the first physical unit and after a preset period of time, the memory control circuit 23 can perform a read detection on the first physical unit. The memory control circuit 23 can determine whether the first physical unit passes the read detection according to the detection result. In one embodiment, in response to the first physical unit failing the read detection, the memory control circuit 23 can continuously retain the first physical block in the bad block handling area 33 and not remove the identification information of the first physical block from the bad block management table.

[0032] In one embodiment, in response to the first physical unit passing the read detection, the memory control circuit 23 may resume using the first physical unit. For example, in response to the first physical unit passing the read detection, the memory control circuit 23 may reclaim the first physical block from the bad block disposal area 33 and re-add the reclaimed first physical block to the idle area 32 to wait to be reused. In addition, in response to the first physical unit passing the read detection, the memory control circuit 23 may remove the identification information of the first physical block from the bad block management table.

[0033] In one embodiment, when reading data from the first physical unit in the data area 31, the decoding circuit 24 may be used to decode the read data (also referred to as the first data). If the decoding circuit 24 still fails to successfully decode the first data after performing decoding on the first data using one or more decoding modes (for example, unable to successfully correct all errors in the first data), the memory control circuit 23 may determine that the first physical unit meets the condition for being determined as a bad block. Conversely, if the first data can be successfully decoded in the one or more decoding modes, the memory control circuit 23 may determine that the first physical unit does not meet the condition for being determined as a bad block.

[0034] In one embodiment, the decoding mode includes at least one of a hard decoding mode for a single frame, a soft decoding mode for a single frame, and a multi-frame decoding mode across frames. The data of one frame may include the data stored in a single physical page. The data of multiple frames may include the data stored in multiple physical pages.

[0035] In one embodiment, in the hard decoding mode for a single frame, the memory control circuit 23 may instruct the memory module 122 to read data from a certain physical page of the first physical unit using a certain read voltage level (also referred to as the first hard decision read voltage level) and instruct the decoding circuit 24 to perform hard decoding for a single frame on this data. If the hard decoding for a single frame fails, the memory control circuit 23 may instruct the memory module 122 to read the data again from the physical page using another read voltage level (also referred to as the second hard decision read voltage level) and instruct the decoding circuit 24 to perform hard decoding for a single frame on this data again until the decoding is successful or the number of retries exceeds the retry threshold value. The voltage value of the first hard decision read voltage level is different from the voltage value of the second hard decision read voltage level. The relevant information of the first hard decision read voltage level and the second hard decision read voltage level may be recorded in the retry table and can be queried in the hard decoding mode for a single frame. In one embodiment, in response to the hard decoding mode for a single frame failing to successfully decode the data, the memory control circuit 23 may enter the soft decoding mode for a single frame.

[0036] In one embodiment, in the soft decoding mode of a single frame, the memory control circuit 23 may instruct the memory module 122 to perform multiple reads on the physical page using multiple read voltage levels (also referred to as soft decision read voltage levels) to obtain soft information corresponding to the physical page. Then, the memory control circuit 23 may instruct the decoding circuit 24 to perform soft decoding of the single frame on the data read from the physical page according to the soft information. In one embodiment, the soft information may include or be used to determine reliability information such as Log Likelihood Ratio (LLR).

[0037] In one embodiment, compared with the hard decoding mode of a single frame, in the soft decoding mode of a single frame, the decoding circuit 24 may improve the decoding success rate of the data read from the physical page according to the soft information. In one embodiment, in response to the fact that the soft decoding mode of a single frame still fails to successfully decode the data read from the physical page, the memory control circuit 23 may enter the multi-frame decoding mode across frames.

[0038] In one embodiment, in the multi-frame decoding mode across frames, the memory control circuit 23 may instruct the memory module 122 to read the data in multiple frames from multiple physical pages including the physical page. Then, the memory control circuit 23 may instruct the decoding circuit 24 to perform multi-frame decoding across frames on the data read from the physical page according to the logical relationship between the data in the multiple frames. Compared with the hard decoding and soft decoding of a single frame, the multi-frame decoding across frames can provide more decoding auxiliary information to the decoding circuit 24 in a cross-frame manner to further improve the decoding success rate of the decoding circuit 24. In one embodiment, the multi-frame decoding across frames is also referred to as redundant arrays of independent disks (RAID) decoding.

[0039] In one embodiment, the memory control circuit 23 may instruct the decoding circuit 24 to decode the data read from the first physical unit one by one in the hard decoding mode of a single frame, the soft decoding mode of a single frame, and the multi-frame decoding mode across frames. If the hard decoding mode of a single frame, the soft decoding mode of a single frame, and the multi-frame decoding mode across frames all fail to successfully decode the data, the memory control circuit 23 may determine that the first physical unit meets the conditions for being determined as a bad block. On the contrary, if the first data can be successfully decoded in at least one of the hard decoding mode of a single frame, the soft decoding mode of a single frame, and the multi-frame decoding mode across frames, the memory control circuit 23 may determine that the first physical unit does not meet the conditions for being determined as a bad block. In one embodiment, the memory control circuit 23 may also refer to other judgment conditions to determine whether the first physical unit is a bad block, which is not limited in the present invention.

[0040] In one embodiment, the memory control circuit 23 may record the physical address information of the available physical units 301(1) to 301(A) and 301(A + 1) to 301(B) in the data area 31 and the idle area 32 respectively in the mapping management table. Then, the memory control circuit 23 may query this mapping management table to use healthy physical units. For example, the mapping management table may include a logical-to-physical mapping table. On the other hand, the memory control circuit 23 may remove the physical address information of the physical units 301(B + 1) to 301(C) marked as bad blocks from the mapping management table to avoid using physical units in poor health states.

[0041] In one embodiment, in the bad block handling of the first physical unit, the memory control circuit 23 may copy the remaining readable data (i.e., data that can be successfully decoded) in the first physical unit to other physical units for storage. At the same time, the memory control circuit 23 may remove the physical address information of the first physical unit from the mapping management table. After copying the remaining readable data in the first physical unit to other physical units for storage, the memory control circuit 23 may instruct the memory module 122 to erase the first physical unit. After erasing the first physical unit, the memory control circuit 23 may instruct the memory module 122 to store verification data in the erased first physical unit. The verification data may include any combination of designed bit values. In one embodiment, the verification data is also referred to as redundant data. In addition, in the bad block handling of the first physical unit, the memory control circuit 23 may also record auxiliary information such as the reason for which the first physical unit is determined to be a bad block and the timestamp when it is determined to be a bad block in the bad block management table for future query.

[0042] In one embodiment, in response to the first physical unit passing the read detection, the memory control circuit 23 may add the physical address information of the first physical unit back to the mapping management table. Then, the memory control circuit 23 can resume the use of the first physical unit based on the mapping management table.

[0043] In one embodiment, after the bad block disposal of the first physical unit is completed, the memory control circuit 23 may start a counter. The count value of the counter may reflect the length of the placement time or idle time elapsed after the bad block disposal is performed on the first physical unit. In one embodiment, the memory control circuit 23 may determine whether the placement time or idle time after the bad block disposal is performed on the first physical unit has reached a preset time according to the count value. For example, the preset time may be 24 hours or other time lengths, which are not limited in the present invention. In response to the placement time or idle time after the bad block disposal is performed on the first physical unit having reached the preset time, indicating that the cumulative storage time of the verification data in the first physical unit has exceeded the preset time, the memory control circuit 23 may perform the read detection on the first physical unit. Alternatively, in one embodiment, the memory control circuit 23 may also determine whether the placement time or idle time after the bad block disposal is performed on the first physical unit has reached the preset time according to the time stamp corresponding to the first physical unit in the bad block management table, which is not limited in the present invention.

[0044] It should be noted that, in one embodiment, if the placement time or idle time does not reach the preset time, the memory control circuit 23 may prohibit specific or any access behavior to the first physical unit. Thereby, it is possible to avoid the subsequent read detection of the first physical unit being inaccurate due to additional access behavior to the first physical unit that is suspended from use.

[0045] In one embodiment, during the read detection, the memory control circuit 23 may instruct the memory module 122 to read data from the first physical unit. For example, the data read includes the verification data stored in the first physical unit. The memory control circuit 23 may instruct the decoding circuit 24 to decode the data read (i.e., the verification data). Then, the memory control circuit 23 may determine whether the first physical unit passes the read detection according to the decoding result.

[0046] In one embodiment, if the decoding result reflects that the verification data read can be successfully decoded, the memory control circuit 23 may directly determine that the first physical unit passes the read detection. In another embodiment, the memory control circuit 23 may determine whether the first physical unit passes the read detection according to other rules.

[0047] In one embodiment, the memory control circuit 23 may obtain an error bit evaluation value corresponding to the first physical unit according to the decoding result of the decoding circuit 24 for the verification data. The error bit evaluation value may reflect the distribution or statistical condition of errors in the verification data read from the first physical unit based on a preset read voltage level in the first physical unit. The memory control circuit 23 may determine whether the first physical unit passes the read detection according to the error bit evaluation value. In one embodiment, the error bit evaluation value may reflect and be positively correlated with the bit error rate of the verification data read from each physical page in the first physical unit based on the preset read voltage level. In one embodiment, the error bit evaluation value may reflect the total number of error bits in the verification data read from each physical page in the first physical unit based on the preset read voltage level and / or the average value of the total number.

[0048] In one embodiment, the memory control circuit 23 may determine whether the error bit evaluation value is greater than a threshold value (also referred to as a first threshold value). In one embodiment, in response to the error bit evaluation value being greater than the first threshold value, the memory control circuit 23 may determine that the first physical unit fails the read detection. In one embodiment, in response to the error bit evaluation value not being greater than the first threshold value, the memory control circuit 23 may determine that the first physical unit passes at least a part of the read detection.

[0049] Figure 4 is a schematic diagram of the preset read voltage level shown in the embodiment of the present invention. Please refer to Figure 4 , assuming that the threshold voltage distribution of the memory cells in one or more physical pages in the first physical unit includes states 401 and 402. State 401 represents the number of memory cells in the first physical unit that store a certain bit value (such as bit "0") or a certain combination of bit values in different voltage states. State 402 represents the number of memory cells in the first physical unit that store another bit value (such as bit "1") or another combination of bit values in different voltage states. The voltage level V(0) is used to represent the preset read voltage level. In particular, when the memory cells in the first physical unit are damaged, the relative position between the voltage level V(0) and the threshold voltage distribution will shift, as Figure 4 shown. The shift will cause errors in the data read from the memory cells using the voltage level V(0). It should be noted that Figure 4 the relative position between the voltage level V(0) and the threshold voltage distribution in is only for illustration and is not intended to limit the present invention.

[0050] In an embodiment, the memory control circuit 23 may obtain a read voltage offset value corresponding to the first physical cell according to the decoding result of the decoding circuit 24 on the verification data. For example, during the process of the decoding circuit 24 performing decoding on the read verification data, the memory control circuit 23 may perform a tracking operation of an optimal read voltage level through the decoding circuit 24. The memory control circuit 23 may determine an optimal read voltage level corresponding to the first physical cell according to the execution result of this tracking operation. The memory control circuit 23 may obtain the voltage difference between this optimal read voltage level and the preset read voltage level. In an embodiment, the read voltage offset value may reflect and / or be positively correlated with this voltage difference.

[0051] In an embodiment, the memory control circuit 23 may determine whether the read voltage offset value is greater than a threshold value (also referred to as the second threshold value). In an embodiment, in response to the read voltage offset value being greater than the second threshold value, the memory control circuit 23 may determine that the first physical cell fails the read detection. In an embodiment, in response to the read voltage offset value not being greater than the second threshold value, the memory control circuit 23 may determine that the first physical cell passes at least a part of the read detection.

[0052] Figure 5 is a schematic diagram of the preset read voltage level and the optimal read voltage level shown according to an embodiment of the present invention. Please refer to Figure 5 , assuming that the threshold voltage distributions of the memory cells in one or more physical pages in the first physical cell include states 401 and 402. The voltage level V(0) is used to represent the preset read voltage level. The voltage level V(1) is used to represent the optimal read voltage level. Compared with the preset read voltage level (i.e., the voltage level V(0)), the optimal read voltage level (i.e., the voltage level V(1)) is closer to the voltage position with the least number of overlaps of the memory cells between states 401 and 402. In an embodiment, the read voltage offset value may reflect or be positively correlated with the voltage difference between the voltage levels V(0) and V(1). It should be noted that Figure 5 the relative positions of the voltage levels V(0) and V(1) and the threshold voltage distribution in are only schematic and are not used to limit the present invention.

[0053] In an embodiment, the memory control circuit 23 may obtain the number of bit flips detected when reading at least some of the memory cells in the first physical cell based on a plurality of soft decision read voltage levels according to the decoding result of the decoding circuit 24 on the verification data. In an embodiment, the number of bit flips may reflect and / or be positively correlated with the number of times the read bits are flipped (i.e., changed) when sequentially using the plurality of soft decision read voltage levels to read data from the memory cells.

[0054] In one embodiment, the memory control circuit 23 may determine whether the number of bit flips is greater than a threshold value (also referred to as the third threshold value). In one embodiment, in response to the number of counted bit flips being greater than the third threshold value, the memory control circuit 23 may determine that the first physical unit fails the read detection. In one embodiment, in response to the number of counted bit flips not being greater than the third threshold value, the memory control circuit 23 may determine that the first physical unit passes at least a part of the read detection.

[0055] Figure 6 is a schematic diagram of soft decision read voltage levels shown according to an embodiment of the present invention. Please refer to Figure 6 , assuming that the threshold voltage distributions of the memory cells in one or more physical pages in the first physical unit include states 401 and 402. During the process of the decoding circuit 24 performing decoding on the verification data, multiple soft decision read voltage levels V(S1) to V(S5) may be used to read the memory cells to obtain soft information. Taking the soft decision read voltage levels V(S1) and V(S2) as an example, assuming that the threshold voltage of a certain memory cell is between the soft decision read voltage levels V(S1) and V(S2), after sequentially using the soft decision read voltage levels V(S1) and V(S2) to read this memory cell, the bit data read from this memory cell will flip (for example, from bit "0" to bit "1" or from bit "1" to bit "0"). In one embodiment, the number of bit flips may reflect the total number of bit flips that occur when sequentially using the soft decision read voltage levels V(S1) to V(S5) to read data from the memory cells. It should be noted that Figure 6 the relative positions between the soft decision read voltage levels V(S1) to V(S5) and the threshold voltage distribution in

[0056] In one embodiment, only after passing all of the read detections (for example, the error bit evaluation value is not greater than the first threshold value, the read voltage offset value is not greater than the second threshold value, and the number of counted bit flips is not greater than the third threshold value), will the memory control circuit 23 determine that the first physical unit passes the read detection. However, the relevant decision mechanism can still be adjusted according to practical requirements, and the present invention does not limit it. For example, in one embodiment, as long as a part of the read detections is passed, the memory control circuit 23 can determine that the first physical unit passes the read detection.

[0057] In one embodiment, after determining that the first physical unit passes the read detection, the first physical unit may be recycled and added back to Figure 3in the idle area 32 to wait to be used next time. However, if the memory control circuit 23 determines that the first physical unit fails the read detection, the first physical unit will continue to be marked as a bad block and be maintained in Figure 3 the bad block disposal area 33.

[0058] Figure 7 is a flowchart of a memory management method according to an embodiment of the present invention. Please refer to Figure 7 , in step S701, perform bad block disposal on the first physical unit and suspend the use of the first physical unit. In step S702, after performing the bad block disposal on the first physical unit and after a preset time, perform a read detection on the first physical unit. In step S703, determine whether the first physical unit passes the read detection. In response to the first physical unit passing the read detection, in step S704, resume the use of the first physical unit. However, if the first physical unit fails the read detection, continue to suspend the use of the first physical unit and return to step S701 to perform bad block disposal on the remaining eligible physical units.

[0059] In summary, after performing bad block disposal on the first physical unit and after a preset time, a read detection can be performed on the first physical unit. In response to the first physical unit passing the read detection, the first physical unit can be recycled and resume use. By recycling and reusing eligible bad blocks, a balance can be achieved between the reliability of the memory module and the device performance (and the durability of the memory module).

[0060] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For a memory module, the memory module includes a plurality of physical units, and the memory management method includes: Performing bad block handling on a first physical unit among the plurality of physical units and suspending the use of the first physical unit; After performing the bad block handling on the first physical unit, starting a counter, and a count value of the counter reflects a time length elapsed after the bad block handling is performed on the first physical unit; If it is determined that the time length reaches a preset time, performing a read detection on the first physical unit; and In response to the first physical unit passing the read detection, resuming the use of the first physical unit, wherein the bad block handling includes: Copying the remaining readable data in the first physical unit to other physical units for storage; Removing the physical address information of the first physical unit from a mapping management table; Instructing the memory module to erase the first physical unit; and Instructing the memory module to store verification data into the erased first physical unit.

2. The memory management method according to claim 1, further including: In response to the first physical unit passing the read detection, adding the physical address information of the first physical unit back to the mapping management table.

3. The memory management method according to claim 1, wherein the read detection includes: Instructing the memory module to read data from the first physical unit; Decoding the read data; And Judging whether the first physical unit passes the read detection according to a decoding result.

4. The memory management method according to claim 3, wherein the step of judging whether the first physical unit passes the read detection according to the decoding result includes: Obtaining an error bit evaluation value corresponding to the first physical unit according to the decoding result; And In response to the error bit evaluation value being greater than a first threshold value, determining that the first physical unit fails the read detection.

5. The memory management method according to claim 4, wherein the step of judging whether the first physical unit passes the read detection according to the decoding result further includes: Obtaining a read voltage offset value corresponding to the first physical unit according to the decoding result; And In response to the read voltage offset value being greater than a second threshold value, determining that the first physical unit fails the read detection.

6. The memory management method according to claim 5, wherein the step of judging whether the first physical unit passes the read detection according to the decoding result further includes: Obtaining a number of bit flips detected when reading at least part of storage units in the first physical unit based on a plurality of soft decision read voltage levels according to the decoding result; In response to the number of bit flips being greater than a third threshold value, determining that the first physical unit fails the read detection; And In response to the number of bit flips not being greater than the third threshold value, determining that the first physical unit passes the read detection.

7. A memory storage device, characterized in that, Including: A connection interface for connecting to a host system; A memory module including a plurality of physical units; And A memory controller, connected to the connection interface and the memory module, wherein the memory controller is configured to: Perform bad block handling on a first physical unit among the plurality of physical units and suspend the use of the first physical unit; After performing the bad block handling on the first physical unit, start a counter, and the count value of the counter reflects the length of time elapsed after the bad block handling is performed on the first physical unit; If it is determined that the length of time reaches a preset time, perform a read detection on the first physical unit; And In response to the first physical unit passing the read detection, resume the use of the first physical unit, wherein the bad block handling includes: Copying the remaining readable data in the first physical unit to other physical units for storage; removing the physical address information of the first physical unit from the mapping management table; Instructing the memory module to erase the first physical unit; and Instructing the memory module to store verification data into the erased first physical unit.

8. The memory storage device according to claim 7, wherein the memory controller is further configured to: In response to the first physical unit passing the read detection, add the physical address information of the first physical unit back to the mapping management table.

9. The memory storage device according to claim 7, wherein the read detection includes: Instructing the memory module to read data from the first physical unit; Decoding the read data; And Judging whether the first physical unit passes the read detection according to the decoding result.

10. The memory storage device according to claim 9, wherein the operation of judging whether the first physical unit passes the read detection according to the decoding result includes: Obtaining an error bit evaluation value corresponding to the first physical unit according to the decoding result; And In response to the error bit evaluation value being greater than a first threshold value, determining that the first physical unit fails the read detection.

11. The memory storage device according to claim 10, wherein the operation of judging whether the first physical unit passes the read detection according to the decoding result further includes: Obtaining a read voltage offset value corresponding to the first physical unit according to the decoding result; And In response to the read voltage offset value being greater than a second threshold value, determining that the first physical unit fails the read detection.

12. The memory storage device according to claim 11, wherein the operation of judging whether the first physical unit passes the read detection according to the decoding result further includes: Obtaining the number of bit flips detected when reading at least some of the memory cells in the first physical unit based on a plurality of soft decision read voltage levels according to the decoding result; In response to the number of bit flips being greater than a third threshold value, determining that the first physical unit fails the read detection; And In response to the number of bit flips not being greater than the third threshold value, determining that the first physical unit passes the read detection.

13. A memory controller, characterized in that, Comprising: A host interface, configured to connect to a host system; A memory interface for connecting to a memory module, the memory module including a plurality of physical units; and A memory control circuit connected to the host interface and the memory interface, wherein the memory control circuit is configured to: Perform bad block handling on a first physical unit among the plurality of physical units and suspend the use of the first physical unit; After performing the bad block handling on the first physical unit, start a counter, and the count value of the counter reflects the length of time elapsed after the first physical unit has been subjected to bad block handling; If it is determined that the length of time has reached a preset time, perform a read detection on the first physical unit; and In response to the first physical unit passing the read detection, resume the use of the first physical unit, wherein the bad block handling includes: Copying the remaining readable data in the first physical unit to other physical units for storage; removing the physical address information of the first physical unit from the mapping management table; Instructing the memory module to erase the first physical unit; and Instructing the memory module to store verification data into the erased first physical unit.

14. The memory controller according to claim 13, wherein the memory control circuit is further configured to: In response to the first physical unit passing the read detection, add the physical address information of the first physical unit back to the mapping management table.

15. The memory controller according to claim 13, wherein the memory controller further includes a decoding circuit, and the read detection includes: Instructing the memory module to read data from the first physical unit; Instructing the decoding circuit to decode the read data; and Judging whether the first physical unit passes the read detection according to the decoding result.

16. The memory controller according to claim 15, wherein the operation of judging whether the first physical unit passes the read detection according to the decoding result includes: Obtaining an error bit evaluation value corresponding to the first physical unit according to the decoding result; and In response to the error bit evaluation value being greater than a first threshold value, determining that the first physical unit fails the read detection.

17. The memory controller according to claim 16, wherein the operation of judging whether the first physical unit passes the read detection according to the decoding result further includes: Obtaining a read voltage offset value corresponding to the first physical unit according to the decoding result; and In response to the read voltage offset value being greater than a second threshold value, determining that the first physical unit fails the read detection.

18. The memory controller according to claim 17, wherein the operation of judging whether the first physical unit passes the read detection according to the decoding result further includes: Obtaining the number of bit flips detected when reading at least some of the memory cells in the first physical unit based on a plurality of soft decision read voltage levels according to the decoding result; In response to the number of bit flips being greater than a third threshold value, determining that the first physical unit fails the read detection; and In response to the number of bit flips not being greater than the third threshold value, it is determined that the first entity unit passes the read detection.

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