A method of manufacturing a semiconductor structure

Abstract

The application provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate; forming a hard mask layer on the substrate; forming a photoresist layer on the hard mask layer; performing photoetching on the photoresist layer to form at least one first groove; the first groove penetrates through the photoresist layer; performing particle injection on at least one photoresist layer sidewall of the first groove; etching the hard mask layer to form at least one second groove; the second groove penetrates through the hard mask layer. Since the photoresist is modified by particle injection, the product generated and deposited on the hard mask layer when the photoresist is etched is reduced, the difference between the micro-etching degree of the pattern feature size in different directions is reduced, the required pattern feature size can be accurately obtained, and the performance of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Technology

[0002] With the continuous development of semiconductor technology, chip manufacturing processes are getting smaller and smaller. Currently, chips with processes such as 14nm, 10nm and 7nm have been developed. However, the existing 193nm DUV (Deep Ultraviolet) lithography technology cannot directly lithographically create the fine patterns required for chip manufacturing processes of 14nm and below.

[0003] The common practice is to miniaturize the feature size of a pattern through an etching process. However, during the miniaturization process, the degree of miniaturization of the feature size varies in different directions, which may prevent the desired feature size from being obtained. For example, in line end shrink (LES), the degree of miniaturization between the short sides of two adjacent trenches and the degree of miniaturization of the trench width may differ significantly. This may lead to misalignment of the formed vias and trenches, affecting the connection between the upper and lower metal layers and impacting device performance.

[0004] Therefore, how to accurately obtain the required graphic feature dimensions to improve device performance is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] To address the above technical problems, this application provides a method for manufacturing a semiconductor structure that can accurately obtain the required pattern feature dimensions and improve device performance.

[0006] This application provides a method for manufacturing a semiconductor structure, including:

[0007] Provide substrate;

[0008] A hard mask layer is formed on the substrate;

[0009] A photoresist layer is formed on the hard mask layer;

[0010] Photolithography is used to form at least one first trench in the photoresist layer; the first trench penetrates the photoresist layer.

[0011] Particles are injected into at least one sidewall of the photoresist layer in the first trench;

[0012] The hard mask layer is etched to form at least one second trench; the second trench penetrates the hard mask layer.

[0013] Optionally, the particles include boron ions, free radicals, or neutral atoms.

[0014] Optionally, the step of particle implantation into at least one photoresist layer sidewall of the first trench includes:

[0015] The first trench is a cuboid; particles are injected into the two opposite photoresist layer sidewalls of the first trench.

[0016] Optionally, the step of injecting particles into the two opposing photoresist layer sidewalls of the first trench includes:

[0017] Particles are injected into the photoresist layer sidewalls on two opposite sides of the first trench; the sidewalls are faces composed of the width and height of the cuboid; the width of the cuboid is the side shorter than the length of the cuboid.

[0018] Optionally, the step of particle implantation into the photoresist layer sidewalls on two opposite sides of the first trench includes:

[0019] The first particle injection is performed on the photoresist layer sidewalls on two opposite sides of the first trench; the angle of the first particle injection is 15-30 degrees.

[0020] A second particle implantation is performed on the photoresist layer sidewalls of the two opposite sides of the first trench; the angle of the second particle implantation is 150-165 degrees; the angle is the size of the angle formed with the direction perpendicular to the substrate; the energy of the first particle implantation is 50-150 eV.

[0021] Optionally, the etching is dry etching; the etching gas is a fluoride gas.

[0022] Optionally, the thickness of the substrate is 1500-2500 Å; the thickness of the hard mask layer is 150-500 Å; and the thickness of the photoresist layer is 600-900 Å.

[0023] Optionally, the hard mask layer includes:

[0024] Silicon oxide-based hard mask layers or advanced patterned film layers.

[0025] Optionally, the substrate includes an organic mask layer.

[0026] Optionally, the organic mask layer comprises a nitrogen-doped silicon carbide layer, a titanium nitride layer, a nitrogen-free antireflective coating, and a carbon coating stacked sequentially; the carbon coating is located on the side close to the hard mask layer.

[0027] Compared with the prior art, this application has at least the following advantages:

[0028] This application provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; forming a hard mask layer on the substrate; forming a photoresist layer on the hard mask layer; photolithographically forming at least one first trench through the photoresist layer; the first trench penetrating the photoresist layer; performing particle implantation on at least one sidewall of the photoresist layer of the first trench; and etching the hard mask layer to form at least one second trench through the hard mask layer. Because the photoresist is modified by particle implantation, the amount of material generated and deposited on the hard mask layer during etching is reduced, thereby reducing the difference in the degree of miniaturization of pattern feature sizes in different directions. This allows for accurate acquisition of the required pattern feature sizes, thereby improving device performance. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this application is shown;

[0031] Figure 2 This paper shows a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0032] Figure 3 This paper shows a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0033] Figure 4 A cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of this application is shown;

[0034] Figure 5 A cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of this application is shown;

[0035] Figure 6 A top view of a semiconductor structure provided in an embodiment of this application is shown;

[0036] Figure 7 This application illustrates an embodiment of a method along... Figure 6 A cross-sectional schematic diagram of a semiconductor structure in the 1D direction;

[0037] Figure 8 This application illustrates an embodiment of a method along... Figure 6 A cross-sectional schematic diagram of a semiconductor structure in the 2D direction;

[0038] Figure 9A top view showing the connection relationship between a semiconductor structure and a via provided in an embodiment of this application is shown;

[0039] Figure 10 A top view showing the connection relationship between the semiconductor structure and vias formed after etching the mask layer at this stage;

[0040] Figure 11 A dot plot showing the degree of miniaturization of the semiconductor structure formed after etching the mask layer at this stage, with respect to the feature sizes in different directions.

[0041] Figure 12 This illustration shows a schematic diagram of particle injection into a photoresist layer according to an embodiment of this application;

[0042] Figure 13 This illustration shows another schematic diagram of particle injection into a photoresist layer provided in an embodiment of this application;

[0043] Figure 14 This illustration shows a schematic diagram of the particle injection angle of a photoresist layer according to an embodiment of this application;

[0044] Figure 15 This illustration shows a top view of the connection relationship between a semiconductor structure formed by etching a mask layer after particle implantation of a photoresist layer and a via, according to an embodiment of this application.

[0045] Figure 16 This application illustrates an embodiment of a method along... Figure 15 A cross-sectional schematic diagram of a semiconductor structure in the 2D direction. Detailed Implementation

[0046] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0048] As described in the background section, with the continuous development of semiconductor technology, chip manufacturing processes are becoming smaller and smaller. Currently, chips with processes such as 14nm, 10nm, and 7nm have been developed. However, the existing 193nm DUV (Deep Ultraviolet) lithography technology cannot directly lithographically create the fine patterns required for chip manufacturing processes of 14nm and below.

[0049] The common practice is to miniaturize the feature size of a pattern through an etching process. However, during the miniaturization process, the degree of miniaturization of the feature size varies in different directions, which may prevent the desired feature size from being obtained. For example, in line end shrink (LES), the degree of miniaturization between the short sides of two adjacent trenches and the degree of miniaturization of the trench width may differ significantly. This may lead to misalignment of the formed vias and trenches, affecting the connection between the upper and lower metal layers and impacting device performance.

[0050] Therefore, how to accurately obtain the required graphic feature dimensions to improve device performance is a technical problem that needs to be solved in this field.

[0051] To address the aforementioned technical problems, this application provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate; forming a hard mask layer on the substrate; forming a photoresist layer on the hard mask layer; photolithographically forming at least one first trench through the photoresist layer; the first trench penetrating the photoresist layer; performing particle implantation on at least one sidewall of the photoresist layer in the first trench; and etching the hard mask layer to form at least one second trench through the hard mask layer. Because the photoresist is modified through particle implantation, the amount of material generated and deposited on the hard mask layer during etching is reduced, thereby reducing the difference in the degree of miniaturization of pattern features in different directions. This allows for accurate acquisition of the required pattern feature dimensions, thereby improving device performance.

[0052] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0053] Exemplary methods

[0054] See Figure 1 As shown in the figure, this is a method for manufacturing a semiconductor structure according to an embodiment of this application, including:

[0055] S101: Provides a substrate.

[0056] In this embodiment, substrate 1 can be an organic underlayer (ODL). Optionally, see... Figure 2 As shown, the organic mask layer may include, in sequence, a nitrogen-doped silicon carbide layer 11 (NDC), a titanium nitride layer 12 (TIN), a nitrogen-free anti-reflective coating 13 (NFDARC), and a carbon coating 14 (SOC). The carbon coating 14 is located on the side closest to the hard mask layer. Figure 2 (not shown in the image)

[0057] Optionally, the overall thickness of the substrate 1 can be 1500-2500 Å, and the substrate pattern can be filled using the spin-coated organic mask layer 1.

[0058] S102: A hard mask layer is formed on the substrate.

[0059] In the embodiments of this application, see Figure 3 As shown, a hard mask layer 2 can be formed on the substrate 1. The hard mask layer 2 can be SHB (SiO-based Hard Mask) or APF (Advanced patterning film).

[0060] Optionally, the thickness of the hard mask layer 2 can be 150-500 Å.

[0061] S103: A photoresist layer is formed on the hard mask layer.

[0062] S104: Photolithography is used to form at least one first trench in the photoresist layer; the first trench penetrates the photoresist layer.

[0063] In the embodiments of this application, see Figure 4 As shown, a photoresist layer 3 can be formed on the hard mask layer 2. Optionally, the thickness of the photoresist layer 3 is 600-900 Å. See [reference needed]. Figure 5 As shown, at least one first trench 4 can be formed by photolithography of the photoresist layer 3, and the first trench 4 penetrates the photoresist layer 3.

[0064] It should be noted that the number of first grooves is not specifically limited in this embodiment of the application, and can be set by those skilled in the art according to the actual situation.

[0065] Optionally, in a specific embodiment of this application, see [link to relevant documentation]. Figure 6 The image shown is a top view of a semiconductor structure provided in an embodiment of this application. The first trench 4 may include a first sub-trench 41 and a second sub-trench 42. The width of the first sub-trench 41 and the second sub-trench 42 formed by photolithography is 52 nm, i.e. Figure 6 The width in the 1D direction is 52nm, and the distance between the short sides of the first sub-trench 41 and the second sub-trench 42 is 52nm, that is... Figure 6 The width in the 2D direction is 52 nm. See [link / reference] Figure 7 The diagram shown is a cross-sectional structural schematic diagram along the 1D direction of an embodiment of this application. (See attached diagram.) Figure 8 The diagram shown is a schematic diagram of the cross-sectional structure along the 2D direction of an embodiment of this application.

[0066] S105: Particle injection is performed on at least one photoresist layer sidewall of the first trench.

[0067] S106: Etch the hard mask layer to form at least one second trench; the second trench penetrates the hard mask layer.

[0068] Currently, traditional methods for miniaturizing the feature size of semiconductor structures do not employ particle implantation to modify the photoresist layer. As a result, the degree of miniaturization varies in different directions during the miniaturization process, making it difficult to obtain the desired feature size.

[0069] For example, taking the fabrication of 64nm trenches using the 14nm technology node as an example, the trenches and vias within them form a multilayer metal interconnect. See [link to documentation]. Figure 9 As shown, the photolithographic photoresist layer 3 forms a first trench 4. The first trench 4 may include a first sub-trench 41 and a second sub-trench 42. Before etching, the width of the first sub-trench 41 and the second sub-trench 42 is 52nm, that is, the distance in the 1D direction is 52nm. The distance between the short sides of the first sub-trench 41 and the second sub-trench 42 is 52nm, that is, the distance in the 2D direction is 52nm. Figure 9 The dashed circle in the image shows a through hole located within the trench.

[0070] right Figure 9 The semiconductor structure shown is further etched and shrunk. At this point, the required feature size is such that the shrinkage changes in the 1D and 2D directions are equal after the semiconductor structure is shrunk. (See also...) Figure 10 The diagram shows a semiconductor structure without further etching and miniaturization after particle implantation. During etching, reactive products from the photoresist layer 3 accumulate on the hard mask layer 2. Therefore, after miniaturization etching of the hard mask layer 2, a second trench 6 is obtained. The second trench 6 can include a third sub-trench 61 and a fourth sub-trench 62. The width of the third sub-trench 61 and the fourth sub-trench 62 is 32 nm, i.e., the distance in the 1D direction is 32 nm. The distance between the short sides of the third sub-trench 61 and the fourth sub-trench 62 is 84 nm, i.e., the distance in the 2D direction is 84 nm. That is, the change in trench end shrinkage (LES) in the 1D direction is 52 - 32 = 20 nm, and the change in trench end shrinkage (LES) in the 2D direction is 84 - 52 = 32 nm. Clearly, the miniaturization degree in the 2D direction is higher than that in the 1D direction. When the difference in miniaturization becomes too great, vias will be located outside the trenches, resulting in increased contact resistance or even open circuit failure. Although computational lithography can improve some of the failures, its adjustable range is very narrow, making most failures unrepairable.

[0071] See Figure 11The figure shows the coordinate graph of the shrinkage variation of the tail end of different grooves in the 1D direction and the corresponding shrinkage variation of the tail end of different grooves in the 2D direction. As can be seen from the figure, the shrinkage degree in the 2D direction is higher than that in the 1D direction, which results in the inability to obtain the required feature size.

[0072] Therefore, in this embodiment of the application, in order to obtain the required feature size and reduce the variation in feature size during the etching and scaling process, see [reference needed]. Figure 12 As shown, at least one photoresist layer sidewall 5 of the first trench can be injected with particles.

[0073] Optionally, particle 5 may include boron ions, free radicals, or neutral atoms. Optionally, the first trench 4 may be a cuboid, and particle implantation is performed on the two opposite photoresist layer sidewalls 51 and 52 of the first trench 4, see [link to documentation]. Figure 13 As shown. Optionally, since the photoresist layer 3 of the first trench 4 has four sides, specifically, particles can be injected into the photoresist layer sidewalls of the two opposite sides 51 and 52 of the first trench 4; sides 51 and 52 are faces composed of the width and height of a cuboid; the width of the cuboid is the side shorter than the length of the cuboid.

[0074] Optionally, a first particle injection is performed on the photoresist layer sidewalls on two opposite sides of the first trench; the angle of the first particle injection is 15-30 degrees.

[0075] A second particle implantation is performed on the photoresist sidewalls of the two opposite sides of the first trench; the angle of the second particle implantation is 150-165 degrees; the angle is the size of the angle between the first particle implantation and the direction perpendicular to the substrate; the energy of the first particle implantation is 50-150 eV.

[0076] See Figure 14 As shown, ∠A is a diagram of the first and second particle injection angles, and region B in the diagram is the area where particles are injected.

[0077] Because the photoresist layer 3 was modified by particle injection, see [link / reference] Figure 15 As shown, etching the hard mask layer 2 forms at least one second trench 6; the second trench 6 penetrates the hard mask layer 2. Particle implantation modifies the photoresist layer 3, thereby reducing reactant accumulation caused by simultaneous etching of the photoresist layer 3 during the etching of the hard mask layer 2. With less reactant accumulated on the hard mask layer 2, the difference in feature size variation in different directions during the etching miniaturization process is reduced, thus allowing for accurate acquisition of the required feature size.

[0078] For example, for Figure 9The semiconductor structure shown is further miniaturized. At this point, the required feature size is such that the miniaturization changes in the 1D and 2D directions are equal. Since the photoresist layer 3 is modified using particle implantation, during the etching process, the modified photoresist layer 3 reduces the reaction products accumulated on the hard mask 2. Therefore, after miniaturization etching, see [reference needed]. Figure 15 As shown, a second trench 6 is obtained. The second trench 6 can include a third sub-trench 61 and a fourth sub-trench 62. The width of the third sub-trench 61 and the fourth sub-trench 62 is 32 nm, meaning the distance in the 1D direction is 32 nm. The distance between the short sides of the third sub-trench 61 and the fourth sub-trench 62 is 72 nm, meaning the distance in the 2D direction is 72 nm. Therefore, the change in trench end shrinkage (LES) in the 1D direction is 52 - 32 = 20 nm, and the change in trench end shrinkage (LES) in the 2D direction is 72 - 52 = 20 nm, meaning the degree of shrinkage in the 2D direction is equal to the degree of shrinkage in the 1D direction. This achieves our target requirement, preventing vias from being located outside the trench, thus improving device performance.

[0079] See Figure 16 The figure shows a cross-sectional view of the miniaturized semiconductor structure along the 2D direction. The dashed boxes in the figure represent the third and fourth sub-trenches obtained by etching the hard mask layer 2 without particle implantation modification of the photoresist layer 3. Compared with the third sub-trench 61 and fourth sub-trench 62 obtained by particle implantation modification of the photoresist layer 3 in the embodiment of this application, too much reaction product of etching the photoresist layer 3 is accumulated on the trench sidewalls, resulting in a higher degree of miniaturization. However, in the embodiment of this application, due to photoresist modification, the accumulation of reaction product on the trench sidewalls is reduced, and the situation where the via is located outside the trench will not occur, thus improving the performance of the device.

[0080] This application provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; forming a hard mask layer on the substrate; forming a photoresist layer on the hard mask layer; photolithographically forming at least one first trench through the photoresist layer; the first trench penetrating the photoresist layer; performing particle implantation on at least one sidewall of the photoresist layer of the first trench; and etching the hard mask layer to form at least one second trench through the hard mask layer. Because the photoresist is modified by particle implantation, the amount of material generated and deposited on the hard mask layer during etching is reduced, thereby reducing the difference in the degree of miniaturization of pattern feature sizes in different directions. This allows for accurate acquisition of the required pattern feature sizes, thereby improving device performance.

[0081] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0082] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A hard mask layer is formed on the substrate; A photoresist layer is formed on the hard mask layer; Photolithography forms at least one first trench in the photoresist layer; The first trench penetrates the photoresist layer; The first groove is a cuboid; Particles are implanted into the photoresist layer sidewalls on two opposite sides of the first trench; the sidewalls are faces composed of the width and height of the cuboid; the width of the cuboid is the side shorter than the length of the cuboid; by implanting particles into the photoresist layer sidewalls, the products generated by photoresist etching and deposited on the hard mask layer are reduced, thereby reducing the difference in the degree of miniaturization of pattern features in different directions. Etching the hard mask layer forms at least one second trench; The second trench penetrates the hard mask layer.

2. The method according to claim 1, characterized in that, The particles include: boron ions, free radicals, or neutral atoms.

3. The method according to claim 1, characterized in that, The step of injecting particles into the photoresist layer sidewalls on two opposite sides of the first trench includes: The first particle injection is performed on the photoresist layer sidewalls on two opposite sides of the first trench; the angle of the first particle injection is 15-30 degrees. A second particle implantation is performed on the photoresist layer sidewalls of the two opposite sides of the first trench; the angle of the second particle implantation is 150-165 degrees; the angle is the size of the angle formed with the direction perpendicular to the substrate; the energy of the first particle implantation is 50-150 eV.

4. The method according to any one of claims 1-3, characterized in that, The etching is a dry etching process; the etching gas is a fluoride gas.

5. The method according to any one of claims 1-3, characterized in that, The thickness of the substrate is 1500-2500 Å; the thickness of the hard mask layer is 150-500 Å; and the thickness of the photoresist layer is 600-900 Å.

6. The method according to any one of claims 1-3, characterized in that, The hard mask layer includes: Silicon oxide-based hard mask layers or advanced patterned film layers.

7. The method according to any one of claims 1-3, characterized in that, The substrate includes an organic mask layer.

8. The method according to claim 7, characterized in that, The organic mask layer comprises a nitrogen-doped silicon carbide layer, a titanium nitride layer, a nitrogen-free anti-reflective coating, and a carbon coating stacked sequentially; the carbon coating is located on the side close to the hard mask layer.

Images