Data definition cache for speculative and normal execution

Abstract

A cache system having a first cache, a second cache, a configurable data bit, and a logic circuit coupled to a processor to control the caches based on the configurable bit. When the configurable bit is in a first state, the logic circuit is configured to implement commands for accessing a memory system via the first cache when an execution type is of a first type and to implement commands for accessing the memory system via the second cache when the execution type is of a second type. When the configurable data bit is in a second state, the logic circuit is configured to implement commands for accessing the memory system via the second cache when the execution type is of the first type and to implement commands for accessing the memory system via the first cache when the execution type is of the second type.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 528,471, filed July 31, 2019, and titled “DATA DEFINED CACHES FOR SPECULATIVE AND NORMAL EXECUTIONS,” the entire disclosure of which is hereby incorporated by reference herein. TECHNICAL FIELD

[0003] At least some embodiments disclosed herein relate generally to cache architectures, and more particularly, but not by way of limitation, to cache architectures for main and speculative execution by computer processors. BACKGROUND

[0004] A cache is a memory component that stores data closer to a processor than main memory so that data stored in the cache can be accessed by the processor. Data can be stored in the cache due to an earlier computation or an earlier access to the data in main memory. A cache hit occurs when data requested by a processor using a memory address can be found in the cache, while a cache miss occurs when the data cannot be found in the cache.

[0005] Generally, a cache is a memory that holds data recently used by a processor. Memory blocks placed in the cache are correspondingly limited to cache lines by placement policies. There are three commonly known placement policies: direct-mapped, fully-associative, and set-associative. In a direct-mapped cache structure, the cache is organized into multiple sets with a single cache line per set. Based on the address of a memory block, the memory block can only occupy a single cache line. For a direct-mapped cache, the cache can be designed as an (n*1) column matrix. In a fully-associative cache structure, the cache is organized into a single cache set with multiple cache lines. A memory block can occupy any of the cache lines in the single cache set. A cache with a fully-associative structure can be designed as a (1*m) row matrix.

[0006] Set-associative caches are intermediate designs for structures that are intermediate between directly mapped caches and fully associative caches. Set-associative caches can be designed as (n*m) matrices, where neither n nor m is 1. The cache is partitioned into n cache sets, and each set contains m cache lines. Memory blocks can be mapped to a cache set, and then placed into any cache line of the set. When considering the hierarchy of levels of set-associativity, set-associative caches can include a range of caches from directly mapped to fully associative. For example, a directly mapped cache can also be described as a one-way set-associative cache, and a fully associative cache with m blocks can be described as an m-way set-associative cache. Directly mapped caches, two-way set-associative caches, and four-way set-associative caches are common in cache systems.

[0007] Speculative execution is a computing technique in which a processor executes one or more instructions based on a speculation that, under some conditions, the instructions need to be executed before a determination can be made as to whether such instructions should be executed.

[0008] Memory addresses in a computing system identify memory locations in the computing system. Memory addresses are fixed-length sequences of digits that are conventionally shown and manipulated as unsigned integers. The length of the sequence of digits or bits can be considered the width of the memory address. Memory addresses can be used in certain structures of a central processing unit (CPU), such as instruction pointers (or program counters) and memory address registers. The size or width of such structures of a CPU typically determines the length of memory addresses used in such a CPU. BRIEF DESCRIPTION OF DRAWINGS

[0009] The embodiments are illustrated by way of example in the figures of the accompanying drawings in which like references indicate similar elements. In the figures:

[0010] Figures 1A to 1E Various ways of splitting memory addresses into multiple parts that can be used with execution types to control the operation of a cache are shown in accordance with some embodiments of the present disclosure.

[0011] Figure 2 , 3A Figs. 3A, 3B, and 3C show example aspects of example computing devices that each include a cache system with interchangeable caches for first and second types of execution in accordance with some embodiments of the present disclosure.

[0012] Figure 4 , 5AAnd 5B specifically show example aspects of example computing devices according to some embodiments of the disclosure, each computing device including a cache system having interchangeable caches for primary and speculative type execution.

[0013] Figure 6 , 7A , 7B, 8A, 8B, 9A, and 9B specifically show example aspects of example computing devices according to some embodiments of the disclosure, each computing device including a cache system having interchangeable cache sets for first and second type execution (e.g., primary and speculative type execution).

[0014] Figure 10 Specifically show example aspects of example computing devices according to some embodiments of the disclosure including a cache system having interchangeable cache sets for primary and speculative type execution.

[0015] Figure 11A And 11B Illustrate background synchronization circuitry for synchronizing content between a primary cache and a shadow cache to save content cached in the primary cache for acceptance of content in the shadow cache according to some embodiments of the disclosure.

[0016] Figure 12 Show example operations of example synchronization circuitry of Figure 11A And 11B according to some embodiments of the disclosure.

[0017] Figure 13 , 14A , 14B, 14C, 15A, 15B, 15C, and 15D specifically show example aspects of example computing devices according to some embodiments of the disclosure having a cache system with interchangeable cache sets with a set of spare caches to accelerate speculative execution.

[0018] Figure 16 And 17 Show example aspects of example computing devices according to some embodiments of the disclosure having a cache system with interchangeable cache sets with extended tags for different types of execution (e.g., speculative and non-speculative execution) by a processor.

[0019] Figure 18 Show example aspects of example computing devices according to some embodiments of the disclosure having a cache system with interchangeable cache sets with a circuit to map physical cache set outputs to logical cache set outputs.

[0020] Figure 19 , 20and 21 show an instance aspect of a cache system having interchangeable cache sets with logical cache set output mapped to physical cache set output using circuitry shown in Figure 18

[0021] Figure 22 and 23 Methods for using interchangeable cache sets for speculative and non-speculative execution by a processor according to some embodiments of the disclosure are shown. DETAILED DESCRIPTION

[0022] The disclosure includes techniques for using multiple caches or cache sets of caches interchangeably with different types of execution by a connected processor. The types of execution can include speculative and non-speculative execution threads. Non-speculative execution can be referred to as main or normal execution.

[0023] To obtain enhanced security, when a processor performs conditional speculative execution of instructions, the processor can be configured to use a shadow cache during the speculative execution of the instructions, where the shadow cache is separate from a main cache used during main or normal execution of the instructions. Some techniques for using a shadow cache to improve security can be found in U.S. Patent Application No. 16 / 028,930, filed July 6, 2018, and entitled “Shadow Cache for Securing Conditional Speculative Instruction Execution,” the entire disclosure of which is hereby incorporated by reference herein. The disclosure includes techniques that allow for a cache to be dynamically configured as a shadow cache or a main cache; a uniform set of cache resources can be dynamically allocated for a shadow cache or for a main cache; and the allocation can be changed during execution of instructions.

[0024] In some embodiments, a system can include a memory system (e.g., including a main memory), a processor, and a cache system coupled between the processor and the memory system. The cache system can have a cache set. Also, the caches in the cache set can be designed in a variety of ways. For example, the caches in the cache set can include a cache set by cache set associativity, which can include physical or logical cache set associativity.

[0025] ​In some embodiments, a cache of the system can be variable between being configured for a first type of execution of instructions by the processor and being configured for a second type of execution of instructions by the processor. The first type can be non-speculative execution of instructions by the processor. The second type can be speculative execution of instructions by the processor.

[0026] In some embodiments, a cache set of the cache can be variable between being configured for a first type of execution of instructions by the processor and being configured for a second type of execution of instructions by the processor. The first type can be non-speculative execution of instructions by the processor. Also, the second type can be speculative execution of instructions by the processor.

[0027] In some embodiments, speculative execution is a case where the processor executes one or more instructions based on a speculation that under some conditions the execution of such instructions is required before a determination as to whether such instructions should be executed is available. Non-speculative execution (or main execution, or normal execution) is a case where instructions are executed in order according to a program sequence of the instructions.

[0028] In some embodiments, a cache set of the system can include at least a first cache and a second cache. In such an instance, the system can include a command bus configured to receive a read command or a write command from the processor. The system can also include an address bus configured to receive a memory address from the processor for accessing a memory for the read command or the write command. Also, a data bus can be included that is configured to communicate data to the processor for the processor to read and receive data from the processor to write in the memory. The memory access request from the processor can be defined by the command bus, the address bus, and the data bus.

[0029] In some embodiments, a common command and address bus can replace the command and address buses described herein. Further, in such embodiments, a common connection to the common command and address bus can replace the respective connections to the command and address buses described herein.

[0030] The system can also include an execution type signal line configured to receive an execution type from the processor. The execution type can be an indication of normal or non-speculative execution or an indication of speculative execution.

[0031] The system can also include a configurable data bit configured to be set to a first state (e.g., “0”) or a second state (e.g., “1”) to change usage of the first cache and the second cache with respect to non-speculative execution and speculative execution.

[0032] The system can also include a logic circuit configured to select a first cache for memory access requests from the processor when the configurable data bit is set to a first state and the execution type signal line receives an indication of a non-speculative execution. The logic circuit can also be configured to select a second cache for memory access requests from the processor when the configurable data bit is set to the first state and the execution type signal line receives an indication of a speculative execution. The logic circuit can also be configured to select the second cache for memory access requests from the processor when the configurable data bit is set to a second state and the execution type signal line receives an indication of a non-speculative execution. The logic circuit can also be configured to select the first cache for memory access requests from the processor when the configurable data bit is set to the second state and the execution type signal line receives an indication of a speculative execution.

[0033] The system can also include a speculation state signal line configured to receive a speculation state from the processor. The speculation state can be a confirmation or denial of a condition with nested instructions that were initially executed by a speculative execution and subsequently executed by a non-speculative execution when the speculation state is a confirmation of the condition.

[0034] The logic circuit can also be configured to select the second cache as identified by the first state of the configurable data bit and restrict the first cache from being used or changed as identified by the first state of the configurable data bit when the signal received by the execution type signal line changes from an indication of a non-speculative execution to an indication of a speculative execution.

[0035] And, the logic circuit can be configured to change the configurable data bit from a first state to a second state and select the second cache for memory access requests when the execution type signal line receives an indication of a non-speculative execution. This can occur when the signal received by the execution type signal line changes from an indication of a speculative execution to an indication of a non-speculative execution and when the speculation state received by the speculation state signal line is a confirmation of the condition.

[0036] The logic circuit can also be configured to maintain the first state of the configurable data bit and select the first cache for memory access requests when the execution type signal line receives an indication of a non-speculative execution. This can occur when the signal received by the execution type signal line changes from an indication of a speculative execution to an indication of a non-speculative execution and when the speculation state received by the speculation state signal line is a denial of the condition. Further, the logic circuit can be configured to invalidate and discard the contents of the second cache when the signal received by the execution type signal line changes from an indication of a speculative execution to an indication of a non-speculative execution and when the speculation state received by the speculation state signal line is a denial of the condition.

[0037] The system can also include a second command bus configured to communicate read or write commands to a main memory connected to the cache system. The read or write commands can be received by the cache system from the processor. The system can also include a second address bus configured to communicate memory addresses to the main memory. The memory addresses can be received by the cache system from the processor. The system can also include a second data bus configured to communicate data to the main memory for writing in the memory and from the main memory to the processor for reading by the processor. Memory access requests from the cache system to the main memory can be defined by the second command bus, the second address bus, and the second data bus.

[0038] As mentioned, caches in a cache set can be designed in a variety of ways, and one of those ways includes a cache partitioned into a set of cache sets by cache set associativity (which can include physical or logical cache set associativity). A benefit of cache design by set associativity is that a single cache with set associativity can have multiple cache sets within a single cache, and thus, different portions of a single cache can be allocated for use by a processor without allocating the entire cache. Thus, a single cache can be used more efficiently. This is especially true when a processor performs multiple types of threads or has multiple execution types. For example, cache sets within a single cache can be used interchangeably with different execution types, rather than using interchangeable caches. Common examples of cache partitioning include having two, four, or eight cache sets within a cache.

[0039] Furthermore, a set associative cache design is advantageous over other common cache designs when a processor performs a main thread and a speculative thread. Since a speculative execution can use less additional cache capacity compared to ordinary or non-speculative execution, selection mechanisms can be implemented at the cache set level, and thus, less space (i.e., a portion of a cache) than the entire cache is reserved for speculative execution. A cache with set associativity can have multiple cache sets within a set (e.g., a partitioning of two, four, or eight cache sets within a cache). For example, as shown in Figure 7A As shown in FIG. 7, there are at least four cache sets in the cache of the cache system (e.g., see cache sets 702, 704, and 706). Ordinary or non-speculative execution, which typically requires most of the cache capacity, can have a larger number of cache sets delegated to it. Also, speculative execution, which has modifications to non-speculative execution, can use one cache set or a smaller number of cache sets since speculative execution typically involves fewer instructions than non-speculative execution.

[0040] As Figure 6 As shown in 10, a cache system can include multiple caches for a processor (e.g., caches 602a, 602b, and 602c depicted in 6) and a cache of the cache system can include a cache set (e.g., cache sets 610a, 610b, and 610c depicted in 6) to further partition the organization of the cache system. This example includes a cache system with set-associativity. Figure 6 Figure 6 As shown in 10, a cache system can include multiple caches for a processor (e.g., caches 602a, 602b, and 602c depicted in 6) and a cache of the cache system can include a cache set (e.g., cache sets 610a, 610b, and 610c depicted in 6) to further partition the organization of the cache system. This example includes a cache system with set-associativity.

[0041] At the cache set level of the cache, a first cache set (e.g., see cache set 702 depicted in Figure 7A , Figure 8A and 9A ) can hold content for use with a first type of execution or a second type by the processor. For example, the first cache set can hold content for use with a non-speculative type or a speculative type of execution by the processor. Further, a second cache set (e.g., see cache sets 704 or 706 depicted in Figure 7A , Figure 8A and 9A ) can hold content for use with the first type of execution or the second type by the processor.

[0042] For example, in a first time instance, the first cache set is used for normal or non-speculative execution and the second cache set is used for speculative execution. In a second time instance, the second cache set is used for normal or non-speculative execution and the first cache set is used for speculative execution. The manner in which the cache sets are delegated / exchanged for non-speculative and speculative execution can use set-associativity via a cache set index within or external to the memory address tag or via a cache set indicator within the memory address tag that is different from the cache set index (e.g., see Figure 7A , 7B , 8A, 8B, 9A, and 9B).

[0043] As shown in at least Figure 1B , 1C , 1D, 1E, 7A, 7B, 8A, 8B, 9A, and 9B, the cache set index or the cache set indicator can be included in cache block addressing to implement cache set addressing and associativity. The cache block addressing can be stored in memory (e.g., SRAM, DRAM, etc., depending on the design of the computing device, i.e., the design of the processor registers, the cache system, another intermediate memory, a main memory, etc.).

[0044] As shown in Figure 6 , 7A ​As shown in 7B, 8A, 8B, 9A, 9B, and 10, each cache set (e.g., L1, L2, or L3 cache) has a corresponding register (e.g., shown in...). Figure 6 and 10 Registers 610a, 610b, or 610c in the database, or shown in... Figure 7A , 7B Registers 712, 714, or 716 in 8A, 8B, 9A, and 9B) and set indices (see, for example, those shown in...) Figure 7A , 7B One of the set indices 722, 724, 726, and 728 in 8A, 8B, 9A, and 9B, which can be swapped between corresponding registers to implement a swapping of cache sets for non-speculating and speculative execution of the processor (or, generally, for the first and second types of execution of the processor). For example, relative to Figure 7A and 7B During the first time period, execution of the first type can use cache sets 702 and 704, and execution of the second type can use cache set 706. Then, during the second time period, execution of the first type can use cache sets 704 and 706, and execution of the second type can use cache set 702. It should be noted that this is only one instance of cache set usage, and it should be understood that, depending on the time period or the set index or indicator stored in the register, any cache set without predetermined restrictions can be used by either the first or second type of execution.

[0045] In some embodiments, several cache sets may be initially allocated for a first type of execution (e.g., non-speculsive execution). During a second type of execution (e.g., speculative execution), one of the cache sets initially allocated for the first type of execution (e.g., a reserved cache set) may be used in the second type of execution. Essentially, the cache set allocated for the second type of execution may initially be an idle cache set awaiting use, or a selection from several cache sets allocated for the first type of execution (e.g., cache sets less likely to be further used for another first type of execution).

[0046] Generally, in some embodiments, a cache system includes multiple cache sets. The multiple cache sets may include a first cache set, a second cache set, and multiple registers, each associated with a cache set. The multiple registers may include a first register associated with the first cache set and a second register associated with the second cache set. The cache system may also include connections to a command bus coupled between the cache system and the processor, connections to an address bus coupled between the cache system and the processor, and connections to a data bus coupled between the cache system and the processor. The cache system may also include logic coupled to the processor to control the multiple cache sets according to the multiple registers.

[0047] In this embodiment, the cache system can be configured to be coupled between the processor and the memory system. Furthermore, when the connection to the address bus receives a memory address from the processor, the logic circuitry can be configured to generate a set index from at least the memory address (e.g., see the examples shown in [reference 1]). Figure 7A , 7B The set indices in 8A, 8B, 9A, and 9B generate 730, 732, 830, 832, 930, and 932, respectively. Furthermore, when a memory address is received from the processor via the address bus connection, the logic circuitry can be configured to determine whether the generated set index matches the contents stored in a first register or a second register. Furthermore, the logic circuitry can be configured to execute a command received in the connection to the command bus via a first cache set in response to a generated set index matching the contents stored in the first register, and to execute the command via a second cache set in response to a generated set index matching the contents stored in the second register. Furthermore, in response to determining that the dataset of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry can be configured to allocate the first cache set for caching the dataset and store the generated set index in the first register. The generated set index may contain a predetermined segment of bits from the memory address.

[0048] The cache system may also include a connection to an execution type signal line from the processor that identifies the execution type (see, for example, see...). Figure 6 and 10 (as depicted in connection 604d). In this embodiment, a generated set index may be further generated based on the type identified by the execution type signal line. Furthermore, the generated set index may include a predetermined segment of bits in the memory address and bits representing the type identified by the execution type signal line (e.g., the generated set index may include a predetermined segment of bits in memory address 102e and bits representing the type shown in...). Figure 1EThe type of one or more bits identified by the execution type signal line of execution type 110e, or derived from the predetermined segment and the one or more bits.

[0049] Furthermore, when the first and second registers are in a first state, the logic circuitry can be configured to: implement commands received from the command bus for accessing the memory system via a first cache set when the execution type is a first type; and implement commands received from the command bus for accessing the memory system via a second cache set when the execution type is a second type. Furthermore, when the first and second registers are in a second state, the logic circuitry can be configured to: implement commands received from the command bus for accessing the memory system via another cache set other than the first cache set when the execution type is a first type; and implement commands received from the command bus for accessing the memory system via yet another cache set other than the second cache set when the execution type is a second type. In this example, each of the multiple registers can be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuitry can be configured to change the contents stored in the first register and the contents stored in the second register.

[0050] In some embodiments, a first type is configured to indicate non-speculatory execution of instructions by the processor; and a second type is configured to indicate speculative execution of instructions by the processor. In such embodiments, the cache system may further include a connection to a speculative state signal line from the processor, the speculative state signal line identifying the state of speculative execution of instructions by the processor (e.g., see illustrated in...). Figure 10 (See connection 1002 in the diagram). The connection to the speculative state signal line can be configured to receive the state of speculative execution, and the state of speculative execution can indicate whether the result of speculative execution will be accepted or rejected. Each of the plurality of registers can be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuit can be configured to change the contents stored in the first register and the contents stored in the second register if the state of speculative execution indicates that the result of speculative execution will be accepted (e.g., see the diagram shown in the diagram). Figure 7A and Figure 7B Between, displayed Figure 8A and Figure 8B Between and displayed in Figure 9A and Figure 9B (Changes to the contents stored in the registers between the two types). Furthermore, when the execution type changes from the second type to the first type, the logic circuit can be configured to maintain the contents stored in the first register and the contents stored in the second register without alteration, provided that the state indication of speculative execution will reject the result of speculative execution.

[0051] Additionally, the cache systems described herein (e.g., cache systems 200, 400, 600, and 1000) can each include or be connected to background synchronization circuitry (e.g., see background synchronization circuitry 1102 shown in Figure 11A and 11B ). The background synchronization circuitry can be configured to synchronize the caches or cache sets before reconfiguring the shadow caches to primary caches and / or reconfiguring the primary caches to shadow caches.

[0052] For example, the contents of the caches or cache sets initially delegated for speculative execution (e.g., the additional caches or backup cache sets delegated for speculative execution) can be synchronized with the corresponding caches or cache sets used by normal or non-speculative execution (to have the cache contents of the normal execution), so that if the speculation is confirmed, the caches or cache sets initially delegated for speculative execution can immediately join the cache sets of the main execution or non-speculative execution. Further, the initial cache sets corresponding to the caches or cache sets initially delegated for speculative execution can be removed from the group of cache sets used for the main execution or non-speculative execution. In such embodiments, circuitry (e.g., circuitry including the background synchronization circuitry) can be configured to synchronize the caches or cache sets in the background to reduce the impact of cache set synchronization on the cache usage of the processor. Further, the synchronization of the caches or cache sets can continue until the speculation is abandoned, or until the speculation is confirmed and the synchronization is complete. The synchronization can optionally include synchronization with memory (e.g., write back).

[0053] In some embodiments, a cache system can include a first cache and a second cache, and a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, and a connection to an execution type signal line from the processor that identifies an execution type (e.g., see cache systems 200 and 400). Such a cache system can also include a logic circuit coupled to control the first cache and the second cache according to the execution type, and the cache system can be configured to be coupled between the processor and a memory system. Further, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache is configured to service commands from the command bus to access the memory system, the logic circuit can be configured to copy a portion of contents of the cache in the first cache to the second cache (e.g., see operation 1202). In addition, the logic circuit can be configured to copy the portion of contents of the cache in the first cache to the second cache independent of a current command received in the command bus.

[0054] In addition, when the execution type is the first type indicating non-speculative execution of instructions by the processor and the first cache is configured to service commands from the command bus to access the memory system, the logic circuit can be configured to service subsequent commands from the command bus using the second cache in response to the execution type changing from the first type to a second type indicating speculative execution of instructions by the processor (e.g., see operation 1208). In such an instance, the logic circuit can be configured to complete synchronizing the portion of contents from the first cache to the second cache before servicing the subsequent commands after the execution type changes from the first type to the second type (e.g., see operation 1210). The logic circuit can also be configured to continue synchronizing the portion of contents from the first cache to the second cache while servicing the subsequent commands (e.g., see operation 1210). Figure 12

[0055] ​In such embodiments, the cache system can further include a configurable data bit, wherein the logic circuit is further coupled to control the first cache and the second cache in accordance with the configurable data bit. Moreover, in such embodiments, the cache system can further include a plurality of cache sets. For example, the first cache and the second cache can collectively include the plurality of cache sets, and the plurality of cache sets can include a first cache set and a second cache set. The cache system can also include a plurality of registers associated with the plurality of cache sets, respectively. The plurality of registers can include a first register associated with the first cache set and a second register associated with the second cache set. Also, in such embodiments, the logic circuit can be further coupled to control the plurality of cache sets in accordance with the plurality of registers.

[0056] In some embodiments, the cache system can include a plurality of cache sets including a first cache set and a second cache set. The cache system can also include a plurality of registers associated with the plurality of cache sets, respectively, including a first register associated with the first cache set and a second register associated with the second cache set. In such embodiments, the cache system can include a plurality of caches including a first cache and a second cache, and the first cache and the second cache can collectively include at least a portion of the plurality of cache sets. Such a cache system can also include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, and a connection to an execution type signal line from the processor identifying an execution type, and a logic circuit coupled to control the plurality of cache sets in accordance with the execution type.

[0057] In such embodiments, the cache system can be configured to be coupled between a processor and a memory system. Also, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache set is configured to service commands from the command bus for accessing the memory system, the logic circuit is configured to copy a portion of contents of the cache in the first cache set to the second cache set. The logic circuit can also be configured to copy the portion of contents of the cache in the first cache set to the second cache set independent of a current command received in the command bus.

[0058] Furthermore, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache set is configured to service commands from the command bus for accessing the memory system, the logic circuit can be configured to service subsequent commands from the command bus using the second cache set in response to the execution type changing from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuit can also be configured to complete the synchronizing of the portion of the content from the first cache set to the second cache set prior to servicing the subsequent commands after the execution type changes from the first type to the second type. The logic circuit can also be configured to continue synchronizing the portion of the content from the first cache set to the second cache set while servicing the subsequent commands. And, the logic circuit can be further coupled to control the plurality of cache sets in accordance with a plurality of registers.

[0059] In addition to using a shadow cache for ensuring speculative execution and synchronizing content between the main cache and the shadow cache to save content stored in the main cache in preparation for accepting content in the shadow cache, a spare cache set can also be used to speed up speculative execution. Moreover, the spare cache set can be used to speed up speculative execution without using a shadow cache. The use of a spare cache set is applicable to a shadow cache implementation because the data saved in the cache set used as a shadow cache and thus used for normal execution can be verified and thus some cache sets used as main caches can not be ready to be used as a shadow cache. Thus, one or more cache sets can be used as a spare cache set to avoid the delay of waiting for cache set availability. In other words, once a speculation is confirmed, the content of the cache set used as a shadow cache is confirmed to be valid and up-to-date; and thus, the previous cache set used as a shadow cache for speculative execution is used for normal execution. However, some of the cache sets originally used as normal caches can not be ready for subsequent speculative execution. Thus, one or more cache sets can be used as a spare to avoid the delay of waiting for cache set availability and to speed up speculative execution.

[0060] In some embodiments, if the synchronization from the cache set in the normal cache to the corresponding cache set in the shadow cache has not been completed, the cache set in the normal cache cannot be released immediately for use by the next speculative execution. In this case, if there is no spare cache set, the next speculative execution has to wait until the synchronization is completed so that the corresponding cache set in the normal cache can be released. This is just one example when a spare cache set is beneficial and can be added to the embodiment. And, there are many other cases when the cache set in the normal cache cannot be released immediately, so a spare cache set can be useful.

[0061] Furthermore, in some embodiments, speculative execution can reference memory regions that do not have overlap with memory regions cached in the cache set used in the normal cache. As a result of accepting speculative execution, the cache set in the shadow cache and the normal cache can all be in the normal cache. This can also cause a delay as the cache system takes time to free the cache set to support the next speculative execution. To free the cache set, the cache system can identify the cache set, such as the least used cache set, and synchronize the cache set with the memory system. If the cache has data that is more up to date than the memory system, the data can be written to the memory system.

[0062] Additionally, systems that use a spare cache set can also use background synchronization circuitry, such as the background synchronization circuitry 1102 depicted in Figure 11A and 11B In some embodiments, the background synchronization circuitry 1102 can be part of the logic circuit 606 or 1006. When an initial speculation is confirmed, the cache set used in the initial speculation can be swapped in to join the set of cache sets used in the main execution. Instead of using the cache set from the previous main execution that is being used for the case of speculation failure, the spare cache set can be made available for the next speculative execution immediately. Furthermore, the spare cache set can be updated for the next speculative execution via the background synchronization circuitry. Also, as a result of the background synchronization, the spare cache set can be ready for use when the cache set currently used for speculative execution is ready to be accepted for normal execution. In this way, there is no delay in waiting for the use of the next cache set for the next speculative execution. To prepare for the next speculative execution, the spare cache set can be synchronized to the normal cache set or the least used cache set in the system that is most likely to be used for the next speculative execution.

[0063] In addition to using a shadow cache, synchronizing content between the main cache and the shadow cache, and using a spare cache set, extended tags can also be used to improve the use of interchangeable caches and cache sets for different types of execution, such as speculative and non-speculative execution, by a processor. There are many different ways to use extended tags to address cache sets and cache blocks within a cache system. Two example ways are shown in Figure 16 and 17

[0064] In general, a cache set and a cache block can be selected via a memory address. In some examples, the selection is via set-associativity. Figure 16 and 17 ​The two instances in the example use set association. Figure 16 In this context, set associativity is implicitly defined (e.g., through algorithms that can be used to determine which tag should be in which cache set for a given execution type). Figure 17 In this context, set association is implemented via bits in the cache set index within the memory address. Furthermore, Figure 16 and 17 The functional parts described herein can be implemented without using set associations (but this is not in...). Figure 16 and 17 (Depicted in Chinese).

[0065] In some embodiments, including those shown in Figure 16 and 17 In the embodiments described, the block index can be used as an address within an individual cache set to identify a specific cache block within the cache set. Furthermore, the extended tag can be used as an address of the cache set. The block index of the memory address can be used for each cache set to obtain the cache block and the tag associated with the cache block. Additionally, as... Figure 16 and 17 As shown, the tag comparison circuit compares an extended tag generated from a cache set with an extended cache tag generated from a memory address and the current execution type. The comparison output can be a cache hit or a miss. The construction of the extended tag ensures that at most one hit exists in the cache set. If a hit exists, a cache block from the selected cache set provides the output. Otherwise, the data associated with the memory address is either cached in either cache set or output from either cache set. In short, Figure 16 and 17 The extended labels described are used to select a cache set, and the block index is used to select a cache block and its label within the cache set.

[0066] In addition, such as Figure 17 As shown, the combination of tags and cache set indexes in the system can provide functionality comparable to using only tags (such as...). Figure 16 Slightly similar functionality (as shown in the example). However, in Figure 17 In this approach, by separating the label and the cache set index, the cache set does not need to store a redundant copy of the cache set index. This is because the cache set can be associated with a cache set register to store the cache set index. And... Figure 16 In this context, the cache set does indeed need to store redundant copies of the cache set indicator in each block of the cache set. However, due to... Figure 16In the embodiments depicted, the tags have the same cache set indicator, so the indicator can be stored in a register for the cache set (e.g., see the example shown in [reference needed]). Figure 17 The tag is stored in the cache set register (in the cache set register). The advantage of using the cache set register is that the tag length can be shorter compared to implementations that do not have a cache set register.

[0067] Shown Figure 16 and 17 Both embodiments in the example have a cache set register configured to store execution types, such that the corresponding cache set can be used to implement different execution types (e.g., speculative and non-speculative execution types). However, the example shown... Figure 17 The embodiments in the example include registers further configured to store execution type and cache set indexes. When the execution type is combined with the cache set index to form an extended cache set index, the extended cache set index can be used to select one of the cache sets regardless of addressing via the tag of the cache block. Furthermore, when comparing tags from the selected cache set with tags in the address to determine a hit or miss, the two-step selection can be similar to the conventional two-step selection using a cache set index, or can be used in combination with extended tags to support interchangeability of cache sets for different execution types.

[0068] In addition to using extended tags and other techniques disclosed herein to improve the use of interchangeable caches and cache sets for different types of execution performed by the processor, circuitry incorporated in or connected to the cache system can be used to map physical outputs from cache sets of the cache hardware system to logical main caches and logical shadow caches, respectively, for normal and speculative execution performed by the processor. The mapping may be based on at least one control register (e.g., a physical-to-logical-set-map (PLSM) register).

[0069] Furthermore, what is disclosed herein is a circuit that utilizes a mapping circuit (e.g., shown in...). Figure 18The mapping circuit 1830) maps the physical cache set outputs to the logical cache set outputs of the interchangeable cache system of the cache system. The processors coupled to the cache system can execute two types of threads, such as speculative and non-speculative execution threads. Speculative threads are executed speculatively with conditions that have not been evaluated. The data of the speculative threads can be in the logical shadow cache. The data of the non-speculative threads can be in the logical main cache or normal cache. Subsequently, when the results of the evaluated conditions become available, when the conditions require execution of the threads or removal of the threads, the system can keep the results of the execution of the speculative threads. With the mapping circuit, the hardware circuit for the shadow cache can be repurposed as the hardware circuit for the main cache by changing the contents of the control registers. Thus, for example, if execution of the speculative threads is required, there is no need to synchronize the main cache with the shadow cache.

[0070] In a conventional cache, each cache set is statically associated with a particular value of "index S" / "block index L". In the cache system disclosed herein, any cache set can be used for any index value S / L and for either the main cache or the shadow cache. The cache set can be used with and defined by the data in the cache set register associated with the cache set. Selection logic can then be used to select the appropriate result based on the index value of S / L and the way the cache set is used.

[0071] For example, four cache sets (cache set 0 through set 3) can initially be used for the main cache for S / L = 00, 01, 10, and 11, respectively. Assuming that speculative execution does not change the cache sets defined by 01, 10, and 11, the fourth cache set can be used as the speculative cache for S / L = 00. If the results of the speculative execution are required, the mapping data can be changed to indicate that the main cache for S / L = 00, 01, 10, and 11 are used for the fourth cache set, cache set 1, cache set 2, and cache set 3, respectively. Cache set 0 can then be released or invalidated for subsequent use in the speculative execution. If the next speculative execution requires changing the cache set S / L to 01, cache set 0 can be used as a shadow cache (e.g., copied from cache set 1 and used to look up the contents of addresses with S / L equal to '01').

[0072] Furthermore, the cache system and processor do not merely switch back and forth between a predetermined main thread and a predetermined speculative thread. Consider the following pseudo program for speculative execution.

[0073] Instruction A;

[0074] If condition = true,

[0075] Then instruction B;

[0076] End condition loop;

[0077] Instruction C; and

[0078] Instruction D.

[0079] For the pseudo program, the processor can run two threads.

[0080] Thread A:

[0081] Instruction A;

[0082] Instruction C; and

[0083] Instruction D.

[0084] Thread B:

[0085] Instruction A;

[0086] Instruction B;

[0087] Instruction C; and

[0088] Instruction D.

[0089] Execution of instruction B is speculative because it depends on the test result of "condition = true" instead of "condition = false". Execution of instruction B is only needed if condition = true. When the result of the test "condition = true" becomes available, execution of thread A reaches instruction D, and execution of thread A can reach instruction C. If the test result requires execution of instruction B, then the cache contents of thread B are correct and the cache contents of thread A are incorrect. Then, all changes made in the cache according to thread B should be preserved, and the processor can continue execution of instruction C with the cache having the result of executing instruction B; and terminate thread A. Since the changes made according to thread B are in the shadow cache, the contents of the shadow cache should be accepted as the main cache. If the test result does not require execution of instruction B, then the results of thread B are discarded (e.g., the contents of the shadow cache are discarded or invalidated).

[0090] Cache sets for shadow and normal caches can be swapped or changed according to a mapping circuit and a control register (e.g., a physical-to-logical-set-mapping (PLSM) register). In some embodiments, a cache system can include a plurality of cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system can also include a connection to a command bus coupled between the cache system and a processor, and a connection to an address bus coupled between the cache system and the processor. The cache system can also include a control register, and a mapping circuit coupled to the control register to map respective physical outputs of the plurality of cache sets to a first logical cache and a second logical cache according to a state of the control register. The cache system can be configured to be coupled between the processor and a memory system.

[0091] When the connection to the address bus receives a memory address from the processor and when the control register is in a first state, the mapping circuit can be configured to map the first physical output to the first logical cache for a first type of execution by the processor to implement commands received from the command bus for accessing the memory system via the first cache set during the first type of execution, and to map the second physical output to the second logical cache for a second type of execution by the processor to implement commands received from the command bus for accessing the memory system via the second cache set during the second type of execution. And, when the connection to the address bus receives a memory address from the processor and when the control register is in a second state, the mapping circuit is configured to map the first physical output to the second logical cache to implement commands received from the command bus for accessing the memory system via the first cache set during the second type of execution, and to map the second physical output to the first logical cache to implement commands received from the command bus for accessing the memory system via the second cache set during the first type of execution.

[0092] In some embodiments, the first logical cache is a normal cache for non-speculative execution by the processor, and the second logical cache is a shadow cache for speculative execution by the processor.

[0093] Furthermore, in some embodiments, the cache system can further include a plurality of registers associated with the plurality of cache sets, respectively, including a first register associated with the first cache set and a second register associated with the second cache set. The cache system can also include a logic circuit coupled to the processor to control the plurality of cache sets according to the plurality of registers. When a connection with the address bus receives a memory address from the processor, the logic circuit can be configured to generate a set index from at least the memory address, and determine whether the generated set index matches contents stored in the first register or contents stored in the second register. Also, the logic circuit can be configured to implement a command received in a connection with the command bus via the first cache set in response to the generated set index matching the contents stored in the first register, and implement the command via the second cache set in response to the generated set index matching the contents stored in the second register.

[0094] In some embodiments, the mapping circuit can be part of or connected to the logic circuit, and the state of the control register can control the state of a cache set of the plurality of cache sets. In some embodiments, the state of the control register can control the state of a cache set of the plurality of cache sets by changing a valid bit of each block of the cache set.

[0095] Furthermore, in some instances, the cache system can further include a connection with a speculation status signal line from the processor identifying a state of speculative execution of instructions by the processor. The connection with the speculation status signal line can be configured to receive the state of speculative execution, and the state of speculative execution can indicate whether results of the speculative execution are to be accepted or rejected. When the type of execution changes from speculative execution to non-speculative execution, the logic circuit can be configured to change the state of the first and second cache sets via the control register if the state of speculative execution indicates that results of the speculative execution are to be accepted (e.g., when the speculative execution is to become a main execution thread). Also, when the type of execution changes from speculative execution to non-speculative execution, the logic circuit can be configured to maintain the state of the first and second cache sets without change via the control register if the state of speculative execution indicates that results of the speculative execution are to be rejected.

[0096] In some embodiments, the mapping circuit is part of or connected to the logic circuit, and the state of the control register can control the state of a cache register of the plurality of cache registers via the mapping circuit. In such an example, the cache system can further include a connection to a speculation status signal line from the processor that identifies a status of speculative execution of instructions by the processor. The connection to the speculation status signal line can be configured to receive a status of speculative execution, and the status of speculative execution indicates whether results of the speculative execution are to be accepted or rejected. When the type of execution changes from speculative execution to non-speculative execution, the logic circuit can be configured to change the state of the first and second registers via the control register if the status of speculative execution indicates that results of the speculative execution are to be accepted. Also, when the type of execution changes from speculative execution to non-speculative execution, the logic circuit can be configured to maintain the state of the first and second registers without change if the status of speculative execution indicates that results of the speculative execution are to be rejected.

[0097] Additionally, the present disclosure includes techniques to ensure speculative instruction execution using a plurality of interchangeable caches that can each interchangeably function as a shadow cache or a main cache. Speculative instruction execution can occur in a processor of a computing device. The processor can execute two different types of threads of instructions. One of the threads can be executed speculatively (e.g., under a condition that has not yet been evaluated). Data of the speculative thread can be in a logical cache that functions as a shadow cache. Data of the main thread can be in a logical cache that functions as a main cache. Subsequently, when the result of evaluating the condition becomes available, the processor can either keep the results of executing the speculative thread, or remove the results, when the condition requires execution of the thread. The hardware circuit of the cache that functions as a shadow cache can be repurposed as a hardware circuit of a main cache by changing the contents of a register. Thus, if execution of the speculative thread is required, there is no need to synchronize the main cache with the shadow cache.

[0098] The techniques disclosed herein also relate to the use of a unified cache structure that can be used to implement a main cache and a shadow cache with improved performance. In the unified cache structure, a set of registers can be used to dynamically remap the results of a set of caches to be swapped in the main cache with the shadow cache. When the speculative execution is successful, the set of caches used with the shadow cache has the correct data and can be remapped as the corresponding set of caches for the main cache. This eliminates the need to copy data from the shadow cache to the main cache as used by other techniques that use a shadow and main cache.

[0099] Generally, a cache can be configured as multiple sets of blocks. Each set of blocks can have multiple blocks, and each block can hold a number of bytes. A memory address can be split into three pieces for accessing the cache, a tag, a block index (which can be used to address a set within a plurality of sets), and a cache block (which can be used to address a byte within a block of bytes). For each block in a set, the cache not only stores data from memory, but also a tag of the address from which the data was loaded and a field indicating whether the contents of the block are valid. Data can be retrieved from the cache using the block index (e.g., set ID) and the cache block (e.g., byte ID). The tag in the retrieved data is compared to the tag portion of the address. A matching tag means that the cache data for the address. Otherwise, it means that the data can be cached for another address that maps to the same location in the cache.

[0100] In the case of the technique using multiple interchangeable caches, the physical cache sets of the interchangeable caches are not hardwired as a primary cache or a shadow cache. The physical cache sets can be used as a primary cache set or a shadow cache set. Also, a register set can be used to specify whether the physical cache set is currently being used as a primary cache set or a shadow cache set. Generally, the mapping can be constructed to translate the output of the physical cache set to the logical output of the corresponding cache set represented by the block index (e.g., set ID) and the primary or shadow state. The remapping allows any available physical cache to be used as a shadow cache.

[0101] In some embodiments, the unified cache architecture can remap a shadow cache (e.g., a speculative cache) to a primary cache, and can remap a primary cache to a speculative cache. It should be understood that the design can include any number of caches or cache sets that can be interchangeable between a primary cache or cache set or a speculative cache or cache set.

[0102] It should be understood that there is no physical distinction in the hardwiring of the primary cache or cache set and the speculative cache or cache set. Also, in some embodiments, there is no physical distinction in the hardwiring of the logic units described herein. It should be understood that the interchangeable cache or cache set does not have different cache capacities and structures. Otherwise, such a cache or cache set would not be interchangeable. Furthermore, the physical cache sets can be dynamically configured to be primary or speculative, e.g., without a priori determination.

[0103] Furthermore, it should be understood that the interchangeability occurs at the cache level rather than the cache block level. Interchangeability at the cache block level can allow the primary cache and the shadow cache to have different capacities; and thus, not be interchangeable.

[0104] Furthermore, in some embodiments, when a speculation is successful by the processor and the cache is being used as a primary cache and another cache is being used as a speculative or shadow cache, all of the valid bits associated with the cache index block of the primary cache are set to indicate invalid (e.g., invalid is indicated by a "0" bit value). In such embodiments, the initial state of all of the valid bits of the speculative cache indicate invalid, but then change to indicate valid due to the successful speculation. In other words, the previous state of the primary cache is voided and the previous state of the speculative cache is set from invalid to valid and is accessible by the main thread.

[0105] In some embodiments, the PLSM register for the primary cache can change from indicating the primary cache to indicating the speculative cache. The change from indicating the primary cache to the speculative cache by the PLSM register can be made by the PLSM register receiving an invalid indication of the primary cache after a successful speculation. For example, after a successful speculation and where the first cache is initially the primary cache and the second cache is initially the speculative cache, an invalid indication of bit "0" can replace the least significant bit in the 3-bit PLSM register for the first cache, which can change "011" to "010" (or change "3" to "2"). Also, for the 3-bit PLSM register for the second cache, a valid indication of bit "1" can replace the least significant bit in the PLSM register, which can change "010" to "011" (or change "2" to "3"). Thus, as the example shows, the PLSM register initially for the first cache (e.g., the primary cache) and initially selecting the first cache changes to select the second cache (e.g., the speculative cache) after a successful speculation. Also, as the example shows, the PLSM register initially for the second cache (e.g., the speculative cache) and initially selecting the second cache changes to select the first cache (e.g., the primary cache) after a successful speculation. With this design, the main thread of the processor can first access the cache initially designated as the primary cache and then access the cache initially designated as the speculative cache after a successful speculation by the processor. Also, the speculative thread of the processor can first access the cache initially designated as the speculative cache and then access the cache initially designated as the primary cache after a successful speculation by the processor.

[0106] Figure 1AThe memory address 102a is shown partitioned into a tag portion 104a, a block index portion 106a, and a block offset portion 108a. According to some embodiments of the present disclosure, an execution type 110a can be combined with portions of the memory address to control cache operations. The total bits used to control addressing in a cache system according to some embodiments disclosed herein is A bits. Also, the sum of the bits used for portions 104a, 106a, and 108a and execution type 110a equals A bits. The tag portion 104a is K bits, the block index portion 106a is L bits, the block offset portion 108a is M bits, and the execution type 110a is one or more T bits.

[0107] For example, for a given execution type, data for all memory addresses having the same block index portion 106a and block offset portion 108a can be stored in the same physical location in the cache. When data at memory address 102a is stored in the cache, the tag portion 104a also stores for the block containing the memory address to identify which of the addresses having the same block index portion 106a and block offset portion 108a is currently being cached in the cache at the location.

[0108] Data at a memory address can be cached in different locations in a unified cache structure for different types of execution. For example, data can be cached in a primary cache during non-speculative execution; and then cached in a shadow cache during speculative execution. The execution type 110a can be combined with the tag portion 104a to select from the cache, which can be dynamically configured for use in both primary and speculative execution without restriction. There can be many different ways in which the use of the combination of execution type 110a and tag portion 104a is implemented to make the selection. For example, Figure 2 and 4 The logic circuit 206 depicted in FIGS. 1, 2, and 3 can use the execution type 110a and / or the tag portion 104a.

[0109] In a relatively simple implementation, the execution type 110a can be combined with the tag portion 104a to form an extended tag in determining whether a cache location contains data for a memory address 102a or data for a current type of execution of an instruction. For example, a cache system can select a cache location using the tag portion 104a without distinguishing the execution type; and when the tag portion 104a is combined with the execution type 110a to form an extended tag, the extended tag can be used in a manner similar to selecting a cache location in having different types of execution (e.g., speculative execution and non-speculative execution) such that the technique of shadow caching can be implemented to enhance security. Moreover, since information regarding the execution type associated with data of a cache is shared among many cache locations (e.g., in a cache set, or in a cache having multiple cache sets), it is not necessary to store the execution type for individual locations; and a selection mechanism (e.g., a switch, filter, or multiplexer, such as a data multiplexer) can be used to implement selection according to the execution type. Alternatively, physical caches or physical cache sets for different types of execution can be remapped to logical caches respectively pre-associated with different types of execution. Thus, use of logical caches can be selected according to the execution type 110a.

[0110] Figure 1B Another way of showing a memory address 102b partitioned into portions to control cache operations is shown. The memory address 102b is partitioned into a tag portion 104b, a cache set index portion 112b, a block index portion 106b, and a block offset portion 108b. The total bits of the memory address 102b is A bits. Also, the sum of the bits for the four portions equals the A bits of the address 102b. The tag portion 104b is K bits, the block index portion 106b is L bits, the block offset portion 108b is M bits, and the cache set index portion 112b is S bits. Thus, for the address 102b, A bits = K bits + L bits + M bits + S bits. According to Figure 1B Partitioning of the memory address 102b allows implementation of set associativity in caching data.

[0111] For example, multiple cache sets can be configured in the cache, where each cache set can be addressed using a cache set index 112b. Sets of data associated with the same cache set index can be cached in the same cache set. The tag portion 104b of a data block cached in a cache set can be stored in the cache in association with the data block. When the address 102b is used to retrieve data from the cache set identified using the cache set index 112b, the tag portion of the data block stored in the cache set can be retrieved and compared with the tag portion 104b to determine whether there is a match between the tag 104b of the address 102b of the access request and the tag 104b stored in the cache set identified by the cache set index 112b and stored for the cache block identified by the block index 106b. If there is a match (e.g., a cache hit), the cache block stored in the cache set is for the memory address 112b; otherwise, the cache block stored in the cache set is for another memory address having the same cache set index 112b and the same block index 106b as the memory address 102b, which results in a cache miss. In response to the cache miss, the cache system accesses the main memory to retrieve the data block according to the address 102b. To implement the shadow cache technique, the cache set index 112b can be combined with the execution type 110a to form an extended cache set index. Thus, the extended cache set index identifying both the cache set index and the execution type can be used to address the cache set for different types of execution of different cache set indexes.

[0112] In Figure 1B the cache set index portion 112b is extracted from a predetermined portion of the address 102b. Data stored at memory addresses having different set indexes can be cached in different cache sets of the cache to implement set associativity in caching data. The cache set of the cache can be selected using the cache set index (e.g., the portion 112b of the address 102b). Alternatively, the cache set associativity can be implemented via the tag 104c including a cache set indicator. Optionally, the cache set indicator is computed from the tag 104c and used as a cache set index to address the cache set. Alternatively, the set associativity can be implemented directly via the tag 104c such that the cache set storing the tag 104c is selected for a cache hit; and when no cache set stores the tag 104c, a cache miss is determined. Alternatively, the address 102d can be used to address the cache set as described in Figure 1C the cache set index portion 112b is extracted from a predetermined portion of the address 102b. Data stored at memory addresses having different set indexes can be cached in different cache sets of the cache to implement set associativity in caching data. The cache set of the cache can be selected using the cache set index (e.g., the portion 112b of the address 102b). Alternatively, the cache set associativity can be implemented via the tag 104c including a cache set indicator. Optionally, the cache set indicator is computed from the tag 104c and used as a cache set index to address the cache set. Alternatively, the set associativity can be implemented directly via the tag 104c such that the cache set storing the tag 104c is selected for a cache hit; and when no cache set stores the tag 104c, a cache miss is determined. Alternatively, the address 102d can be used to address the cache set as described in Figure 1DThe manner of partitioning for cache operations as illustrated in FIG. 1, where tag portion 104d contains cache set index 112d, where the cache sets are not explicitly and separately addressed using cache set index. For example, to implement shadow cache techniques, the combination of execution type 110e and tag 104e with embedded cache set indicator (as depicted in FIG. 1) can be used to select a cache set for the correct execution type and store the same tag 104e for cache hit. When no cache set has the matching execution type and stores the same tag 104e, a cache miss is determined. Figure 1E

[0113] Further, as shown in FIG. 1, Figure 1C Figure 1C depicts another manner of partitioning memory address 102c into portions to control cache operations. Memory address 102c is partitioned into tag portion 104c with cache set indicator, block index portion 106c, and block offset portion 108c. The total bits of memory address 102c is A bits. And, the sum of bits for the three portions equals A bits of address 102c. Tag portion 104c is K bits, block index portion 106c is L bits, and block offset portion 108c is M bits. Thus, for address 102c, its A bits = K bits + L bits + M bits. As mentioned, the partitioning of memory address 102c according to FIG. 1 allows for the implementation of set associativity in caching data. Figure 1C

[0114] Further, as shown in FIG. 1, Figure 1D Figure 1D depicts another manner of partitioning memory address 102d into portions to control cache operations. Memory address 102d is partitioned into tag portion 104d with cache set index 112d, block index portion 106d, and block offset portion 108d. The total bits of memory address 102d is A bits. And, the sum of bits for the three portions equals A bits of address 102d. Tag portion 104d is K bits, block index portion 106d is L bits, and block offset portion 108d is M bits. Thus, for address 102d, its A bits = K bits + L bits + M bits. As mentioned, the partitioning of memory address 102d according to FIG. 1 allows for the implementation of set associativity in caching data. Figure 1D

[0115] Further, as shown in FIG. 1, Figure 1E Figure 1E depicts another manner of partitioning memory address 102e into portions to control cache operations. Figure 1E ​​​​​​The memory address 102e is shown partitioned into a tag portion 104e, a block index portion 106e, and a block offset portion 108e having cache set indicators. According to some embodiments of the present disclosure, an execution type 110e can be combined with portions of the memory address to control cache operations. The total bits for controlling addressing in a cache system according to some embodiments disclosed herein is A bits. And, the sum of the bits for portions 104e, 106e, and 108e and execution type 110e equals A bits. Tag portion 104e is K bits, block index portion 106e is L bits, block offset portion 108e is M bits, and execution type 110e is T bits.

[0116] Figure 2 、 3A And 3B shows example aspects of example computing devices including cache systems having caches that can interchanged for first and second types of execution, e.g., for implementing shadow cache techniques with enhanced security, according to some embodiments of the present disclosure.

[0117] Figure 2 Particular aspects are shown of an example computing device including a cache system 200 having a plurality of caches (see, e.g., caches 202a, 202b, and 202c). The example computing device is also shown as having a processor 201 and a memory system 203. The cache system 200 is configured to be coupled between the processor 201 and the memory system 203.

[0118] The cache system 200 is shown as including a connection 204a to a command bus 205a coupled between the cache system and the processor 201. The cache system 200 is shown as including a connection 204b to an address bus 205b coupled between the cache system and the processor 201. The address 102a, 102b, 102c, 102d, and 102e depicted in Figure 1A 、 1B The addresses 102a, 102b, 102c, 102d, and 102e depicted in 1C, 1D, and 1E can each be communicated via the address bus 205b depending on the implementation of the cache system 200. The cache system 200 is also shown as including a connection 204c to a data bus 205c coupled between the cache system and the processor 201. The cache system 200 is also shown as including a connection 204d to an execution type signal line 205d from the processor 201 identifying an execution type.

[0119] Not shown in Figure 2 , the cache system 200 can include configurable data bits. The configurable data bits can be included in or be the data 312 shown in the first state shown in Figure 3A , Figure 3Bdata 314 in the second state or for the data 314. Memory access requests from the processor and memory usage by the processor can be controlled through the command bus 205a, the address bus 205b, and the data bus 205c.

[0120] In some embodiments, the cache system 200 can include a first cache (see, e.g., cache 202a) and a second cache (see, e.g., cache 202b). In such embodiments, as Figure 2 illustrated in FIG. 2, the cache system 200 can include a logic circuit 206 coupled to the processor 201. Further, in such embodiments, the logic circuit 206 can be configured to control the first cache (see, e.g., cache 202a) and the second cache (see, e.g., cache 202b) based on a configurable data bit.

[0121] When the configurable data bit is in the first state (see, e.g., data 312 depicted in Figure 3A FIG. 2), the logic circuit 206 can be configured to implement commands received from the command bus 205a for accessing the memory system 203 via the first cache when the type of execution is the first type. Further, when the configurable data bit is in the first state (see, e.g., data 312 depicted in Figure 3A FIG. 2), the logic circuit 206 can be configured to implement commands received from the command bus 205a for accessing the memory system 203 via the second cache when the type of execution is the second type.

[0122] When the configurable data bit is in the second state (see, e.g., data 314 depicted in Figure 3B FIG. 2), the logic circuit 206 can be configured to implement commands received from the command bus 205a for accessing the memory system 203 via the second cache when the type of execution is the first type. Further, when the configurable data bit is in the second state (see, e.g., data 314 depicted in Figure 3B FIG. 2), the logic circuit 206 can be configured to implement commands received from the command bus 205a for accessing the memory system 203 via the first cache when the type of execution is the second type.

[0123] In some embodiments, the logic circuit 206 is configured to toggle the configurable data bit when the type of execution changes from the second type to the first type.

[0124] Further, as Figure 2As shown in the middle, the cache system 200 further includes a connection 208a to a second command bus 209a coupled between the cache system and the memory system 203. The cache system 200 also includes a connection 208b to a second address bus 209b coupled between the cache system and the memory system 203. The cache system 200 also includes a connection 208c to a second data bus 209c coupled between the cache system and the memory system 203. When the configurable data bit is in the first state, when the type of execution is of a first type (e.g., a non-speculative type), the logic circuit 206 is configured to provide commands for accessing the memory system 203 via the first cache to the second command bus 209a. When the configurable data bit is in the first state, when the type of execution is of a second type (e.g., a speculative type), the logic circuit 206 is also configured to provide commands for accessing the memory system via the second cache to the second command bus 209a.

[0125] When the configurable data bit is in the second state, when the type of execution is of the first type, the logic circuit 206 is configured to provide commands for accessing the memory system 203 via the second cache to the second command bus 209a. Also, when the configurable data bit is in the second state, when the type of execution is of the second type, the logic circuit 206 is configured to provide commands for accessing the memory system 203 via the first cache to the second command bus 209a.

[0126] In some embodiments, the connection 204a to the command bus 205a is configured to receive a read command or a write command from the processor 201 for accessing the memory system 203. Also, the connection 204b to the address bus 205b is configurable to receive a memory address from the processor 201 for accessing the memory system 203 for the read command or the write command. Further, the connection 204c to the data bus 205c is configurable to communicate data to the processor 201 for the processor to read data for the read command. Also, the connection 204c to the data bus 205c is also configurable to receive data from the processor 201 to write in the memory system 203 for the write command. Further, the connection 204d to the execution type signal line 205d is configurable to receive an identification of the type of execution (e.g., an identification of a non-speculative or a speculative type of execution by the processor) from the processor 201.

[0127] In some embodiments, the logic circuit 206 can be configured to select a first cache for a memory access request (e.g., one of the commands received from a command bus for accessing a memory system) from the processor 201 when the configurable data bit is in a first state and the connection 204d to the execution type signal line 205d receives an indication of a first type (e.g., a non-speculative type). Further, the logic circuit 206 can be configured to select a second cache for the memory access request from the processor 201 when the configurable data bit is in the first state and the connection 204d to the execution type signal line 205d receives an indication of a second type (e.g., a speculative type). Further, the logic circuit 206 can be configured to select the second cache for the memory access request from the processor 201 when the configurable data bit is in a second state and the connection 204d to the execution type signal line 205d receives an indication of the first type. Also, the logic circuit 206 can be configured to select the first cache for the memory access request from the processor 201 when the configurable data bit is in the second state and the connection 204d to the execution type signal line 205d receives an indication of the second type.

[0128] Figure 3A Particular aspects of an example computing device including a cache system (e.g., cache system 200) having multiple caches (e.g., see caches 302 and 304) are shown. The example computing device is also shown as having a register 306 storing data 312 that can include a configurable bit. The register 306 can be connected to or part of the logic circuit 206. In Figure 3A In the first time instance ("time instance X"), the register 306 is shown as storing data 312 that can be a configurable bit in a first state. Content 308a received from a first cache (e.g., cache 302) during the first time instance includes content for a first type of execution. Also, content 310a received from a second cache (e.g., cache 304) during the first time instance includes content for a second type of execution.

[0129] Figure 3B Particular aspects of an example computing device including a cache system (e.g., cache system 200) having multiple caches (e.g., see caches 302 and 304) are shown. The example computing device is also shown as having a register 306 storing data 314 that can include a configurable bit. The register 306 can be connected to or part of the logic circuit 206. In Figure 3BIn particular, it is shown that during a second time instance ("time instance Y"), the register 306 stores data 314 that can be a configurable bit in a second state. The content 308b received from the first cache (e.g., cache 302) during the second time instance includes content for the second type of execution. Also, the content 310b received from the second cache (e.g., cache 304) during the second time instance includes content for the first type of execution.

[0130] The illustrated line 320 connecting the register 306 to the caches 302 and 304 can be part of the logic circuit 206.

[0131] In some embodiments, instead of using a configurable bit to control the use of the caches of the cache system 200, another form of data can be used to control the use of the caches of the cache system. For example, the logic circuit 206 can be configured to control the first cache (e.g., see cache 202a) and the second cache (e.g., see cache 202b) based on different data stored in the register 306 that is not a configurable bit. In such an example, when the register 306 stores first data or is in a first state, the logic circuit can be configured to: when the type of execution is the first type, implement commands received from the command bus for accessing the memory system via the first cache; and when the type of execution is the second type, implement commands received from the command bus for accessing the memory system via the second cache. Also, when the register 306 stores second data or is in a second state, the logic circuit can be configured to: when the type of execution is the first type, implement commands received from the command bus for accessing the memory system via the second cache; and when the type of execution is the second type, implement commands received from the command bus for accessing the memory system via the first cache.

[0132] Figure 4 、 5A And 5B shows example aspects of example computing devices that each include a cache system having interchangeable caches for main or normal type execution (e.g., non-speculative execution) and speculative execution, in accordance with some embodiments of the present disclosure.

[0133] Figure 4 In particular, aspects of example computing devices that include a cache system having multiple caches (e.g., see caches 202a, 202b, and 202c) depicted in Figure 4 In particular, aspects of example computing devices that include a cache system having multiple caches (e.g., see caches 202a, 202b, and 202c) depicted in Figure 4 In particular, aspects of example computing devices that include a cache system having multiple caches (e.g., see caches 202a, 202b, and 202c) depicted in Figure 4As shown, cache system 400 is similar to cache system 200, but cache system 400 also includes a connection 402 to a speculative state signal line 404 from processor 401 that identifies the state of speculative execution of instructions by processor 401.

[0134] Similarly, cache system 400 is shown as including connection 204a to command bus 205a coupled between cache system and processor 401. System 400 also includes connection 204b to address bus 205b coupled between cache system and processor 401. (The last two sentences appear to be incomplete and possibly unrelated to the preceding text.) Figure 1A , 1B Addresses 102a, 102b, 102c, 102d, and 102e, as depicted in 1C, 1D, and 1E, may be communicated via address bus 205b, depending on the implementation of cache system 400. System 400 also includes a connection 204c to data bus 205c coupled between cache system and processor 401. It also includes a connection 204d to execution type signal line 205d from processor 401 that identifies non-speculsive or speculative execution types. (Not shown in...) Figure 4 As shown in the diagram, the cache system 400 may also include configurable data bits. These configurable data bits may be included in the diagram shown in the diagram. Figure 5A The data 312 in the first state may be the data 312 mentioned above, and may be included in the data displayed in Figure 5B The data 314 in the second state may be the data 314.

[0135] In some embodiments, the cache system 400 may include a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b). In such embodiments, as Figure 4 As shown, cache system 400 may include logic circuitry 406 coupled to processor 401. Furthermore, in this embodiment, logic circuitry 406 may be configured to control a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b) based on configurable data bits. When the configurable data bits are in a first state (e.g., see...), Figure 5A As depicted in data 312), logic circuit 406 can be configured to: execute commands received from command bus 205a for accessing memory system 203 via first cache when the execution type is non-speculsive; and execute commands received from command bus 205a for accessing memory system 203 via second cache when the execution type is speculative. When the configurable data bit is in the second state (e.g., see...), Figure 5BThe logic circuit 406 can be configured to implement commands received from the command bus 205a for accessing the memory system 203 via the second cache when the type of execution is of the non-speculative type, as depicted in the data 314. Further, the logic circuit 406 can be configured to implement commands received from the command bus 205a for accessing the memory system 203 via the first cache when the type of execution is of the speculative type, as depicted in the data 314. Figure 5B The logic circuit 406 can be configured to implement commands received from the command bus 205a for accessing the memory system 203 via the second cache when the type of execution is of the non-speculative type, as depicted in the data 314. Further, the logic circuit 406 can be configured to implement commands received from the command bus 205a for accessing the memory system 203 via the first cache when the type of execution is of the speculative type, as depicted in the data 314.

[0136] In some embodiments, for example Figure 4 As shown in the data 314, the first type can be configured to indicate non-speculative execution of instructions by the processor. In such an example, the second type can be configured to indicate speculative execution of instructions by the processor. In such an embodiment, the cache system 400 can further include a connection 402 to a speculation status signal line 404 from the processor 401 identifying a status of speculative execution of instructions by the processor. The connection 402 to the speculation status signal line 404 can be configured to receive the status of speculative execution, and the status of speculative execution can indicate whether results of speculative execution are to be accepted or rejected.

[0137] Further, the logic circuit 406 of the system 400 can be configured to toggle the configurable data bit if the status of speculative execution indicates that results of speculative execution are to be accepted, when the type of execution changes from the second type or the speculative type to the first type or the non-speculative type. Additionally, the logic circuit 406 of the system 400 can be configured to maintain the configurable data bit without changing if the status of speculative execution indicates that results of speculative execution are to be rejected, when the type of execution changes from the second type or the speculative type to the first type or the non-speculative type.

[0138] Figure 5A Particular aspects include example computing devices including a cache system (e.g., the cache system 400) having a plurality of caches (e.g., see the caches 302 and 304). The example computing devices are also shown as having a register 306 storing data 312 that can include a configurable bit. In Figure 5A In the first time instance ("time instance X"), the register 306 is shown as storing data 312 that can be a configurable bit in a first state. This is similar to Figure 3A The difference is that the content 502a received from the first cache (e.g., the cache 302) during the first time instance includes content for non-speculative execution. Also, the content 504a received from the second cache (e.g., the cache 304) during the first time instance includes content for speculative execution.

[0139] Figure 5BParticular aspects are shown of an example computing device that includes a cache system (e.g., cache system 400) having multiple caches (e.g., see caches 302 and 304). The example computing device is also shown as having a register 306 that stores data 314 that can include a configurable bit. In Figure 5B In particular, during a second time instance ("time instance Y"), register 306 stores data 314 that can be the configurable bit in a second state. This is similar to Figure 3B except that content 502b received from the first cache (e.g., cache 302) during the second time instance includes content for speculative execution. Also, content 504b received from the second cache (e.g., cache 304) during the second time instance includes content for non-speculative execution.

[0140] Further, similarly, in Figure 5A and 5B The illustrated line 320 connecting register 306 to caches 302 and 304 can be part of logic circuit 406 of cache system 400.

[0141] In some embodiments, instead of using a configurable bit to control use of the caches of cache system 400, another form of data can be used to control use of the caches of cache system 400. For example, logic circuit 406 in system 400 can be configured to control a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b) based on different data stored in register 306 that is not a configurable bit. In such an example, when register 306 stores first data or is in a first state, the logic circuit can be configured to implement commands received from a command bus for accessing a memory system via the first cache when the type of execution is of a non-speculative type and to implement commands received from the command bus for accessing the memory system via the second cache when the type of execution is of a speculative type. Also, when register 306 stores second data or is in a second state, the logic circuit can be configured to implement commands received from the command bus for accessing the memory system via the second cache when the type of execution is of a non-speculative type and to implement commands received from the command bus for accessing the memory system via the first cache when the type of execution is of a speculative type.

[0142] Some embodiments can include a cache system and the cache system can include a plurality of caches including a first cache and a second cache. The system can also include a connection to a command bus configured to receive a read command or a write command from a processor connected to the cache system for reading from or writing to a memory system. The system can also include a connection to an address bus configured to receive a memory address from the processor for accessing the memory system for the read command or the write command. The system can also include a connection to a data bus configured to: communicate data to the processor for the processor to read data for the read command; and receive data from the processor for writing in the memory system for the write command. In such an example, the memory access request from the processor and the memory used by the processor can be defined by the command bus, the address bus, and the data bus. The system can also include an identified execution type signal line configured to receive an execution type from the processor. The execution type is a first execution type or a second execution type (e.g., normal or non-speculative execution or speculative execution).

[0143] The system can also include a configurable data bit configured to be set to a first state (e.g., “0”) or a second state (e.g., “1”) to control selection of the first cache and the second cache for use by the processor.

[0144] The system can also include a logic circuit configured to select the first cache for use by the processor when the configurable data bit is in the first state and the execution type signal line receives an indication of the first type of execution. The logic circuit can also be configured to select the second cache for use by the processor when the configurable data bit is in the first state and the execution type signal line receives an indication of the second type of execution. The logic circuit can also be configured to select the second cache for use by the processor when the configurable data bit is in the second state and the execution type signal line receives an indication of the first type of execution. The logic circuit can also be configured to select the first cache for use by the processor when the configurable data bit is in the second state and the execution type signal line receives an indication of the second type of execution.

[0145] In some embodiments, the first type of execution is a speculative execution of instructions by the processor and the second type of execution is a non-speculative execution of instructions by the processor (e.g., normal or main execution). In such an example, the system can further include a connection to a speculation state signal line configured to receive a speculation state from the processor. The speculation state can be an acceptance or rejection of a condition with a nested instruction that is initially executed by a speculative execution of the processor and subsequently executed by a normal execution of the processor when the speculation state is an acceptance of the condition.

[0146] In some embodiments, the logic circuit is configured to swap the configurable data bit from a first state to a second state when the speculation status received by the speculation status signal line is an acceptance of the condition. The logic circuit can also be configured to maintain the state of the configurable data bit when the speculation status received by the speculation status signal line is a rejection of the condition.

[0147] In some embodiments, the logic circuit is configured to select the second cache as identified by the first state of the configurable data bit and restrict use of the first cache as identified by the first state of the configurable data bit when the signal received by the execution type signal line changes from an indication of normal execution to an indication of speculative execution. The speculation status can be ignored / bypassed by the logic circuit under this change because the processor is not aware in the speculative execution whether the instructions previously formed under the speculative execution should be executed by the main execution.

[0148] The logic circuit can also be configured to maintain the first state of the configurable data bit and select the first cache for memory access requests when the execution type signal line receives an indication of normal execution, when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of normal execution, and when the speculation status received by the speculation status signal line is a rejection of the condition.

[0149] In some embodiments, the logic circuit is configured to invalidate and discard the contents of the second cache when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of normal execution and when the speculation status received by the speculation status signal line is a rejection of the condition.

[0150] In some embodiments, the system further includes a connection to a second command bus configured to communicate a read command or a write command to a memory system (e.g., including a main memory). The read command or the write command can be received by the cache system from the processor. The system can also include a connection to a second address bus configured to communicate a memory address to the memory system. The memory address can be received by the cache system from the processor. The system can also include a connection to a second data bus configured to: communicate data to the memory system for writing in the memory system; and receive data from the memory system for communication to the processor for reading by the processor. For example, a memory access request from the cache system to the memory system can be defined by the second command bus, the second address bus, and the second data bus.

[0151] In some embodiments, when the configurable data bit is in a first state, the logic circuit is configured to: provide commands for accessing the memory system via the first cache to the second command bus when the type of execution is of a first type; and provide commands for accessing the memory system via the second cache to the second command bus when the type of execution is of a second type. And, when the configurable data bit is in a second state, the logic circuit is configurable to: provide commands for accessing the memory system via the second cache to the second command bus when the type of execution is of the first type; and provide commands for accessing the memory system via the first cache to the second command bus when the type of execution is of the second type.

[0152] Some embodiments can include a system including a processor, a memory system, and a cache system coupled between the processor and the memory system. The cache system of the system can include a plurality of caches including a first cache and a second cache. The cache system of the system can also include a connection to a command bus coupled between the cache system and the processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, and a connection to an execution type signal line from the processor identifying a type of execution.

[0153] The cache system of the system can also include a configurable data bit, and a logic circuit coupled to the processor to control the first cache and the second cache based on the configurable data bit. When the configurable data bit is in a first state, the logic circuit is configurable to: implement commands received from the command bus for accessing the memory system via the first cache when the type of execution is of a first type; and implement commands received from the command bus for accessing the memory system via the second cache when the type of execution is of a second type. And, when the configurable data bit is in a second state, the logic circuit is configurable to: implement commands received from the command bus for accessing the memory system via the second cache when the type of execution is of the first type; and implement commands received from the command bus for accessing the memory system via the first cache when the type of execution is of the second type.

[0154] In such a system, the first type can be configured to indicate non-speculative execution of instructions by the processor, and the second type can be configured to indicate speculative execution of instructions by the processor. Further, the cache system of the system can further include a connection to a speculation status signal line from the processor that identifies a status of speculative execution of instructions by the processor. The connection to the speculation status signal line can be configured to receive a status of speculative execution, and the status of speculative execution can indicate whether results of speculative execution are to be accepted or rejected. The logic circuit can be configured to toggle the configurable data bit if the status of speculative execution indicates that results of speculative execution are to be accepted, when the execution type changes from the second type (speculative type) to the first type (non-speculative type). Also, the logic circuit can be configured to maintain the configurable data bit without changing if the status of speculative execution indicates that results of speculative execution are to be rejected, when the execution type changes from the second type (speculative type) to the first type (non-speculative type).

[0155] Figure 6 、 7A , 7B, 8A, 8B, 9A, and 9B illustrate example aspects of example computing devices that each include a cache system having interchangeable cache sets for first and second type execution (e.g., for implementing shadow cache techniques with enhanced security and / or for main and speculative type execution) in accordance with some embodiments of the present disclosure.

[0156] Figure 6 Particularly, aspects of example computing devices are illustrated that include a cache system 600 having a plurality of caches (see, e.g., caches 602a, 602b, and 602c), where at least one of the caches implements cache set associativity. The example computing devices are also illustrated as having a processor 601 and a memory system 603. The cache system 600 is configured to be coupled between the processor 601 and the memory system 603.

[0157] The cache system 600 is illustrated as including a connection 604a to a command bus 605a that is coupled between the cache system and the processor 601. The cache system 600 is illustrated as including a connection 604b to an address bus 605b that is coupled between the cache system and the processor 601. The connections 604a and 604b are configured to receive commands and addresses, respectively, from the processor 601. Figure 1A 、 1BThe addresses 102a, 102b, 102c, 102d, and 102e depicted in 1C, 1D, and 1E can each be communicated via an address bus 605b depending on the implementation of the cache system 600. The cache system 600 is shown to include a connection 604c to a data bus 605c coupled between the cache system and the processor 601. The cache system 600 is also shown to include a connection 604d to an execution type signal line 605d from the processor 601 identifying an execution type. The connections 604a, 604b, 604c, and 604d can provide communicative coupling between the buses 605a, 605b, 605c, and 605d and the logic circuit 606 of the cache system 600.

[0158] Furthermore, as shown in Figure 6 The cache system 600 is further shown to include a connection 608a to a second command bus 609a coupled between the cache system and the memory system 603. The cache system 600 is also shown to include a connection 608b to a second address bus 609b coupled between the cache system and the memory system 603. The cache system 600 is also shown to include a connection 608c to a second data bus 609c coupled between the cache system and the memory system 603.

[0159] The cache system 600 also includes a plurality of cache sets (see, e.g., cache sets 610a, 610b, and 610c). The cache sets can include a first cache set (see, e.g., cache set 610a) and a second cache set (see, e.g., cache set 610b).

[0160] Furthermore, as shown in Figure 6 The cache system 600 is further shown to include a plurality of registers (see, e.g., registers 612a, 612b, and 612c) associated with the plurality of cache sets, respectively. The registers (or cache set registers) can include a first register (see, e.g., register 612a) associated with the first cache set (see, e.g., cache set 610a) and a second register (see, e.g., register 612a) associated with the second cache set (see, e.g., cache set 610b). Each of the plurality of registers (see, e.g., registers 612a, 612b, and 612c) can be configured to store a set index.

[0161] As Figure 6 and Figure 10As shown in the middle, caches 602a and 602b through 602c (caches 1 through N) are not fixed structures. However, it should be understood that in some embodiments, the caches can be fixed structures. Each of the depicted caches can be considered a logical grouping of cache sets, and such logical groupings are shown by the dashed lines representing each logical cache. Cache sets 610a through 610c (cache sets 1 through N) can be based on the contents of registers 610a through 610c (registers 1 through N). Cache sets 1 through N can be a set of cache sets within a cache system that are shared among cache 1 and caches 2 through N. Cache 1 can be a subset of the set; cache 2 can be another non-overlapping subset. The member cache sets in each of the caches can change based on the contents in registers 1 through N.

[0162] Depending on the embodiment, cache set 1 (in the conventional sense) can or can not communicate with its register 1. The dashed lines also show the logical relationship between Figure 7A , 7B , 8A, 8B, 9A, and 9B to indicate the logical relationship between a cache set and Figure 7A , 7B , 8A, 8B, 9A, and 9B. The contents of register 1 determine how to address cache set 1 (e.g., what cache set index will cause cache set 1 to be selected to output data). In some embodiments, there is no direct interaction between cache set 1 and its corresponding register 1. Depending on the embodiment, logic circuit 606 or 1006 interacts with both the cache set and the corresponding register.

[0163] In some embodiments, the logic circuit 606 can be coupled to the processor 601 to control a plurality of cache sets (e.g., cache sets 610a, 610b, and 610c) from a plurality of registers (e.g., registers 612a, 612b, and 612c). In such embodiments, the cache system 600 can be configured to be coupled between the processor 601 and the memory system 603. Also, when the connection 604b to the address bus 605b receives a memory address from the processor 601, the logic circuit 606 can be configured to generate a set index from at least the memory address, and determine whether the generated set index matches contents stored in a first register (e.g., register 612a) or contents stored in a second register (e.g., register 612b). The logic circuit 606 can also be configured to implement a command received in the connection 604a to the command bus 605a via a first cache set (e.g., cache set 610a) in response to the generated set index matching the contents stored in the first register (e.g., register 612a), and implement the command via a second cache set (e.g., cache set 610b) in response to the generated set index matching the contents stored in the second register (e.g., register 612b).

[0164] In some embodiments, the cache system 600 can include a first cache (e.g., see cache 602a) and a second cache (e.g., see cache 602b). In such embodiments, as shown in Figure 2 In some embodiments, the cache system 600 can include a first cache (e.g., see cache 602a) and a second cache (e.g., see cache 602b). In such embodiments, as shown in

[0165] In some embodiments, in response to determining that the data set of the memory system 603 associated with the memory address is not currently cached in the cache system 600 (e.g., not cached in the cache 602a of the system), the logic circuit 606 is configured to allocate a first cache set (e.g., cache set 610a) for caching the data set and store the generated set index in a first register (e.g., register 612a). In such embodiments and other embodiments, the cache system can include a connection (e.g., connection 604d) with an execution type signal line from a processor (e.g., processor 601) that identifies a type of execution. Also, in such embodiments and other embodiments, the generated set index is generated based further on the type identified by the execution type signal line. Moreover, the generated set index can include a predetermined segment of bits in the memory address and a bit that represents the type identified by the execution type signal line 605d.

[0166] Moreover, when the first and second registers (e.g., registers 612a and 612b) are in the first state, the logic circuit 606 can be configured to implement a command received from the command bus 605a for accessing the memory system 601 via the first cache set (e.g., cache set 610a) when the type of execution is the first type. Also, when the first and second registers (e.g., registers 612a and 612b) are in the first state, the logic circuit 606 can be configured to implement a command received from the command bus 605a for accessing the memory system 601 via the second cache set (e.g., cache set 610b) when the type of execution is the second type.

[0167] Moreover, when the first and second registers (e.g., registers 612a and 612b) are in the second state, the logic circuit 606 can be configured to implement a command received from the command bus 605a for accessing the memory system 601 via another cache set (e.g., cache set 610b or 610c) of the plurality of cache sets other than the first cache set when the type of execution is the first type. Also, when the first and second registers (e.g., registers 612a and 612b) are in the second state, the logic circuit 606 can be configured to implement a command received from the command bus 605a for accessing the memory system 601 via another cache set (e.g., cache set 610a or 610c, or Figure 6 another cache set of the plurality of cache sets other than the second cache set when the type of execution is the second type.

[0168] In some embodiments, each of the plurality of registers (see, e.g., registers 612a, 612b, and 612c) can be configured to store a set index, and when the type of execution changes from the second type to the first type (e.g., from non-speculative type of execution to speculative type of execution), the logic circuit 606 can be configured to change the contents stored in the first register (e.g., register 612a) and the contents stored in the second register (e.g., register 612b). Examples of the change in the contents stored in the first register (e.g., register 612a) and the contents stored in the second register (e.g., register 612b) are described in Figure 7A and 7B , Figure 8A and 8B and Figure 9A and 9B .

[0169] Figure 7A , 7B Each of 8A, 8B, 9A, and 9B specifically illustrate aspects of example computing devices that include a cache system having a plurality of cache sets (see, e.g., caches 702, 704, and 706), where the cache sets are implemented via cache set associativity. The respective cache systems of each of these figures are also shown as having a plurality of registers associated with the cache sets, respectively. The plurality of registers includes at least register 712, register 714, and register 716. The plurality of registers includes at least one additional register that is not shown in the figures. Register 712 is shown as being associated with or connected to cache set 702, register 714 is shown as being associated with or connected to cache set 704, and register 716 is shown as being associated with or connected to cache set 706.

[0170] Not shown in Figure 7A , 7B Each of the respective cache systems can also include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, and a connection to a data bus coupled between the cache system and the processor, not shown in 8A, 8B, 9A, and 9B. Each of the cache systems can also include a logic circuit coupled to the processor to control the plurality of cache sets (e.g., cache sets 702, 704, and 706) according to the plurality of registers (e.g., registers 712, 714, and 716).

[0171] As shown by Figure 7A , 7BAs illustrated in 8A, 8B, 9A, and 9B, when the connection to the address bus of the cache system receives a memory address from the processor (e.g., see memory address 102b, 102c, or 102d), the logic circuitry of the cache system can be configured to generate a set index from the memory address (e.g., see set index 722, 724, 726, or 728) (e.g., see set index generation 730, 732, 830, 832, 930, or 932).

[0172] Specifically, such as Figure 7A As shown, at least registers 712, 714, and 716 are configured in a first state. When the address bus connection to the cache system receives memory address 102b from the processor, the cache system's logic circuitry generates set indices 722, 724, or 726 based on at least set index generation 730a, 730b, or 730c and an entry in cache set index 112b for address 102b. Set index generation 730a, 730b, or 730c can be used to store set indices 722, 724, or 726 in registers 712, 714, or 716, respectively. Set index generation 730a, 730b, or 730c can also be used to compare the most recently generated set index with the contents already stored in registers 712, 714, or 716, respectively. Set index generation 730a, 730b, and 730c occur when the registers are configured in the first state. The configuration of the first state can be achieved through set index generation and storage.

[0173] Specifically, such as Figure 7B As shown, at least registers 712, 714, and 716 are configured in a second state. When the address bus connection to the cache system receives memory address 102b from the processor, the cache system's logic circuitry generates set indices 726, 722, or 728 based on at least set index generation 732a, 732b, or 732c and an entry in cache set index 112b for address 102b. Set index generation 732a, 732b, or 732c can be used to store set indices 726, 722, or 728 in registers 712, 714, or 716, respectively. Set index generation 732a, 732b, or 732c can also be used to compare the most recently generated set index with the contents already stored in registers 712, 714, or 716, respectively. Set index generation 732a, 732b, and 732c occur when the registers are configured in the second state. The configuration of the second state can be achieved through set index generation and storage.

[0174] Specifically, such as Figure 8AAs shown in the middle, at least registers 712, 714, and 716 are configured in the first state. When a connection with an address bus of the cache system receives a memory address 102c from a processor, logic circuitry of the cache system generates 830a, 830b, or 830c a set index 722, 724, or 726, respectively, from at least a set index and an instance of tag 104c of address 102b with a cache set indicator. Set index generation 830a, 830b, or 830c can be used to store set index 722, 724, or 726 in register 712, 714, or 716, respectively. Set index generation 830a, 830b, or 830c can also be used to use a most recently generated set index in a comparison of the most recently generated set index with contents already stored in register 712, 714, or 716, respectively. Set index generation 830a, 830b, and 830c occurs when the registers are configured in the first state.

[0175] In particular, as Figure 8B As shown in the middle, at least registers 712, 714, and 716 are configured in the first state. When a connection with an address bus of the cache system receives a memory address 102c from a processor, logic circuitry of the cache system generates 830a, 830b, or 830c a set index 722, 724, or 726, respectively, from at least a set index and an instance of tag 104c of address 102b with a cache set indicator. Set index generation 830a, 830b, or 830c can be used to store set index 722, 724, or 726 in register 712, 714, or 716, respectively. Set index generation 830a, 830b, or 830c can also be used to use a most recently generated set index in a comparison of the most recently generated set index with contents already stored in register 712, 714, or 716, respectively. Set index generation 830a, 830b, and 830c occurs when the registers are configured in the first state.

[0176] In particular, as Figure 9AAs shown in FIG. 7, at least registers 712, 714, and 716 are configured in the first state. When a connection to the address bus of the cache system receives a memory address 102d from the processor, logic circuitry of the cache system generates a set index 722, 724, or 726 from at least a set index generation 930a, 930b, or 930c and an instance of the cache set index 112d in the tag 104d of the address 102b, respectively. The set index generation 930a, 930b, or 930c can be used to store the set index 722, 724, or 726 in the register 712, 714, or 716, respectively. The set index generation 930a, 930b, or 930c can also be used to use the most recently generated set index in a comparison of the most recently generated set index to the contents already stored in the register 712, 714, or 716, respectively. The set index generation 930a, 930b, and 930c occurs when the registers are configured in the first state.

[0177] In particular, as Figure 7B As shown in FIG. 7, at least registers 712, 714, and 716 are configured in the first state. When a connection to the address bus of the cache system receives a memory address 102d from the processor, logic circuitry of the cache system generates a set index 722, 724, or 726 from at least a set index generation 930a, 930b, or 930c and an instance of the cache set index 112d in the tag 104d of the address 102b, respectively. The set index generation 930a, 930b, or 930c can be used to store the set index 722, 724, or 726 in the register 712, 714, or 716, respectively. The set index generation 930a, 930b, or 930c can also be used to use the most recently generated set index in a comparison of the most recently generated set index to the contents already stored in the register 712, 714, or 716, respectively. The set index generation 930a, 930b, and 930c occurs when the registers are configured in the first state.

[0178] In some embodiments of the cache system implementations described in Figure 7A and 7B When a connection to the address bus receives a memory address from the processor, the logic circuitry can be configured to determine whether the generated set index matches the contents stored in one of the registers (e.g., registers 712, 714, and 716). The contents stored in the registers can be from a previous generation of the set index and storage of the set index in the registers.

[0179] In addition, in some embodiments of the cache system implementations described in Figure 7A and 7BIn some embodiments of the cache system implementations described in 8A and 8B or 9A and 9B, the logic circuitry may be configured to execute a command received in a connection to a command bus via a first cache set in response to a generated set index matching the contents stored in an associated first register, and to execute the command via a second cache set in response to a generated set index matching the contents stored in an associated second register. Furthermore, in response to determining that a dataset of the memory system associated with a memory address is not currently cached in the cache system, the logic circuitry may be configured to allocate a first cache set for caching the dataset and store the generated set index in a first register. The generated set index may contain a predetermined segment of bits in the memory address.

[0180] Furthermore, in this embodiment, when the first and second registers are in a first state, the logic circuitry can be configured to: implement commands received from the command bus for accessing the memory system via a first cache set when the processor's execution type is a first type; and implement commands received from the command bus for accessing the memory system via a second cache set when the execution type is a second type. Furthermore, when the first and second registers are in a second state, the logic circuitry can be configured to: implement commands received from the command bus for accessing the memory system via another cache set other than the first cache set when the execution type is a first type; and implement commands received from the command bus for accessing the memory system via yet another cache set other than the second cache set when the execution type is a second type. In this example, each of the multiple registers can be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuitry can be configured to change the contents stored in the first register and the contents stored in the second register.

[0181] Figure 10 Specifically, it displays content that includes multiple caches (for example, see...). Figure 10 This relates to an instance computing device aspect of the cache system 1000 (depicted in the diagram as caches 602a, 602b, and 602c), wherein at least one of the caches is implemented with cache set associativity (e.g., see cache sets 610a, 610b, and 601c). Figure 10 In the example, the computing device is also shown to have a processor 1001 and a memory system 603. (As shown by...) Figure 10The illustrated cache system 1000 is similar to the cache system 600, but the cache system 1000 also includes a connection 1002 to a speculation status signal line 1004 from the processor 1001 that identifies a state of speculative execution of instructions by the processor 1001.

[0182] Similarly, the cache system 1000 is illustrated as including a connection 604a to a command bus 605a coupled between the cache system and the processor 1001. The system 1000 also includes a connection 604b to an address bus 605b coupled between the cache system and the processor 1001. The addresses 102a, 102b, 102c, 102d, and 102e depicted in 1A, IB, 1C, ID, and IE, respectively, can be communicated via the address bus 605b, depending on the implementation of the cache system 1000. Figure 1A 、 1B The addresses 102a, 102b, 102c, 102d, and 102e depicted in 1A, IB, 1C, ID, and IE, respectively, can be communicated via the address bus 605b, depending on the implementation of the cache system 1000. The system 1000 also includes a connection 604c to a data bus 605c coupled between the cache system and the processor 1001. It also includes a connection 604d to an execution type signal line 605d from the processor 1001 that identifies a non-speculative or a speculative type of execution.

[0183] Similarly, the cache system 1000 is also illustrated as including a logic circuit 1006 that can be similar to the logic circuit 606, but its circuitry is coupled to the connection 1002 to the speculation status signal line 1004.

[0184] In some embodiments, the logic circuit 1006 can be coupled to the processor 1001 to control a plurality of cache sets (e.g., cache sets 610a, 610b, and 610c) from a plurality of registers (e.g., registers 612a, 612b, and 612c). Each of the plurality of registers (see, e.g., registers 612a, 612b, and 612c) can be configured to store a set index.

[0185] In such embodiments, the cache system 1000 can be configured to be coupled between the processor 1001 and the memory system 603. Also, when the connection 604b to the address bus 605b receives a memory address from the processor 1001, the logic circuit 1006 can be configured to generate a set index from at least the memory address, and determine whether the generated set index matches the contents stored in the first register (e.g., register 612a) or the contents stored in the second register (e.g., register 612b). The logic circuit 1006 can also be configured to implement a command received in the connection 604a to the command bus 605a via the first cache set (e.g., cache set 610a) in response to the generated set index matching the contents stored in the first register (e.g., register 612a), and implement the command via the second cache set (e.g., cache set 610b) in response to the generated set index matching the contents stored in the second register (e.g., register 612b).

[0186] Further, the cache system 1000 is shown to include connections 608a, 608b, and 608c similar to the corresponding connections shown in Figure 6 Figure 6 and 10 With the connections 608a, 608b, and 608c depicted in

[0187] Further, when the first and second registers (e.g., registers 612a and 612b) are in the first state, the logic circuit 606 or 1006 can be configured to provide commands for accessing the memory system 603 via the first cache set (e.g., cache set 610a) to the second command bus 609a when the type of execution is the first type (e.g., non-speculative type). Also, when the first and second registers (e.g., registers 612a and 612b) are in the first state, the logic circuit 606 or 1006 can be configured to provide commands for accessing the memory system via the second cache set (e.g., cache set 610b) to the second command bus 609a when the type of execution is the second type (e.g., speculative type). Figure 6 ​commands for accessing the memory system 603 via another cache set not depicted in FIG. 10 (e.g., cache set 610b or 610d) are provided to the second command bus 609a. Further, when the first and second registers (e.g., registers 612a and 612b) are in the second state, the logic circuit 606 or 1006 can be configured to change the contents stored in the first register (e.g., register 612a) and the contents stored in the second register (e.g., register 612b) when the type of execution is changed from the first type to the second type. Figure 6 commands for accessing the memory system 603 via another cache set not depicted in FIG. 10 (e.g., cache set 610b or 610d) are provided to the second command bus 609a.

[0188] In some embodiments, such as shown in FIG. 10, the first type can be configured to indicate non-speculative execution of instructions by the processor 1001; and the second type can be configured to indicate speculative execution of instructions by the processor. In FIG. 10, the first register (e.g., register 612a) is coupled to the first command bus 609b, and the second register (e.g., register 612b) is coupled to the second command bus 609a. Figure 10 In some embodiments, such as shown in FIG. 10, the first type can be configured to indicate non-speculative execution of instructions by the processor 1001; and the second type can be configured to indicate speculative execution of instructions by the processor. In FIG. 10, the first register (e.g., register 612a) is coupled to the first command bus 609b, and the second register (e.g., register 612b) is coupled to the second command bus 609a. Figure 10 In FIG. 10, the cache system 1000 further includes a connection 1002 to a speculation status signal line 1004 from the processor 1001 identifying a status of speculative execution of instructions by the processor. The connection 1002 to the speculation status signal line 1004 can be configured to receive the status of speculative execution, and the status of speculative execution can indicate whether the results of speculative execution are to be accepted or rejected.

[0189] In such embodiments, each of the plurality of registers (e.g., registers 612a, 612b, and 612c) can be configured to store a set index, and when the type of execution is changed from the speculative execution type to the non-speculative type, the logic circuit 1006 can be configured to change the contents stored in the first register (e.g., register 612a) and the contents stored in the second register (e.g., register 612b) if the status of execution of the speculative type indicates that the results of speculative execution are to be accepted. Also, when the type of execution is changed from the speculative type to the non-speculative type, the logic circuit 1006 can be configured to maintain the contents stored in the first register and the contents stored in the second register without change if the status of execution of the speculative type indicates that the results of execution of the speculative type are to be rejected.

[0190] Some embodiments can include a cache system including a plurality of cache sets having at least a first cache set and a second cache set. The cache system can also include a plurality of registers associated with the plurality of cache sets, respectively. The plurality of registers can include at least a first register associated with the first cache set configured to store a set index and a second register associated with the second cache set configured to store a set index. The cache system can also include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, and a connection to an execution type signal line from the processor identifying an execution type.

[0191] The cache system can also include a logic circuit coupled to the processor to control the plurality of cache sets according to the plurality of registers. Also, the cache system can be configured to be coupled between the processor and a memory system. When the first and second registers are in a first state, the logic circuit can be configured to implement a command received from the command bus for accessing the memory system via the first cache set when the execution type is a first type and to implement a command received from the command bus for accessing the memory system via the second cache set when the execution type is a second type. Further, when the first and second registers are in a second state, the logic circuit can be configured to implement a command received from the command bus for accessing the memory system via another cache set of the plurality of cache sets other than the first cache set when the execution type is the first type and to implement a command received from the command bus for accessing the memory system via another other cache set of the plurality of cache sets other than the second cache set when the execution type is the second type.

[0192] The connection to the address bus can be configured to receive a memory address from the processor, and the memory address can include a set index.

[0193] In some embodiments, when the first and second registers are in the first state, a first set index associated with the first cache set is stored in the first register and a second set index associated with the second cache set is stored in the second register. When the first and second registers are in the second state, the first set index can be stored in another register of the plurality of registers other than the first register and the second set index can be stored in another register of the plurality of registers other than the second register. In such an instance, when a connection with the address bus receives a memory address from the processor, the logic circuit can be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches the contents stored in the first register or the contents stored in the second register. And, the logic circuit can be further configured to implement a command received in a connection with the command bus via the first cache set in response to the generated set index matching the contents stored in the first register and implement the command via the second cache set in response to the generated set index matching the contents stored in the second register.

[0194] In response to determining that a data set of the memory system associated with the memory address is not currently cached in the cache system, the logic circuit can be configured to allocate the first cache set for caching the data set and store the generated set index in the first register.

[0195] In some embodiments, the generated set index is further based on an execution type identified by the execution type signal line. In such an instance, the generated set index can include a predetermined segment of bits in the memory address and a bit representing the execution type identified by the execution type signal line.

[0196] Some embodiments can include a system including a processor, a memory system, and a cache system. The cache system can include: a plurality of cache sets including a first cache set and a second cache set; and a plurality of registers associated with the plurality of cache sets, respectively, including a first register associated with the first cache set and a second register associated with the second cache set. The cache system can also include a connection with a command bus coupled between the cache system and the processor, a connection with an address bus coupled between the cache system and the processor, and a connection with a data bus coupled between the cache system and the processor.

[0197] The cache system can further include a logic circuit coupled to the processor to control the plurality of cache sets in accordance with a plurality of registers. When a connection to the address bus receives a memory address from the processor, the logic circuit can be configured to generate a set index from at least the memory address, and determine whether the generated set index matches contents stored in a first register or matches contents stored in a second register. Also, the logic circuit can be configured to implement a command received in a connection to the command bus via a first cache set in response to the generated set index matching the contents stored in the first register, and implement the command via a second cache set in response to the generated set index matching the contents stored in the second register.

[0198] The cache system can further include a connection to an execution type signal line from the processor that identifies a type of execution. The generated set index can be further generated based on the type identified by the execution type signal line. The generated set index can include a predetermined segment of bits in the memory address and a bit that represents the type identified by the execution type signal line.

[0199] Figure 11A and 11B A background synchronization circuitry is described for synchronizing content between a primary cache and a shadow cache to save content cached in the primary cache for a background synchronization of the content in the shadow cache in accordance with some embodiments of the present disclosure. Figure 11A and 11B The cache system in 1000 includes a background synchronization circuitry 1102. For example, the cache 1124 and the cache 1126 can be Figure 2 the caches 202a and 202b in 2000, or Figure 6 the caches 602a and 602b in 6000. The background synchronization circuitry 1102 can be part of the logic circuit 206, 406, 606, or 1006.

[0200] Figure 11AThe context in which cache 1124 is used as a main cache in non-speculative execution and cache 1126 is used as a shadow cache in speculative execution is described. Background synchronization circuitry 1102 is configured to synchronize 1130 the contents of the cache from cache 1124 to cache 1126 so that if it is determined that conditional speculative execution is needed, cache 1126 can be used as a main cache in subsequent non-speculative execution; and cache 1124 can be used as a shadow cache in further instances of speculative execution. Synchronizing 1130 the contents of the cache from cache 1124 to cache 1126 copies the results of the previous execution into cache 1126 so that the results of the execution are not lost when cache 1124 is later repurposed as a shadow cache. The contents of the cache from cache 1124 can be cached in cache 1124, but not yet flushed to memory (e.g., memory 203 or 603). Additionally, some of the memory contents with identical copies that are cached in cache 1124 can also be copied from cache 1124 to cache 1126 so that when cache 1126 is later used as a main cache, the contents that were previously cached in cache 1124 are also available in cache 1126. This can speed up access to the previously cached contents. Copying contents between cache 1124 and cache 1126 is faster than retrieving data from memory to the cache system.

[0201] In some embodiments, if a variable is referenced during normal execution, the variable can be cached. In such instances, if the variable is referenced during speculation while the cache is in a write-through mode, the value in main memory is valid and correct. If the variable is referenced during speculation while the cache is in a write-back mode, the value in main memory can be used. The valid value of the variable can be in cache 1124. Figure 11A The foregoing example features are described; and the valid value of the variable can be in cache 1124.

[0202] In the context described in Figure 11A the processor (e.g., processor 201, 401, 601, or 1001) can execute a first set of instructions in a mode of non-speculative execution. During execution of the first set of instructions, the processor can access memory addresses to load data (e.g., instructions and operands) from memory and store results of computations. Since cache 1124 is used as a main cache, the contents of the data and / or the results of the computations can be cached in cache 1124. For example, cache 1124 can store results of computations that have not yet been written back to memory; and cache 1124 can store loaded data (e.g., instructions and operands) that can be used in subsequent execution of instructions.

[0203] In preparing cache B 1226 for use as a shadow cache in the speculative execution of the second instruction set, background synchronization circuitry 1102 copies the contents of the cache from cache 1124 to cache 1126 in synchronization 1130. At least part of the copying operation can be performed in the background in a manner independent of the processor accessing memory via the cache system. For example, while the processor is accessing a first memory address in non-speculative execution of the first instruction set, background synchronization circuitry 1102 can copy the contents of the cache in cache 1124 for a second memory address into cache 1126. In some cases, the copying operation can be performed in the background concurrently with accessing memory via the cache system. For example, while the processor is accessing a first memory address in non-speculative execution of the first instruction set to store a computation result, background synchronization circuitry can copy the computation result into cache 1126 as the cache contents for the first memory address.

[0204] In one embodiment, background synchronization circuitry 1102 is configured to complete the synchronization operation before allowing cache 1126 to be used in speculative execution of the second instruction set. Thus, when cache 1126 is enabled to be used in speculative execution of the second instruction set, valid contents in cache 1124 can also be found in cache 1126. However, the synchronization operation can delay the use of cache 1126 as a shadow cache. Alternatively, background synchronization circuitry 1102 is configured to prioritize the synchronization of dirty contents from cache 1124 to cache 1126. Dirty contents can be a case where the data in the cache has been modified and the data in the main memory has not been modified.

[0205] Dirty contents cached in cache 1124 can be more up-to-date than the contents stored in the memory at the corresponding one or more addresses. For example, when the processor stores a computation result at an address, cache 1124 can cache the computation result for the address without immediately writing the computation result to the memory at the address. When the computation result is written back to the memory at the address, the cached contents are no longer considered dirty. Cache 1124 stores data to track dirty contents cached in cache 1124. Background synchronization circuit 1102 can automatically copy dirty contents from cache 1124 to cache 1126 in preparation for cache 1126 to act as a shadow cache.

[0206] Optionally, before completing the synchronization operation, the background synchronization circuitry 1102 can allow the cache 1126 to act as a shadow cache in the conditionally speculative execution of the second instruction set. During the period of time that the cache 1126 is used as a shadow cache in speculative execution, the background synchronization circuit 1102 can continue the synchronization operation 1130 of copying the contents of the cache from the cache 1124 to the cache 1126. The background synchronization circuitry 1102 is configured to at least complete the synchronization of dirty contents from the cache 1124 to the cache 1126 before allowing the cache 1126 to be accepted as a primary cache. For example, after an indication is needed for execution of the second instruction set, the background synchronization circuitry 1102 determines whether dirty contents in the cache 1124 have been synchronized to the cache 1126; and if not, defers use of the cache 1126 as a primary cache until synchronization is complete.

[0207] In some embodiments, the background synchronization circuitry 1102 can continue its synchronization operation even after accepting the cache 1126 as a primary cache, but before the cache 1124 is used as a shadow cache in the conditionally speculative execution of the third instruction set.

[0208] Before completing the synchronization operation 1130, the cache system can configure the cache 1124 as a secondary cache between the cache 1126 and the memory during speculative execution, such that when the contents of a memory address are not found in the cache 1126, the cache system checks the cache 1124 to determine whether the contents are in the cache 1124; and if so, copies the contents from the cache 1124 to the cache 1126 (rather than loading directly from the memory). When the processor stores data at a memory address and caches the data in the cache 1126, the cache system checks to invalidate the contents in the cache 1124 that is cached as a secondary cache.

[0209] After the cache 1126 is reconfigured as a primary cache after accepting the results of the speculative execution of the second instruction set, the background synchronization circuitry 1102 can begin to synchronize 1132 the contents of the cache from the cache 1126 to the cache 1124, as described in Figure 11B

[0210] After the speculative execution of the second instruction set, if the speculative state from the processor indicates that the results of the execution of the second instruction set should be rejected, the cache 1124 still acts as a primary cache; and the contents in the cache 1126 can be invalidated. The invalidation can include the cache 1126 marking all of its entries as empty; thus, any subsequent speculation begins with an empty speculative cache. ​

[0211] Background synchronization circuitry 1102 can again synchronize 1130 the contents of the cache from cache 1124 to cache 1126 in preparation for speculative execution of the third instruction set.

[0212] In some embodiments, each of cache 1124 and cache 1126 has a dedicated and fixed set of cache sets; and a configuration bit can be used to control the use of cache 1124 and 1126 as the primary cache and shadow cache, respectively, as explained in Figure 3A , 3B , 5A and 5B.

[0213] In other embodiments, cache 1124 and cache 1126 can share a pool of cache sets, some of which can be dynamically allocated to cache 1124 and cache 1126, as explained in Figures 6 to 10 . When cache 1124 is used as the primary cache and cache 1126 is used as the shadow cache, cache 1126 can have a smaller number of cache sets than cache 1124. Some of the cache sets in cache 1126 can be shadows of portions of the cache sets in cache 1124, such that when the results of a speculative execution are determined to be accepted, the portions of the cache sets in cache 1124 can be reconfigured for use as the shadow cache in the next speculative execution; and the remaining portions of the cache sets that were not affected by the speculative execution can be reallocated from cache 1124 to cache 1126, such that the contents of the caches in the unaffected portions can be further used in subsequent non-speculative executions.

[0214] Figure 12 An example operation of background synchronization circuitry 1102 according to some embodiments of the disclosure is shown. Figure 11A and 11B .

[0215] As shown in Figure 12 , at operation 1202, the cache system configures a first cache as a primary cache and a second cache as a shadow cache. For example, when dedicated caches with fixed hardware structures are used as the first and second caches, a configuration bit can be used to configure the first cache as the primary cache and the second cache as the shadow cache, as explained in Figures 2 to 5B . Alternatively, registers can be used to allocate cache sets into and out of the first and second caches from a pool of cache sets, in the manner explained in Figures 6 to 10 .

[0216] At operation 1204, the cache system determines whether the current execution type changes from non-speculative to speculative. For example, when the processor accesses memory via the cache system 200, the processor further provides an indication of whether the current memory access is associated with conditional speculative execution. For example, the indication can be provided in the signal line 205d configured to designate the execution type.

[0217] If the current execution type does not change from non-speculative to speculative, the cache system serves memory access requests from the processor using the first cache as the master cache at operation 1206. When the memory access changes the contents of the cache in the first cache, the background synchronization circuitry 1102 can copy the contents of the cache in the first cache to the second cache in operation 1208. For example, the background synchronization circuitry 1102 can be part of the logic circuit 206 in the Figure 2 Figure 4 406 in the Figure 6 606 in the and / or Figure 10 1006 in the background synchronization circuitry 1102 can prioritize the copying of dirty contents cached in the first cache.

[0218] In the Figure 12 , the operations 1204-1208 are repeated until the cache system 200 determines that the current execution type changes to speculative.

[0219] Optionally, the background synchronization circuitry 1102 is configured to continue copying the contents of the cache in the first cache to the second cache to complete the synchronization of at least the dirty contents from the first cache to the second cache in operation 1210, and then allow the cache system to serve memory requests from the processor during speculative execution using the second cache in operation 1212.

[0220] Optionally, the background synchronization circuitry 1102 can continue the synchronization operation while the cache system serves memory requests from the processor using the second cache during speculative execution in operation 1212.

[0221] At operation 1214, the cache system determines whether the current execution type changes to non-speculative. If the current execution type is still speculative, the operations 1210 and 1212 can be repeated.

[0222] In response to determining that the current execution type changes to non-speculative at operation 1214, the cache system determines whether to accept the results of the speculative execution. The results of the speculative execution correspond to changes in the contents of the cache in the second cache. For example, the processor 401 can provide an indication of whether to accept the results of the speculative execution via the Figure 4 ​the speculative state signal line 404 or Figure 10 the speculative state signal line 1004 in

[0223] If, in operation 1216, the cache system determines that the result of the speculative execution is to be rejected, the cache system can discard the contents of the cache currently cached in the second cache (e.g., via setting the invalid bits of the cache blocks in the second cache) in operation 1222. Subsequently, in operation 1244, the cache system can keep the first cache as the master cache and keep the second cache as the shadow cache; and in operation 1208, the background synchronization circuitry 1102 can copy the contents of the cache from the first cache to the second cache. Operations 1204-1208 can be repeated while the execution is still non-speculative.

[0224] If, in operation 1216, the cache system determines that the result of the speculative execution is to be accepted, the background synchronization circuitry 1102 is configured to further copy the contents of the cache cached in the first cache to the second cache in operation 1218 to complete the synchronization of at least the dirty contents from the first cache to the second cache before allowing the cache system to reconfigure the first cache as a shadow cache. In operation 1220, the cache system configures the first cache as a shadow cache and the second cache as a master cache in a manner slightly similar to operation 1202. In configuring the first cache as a shadow cache, the cache system can invalidate its contents and then synchronize the contents of the cache in the second cache to the first cache in a manner slightly similar to operations 1222, 1224, 1208, and 1204.

[0225] For example, when a dedicated cache with a fixed hardware structure is used as the first cache and the second cache, a configuration bit can change to configure the first cache as a shadow cache and the second cache as a master cache in operation 1220. Alternatively, when registers are used to allocate cache sets from a pool of cache sets to the first cache and the second cache in a manner as described in Figures 6 to 10 Figure 6 and 10 ​The registers 612a and 612b described in the middle are reconfigured to join the second cache. The cache set that was initially in the first cache (but now has no data content in view of the contents in the second cache) can be reconfigured as in the new first cache. Optionally, an additional cache set can be allocated from the pool of available cache sets and added to the new first cache. Optionally, some of the cache sets with invalidated cache content can be put back into the pool of available cache sets for future allocation (e.g., for addition to the second cache as a primary cache or to the first cache as a shadow cache).

[0226] In this description, the disclosure has been presented in reference to particular exemplary embodiments thereof. It is to be understood that various modifications can be made without departing from the spirit and scope of the disclosure as set forth in the appended claims. Therefore, the present description and drawings should not be taken as limiting, but rather as illustrative.

[0227] For example, embodiments can include a cache system including: a first cache; a second cache; a connection to a command bus coupled between the cache system and a processor; a connection to an address bus coupled between the cache system and the processor; a connection to a data bus coupled between the cache system and the processor; a connection to an execution type signal line from the processor identifying an execution type; and a logic circuit coupled to control the first cache and the second cache according to the execution type. In such embodiments, the cache system is configured to be coupled between the processor and a memory system. Further, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache is configured to service commands from the command bus to access the memory system, the logic circuit is configured to copy a portion of content in the first cache to the second cache.

[0228] In such embodiments, the logic circuit can be configured to copy the portion of content in the first cache to the second cache independent of a current command received in the command bus.

[0229] Further, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache is configured to service commands from the command bus for accessing the memory system, the logic circuit can be configured to service subsequent commands from the command bus using the second cache in response to the execution type changing from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuit can also be configured to complete synchronizing the portion of the contents from the first cache to the second cache before servicing the subsequent commands after the execution type changes from the first type to the second type. The logic circuit can also be configured to continue synchronizing the portion of the contents from the first cache to the second cache while servicing the subsequent commands.

[0230] In such embodiments, the cache system can further include a configurable data bit, and the logic circuit is further coupled to control the first cache and the second cache according to the configurable data bit. When the configurable data bit is in a first state, the logic circuit can be configured to: when the execution type is the first type, implement commands received from the command bus for accessing the memory system via the first cache; and when the execution type is the second type, implement commands received from the command bus for accessing the memory system via the second cache. And, when the configurable data bit is in a second state, the logic circuit can be configured to: when the execution type is the first type, implement commands received from the command bus for accessing the memory system via the second cache; and when the execution type is the second type, implement commands received from the command bus for accessing the memory system via the first cache. The logic circuit can also be configured to toggle the configurable data bit when the execution type changes from the second type to the first type.

[0231] In such embodiments, the cache system can further include a connection to a speculation status signal line from the processor identifying a status of speculative execution of instructions by the processor. The connection to the speculation status signal line is configured to receive the status of speculative execution. The status of speculative execution indicates whether results of speculative execution are to be accepted or rejected. The logic circuit can be configured to: toggle the configurable data bit if the status of speculative execution indicates that results of speculative execution are to be accepted; and maintain the configurable data bit without change if the status of speculative execution indicates that results of speculative execution are to be rejected when the execution type changes from the second type to the first type.

[0232] Furthermore, in such embodiments, the first cache and the second cache collectively include: a plurality of cache sets including the first cache set and the second cache set; and a plurality of registers associated with the plurality of cache sets, respectively, including the first register associated with the first cache set and the second register associated with the second cache set. In such instances, the logic circuit can be further coupled to control the plurality of cache sets in accordance with the plurality of registers. Moreover, when the connection with the address bus receives a memory address from the processor, the logic circuit can be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches contents stored in the first register or contents stored in the second register. The logic circuit can also be configured to implement a command received in the connection with the command bus via the first cache set in response to the generated set index matching the contents stored in the first register, and implement the command via the second cache set in response to the generated set index matching the contents stored in the second register. Furthermore, in response to determining that a data set of a memory system associated with the memory address is not currently cached in the cache system, the logic circuit can be configured to allocate the first cache set for caching the data set and store the generated set index in the first register.

[0233] Additionally, in such embodiments having cache sets, the cache system can also include a connection with an execution type signal line from the processor identifying a type of execution, and the generated set index is further generated based on the type identified by the execution type signal line. The generated set index can include a predetermined segment of bits in the memory address and a bit representing the type identified by the execution type signal line. Moreover, when the first and second registers are in the first state, the logic circuit can be configured to: implement a command received from the command bus for accessing the memory system via the first cache set when the type of execution is a first type; and implement a command received from the command bus for accessing the memory system via the second cache set when the type of execution is a second type. And, when the first and second registers are in the second state, the logic circuit is configured to: implement a command received from the command bus for accessing the memory system via another cache set of the plurality of cache sets other than the first cache set when the type of execution is the first type; and implement a command received from the command bus for accessing the memory system via another cache set of the plurality of cache sets other than the second cache set when the type of execution is the second type.

[0234] In such embodiments having a set of caches, each of the plurality of registers can be configured to store a set index. Also, when the type of execution changes from the second type to the first type, the logic circuit can be configured to change the contents stored in the first register and the contents stored in the second register. Further, the first type can be configured to indicate non-speculative execution of the instruction by the processor, and the second type can be configured to indicate speculative execution of the instruction by the processor. In such an instance, the cache system can further include a connection to a speculation status signal line from the processor that identifies a status of the speculative execution of the instruction by the processor. The connection to the speculation status signal line is configured to receive the status of the speculative execution, and the status of the speculative execution indicates whether a result of the speculative execution is to be accepted or rejected. When the type of execution changes from the second type to the first type, the logic circuit can be configured to: if the status of the speculative execution indicates that the result of the speculative execution is to be accepted, change the contents stored in the first register and the contents stored in the second register; and if the status of the speculative execution indicates that the result of the speculative execution is to be rejected, maintain the contents stored in the first register and the contents stored in the second register without change.

[0235] Further, for example, embodiments can include a cache system including, in general, a plurality of cache sets and a plurality of registers respectively associated with the plurality of cache sets. The plurality of cache sets includes a first cache set and a second cache set, and the plurality of registers includes a first register associated with the first cache set and a second register associated with the second cache set. Similarly, in such embodiments, the cache system can include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, a connection to an execution type signal line from the processor that identifies a type of execution, and a logic circuit coupled to control the plurality of cache sets according to the type of execution. The cache system can also be configured to be coupled between the processor and a memory system. Also, when the type of execution is a first type indicating non-speculative execution of an instruction by the processor and the first cache set is configured to service a command from the command bus to access the memory system, the logic circuit can be configured to copy a portion of contents of the cache in the first cache set to the second cache set.

[0236] In such embodiments having a set of caches, the logic circuit can be configured to copy a portion of the contents of the cache in the first set of caches to the second set of caches independent of a current command received in the command bus. When the execution type is a first type indicating non-speculative execution of instructions by the processor and the first set of caches is configured to service commands from the command bus for accessing the memory system, the logic circuit can be configured to service subsequent commands from the command bus using the second set of caches in response to the execution type changing from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuit can also be configured to complete the synchronization of the portion of the contents from the first set of caches to the second set of caches prior to servicing the subsequent commands after the execution type changes from the first type to the second type. The logic circuit can also be configured to continue synchronizing the portion of the contents from the first set of caches to the second set of caches while servicing the subsequent commands.

[0237] Further, in such embodiments having a set of caches, the logic circuit can be further coupled to control the plurality of sets of caches according to a plurality of registers. When a memory address is received from the processor in connection with the address bus, the logic circuit can be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches contents stored in a first register or contents stored in a second register. The logic circuit can also be configured to implement a command received in connection with the command bus via the first set of caches in response to the generated set index matching the contents stored in the first register, and implement the command via the second set of caches in response to the generated set index matching the contents stored in the second register. Further, in response to determining that a data set of the memory system associated with the memory address is not currently cached in the cache system, the logic circuit can be configured to allocate the first set of caches for caching the data set and store the generated set index in the first register.

[0238] Additionally, in such embodiments having a set of cache banks, the cache system can further include a connection to an execution type signal line from the processor that identifies an execution type, and the generated set index can be further generated based on the type identified by the execution type signal line. The generated set index can include a predetermined segment of bits in the memory address and a bit that represents the type identified by the execution type signal line. When the first and second registers are in the first state, the logic circuit can be configured to: implement a command received from the command bus for accessing the memory system via the first cache bank when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via the second cache bank when the execution type is the second type. And, when the first and second registers are in the second state, the logic circuit can be configured to: implement a command received from the command bus for accessing the memory system via another cache bank of the plurality of cache banks other than the first cache bank when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via another cache bank of the plurality of cache banks other than the second cache bank when the execution type is the second type.

[0239] In such embodiments having a set of cache banks, each of the plurality of registers can be configured to store a set index, and the logic circuit can be configured to change the contents stored in the first register and the contents stored in the second register when the execution type changes from the second type to the first type. Further, the first type can be configured to indicate a non-speculative execution of an instruction by the processor, and the second type is configured to indicate a speculative execution of an instruction by the processor.

[0240] In such embodiments having a set of cache banks, the cache system can further include a connection to a speculation status signal line from the processor that identifies a status of a speculative execution of an instruction by the processor. The connection to the speculation status signal line is configured to receive the status of the speculative execution, and the status of the speculative execution indicates whether a result of the speculative execution is to be accepted or rejected. The logic circuit can be configured to: change the contents stored in the first register and the contents stored in the second register if the status of the speculative execution indicates that the result of the speculative execution is to be accepted; and maintain the contents stored in the first register and the contents stored in the second register without change if the status of the speculative execution indicates that the result of the speculative execution is to be rejected when the execution type changes from the second type to the first type.

[0241] Further, in such embodiments having a set of cache banks, the set of cache banks can be divided among a plurality of caches within the cache system. For example, the set of cache banks can be divided among first and second caches of the plurality of caches.

[0242] Figure 13 、 14A , 14B, 14C, 15A, 15B, 15C, and 15D illustrate example aspects of a cache system (e.g., see cache system 1000 illustrated in Figure 14A and 15A ) of an example computing device having interchangeable cache sets (e.g., see cache sets 1310a, 1310b, 1310c, and 1310d) with a spare cache set (e.g., see spare cache set 1310d illustrated in Figure 13 ) to accelerate speculative execution.

[0243] In addition to using a shadow cache to ensure speculative execution and to synchronize content between a main cache and the shadow cache to save content cached in the main cache in preparation for accepting content in the shadow cache, a spare cache set can also be used to accelerate speculative execution (e.g., see spare cache set 1310d as depicted in Figure 14A and 15A , and cache set 1310b as depicted in Figure 15B and 15C , and cache set 1310c as depicted in Figure 15D ). A spare cache set can also be used to accelerate speculative execution without using a shadow cache. Data saved in a cache set used as a shadow cache can be verified and thus used for normal execution (e.g., see cache set 1310c as depicted in Figure 14A and 15A , and cache set 1310d as depicted in Figure 15B and 15C , and cache set 1310b as depicted in Figure 15D , each of which can be used for speculative execution and a cache set of a shadow cache, and then used for normal execution after content verification). Also, some cache sets used as main caches for normal or non-speculative execution (e.g., see cache set 1310b as depicted in Figure 14A and 15A , and cache set 1310c as depicted in Figure 15B and 15C , and cache set 1310d as depicted in Figure 15D ) can not be ready to be used as a shadow cache for speculative execution. Thus, one or more cache sets can be used as a spare cache set to avoid the delay of waiting for cache set availability (e.g., see cache set 1310d as depicted in Figure 14A and15A The cache set 1310d described in the document, and such as Figure 15B and 15C The cache set 1310b described in the document and such Figure 15D The cache set described in the document is 1310c.

[0244] Once the speculation is confirmed, the contents of the cache set used as the shadow cache are confirmed to be valid and up-to-date; and therefore, the previous cache set used as the shadow cache for speculative execution is used for normal execution. For example, see... Figure 14A and 15A The cache set 1310c described in the document, and such as Figure 15B and 15C The cache set 1310d described in the document and such Figure 15D The cache set 1310b described herein, each of which is a cache set available for speculative execution and is a shadow cache set, and then available for normal execution after content verification. However, some of the cache sets initially used as normal caches may not be ready for subsequent speculative execution. For example, see, Figure 14A and 15A The cache set 1310b described in the document, and such as Figure 15B and 15C The cache set 1310c described in the document and such Figure 15D The cache set 1310d described in the document, each of which serves as a portion of the general cache but may not be ready for subsequent speculative execution. Therefore, one or more cache sets can be used as backup cache sets to avoid delays while waiting for cache set availability and to accelerate speculative execution. For example, see [reference needed]. Figure 14A and 15A The cache set 1310d described in the document, and such as Figure 15B and 15C The cache set 1310b described in the document and such Figure 15D The cache set 1310c described in the document, each of which is used as a spare cache set.

[0245] In some embodiments, when the cache system has a background synchronization circuitry (e.g., see background synchronization circuitry 1102), if synchronization from the cache set in the general cache to the corresponding cache set in the shadow cache has not yet been completed (e.g., see illustrated in...), Figure 11AIf the synchronization 1130 in the example of FIG. 11 is not completed, then the cache set in the normal cache cannot be released immediately for use in the next speculative execution. In this case, if there is no spare cache set, then the next speculative execution must wait until the synchronization is completed so that the corresponding cache set in the normal cache can be released. This is just one example when a spare cache set is beneficial. There are many other cases when a cache set in the normal cache cannot be released immediately.

[0246] In addition, for example, the speculative execution can reference a memory region in the memory system (e.g., see memory system 603 in Figure 6 , 10 and 13) that does not have an overlap with the memory region that is cached in the cache set used for the normal cache. As a result of accepting the speculative execution, the cache set in the shadow cache and the normal cache are now all in the normal cache. This can also cause a delay because the cache system takes time to release the cache set to support the next speculative execution. To release the cache set, the cache system needs to identify the cache set, e.g., the least used cache set, and synchronize the cache set with the memory system. If the cache has data that is more up to date than the memory system, then the data needs to be written to the memory system.

[0247] In addition, systems that use spare cache sets (e.g., see cache set 1310d as depicted in Figure 14A and 15A , cache set 1310b as depicted in Figure 15B and 15C , and cache set 1310c as depicted in Figure 15D , can also use background synchronization circuitry (e.g., background synchronization circuitry 1102). When an initial speculation is confirmed, the cache set used in the initial speculation can be swapped (e.g., see cache set 1310c as depicted in Figure 14A and 15A ) to join the set of cache sets used for the main execution (e.g., see cache set 1310a as shown in Figure 14A , B, and C and as depicted in Figure 15A , B, C, and D, which is a cache set that is in the set of cache sets used for the main execution or non-speculative execution). Instead of using the cache set from the previous main execution that is being used for the case of a speculation failure (e.g., see cache set 1310b as depicted in Figure 14A and 15A , and cache set 1310c as depicted in Figure 15B and 15Cthe cache set 1310c as depicted in Figure 15D the cache set 1310d as depicted in Figure 14A and 15A the cache set 1310d as depicted in Figure 15B and 15C the cache set 1310b as depicted in Figure 15D the cache set 1310c as depicted in Figure 14A and 15A the cache set 1310c as depicted in Figure 14A and 15A the cache set 1310d as depicted in Figure 14A and 15A the cache set 1310b as depicted in Figure 14A and 15A the cache set 1310b as depicted in

[0248] Figure 13 An example aspect of an example computing device having a cache system 1000 with interchangeable cache sets including a standby cache set to speed up speculative execution (see, e.g., cache sets 1310a, 1310b, 1310c, and 1310d) in accordance with some embodiments of the present disclosure is shown. Figure 13 The computing device in Figure 10 is similar to the computing device depicted in Figure 13 For example, the device shown in

[0249] In Figure 13In particular embodiments, cache system 1000 is shown with a set of caches (e.g., cache set 1310a, 1310b, 1310c, and 1310d). Cache system 1000 is also shown with a connection 604d to an execution type signal line 605d from processor 1001 that identifies the type of execution, and a connection 1002 to a signal line 1004 from processor 1001 that identifies the state of speculative execution.

[0250] Cache system 1000 is also shown as including a logic circuit 1006 that can be configured to allocate a first subset of the set of caches (e.g., see cache 602a as shown in Figure 13 In particular embodiments, cache system 1000 is shown with a set of caches (e.g., cache set 1310a, 1310b, 1310c, and 1310d). Cache system 1000 is also shown with a connection 604d to an execution type signal line 605d from processor 1001 that identifies the type of execution, and a connection 1002 to a signal line 1004 from processor 1001 that identifies the state of speculative execution. Figure 13 Figure 13 In particular embodiments, cache system 1000 is shown with a set of caches (e.g., cache set 1310a, 1310b, 1310c, and 1310d). Cache system 1000 is also shown with a connection 604d to an execution type signal line 605d from processor 1001 that identifies the type of execution, and a connection 1002 to a signal line 1004 from processor 1001 that identifies the state of speculative execution.

[0251] In particular embodiments, cache system 1000 is shown with a set of caches (e.g., cache set 1310a, 1310b, 1310c, and 1310d). Cache system 1000 is also shown with a connection 604d to an execution type signal line 605d from processor 1001 that identifies the type of execution, and a connection 1002 to a signal line 1004 from processor 1001 that identifies the state of speculative execution. Figure 13 Figure 13 In particular embodiments, cache system 1000 is shown with a set of caches (e.g., cache set 1310a, 1310b, 1310c, and 1310d). Cache system 1000 is also shown with a connection 604d to an execution type signal line 605d from processor 1001 that identifies the type of execution, and a connection 1002 to a signal line 1004 from processor 1001 that identifies the state of speculative execution. Figure 13

[0252] ​​​In some embodiments, the cache system can include one or more mapping tables that can map the cache sets mentioned herein. And, in such embodiments, logic circuitry, such as the logic circuitry mentioned herein, can be configured to allocate and reconfigure subsets of the cache sets, such as the caches in the cache system, according to the one or more mapping tables. The mapping can be used in addition to or instead of the cache set registers described herein.

[0253] In some embodiments, as at least Figure 13 , 14A As shown in FIGS. 14C and 15A-D, the cache system 1000 can include cache set registers (e.g., see cache set registers 1312a, 1312b, 1312c, and 1312d) associated with cache sets (e.g., see cache sets 1310a, 1310b, 1310c, and 1310d), respectively. In such embodiments, the logic circuitry 1006 can be configured to allocate and reconfigure subsets of the cache sets (e.g., see caches 602a, 602b, and 602c as shown in FIG. 16B) according to the cache set registers. Figure 13

[0254] Further, in some embodiments, as shown in FIG. 16A, a first subset of the cache sets can include a first cache set, a second subset of the cache sets can include a second cache set, and a third subset can include a third cache set. In such embodiments, the cache set registers can include a first cache set register associated with the first cache set, the first cache set register configured to initially store a first cache set index such that the first cache set is used for non-speculative execution (e.g., see cache set index 1504b saved in cache set register 1312b as shown in FIG. 16B). The cache set registers can also include a second cache set register associated with the second cache set, the second cache set register configured to initially store a second cache set index such that the second cache set is used for non-speculative execution (e.g., see cache set index 1504c saved in cache set register 1312c as shown in FIG. 16B). The cache set registers can also include a third cache set register associated with the third cache set, the third cache set register configured to initially store a third cache set index such that the third cache set is used as a spare cache set (e.g., see cache set index 1504d saved in cache set register 1312d as shown in FIG. 16B). Figures 15A to 15D Figure 15A Figure 15A Figure 15A ​​​​The cache set index 1504d saved in the cache set register 1312d is shown in the middle.

[0255] Further, in such embodiments, the logic circuit 1006 can be configured to generate a set index based on a memory address received from the address bus 605b from the processor 1001 and an identification of speculative execution or non-speculative execution received from the execution type signal line 605d from the processor identifying the type of execution. Also, the logic circuit 1006 can be configured to determine whether the set index matches the contents stored in the first cache set register, the second cache set register, or the third cache set register.

[0256] Also, in such embodiments, the logic circuit 1006 can be configured to store the first cache set index in the second cache set register or another cache set register associated with another cache set in the second subset of the plurality of cache sets, such that when the type of execution changes from the second type to the first type and the state of speculative execution indicates that results of speculative execution are to be accepted, the second cache set or the other cache set in the second subset is used for non-speculative execution. For example, see the depiction of the cache set index 1504b saved in the second cache set register 1312c Figure 15B such that the second cache set 1310c is available for non-speculative execution. In addition, the logic circuit 1006 can be configured to store the second cache set index in the third cache set register or another cache set register associated with another cache set in the at least one cache set, such that when the type of execution changes from the second type to the first type and the state of speculative execution indicates that results of speculative execution are to be accepted, the third cache set or the other cache set in the at least one cache set is used for speculative execution. For example, see the depiction of the cache set index 1504c saved in the third cache set register 1312d Figure 15B such that the third cache set 1310d is available and can be used for speculative execution. The logic circuit 1006 can also be configured to store the third cache set index in the first cache set register or another cache set register associated with another cache set in the first subset of the plurality of cache sets, such that when the type of execution changes from the second type to the first type and the state of speculative execution indicates that results of speculative execution are to be accepted, the first cache set or the other cache set in the first subset is used as a backup cache set. For example, see the depiction of the cache set index 1504d saved in the first cache set register 1312b Figure 15B such that the first cache set 1310b is used as a spare cache set.

[0257] Figure 14A 、 14B and 14C each illustrate example aspects of an example computing device having a cache system 1000 with interchangeable cache sets (e.g., see cache sets 1310a, 1310b, 1310c, and 1310d) with a spare cache set (e.g., see spare cache set 1310d as illustrated in FIG. 14B and spare cache set 1310b as illustrated in FIG. 14A) to accelerate speculative execution in accordance with some embodiments of the present disclosure. In particular, Figure 14A and 14B FIG. 14A illustrates cache sets in a first state in which cache sets 1310a and 1310b are available for non-speculative execution, cache set 1310c is available for speculative execution, and cache set 1310b is used as a spare cache set. Figure 14C FIG. 14B illustrates cache sets in a second state in which cache sets 1310a, 1310b, and 1310c are available for non-speculative execution, and cache set 1310c is available for and available for speculative execution. Figure 14A FIG. 14C illustrates cache sets in a third state in which cache sets 1310a and 1310c are available for non-speculative execution, cache set 1310d is available for speculative execution, and cache set 1310b is used as a spare cache set. Figure 14B Figure 14C

[0258] Figure 15A 、 15B , 15C, and 15D each illustrate example aspects of an example computing device having a cache system 1000 with interchangeable cache sets (e.g., see cache sets 1310a, 1310b, 1310c, and 1310d) with a spare cache set to accelerate speculative execution in accordance with some embodiments of the present disclosure.

[0259] In particular, Figure 15A FIG. 14A illustrates cache sets in a first state in which cache sets 1310a and 1310b are available for non-speculative execution (or a first type of execution), cache set 1310c is available for speculative execution (or a second type of execution), and cache set 1310b is used as a spare cache set. As Figure 15A ​​In this first state, logic circuit 1006 can be configured to store cache set index 1504b in cache set register 1312b such that contents 1502b in cache set 1310b are used for non-speculative execution. Additionally, in this first state, logic circuit 1006 can be configured to store cache set index 1504c in cache set register 1312c such that cache set 1310c is available and usable for speculative execution. Logic circuit 1006 can also be configured to store cache set index 1504d in cache set register 1312d such that cache set 1310d is used as a spare cache set in this first state.

[0260] Figure 15B The cache sets in the second state are shown in which cache sets 1310a and 1310c are available for non-speculative execution, cache set 1310d is available for speculative execution, and cache set 1310b is used as a spare cache set. Figure 15B The second state depicted in FIG. 10 occurs when the type of execution changes from the second type to the first type and the state indication of the speculative execution will accept the results of the speculative execution. As Figure 15B In this second state, logic circuit 1006 can be configured to store cache set index 1504b in cache set register 1312c such that contents 1502b in cache set 1310c are used for non-speculative execution. Additionally, in this second state, logic circuit 1006 can be configured to store cache set index 1504c in cache set register 1312d such that cache set 1310d is available for speculative execution. Logic circuit 1006 can also be configured to store cache set index 1504d in cache set register 1312b such that cache set 1310b is used as a spare cache set in this second state.

[0261] Figure 15C The cache sets in the second state are shown in which cache sets 1310a and 1310c are available for non-speculative execution, and cache set 1310b is used as a spare cache set. However, in Figure 15C In this second state, logic circuit 1006 can be configured to store cache set index 1504c in cache set register 1312d such that contents 1502c saved in cache set 1310d are also available for speculative execution. Figure 15C

[0262] ​ Figure 15D The third state is shown in which cache set 1310a and 1310d are available for non-speculative execution, cache set 1310b is available for speculative execution, and cache set 1310c is used as a spare cache set. In a subsequent cycle after the second state, Figure 15D The third state depicted in FIG. 13B occurs when the type of execution changes again from the second type to the first type and the state indication of speculative execution is to accept the results of speculative execution. As Figure 15D In this third state, logic circuit 1006 is configured to store cache set index 1504b in cache set register 1312d so that contents 1502b in cache set 1310d are used for non-speculative execution, as shown in FIG. 13B. In addition, in this third state, logic circuit 1006 is configured to store cache set index 1504c in cache set register 1312b so that cache set 1310b is available for speculative execution. Logic circuit 1006 is also configured to store cache set index 1504d in cache set register 1312c so that cache set 1310c is used as a spare cache set in this third state.

[0263] As shown by the arrows in FIG. 13B, the cache sets are interchangeable and the cache sets used as spare cache sets are also interchangeable. Figures 15A to 15D As shown by the arrows in FIG. 13B, the cache sets are interchangeable and the cache sets used as spare cache sets are also interchangeable.

[0264] In such embodiments, when connection 604b to address bus 605b receives a memory address from processor 1001, logic circuit 1006 can be configured to generate a set index from at least the memory address 102b according to this cache set index of the address 112b (e.g., see set index generation 1506a, 1506b, 1506c, and 1506d generating set indexes 1504a, 1504b, 1504c, and 1504d, respectively). Further, when connection 604b to address bus 605b receives a memory address from processor 1001, logic circuit 1006 can be configured to determine whether the generated set index matches the contents stored in one of the registers, which can be stored set index 1504a, 1504b, 1504c, or 1504d. Further, logic circuit 1006 can be configured to implement a command received in connection 604a to command bus 605a in response to the generated set index matching the contents stored in the corresponding register. Further, in response to determining that the data set of the memory system associated with the memory address is not currently cached in the cache system, logic circuit 1001 can be configured to allocate a cache set for caching the data set and store the generated set index in the corresponding register. The generated set index can include a predetermined segment of bits in the memory address, as shown in Figures 15A to 15B

[0265] Further, in such embodiments, logic circuit 1006 can be configured to generate a set index based on a memory address received from address bus 605b from processor 1001 (e.g., memory address 102b) and an identification of a speculative execution or a non-speculative execution received from execution type signal line 605d from the processor identifying the type of execution (e.g., see set indexes 1504a, 1504b, 1504c, and 1504d). And, logic circuit 1006 can be configured to determine whether the set index matches the contents stored in cache set register 1312b, cache set register 1312c, or cache set register 1312d.

[0266] ​In some embodiments, a cache system can include a plurality of cache sets, a connection to an execution type signal line from a processor identifying an execution type, a connection to a signal line from the processor identifying a state of a speculative execution, and a logic circuit. The logic circuit can be configured to allocate a first subset of the plurality of cache sets for use in cache operations when the execution type is a first type indicating non-speculative execution of instructions by the processor, and to allocate a second subset of the plurality of cache sets for use in cache operations when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuit can also be configured to retain at least one cache set (or a third subset of the plurality of cache sets) when the execution type is the second type. The logic circuit can also be configured to reconfigure the second subset for use in cache operations when the execution type is the first type when the execution type changes from the second type to the first type and the state of the speculative execution indicates that results of the speculative execution are to be accepted. Also, the logic circuit can be configured to allocate the at least one cache set (or the third subset of the plurality of cache sets) for use in cache operations when the execution type changes from the first type to the second type when the execution type changes from the second type to the first type and the state of the speculative execution indicates that results of the speculative execution are to be accepted.

[0267] In such embodiments, the logic circuit can be configured to retain the at least one cache set (or the third subset of the plurality of cache sets) when the execution type is the second type and the at least one cache set (or the third subset of the plurality of cache sets) includes a least used cache set of the plurality of cache sets.

[0268] Further, in such embodiments, the cache system can include one or more mapping tables mapping the plurality of cache sets. In such instances, the logic circuit is configured to allocate and reconfigure subsets of the plurality of cache sets according to the one or more mapping tables.

[0269] Furthermore, in such embodiments, the cache system can include a plurality of cache set registers associated with a plurality of cache sets, respectively. In such instances, the logic circuit is configured to allocate and reconfigure subsets of the plurality of cache sets according to the plurality of cache set registers. In such instances, a first subset of the plurality of cache sets can include a first cache set, a second subset of the plurality of cache sets can include a second cache set, and at least one cache set (or a third subset of the plurality of cache sets) can include a third cache set. Furthermore, the plurality of cache set registers can include a first cache set register associated with the first cache set, the first cache set register configured to initially store a first cache set index such that the first cache set is used for non-speculative execution. The plurality of cache set registers can also include a second cache set register associated with the second cache set, the second cache set register configured to initially store a second cache set index such that the second cache set is used for speculative execution. The plurality of cache set registers can also include a third cache set register associated with the third cache set, the third cache set register configured to initially store a third cache set index such that the third cache set is used as a spare cache set.

[0270] In such embodiments, the logic circuit can be configured to generate the set index based on a memory address received from an address bus from the processor and an identification of speculative execution or non-speculative execution received from an execution type signal line from the processor that identifies the type of execution. Also, the logic circuit can be configured to determine whether the set index matches contents stored in the first cache set register, the second cache set register, or the third cache set register. When the type of execution changes from the second type to the first type and the status of speculative execution indicates that results of speculative execution are to be accepted, the logic circuit can be further configured to store the first cache set index in the second cache set register or another cache set register associated with another cache set of the second subset of the plurality of cache sets, such that the second cache set or the another cache set of the second subset is used for non-speculative execution. When the type of execution changes from the second type to the first type and the status of speculative execution indicates that results of speculative execution are to be accepted, the logic circuit can be further configured to store the second cache set index in the third cache set register or another cache set register associated with another cache set of the at least one cache set (or a third subset of the plurality of cache sets), such that the third cache set or the another cache set of the at least one cache set (or the third subset of the plurality of cache sets) is used for speculative execution. When the type of execution changes from the second type to the first type and the status of speculative execution indicates that results of speculative execution are to be accepted, the logic circuit can be further configured to store the third cache set index in the first cache set register or another cache set register associated with another cache set of the first subset of the plurality of cache sets, such that the first cache set or the another cache set of the first subset is used as a spare cache set.

[0271] In some embodiments, a cache system can include a plurality of cache sets having a first subset of cache sets, a second subset of cache sets, and a third subset of cache sets. The cache system can also include a connection to an execution type signal line from a processor identifying an execution type, a connection to a signal line from the processor identifying a state of speculative execution, and a logic circuit. The logic circuit can be configured to allocate the first subset of the plurality of cache sets for use in cache operations when the execution type is a first type indicating non-speculative execution of instructions by the processor, and to allocate the second subset of the plurality of cache sets for use in cache operations when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuit can also be configured to retain the third subset of the plurality of cache sets when the execution type is the second type. The logic circuit can also be configured to reconfigure the second subset for use in cache operations when the execution type is the first type when the execution type changes from the second type to the first type and the state of speculative execution indicates that results of speculative execution are to be accepted. The logic circuit can also be configured to allocate the third subset for use in cache operations when the execution type changes from the first type to the second type when the execution type changes from the second type to the first type and the state of speculative execution indicates that results of speculative execution are to be accepted.

[0272] In some embodiments, a cache system can include a plurality of caches including a first cache, a second cache, and a third cache. The cache system can also include a connection to an execution type signal line from a processor identifying an execution type, a connection to a signal line from the processor identifying a state of speculative execution, and a logic circuit. The logic circuit can be configured to allocate the first cache for use in cache operations when the execution type is a first type indicating non-speculative execution of instructions by the processor, and to allocate the second cache for use in cache operations when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuit can also be configured to retain the third cache when the execution type is the second type. The logic circuit can also be configured to reconfigure the second cache for use in cache operations when the execution type is the first type when the execution type changes from the second type to the first type and the state of speculative execution indicates that results of speculative execution are to be accepted. And, the logic circuit can also be configured to allocate the third cache for use in cache operations when the execution type changes from the first type to the second type.

[0273] Figure 16 and 17An example aspect of an example computing device that exhibits a cache system having interchangeable cache sets (see, e.g., cache sets 1610a, 1610b, 1710a, and 1710b) with extended tags (see, e.g., extended tags 1640a, 1640b, 1740a, and 1740b) that utilize different types of execution (e.g., speculative and non-speculative execution) for execution by a processor in accordance with some embodiments of the present disclosure is shown. Moreover, Figure 16 and 17 Different ways of addressing cache sets and cache blocks within a cache system (e.g., cache systems 600 and 1000 depicted in Figure 6 , 10 and 13, respectively) are illustrated. Moreover, ways in which cache sets and cache blocks can be selected via memory addresses (e.g., memory addresses 102e or 102b and memory addresses 102a, 102c, or 102d (shown in FIG. 1)) are shown.

[0274] Figure 16 and 17 Two examples in Figure 16 use set-associativity, and cache systems such as cache systems 600 and 1000 can be implemented using set-associativity. In Figure 17 , set-associativity is defined implicitly (e.g., by an algorithm that can be used to determine which tag should be in which cache set for a given type of execution). In Figure 16 , set-associativity is implemented via bits in a memory address that are cache set indexes. Moreover, 17 and Figure 2 The functionality illustrated in 4 and may be implemented without using set-associativity (although this is not depicted), e.g., by cache systems 200 and 400 shown in

[0275] and Figure 16 , respectively. 17In particular, the block index (see, e.g., block indexes 106e and 106b) can be used as an address within an individual cache set (see, e.g., cache sets 1610a, 1610b, 1710a, and 1710b) to identify a particular cache block (see, e.g., cache blocks 1624a, 1624b, 1628a, 1628b, 1724a, 1724b, 1728a, and 1728b) in the cache set. Also, the extended tag (see, e.g., extended tags 1640a, 1640b, 1740a, 1740b, 1650, and 1750) can be used as an address for the cache set. The block index (see, e.g., block indexes 106e and 106b) of the memory address (see, e.g., memory addresses 102e and 102b) can be used for each cache set (see, e.g., cache sets 1610a, 1610b, 1710a, and 1710b) to obtain the cache block (see, e.g., cache blocks 1624a, 1624b, 1628a, 1628b, 1724a, 1724b, 1728a, and 1728b) and the tag (see, e.g., corresponding tags 1622a, 1622b, 1626a, 1626b, 1722a, 1722b, 1726a, and 1726b) associated with the cache block.

[0276] Further, as shown in Figure 16 and 17 The extended tag depicted in Figure 16 and 17 is used to select a cache set, and the block index is used to select a cache block within the cache set and its tag.

[0277] Furthermore, as shown in Figure 16 and 17 the memory addresses are partitioned differently (see, e.g., addresses 102e and 102b); and thus, the control of cache operations according to the addresses is also different. However, there are some similarities. For example, the systems shown in Figure 16 and 17 control cache set usage via set associativity. The control of cache operations can include controlling whether the cache set is for a first or second type of execution by the processor (e.g., non-speculative and speculative execution), and such control can be controlled via set associativity to some extent or entirely.

[0278] In Figure 16 the extended tag 1650 for memory address 102e has an execution type 110e and a tag 104e that has a cache set indicator that implements set associativity. In Figure 17 the extended tag 1750 for memory address 102b has an execution type 110e, a cache set index 112b, and a tag 104b. In this example, the cache set index 112b implements set associativity instead of a cache set indicator in the tag. The different partitioning of the memory addresses slightly changes the way the extended tags (e.g., extended tags 1640a, 1640b, 1650, 1740a, and 1740b, and 1750) control cache operations via set associativity.

[0279] In the case of memory address partitioning, in instances, an extended tag from the memory address and the execution type (see, e.g., extended tags 1650 and 1750) is compared to an extended tag for the cache set (see, e.g., extended tags 1640a, 1640b, 1740a, and 1740b) for controlling cache operations implemented via the cache set. Depending on whether the extended tags input into the comparison circuit match or do not match, the tag comparison circuit (e.g., tag comparison circuits 1660a, 1660b, 1760a, and 1760b) can output a hit or a miss. The extended tag for the cache set (see, e.g., extended tags 1640a, 1640b, 1740a, and 1740b) can be derived from the execution type (see, e.g., execution types 1632a, 1632b, 1732a, and 1732b) saved in a register (see, e.g., registers 1612a, 1612b, 1712a, and 1712b) and a block tag from the first cache set (see, e.g., cache sets 1610a, 1610b, 1710a, and 1710b) (see, e.g., tags 1622a, 1622b, 1626a, 1626b, 1722a, 1722b, 1726a, and 1726b). Also, as shown in Figure 16 and 17 the execution type is different in each register of the cache set. For the instances shown, a first cache set (e.g., cache set 1610a or 1710a) can be used for a first type of execution (e.g., non-speculative execution) and a second cache set (e.g., cache set 1610b or 1710b) can be used for a second type of execution (e.g., speculative execution).

[0280] In Figure 17 the combination of tag 104b and cache set index 112b provides similar functionality to tag 104e shown in Figure 16 However, in Figure 17 by separating tag 104b and cache set index 112b, the cache set does not have to store a redundant copy of cache set index 112b since the cache set (see, e.g., cache sets 1710a and 1710b) can be associated with a cache set register (see, e.g., registers 1732a and 1732b) to save the cache set index (see, e.g., cache set indexes 1732a and 1732b). In contrast, in Figure 16In particular, the cache set (see, e.g., cache sets 1610a and 1610b) does need to store a redundant copy of the cache set indicator in each of its blocks (see, e.g., blocks 1624a, 1624b, 1628a, and 1628b) because the cache set's associated register is not configured to hold the cache set index.

[0281] In other words, because tags 1622a, 1622b, etc. have the same cache set indicator, the indicator can be stored once in the register for the cache set (see, e.g., cache set registers 1712a and 1712b). This is Figure 17 The arrangement depicted in FIG. 17 has one benefit over the arrangement depicted in FIG. 16. In particular, the arrangement depicted in FIG. 17 has one less register (see, e.g., registers 1710a and 1710b) than the arrangement depicted in FIG. 16. Figure 16 In addition, the arrangement depicted in FIG. 17 has one less tag (see, e.g., tags 1722a, 1722b, 1726a, and 1726b) than the arrangement depicted in FIG. 16. Figure 17 The tags 1722a, 1722b, 1726a, and 1726b in FIG. 17 are shorter than the tags (see, e.g., 1622a, 1622b, 1626a, and 1626b) in FIG. 16 because Figure 16 The cache set registers (see, e.g., registers 1710a and 1710b) depicted in FIG. 17 store both the cache set index and the execution type. Figure 17

[0282] When the execution type is combined with the cache set index to form an extended cache set index, the extended cache set index can be used to select one of the cache sets. The tags from the selected cache set are then compared with the tags in the address to determine a hit or miss. The two-step selection can be similar to the conventional two-step selection using the cache set index, or can be used in combination with the extended tags to support more efficient interchanging of cache sets for different execution types (e.g., speculative and non-speculative execution types).

[0283] ​In some embodiments, a cache system (e.g., cache system 600 or 1000) can include a plurality of cache sets (e.g., cache sets 610a-c, 1010a-c, 1310a-d, 1610a-b, or 1710a-b). The plurality of cache sets can include a first cache set and a second cache set (e.g., see cache sets 1610a-b and sets 1710a-b). The cache system can also include a plurality of registers (e.g., registers 612a-c, 1012a-c, 1312a-d, 1612a-b, or 1712a-b) associated with the plurality of cache sets, respectively. The plurality of registers can include a first register associated with the first cache set and a second register associated with the second cache set (e.g., see registers 1612a-b and registers 1712a-b).

[0284] The cache system can also include a connection (e.g., see connection 604a) to a command bus (e.g., see command bus 605a) coupled between the cache system and a processor (e.g., see processors 601 and 1001). The cache system can also include a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) coupled between the cache system and the processor.

[0285] The cache system can also include a logic circuit (e.g., see logic circuits 606 and 1006) coupled to the processor to control the plurality of cache sets according to the plurality of registers. When the connection to the address bus receives a memory address from the processor (e.g., see memory addresses 102a-e shown in FIG. 1 and addresses 102e and 102b shown in FIGS. 16 and 17, respectively), the logic circuit can be configured to generate an extended tag (e.g., see extended tags 1650 and 1750) from at least the memory address. In addition, when the connection to the address bus receives a memory address from the processor, the logic circuit can be configured to determine whether the generated extended tag (e.g., see extended tags 1650 and 1750) matches a first extended tag (e.g., see extended tags 1640a and 1740a) of the first cache set (e.g., see cache sets 1610a and 1710a) or a second extended tag (e.g., see extended tags 1640b and 1740b) of the second cache set (e.g., see cache sets 1610b and 1710b). Figure 16 and 17 In addition, when the connection to the address bus receives a memory address from the processor, the logic circuit can be configured to determine whether the generated extended tag (e.g., see extended tags 1650 and 1750) matches a first extended tag (e.g., see extended tags 1640a and 1740a) of the first cache set (e.g., see cache sets 1610a and 1710a) or a second extended tag (e.g., see extended tags 1640b and 1740b) of the second cache set (e.g., see cache sets 1610b and 1710b).

[0286] The logic circuit (see, e.g., logic circuit 606 and 1006) can also be configured to implement a command received in a connection (see, e.g., connection 604a) with a command bus (see, e.g., command bus 605a) via a first cache set (see, e.g., cache set 1610a and 1710a) in response to a generated extended tag (see, e.g., extended tag 1650 and 1750) matching a first extended tag (see, e.g., extended tag 1640a and 1740a), and to implement the command via a second cache set (see, e.g., cache set 1610b and 1710b) in response to the generated extended tag matching a second extended tag (see, e.g., extended tag 1640b and 1740b).

[0287] The logic circuit (see, e.g., logic circuit 606 and 1006) can also be configured to generate a first extended tag (see, e.g., extended tag 1640a and 1740a) from cache addresses (see, e.g., blocks labeled 'Tag' in extended tags 1640a and 1740a, and tags 1622a, 1622b, 1722a, 1722b, etc.) of a first cache set (see, e.g., cache set 1610a and 1710a) and contents stored in a first register (see, e.g., register 1612a and 1712a) (see, e.g., blocks labeled 'Execution Type' in extended tags 1640a and 1740a, and block labeled 'Cache Set Index' in extended tag 1740a, and execution type 1632a and cache set index 1732a). The logic circuit can also be configured to generate a second extended tag (see, e.g., extended tag 1640b and 1740b) from cache addresses (see, e.g., blocks labeled 'Tag' in extended tags 1640b and 1740b, and tags 1626a, 1626b, 1726a, 1726b, etc.) of a second cache set (see, e.g., cache set 1610b and 1710b) and contents stored in a second register (see, e.g., register 1612b and 1712b) (see, e.g., blocks labeled 'Execution Type' in extended tags 1640b and 1740b, and block labeled 'Cache Set Index' in extended tag 1740b, and execution type 1632b and cache set index 1732b).

[0288] In some embodiments, a cache system (e.g., cache system 600 or 1000) can further include a connection (e.g., connection 604d) to an execution type signal line (e.g., see execution type signal line 605d) from a processor (e.g., see processors 601 and 1001) that identifies an execution type. In such embodiments, a logic circuit (e.g., see logic circuits 606 and 1006) can be configured to generate an extended tag (e.g., see extended tags 1650 and 1750) from a memory address (e.g., see memory addresses 102e and 102b shown in Figure 16 and 17 respectively) and the execution type identified by the execution type signal line (e.g., see execution type 110e shown in Figure 16 and 17 respectively). Moreover, in such embodiments, the content stored in each of the first register and the second register (e.g., see registers 1612a, 1612b, 1712a, and 1712b) can include the execution type (e.g., see first execution type 1632a and second execution type 1632b).

[0289] In some embodiments, to determine whether the generated extended tag (e.g., see extended tags 1650 and 1750) matches the first extended tag (e.g., see extended tags 1640a and 1740a) of the first cache set or the second extended tag (e.g., see extended tags 1640b and 1740b) of the second cache set, the logic circuit (e.g., see logic circuits 606 and 1006) can be configured to compare the first extended tag (e.g., see extended tags 1640a and 1740a) to the generated extended tag (e.g., see extended tags 1650 and 1750) to determine a cache hit or miss of the first cache set (e.g., see cache sets 1610a and 1710a). In particular, as shown in Figure 16 and 17 respectively, a first tag comparison circuit (e.g., see tag comparison circuits 1660a and 1760a) is configured to receive as input the first extended tag (e.g., see extended tags 1640a and 1740a) and the generated extended tag (e.g., see extended tags 1650 and 1750). The first tag comparison circuit (e.g., see tag comparison circuits 1660a and 1760a) is also configured to compare the first extended tag to the generated extended tag to determine a cache hit or miss of the first cache set. The first tag comparison circuit (e.g., see tag comparison circuits 1660a and 1760a) is also configured to output the determined cache hit or miss of the first cache set (e.g., see outputs 1662a and 1762a).

[0290] Furthermore, to determine whether the generated extended tag matches the first extended tag of the first cache set or the second extended tag of the second cache set, the logic circuit can be configured to compare the second extended tag (e.g., see extended tags 1640b and 1740b) to the generated extended tag (e.g., see extended tags 1650 and 1750) to determine a cache hit or miss of the second cache set (e.g., see cache sets 1610b and 1710b). In particular, as shown in Figure 16 and 17 The second tag comparison circuit (e.g., see tag comparison circuits 1660b and 1760b) is configured to receive the second extended tag (e.g., see extended tags 1640b and 1740b) and the generated extended tag (e.g., see extended tags 1650 and 1750) as inputs. The second tag comparison circuit (e.g., see tag comparison circuits 1660b and 1760b) is also configured to compare the second extended tag to the generated extended tag to determine a cache hit or miss of the second cache set. The second tag comparison circuit (e.g., see tag comparison circuits 1660b and 1760b) is also configured to output the determined cache hit or miss of the second cache set (e.g., see outputs 1662b and 1762b).

[0291] In some embodiments, the logic circuit (e.g., see logic circuits 606 and 1006) can be further configured to receive an output from the first cache set (e.g., see cache sets 1610a and 1710a) when the logic circuit determines that the generated extended tag (e.g., see extended tags 1640a and 1740a) matches the first extended tag of the first cache set (e.g., see extended tags 1640a and 1740a). The logic circuit can be further configured to receive an output from the second cache set (e.g., see cache sets 1610b and 1710b) when the logic circuit determines that the generated extended tag (e.g., see cache sets 1610a and 1710a) matches the second extended tag of the second cache set (e.g., see extended tags 1640a and 1740a).

[0292] In some embodiments, the cache address of the first cache set includes a first tag (e.g., see tags 1622a, 1622b, 1722a, and 1722b) of cache blocks (e.g., see cache blocks 1624a, 1624b, 1724a, and 1724b) in the first cache set (e.g., see cache sets 1610a and 1710a). In this embodiment, the cache address of the second cache set includes a second tag (e.g., see tags 1626a, 1626b, 1726a, and 1726b) of cache blocks (e.g., see cache blocks 1628a, 1628b, 1728a, and 1728b) in the second cache set (e.g., see cache sets 1610b and 1710b). Furthermore, in this embodiment, generally, the block index is used as an address within an individual cache set. For example, in this embodiment, the logic circuitry (e.g., see logic circuitry 606 and 1006) may be configured to use a first block index from the memory address (e.g., see the examples shown respectively). Figure 16 and 17 The block indices 106e and 106b from memory addresses 102e and 102b are used to obtain the first cache block in the first cache set and the tag associated with the first cache block (e.g., see cache blocks 1624a, 1624b, 1724a and 1724b and their corresponding associated tags 1622a, 1622b, 1722a and 1722b). Furthermore, logic circuits (e.g., see logic circuits 606 and 1006) can be configured to use a second block index from the memory address (e.g., see the examples shown in [references to be inserted here]). Figure 16 and 17 The second cache block in the second cache set and the tag associated with the second cache block are obtained by using the block indices 106e and 106b from memory addresses 102e and 102b (e.g., see cache blocks 1628a, 1628b, 1728a and 1728b and their corresponding associated tags 1626a, 1626b, 1726a and 1726b).

[0293] In some embodiments (e.g.) Figure 16In the embodiments described herein, when the first and second cache sets (e.g., see cache sets 1610a and 1610b) are in a first state, the cache address of the first cache set (e.g., see labels 1622a, 1622b, etc.) contains a first cache set indicator associated with the first cache set. The first cache set indicator may be a first cache set index. In this embodiment, when the first and second cache sets are in the first state, the cache address of the second cache set (e.g., see labels 1626a, 1626b, etc.) contains a second cache set indicator associated with the second cache set. The second cache set indicator may be a second cache set index.

[0294] In addition, in the exhibition Figure 16 In the embodiments described, when the first and second cache sets (e.g., see cache sets 1610a and 1610b) are in the second state (this is not in Figure 16 As depicted in [the text], the cache address of the first cache set contains a second cache set indicator associated with the second cache set. Additionally, when both the first and second cache sets are in a second state, the cache address of the second cache set contains a first cache set indicator associated with the first cache set. This change in the contents within the cache address enables interchangeability between cache sets.

[0295] In display Figure 16 In the embodiments described above, the cache set indicator is repeated in the tag of each cache block in the cache set, and therefore, the tags are more numerous than those in the cache set. Figure 17 The label for each cache block in the cache set depicted is longer. Figure 17 Instead of repeating the cache set index in the label of each cache block, the set index is stored in the cache set register associated with the cache set (see, for example, registers 1712a and 1712b).

[0296] In some embodiments (e.g.) Figure 17In the embodiment shown in FIG. 17, the first and second cache sets (e.g., see cache sets 1710a and 1710b) can be in a first state. When the first and second cache sets are in the first state, the cache addresses (e.g., see tags 1722a, 1722b, etc.) of the first cache set can not include a first cache set indicator associated with the first cache set. Instead, the first cache set indicator is shown as stored in the first cache set register 1712a (e.g., see first cache set index 1732a saved in cache set register 1712a). This can reduce the size of the tags of the cache blocks in the first cache set since the cache set indicator is stored in a register associated with the first cache set. Further, when the first and second cache sets are in the first state, the cache addresses (e.g., see tags 1726a, 1726b, etc.) of the second cache set can not include a second cache set indicator associated with the second cache set. Instead, the second cache set indicator is shown as stored in the second cache set register 1712b (e.g., see second cache set index 1732b saved in cache set register 1712b). This can reduce the size of the tags of the cache blocks in the second cache set since the cache set indicator is stored in a register associated with the second cache set.

[0297] Further, in the embodiment shown in FIG. 17, the first and second cache sets (e.g., see cache sets 1710a and 1710b) can be in a second state. When the first and second cache sets are in the second state, the cache addresses (e.g., see tags 1722a, 1722b, etc.) of the first cache set can not include a first cache set indicator associated with the first cache set. Instead, the first cache set indicator is shown as stored in the second cache set register 1712b. Further, when the first and second cache sets are in the second state, the cache addresses (e.g., see tags 1726a, 1726b, etc.) of the second cache set can not include a second cache set indicator associated with the second cache set. Instead, the second cache set indicator is shown as stored in the first cache set register 1712a. This change in the contents of the cache set registers can implement interchangeability between the cache sets. Figure 17 Figure 17 In the embodiment shown in FIG. 17, the first and second cache sets (e.g., see cache sets 1710a and 1710b) can be in a first state. When the first and second cache sets are in the first state, the cache addresses (e.g., see tags 1722a, 1722b, etc.) of the first cache set can not include a first cache set indicator associated with the first cache set. Instead, the first cache set indicator is shown as stored in the first cache set register 1712a (e.g., see first cache set index 1732a saved in cache set register 1712a). This can reduce the size of the tags of the cache blocks in the first cache set since the cache set indicator is stored in a register associated with the first cache set. Further, when the first and second cache sets are in the first state, the cache addresses (e.g., see tags 1726a, 1726b, etc.) of the second cache set can not include a second cache set indicator associated with the second cache set. Instead, the second cache set indicator is shown as stored in the second cache set register 1712b (e.g., see second cache set index 1732b saved in cache set register 1712b). This can reduce the size of the tags of the cache blocks in the second cache set since the cache set indicator is stored in a register associated with the second cache set.

[0298] In some embodiments, as described above, the first and second cache sets (e.g., see cache sets 1710a and 1710b) can be in a first state. When the first and second cache sets are in the first state, the cache addresses (e.g., see tags 1722a, 1722b, etc.) of the first cache set can not include a first cache set indicator associated with the first cache set. Instead, the first cache set indicator is shown as stored in the first cache set register 1712a (e.g., see first cache set index 1732a saved in cache set register 1712a). This can reduce the size of the tags of the cache blocks in the first cache set since the cache set indicator is stored in a register associated with the first cache set. Further, when the first and second cache sets are in the first state, the cache addresses (e.g., see tags 1726a, 1726b, etc.) of the second cache set can not include a second cache set indicator associated with the second cache set. Instead, the second cache set indicator is shown as stored in the second cache set register 1712b (e.g., see second cache set index 1732b saved in cache set register 1712b). This can reduce the size of the tags of the cache blocks in the second cache set since the cache set indicator is stored in a register associated with the second cache set. Figure 17 ​As shown, when the first and second registers (e.g., see registers 1712a and 1712b) are in a first state, the content stored in the first register (e.g., see register 1712a) may include a first cache set index (e.g., see cache set index 1732a) associated with a first cache set (e.g., see cache set index 1710a). And, the content stored in the second register (e.g., see register 1712b) may include a second cache set index (e.g., see cache set index 1732b) associated with a second cache set (e.g., see cache set index 1710a). In this embodiment, although not in Figure 17 As described in the text, when the first and second registers are in the second state, the contents stored in the first register may include a second cache set index associated with the second cache set, and the contents stored in the second register may include a first cache set index associated with the first cache set.

[0299] In some embodiments (e.g., Figure 16 In the embodiments shown and, for example, embodiments having a connection to an execution type signal line that identifies the execution type, the cache system (e.g., see cache system 1000) may further include a connection (e.g., see connection 1002) to a speculative state signal line (e.g., see speculative state signal line 1004) from a processor (e.g., see processor 1001) that identifies the state of speculative execution of instructions by the processor. In this embodiment, the connection to the speculative state signal line may be configured to receive the state of speculative execution. The state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to change the state of the first and second cache sets (e.g., see cache sets 1610a and 1610b) if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from speculative execution to non-speculative execution, the logic circuit can be configured to maintain the state of the first and second cache sets (e.g., see cache sets 1610a and 1610b) without changing if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0300] Similarly, in some embodiments (e.g., as...) Figure 17In some embodiments, the cache system can include a plurality of cache sets including a first cache set and a second cache set. The cache system can also include a plurality of registers associated with the plurality of cache sets, respectively, including a first register associated with the first cache set and a second register associated with the second cache set. The cache system can further include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, and a logic circuit coupled to the processor to control the plurality of cache sets according to the plurality of registers. The logic circuit can be configured to generate a first extended tag from a cache address of the first cache set and contents stored in the first register, and to generate a second extended tag from a cache address of the second cache set and contents stored in the second register. The logic circuit can also be configured to determine whether the first extended tag of the first cache set or the second extended tag of the second cache set matches a generated extended tag generated from a memory address received from the processor. And, the logic circuit can be configured to implement a command received in the connection to the command bus via the first cache set in response to the generated extended tag matching the first extended tag, and to implement the command via the second cache set in response to the generated extended tag matching the second extended tag.

[0301] In some embodiments, the cache system can include a plurality of cache sets including a first cache set and a second cache set. The cache system can also include a plurality of registers associated with the plurality of cache sets, respectively, including a first register associated with the first cache set and a second register associated with the second cache set. The cache system can further include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, and a logic circuit coupled to the processor to control the plurality of cache sets according to the plurality of registers. The logic circuit can be configured to generate a first extended tag from a cache address of the first cache set and contents stored in the first register, and to generate a second extended tag from a cache address of the second cache set and contents stored in the second register. The logic circuit can also be configured to determine whether the first extended tag of the first cache set or the second extended tag of the second cache set matches a generated extended tag generated from a memory address received from the processor. And, the logic circuit can be configured to implement a command received in the connection to the command bus via the first cache set in response to the generated extended tag matching the first extended tag, and to implement the command via the second cache set in response to the generated extended tag matching the second extended tag.

[0302] In such embodiments, the cache system can also include a connection to an address bus coupled between the cache system and the processor. When the connection to the address bus receives a memory address from the processor, the logic circuit can be configured to generate an extended tag from at least the memory address. Further, the cache system can include a connection to an execution type signal line from the processor that identifies an execution type. In such instances, the logic circuit can be configured to generate the extended tag from the memory address and the execution type identified by the execution type signal line. Further, the contents stored in each of the first register and the second register can include the execution type.

[0303] Additionally, to determine whether the generated extended tag matches the first extended tag of the first cache set or the second extended tag of the second cache set, the logic circuit can be configured to: compare the first extended tag to the generated extended tag to determine a cache hit or miss of the first cache set; and compare the second extended tag to the generated extended tag to determine a cache hit or miss of the second cache set. Further, the logic circuit can be configured to: receive an output from the first cache set when the logic circuit determines that the generated extended tag matches the first extended tag of the first cache set; and receive an output from the second cache set when the logic circuit determines that the generated extended tag matches the second extended tag of the second cache set. In such embodiments and other embodiments, the cache address of the first cache set can include a first tag of a cache block in the first cache set, and the cache address of the second cache set can include a second tag of a cache block in the second cache set.

[0304] In some embodiments, a cache system can include a plurality of cache sets including a first cache set and a second cache set. The cache system can also include a plurality of registers associated with the plurality of cache sets, respectively, including a first register associated with the first cache set and a second register associated with the second cache set. Also, the cache system can include a connection to a command bus coupled between the cache system and a processor, a connection to an execution type signal line from the processor identifying an execution type, a connection to an address bus coupled between the cache system and the processor, and a logic circuit coupled to the processor to control the plurality of cache sets according to the plurality of registers. When the connection to the address bus receives a memory address from the processor, the logic circuit can be configured to generate an extended tag from the memory address and the execution type identified by the execution type signal line, and determine whether the generated extended tag matches a first extended tag of the first cache set or a second extended tag of the second cache set. Further, the logic circuit can be configured to implement a command received in the connection to the command bus via the first cache set in response to the generated extended tag matching the first extended tag, and implement the command via the second cache set in response to the generated extended tag matching the second extended tag.

[0305] Figure 18 Example aspects of example computing devices exhibiting cache systems (e.g., see cache systems 600 and 1000 exhibited in FIGS. 6 and 10, respectively) having interchangeable cache sets (e.g., see cache sets 1810a, 1810b, and 1810c) with physical cache set outputs (e.g., see physical outputs 1820a, 1820b, and 1820c) mapped to logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c) with mapping circuitry 1830 in accordance with some embodiments of the present disclosure are shown. Figure 6 and 10

[0306] ​As shown, the cache system can include a plurality of cache sets (see, e.g., cache sets 1810a, 1810b, and 1810c). The plurality of cache sets includes a first cache set (see, e.g., cache set 1810a) configured to provide a first physical output (see, e.g., physical output 1820a) upon a cache hit, and a second cache set (see, e.g., cache set 1810b) configured to provide a second physical output (see, e.g., physical output 1820b) upon a cache hit. The cache system can also include a connection (see, e.g., connection 604a) to a command bus (see, e.g., command bus 605a) coupled between the cache system and a processor (see, e.g., processors 601 and 1001). The cache system can also include a connection (see, e.g., connection 604b) to an address bus (see, e.g., address bus 605b) coupled between the cache system and the processor. Figure 6 and 10

[0307] As shown in Figure 18 , the cache system includes a control register 1832 (e.g., a physical-to-logical-set-map (PLSM) register 1832) and a mapping circuit 1830 coupled to the control register to map respective physical outputs (see, e.g., physical outputs 1820a, 1820b, and 1820c) of the plurality of cache sets (see, e.g., cache sets 1810a, 1810b, and 1810c) to a first logical cache (e.g., a normal cache) and a second logical cache (e.g., a shadow cache) as corresponding logical cache set outputs (see, e.g., logical outputs 1840a, 1840b, and 1840c). The mapping of the physical outputs (see, e.g., physical outputs 1820a, 1820b, and 1820c) to the logical cache set outputs (see, e.g., logical outputs 1840a, 1840b, and 1840c) by the mapping circuit 1830 is in accordance with a state of the control register 1832. As shown in Figure 18 , at least logical outputs 1840a and 1840b are mapped to the first logical cache for a first type of execution, and at least logical output 1840c is mapped to the second logical cache for a second type of execution. Not shown, the cache system can be configured to be coupled between the processor and a memory system (see, e.g., memory system 603).

[0308] ​When a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when control register 1832 is in a first state (shown in Figure 18 FIG. 18B), mapping circuit 1830 can be configured to map a first physical output (e.g., see physical output 1820a) to a first logical cache (e.g., see logical output 1840a) for a first type of execution by the processor to implement a command received from a command bus (e.g., see command bus 605a) to access a memory system (e.g., see memory system 601) via a first cache set (e.g., cache set 1820a) during the first type of execution (e.g., non-speculative execution).

[0309] Further, when a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when control register 1832 is in a first state (shown in Figure 18 FIG. 18B), mapping circuit 1830 can be configured to map a second physical output (e.g., see physical output 1820b) to a second logical cache (e.g., see logical output 1840b) for a second type of execution by the processor to implement a command received from a command bus (e.g., see command bus 605a) to access a memory system (e.g., see memory system 601) via a second cache set (e.g., cache set 1820b) during the second type of execution (e.g., speculative execution).

[0310] When a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when control register 1832 is in a second state (not shown in Figure 18 FIG. 18B), mapping circuit 1830 can be configured to map a first physical output (e.g., see physical output 1820a) to a second logical cache (e.g., see logical output 1840b) to implement a command received from a command bus (e.g., see command bus 605a) to access a memory system (e.g., see memory system 601) via a first cache set (e.g., cache set 1820a) during the second type of execution (e.g., speculative execution).

[0311] Furthermore, when a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when a control register 1832 is in a second state (not shown in Figure 18 the mapping circuit 1830 is configured to map a second physical output (e.g., see physical output 1820b) to a first logical cache (e.g., see logical output 1840a) to implement a command received from a command bus (e.g., see command bus 605a) to access a memory system (e.g., see memory system 601) via a second cache set (e.g., cache set 1820b) during a first type of execution (e.g., non-speculative execution).

[0312] In some embodiments, the first logical cache is a normal cache for non-speculative execution by the processor, and the second logical cache is a shadow cache for speculative execution by the processor.

[0313] The mapping circuit 1830 addresses issues related to execution type. The mapping circuit 1830 provides a solution on how execution type is involved in mapping physical cache sets to logical cache sets. If the mapping circuit 1830 is used, a memory address (e.g., see address 102b) can be applied in each cache set (e.g., see cache sets 1810a, 1810b, and 1810c) to produce a physical output (e.g., see physical outputs 1820a, 1820b, and 1820c). The physical output (e.g., see physical outputs 1820a, 1820b, and 1820c) includes a tag and a cache block (e.g., see block index 106b) found using a block index of the memory address. The mapping circuit 1830 can re-route the physical output (e.g., see physical outputs 1820a, 1820b, and 1820c) to one of the logical outputs (e.g., see logical outputs 1840a, 1840b, and 1840c). The cache system can do a tag comparison at the physical output or at the logical output. If the tag comparison is done at the physical output, a tag hit or miss of the physical output is routed through the mapping circuit 1830 to produce a hit or miss of the logical output. Otherwise, the tag itself is routed through the mapping circuit 1830; and the tag comparison is done at the logical output to produce a corresponding tag hit or miss result.

[0314] As Figure 18As explained in Figure 18 , the logical outputs are predefined for speculative execution and non-speculative execution. Thus, the current execution type (see, e.g., execution type 110e) can be used to select which portion of the logical outputs will be used. For example, since it is predefined that the logical output 1840c is for speculative execution in Figure 18 , if the current execution type is normal execution, the result thereof can be discarded. Otherwise, if the current execution type is speculative, the result from the first portion of the logical outputs (e.g., outputs 1840a and 1840b) in

[0315] In the embodiment shown in Figure 18 , if the current execution type is speculative, the hit or miss result from the logical output for non-speculative execution can be ANDed with Ό' to force the cache "miss"; and the hit or miss result from the logical output for non-speculative execution can be ANDed with '1' to leave the result unaltered. The execution type 110e can be configured such that speculative execution = 0 and non-speculative execution = 1, and the tag hit or miss result from the non-speculative output 1840a to 1840b can be ANDed with the execution type (e.g., execution type 110e) to produce a hit or miss that includes the consideration of both the matching tag and the execution type. Also, the tag hit or miss result from 1840c can be ANDed with the inverse of the execution type 110e to produce a hit or miss.

[0316] Figure 19 and 20 An example aspect of an example computing device having a cache system (see, e.g., cache systems 600 and 1000 shown in Figure 18 and Figure 18 , respectively) with interchangeable cache sets (see, e.g., cache sets 1810a, 1810b, and 1810c depicted in Figure 19 ) that map physical cache set outputs (see, e.g., physical outputs 1820a, 1820b, and 1820c depicted in Figures 18 to 21 ) to logical cache set outputs (see, e.g., logical outputs 1840a, 1840b, and 1840c) with circuitry (mapping circuitry 1830) that maps the physical cache set outputs (e.g., see physical outputs 1820a, 1820b, and 1820c depicted in Figure 6 and 10 ) to the logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c) according to some embodiments of the present disclosure is shown.

[0317] In particular, Figure 19The first cache set 1810a, the first cache set register 1812a, the tag 1815a for the first cache set (which includes the current tag and cache set index), the tag and set index 1850 from the address 102b (which includes the current tag 104b and current cache set index 112b from the memory address 102b), and the tag comparison circuit 1860a for the first cache set 1810a are shown. In addition, Figure 19 The first cache set 1810a is shown with cache blocks and associated tags (see, e.g., cache blocks 1818a and 1818b, and tags 1816a and 1816b), and the first cache set register 1812a holding the cache set index 1813a for the first cache set. In addition, Figure 19 The tag comparison circuit 1860b for the second cache set 1810b is shown. The figure shows the physical output 1820a from the first cache set 1810a being output to the mapping circuit 1830. The second cache set 1810b and other cache sets of the system can also provide their respective physical outputs to the mapping circuit 1830 (although this is not depicted in Figure 19

[0318] Figure 20 An example of multiple cache sets of a system providing physical outputs to the mapping circuit 1830 (see, e.g., physical outputs 1820a, 1820b, and 1820c provided by cache sets 1810a, 1810b, and 1810c, respectively, as shown in Figure 20 Figure 20 Portions of the mapping circuit 1830 are also depicted (see, e.g., multiplexers 2004a, 2004b, and 2004c, and PLSM registers 2006a, 2006b, and 2006c). Figure 20 The first cache 1810a is also shown with at least cache blocks 1818a and 1818b and associated tags 1816a and 1816b. Also, the second cache 1810b is shown with at least cache blocks 1818c and 1818d and associated tags 1816c and 1816d.

[0319] Figure 19 ​​Multiplexers 1904a and 1904b and PLSM registers 1906a and 1906b are also shown, which may be part of logic circuitry (e.g., see logic circuitry 606 and 1006) and / or mapping circuitry (e.g., see mapping circuitry 1830). Each of multiplexers 1904a and 1904b receives at least hit or miss results 1862a and 1862b from tag comparison circuits 1860a and 1860b, which each compares a corresponding tag of a cache set (e.g., see the tag of the first cache set 1815a) with a tag and set index from a memory address (e.g., see tag and set index 1850). In some instances, an equivalent multiplexer may exist for each tag comparison for each cache set of the system. Each of the multiplexers (e.g., see multiplexers 1904a and 1904b) can output a selected hit or miss result based on the state of the corresponding PLSM register of the multiplexer (e.g., see PLSM registers 1906a and 1906b). The PLSM register controlling the selection of the multiplexer for outputting cache hit or miss results from cache set comparisons can be controlled by such a register when the main PLSM register (e.g., control register 1832) is part of the mapping circuit 1830.

[0320] In some embodiments, the PLSM register (e.g., see PLSM registers 1906a and 1906b, and...) Figure 21 Each of the PLSM registers 2110a, 2110b, and 2110c depicted herein may be a one-, two-, or three-bit register, or a register of any bit length, depending on the specific implementation. Such PLSM registers (e.g., used by multiplexers) can be used to select the correct result for the appropriate physical tag comparison result or to output the correct result for one of the logic cells that hit or missed.

[0321] exist Figure 20 In the case of the PLSM registers 2006a, 2006b, and 2006c depicted, such registers (e.g., used by a multiplexer) can be used to select a cache set (e.g., see...). Figure 20 The appropriate physical output of the cache sets 1810a, 1810b, and 1810c shown in the figure (e.g., see the figure shown in the figure). Figure 20 The physical outputs 1820a, 1820b, and 1820c are shown in the diagram. These PLSM registers can also be, depending on the specific implementation, one-, two-, or three-bit registers, or registers of any bit length. Furthermore, the control register 1832 can be, depending on the specific implementation, a one-, two-, or three-bit register, or registers of any bit length.

[0322] In some embodiments, the selection of the physical output from the cache set or the selection of the cache hit or miss is made by a multiplexer (see, e.g., multiplexers 1904a and 1904b shown in FIG. 19, multiplexers 2004a, 2004b, and 2004c shown in FIG. 20, and multiplexers 2110a, 2110b, and 2110c shown in FIG. 21) that is arranged in the system with at least one multiplexer per output type and per logical unit or per cache set. As shown in the figures, in some embodiments, where there are n number of cache sets or logical comparison units, there are n number of n-to-l multiplexers. Figure 19 Figure 20 Figure 21

[0323] As shown in FIG. 19, the computing device can include a first multiplexer (e.g., multiplexer 1904a) configured to output a first hit or miss result or a second hit or miss result (e.g., see hit or miss outputs 1862a and 1862b as shown in FIG. 18) to the processor according to content received by a first PLSM register (e.g., see PLSM register 1906a). The computing device can also include a second multiplexer (e.g., multiplexer 1904b) configured to output a second hit or miss result or a first hit or miss result (e.g., see hit or miss outputs 1862b and 1862a as shown in FIG. 18) to the processor according to content received by a second PLSM register (e.g., see PLSM register 1906b). Figure 19 Figure 19 Figure 19

[0324] In some embodiments, the content of the PLSM registers can be received from a control register (e.g., control register 1832 shown in FIG. 18). For example, in some embodiments, the first multiplexer outputs the first hit or miss result when the content received by the first PLSM register indicates a first state and outputs the second hit or miss result when the content received by the first PLSM register indicates a second state. Also, the second multiplexer can output the second hit or miss result when the content received by the second PLSM register indicates the first state. And, the second multiplexer can output the first hit or miss result when the content received by the second PLSM register indicates the second state. Figure 18

[0325] As shown in FIG. 19, the computing device can include a first multiplexer (e.g., multiplexer 1904a) configured to output a first hit or miss result or a second hit or miss result (e.g., see hit or miss outputs 1862a and 1862b as shown in FIG. 18) to the processor according to content received by a first PLSM register (e.g., see PLSM register 1906a). The computing device can also include a second multiplexer (e.g., multiplexer 1904b) configured to output a second hit or miss result or a first hit or miss result (e.g., see hit or miss outputs 1862b and 1862a as shown in FIG. 18) to the processor according to content received by a second PLSM register (e.g., see PLSM register 1906b). Figure 20 ​​​​​​​As shown in the middle, the computing device can include a first multiplexer (e.g., multiplexer 2004a) configured to output either the first physical output 1820a of the first cache set or the second physical output 1820b of the second cache set to the processor according to content received by the first PLSM register (e.g., PLSM register 2006a). The computing device can include a second multiplexer (e.g., multiplexer 2004b) configured to output either the first physical output 1820a of the first cache set or the second physical output 1820b of the second cache set to the processor according to content received by the second PLSM register (e.g., PLSM register 2006b).

[0326] In some embodiments, the content of the PLSM registers can be received from a control register (e.g., control register 1832 shown in the middle). For example, in some embodiments, when the content received by the first PLSM register indicates a first state, the first multiplexer outputs the first physical output 1820a, and when the content received by the first PLSM register indicates a second state, the first multiplexer outputs the second physical output 1820b. Also, when the content received by the second PLSM register indicates a first state, the second multiplexer can output the second physical output 1820b. And, when the content received by the second PLSM register indicates a second state, the second multiplexer can output the first physical output 1820a. Figure 18

[0327] In some embodiments, the block selection can be based on a combination of the block index and either the primary or shadow setting. Such a parameter can control the PLSM register.

[0328] In some embodiments (e.g., the example shown in the middle of Figure 19 and 20 In some embodiments, only one address (e.g., tag and index) is fed into the interchangeable cache set (e.g., cache sets 1810a, 1810b, and 1810c). In such embodiments, if a cache set misses, there is a signal to update which cache set according to the memory control.

[0329] ​When the cache set is in the first state, multiplexer 1904a is controlled by PLSM register 1906a to provide the hit or miss output of cache set 1810a, and thus the hit or miss status of the cache set for main execution or normal execution. When the cache set is in the first state, multiplexer 1904b is controlled by PLSM register 1906b to provide the hit or miss output of cache set 1810b, and thus the hit or miss status of the cache set for speculative execution. On the other hand, when the cache set is in the second state, multiplexer 1904a is controlled by PLSM register 1906a to provide the hit or miss output of cache set 1810b, and thus the hit or miss status of the cache set for main execution or normal execution. When the cache set is in the second state, multiplexer 1904b is controlled by PLSM register 1906b to provide the hit or miss output of cache set 1810a, and thus the hit or miss status of the cache set for speculative execution.

[0330] Similar to the selection of the hit or miss signal, the data found from the interchangeable cache can be selected to produce one result for the processor (e.g., in the case that there is a hit), e.g., see physical outputs 1820a, 1820b, and 1820c shown in Figure 20

[0331] ​For example, in the first state of cache set, when cache set 1810a is used as the primary cache set and cache set 1810b is used as the shadow cache set, multiplexer 2004a is controlled by PLSM register 2006a to select the physical output 1820a of cache set 1810a for the primary cache or normal logical cache for non-speculative execution. Also, for example, in the second state of cache set, when cache set 1810b is used as the primary cache set and cache set 1810a is used as the shadow cache set, then multiplexer 2004a is controlled by PLSM register 2006a to select the physical output 1820b of cache set 1810b for the primary cache or normal logical cache for non-speculative execution. In such an example, in the first state of cache set, when cache set 1810a is used as the primary cache set and cache set 1810b is used as the shadow cache set, then multiplexer 2004b is controlled by PLSM register 2006b to select the physical output 1820b of cache set 1810b for the shadow logical cache for speculative execution. Also, for example, in the second state of cache set, when cache set 1810a is used as the primary cache set and cache set 1810b is used as the shadow cache set, then multiplexer 2004b is controlled by PLSM register 2006b to select the physical output 1820a of cache set 1810a for the shadow logical cache for speculative execution.

[0332] In some embodiments, the cache system can further include a plurality of registers (e.g., see registers 1812a as shown in Figures 18 to 21 FIG. 1C) associated with the plurality of cache sets (e.g., see cache sets 1810a, 1810b, and 1810c as shown in Figure 19 FIG. 1C). The registers can include a first register (e.g., see register 1812a) associated with a first cache set (e.g., see cache set 1810a), and a second register (not depicted in Figures 18 to 21 FIG. 1C but depicted in Figure 6 and 10The cache system can further include a logic circuit (e.g., see logic circuit 606 and 1006) coupled to the processor (e.g., see logic circuits 601 and 1001) to control the plurality of cache sets in accordance with a plurality of registers. When a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) receives a memory address from the processor, the logic circuit can be configured to generate a set index from at least the memory address, and determine whether the generated set index matches contents stored in a first register or matches contents stored in a second register. Also, the logic circuit can be configured to implement a command received in a connection (e.g., see connection 604a) to a command bus (e.g., see command bus 605a) via a first cache set in response to the generated set index matching the contents stored in the first register, and implement the command via a second cache set in response to the generated set index matching the contents stored in the second register.

[0333] In some embodiments, a mapping circuit (e.g., see mapping circuit 1830) can be part of or connected to the logic circuit, and a state of a control register (e.g., see control register 1832) can control a state of a cache set of the plurality of cache sets. In some embodiments, the state of the control register can control the state of the cache set of the plurality of cache sets by changing a valid bit of each block of the cache set (e.g., see Figures 21 to 23 ).

[0334] Further, in some instances, the cache system can further include a connection (e.g., see connection 1002) to a speculation status signal line (e.g., see speculation status signal line 1004) from the processor that identifies a status of speculative execution of instructions by the processor. The connection to the speculation status signal line can be configured to receive the status of speculative execution, and the status of speculative execution can indicate whether results of the speculative execution are to be accepted or rejected. When the type of execution changes from speculative execution to non-speculative execution, the logic circuit (e.g., see logic circuit 606 and 1006) can be configured to change the state of the first and second cache sets via the control register (e.g., see control register 1832) if the status of speculative execution indicates that results of the speculative execution are to be accepted. Also, when the type of execution changes from speculative execution to non-speculative execution, the logic circuit can be configured to maintain the state of the first and second cache sets without change via the control register if the status of speculative execution indicates that results of the speculative execution are to be rejected.

[0335] In some embodiments, a mapping circuit (e.g., see mapping circuit 1830) is part of or connected to a logic circuit (e.g., see logic circuit 606 and 1006), and a state of a control register (e.g., see control register 1832) can control a state of a cache register (e.g., see register 1812a as shown in Figure 19 In such an example, the cache system can further include a connection (e.g., see connection 1002) to a speculation status signal line (e.g., see speculation status signal line 1004) from the processor that identifies a status of speculative execution of instructions by the processor. The connection to the speculation status signal line can be configured to receive a status of speculative execution, and the status of speculative execution indicates whether a result of the speculative execution is to be accepted or rejected. When the type of execution changes from speculative execution to non-speculative execution, the logic circuit can be configured to change the states of the first and second registers via the control register if the status of speculative execution indicates that the result of the speculative execution is to be accepted. Also, when the type of execution changes from speculative execution to non-speculative execution, the logic circuit can be configured to maintain the states of the first and second registers without change via the control register if the status of speculative execution indicates that the result of the speculative execution is to be rejected.

[0336] Figure 21 An example aspect of an example computing device having a cache system with interchangeable cache sets (e.g., cache sets shown in Figure 18 , including cache sets 1810a, 1810b, and 1810c) in accordance with some embodiments of the present disclosure is shown. The cache sets (e.g., cache sets 1810a, 1810b, and 1810c) are shown with a physical cache set output mapped to a logical cache set output with a circuit (mapping circuit 1830) shown in Figure 18

[0337] Figure 21 The portion depicted in

[0338] As shown in Figure 21 , a first cache set (e.g., cache set 1810a) can be coupled between the memory and the processor, and can include a first plurality of blocks (e.g., see blocks 1812a-1, 1812a-2, 1812a-3, and 1812a-4 shown in Figure 21 ​Each of the first plurality of blocks can include cached data, a first valid bit, and a block address including an index and a tag. Also, the processor (alone or in conjunction with the cache controller) can be configured to change each first valid bit from indicating valid to indicating invalid when the speculation of the speculative thread succeeds, such that in the second state of the cache set, the first plurality of blocks become accessible for the main thread and blocked for the speculative thread.

[0339] As shown in Figure 21 , a second cache set (e.g., cache set 1810b) can be coupled between the main memory and the processor, and can include a second plurality of blocks for the speculative thread in the first state of the cache set (see, e.g., blocks 2101d, 2101e, and 2101f shown in Figure 21 Each of the second plurality of blocks can include cached data, a second valid bit, and a block address including an index and a tag. Also, the processor (alone or in conjunction with the cache controller) can be configured to change each second valid bit from indicating invalid to indicating valid when the speculation of the speculative thread succeeds, such that in the second state of the cache set, the second plurality of blocks become accessible for the main thread and blocked for the speculative thread.

[0340] In some embodiments, as shown in Figure 21 , a block of the first plurality of blocks can correspond to a respective block of the second plurality of blocks. Also, a block of the first plurality of blocks can correspond to a respective block of the second plurality of blocks by having the same block address as the respective block of the second plurality of blocks.

[0341] Further, as shown in Figure 21 , the computing device can include a first physical-to-logical-map-set-map (PLSM) register (e.g., PLSM register 1 2108a) configured to receive a first valid bit of a block of the first plurality of blocks. The first valid bit can indicate a validity of cached data of the block of the first plurality of blocks. It can also indicate whether the block of the first plurality of blocks or a corresponding block of the second plurality of blocks is used in the main thread.

[0342] Further, as shown in Figure 21 , the computing device can include a second PLSM register (e.g., PLSM register 2 2108b) configured to receive a second valid bit of a block of the second plurality of blocks. The second valid bit indicates a validity of cached data of the block of the second plurality of blocks. It can also indicate whether the block of the second plurality of blocks or a corresponding block of the first plurality of blocks is used in the main thread.

[0343] Further, as shown in Figure 21As shown in the middle, the computing device can include a logic unit 2104a for the first cache set, which is configured to determine whether a block of the first plurality of blocks is a hit or a miss. The logic unit 2104a is shown to include a comparator 2106a and an AND gate 2107a. The comparator 2106a can determine whether there is a match between the tag of the block and the corresponding tag of the address in the memory. And, if the tags match and the valid bit of the block is valid, the AND gate 2107a outputs an indication of a block hit. Otherwise, the AND gate 2107a outputs an indication of a block miss. In other words, the logic unit 2104a for the first cache is configured to output a first hit or miss result according to the determination at the logic unit.

[0344] Further, as shown in the middle, Figure 22 As shown in the middle, the computing device can include a logic unit 2104b for the second cache set, which is configured to determine whether a block of the second plurality of blocks is a hit or a miss. The logic unit 2104b is shown to include a comparator 2106b and an AND gate 2107b. The comparator 2106b can determine whether there is a match between the tag of the block and the corresponding tag of the address in the memory. And, if the tags match and the valid bit of the block is valid, the AND gate 2107b outputs an indication of a block hit. Otherwise, the AND gate 2107b outputs an indication of a block miss. In other words, the logic unit 2104b for the second cache is configured to output a second hit or miss result according to the determination at the logic unit.

[0345] Further, as shown in the middle, Figure 21 As shown in the middle, the computing device can include a logic unit 2104b for the second cache set, which is configured to determine whether a block of the second plurality of blocks is a hit or a miss. The logic unit 2104b is shown to include a comparator 2106b and an AND gate 2107b. The comparator 2106b can determine whether there is a match between the tag of the block and the corresponding tag of the address in the memory. And, if the tags match and the valid bit of the block is valid, the AND gate 2107b outputs an indication of a block hit. Otherwise, the AND gate 2107b outputs an indication of a block miss. In other words, the logic unit 2104b for the second cache is configured to output a second hit or miss result according to the determination at the logic unit.

[0346] In some embodiments, the block selection can be based on a combination of the block index and the primary or shadow setting.

[0347] In some embodiments, only one address (e.g., tag and index) is fed into the interchangeable cache set (e.g., cache sets 1810a, 1810b, and 1810c). In such embodiments, if a cache set produces a miss, there is a signal that updates which cache set according to the memory control. Similar to the selection of the hit or miss signal, the data found from the interchangeable cache can be selected to produce one result for the processor (e.g., in the case there is a hit). For example, in a first state of the cache sets, if cache set 1810a is used as the primary cache set and cache set 1810b is used as the shadow cache set, multiplexer 2110a is controlled by PLSM register 2108a to select the hit or miss output of cache set 1804a and the hit or miss state of the primary cache set. Also, multiplexer 2110b is controlled by PLSM register 2108b to provide the hit or miss output of cache set 1810b, and thus the hit or miss state of the shadow cache set.

[0348] In such embodiments, when the cache sets are in a second state, when cache set 1810a is used as the shadow cache and cache set 1810b is used as the primary cache, multiplexer 2110a can be controlled by PLSM register 2108b to select the hit or miss output of cache set 1810b and the hit or miss state of the primary cache. Also, multiplexer 2110b can be controlled by PLSM register 2108b to provide the hit or miss output of cache set 1810a, and thus the hit or miss state of the shadow cache.

[0349] Thus, multiplexer 2110a can output whether the primary cache has a hit or miss in cache for the address; and multiplexer 2110b can output whether the shadow cache has a hit or miss in cache for the same address. Then, depending on whether the address is speculative or not, one of the outputs can be selected. When there is a cache miss, the address is used in memory to load the data to the corresponding cache. The PLSM register can similarly implement the update of the corresponding cache set 1810a or set 1810b.

[0350] In some embodiments, in the first state of the cache set, during speculative execution of the first instruction by the speculative thread, effects of the speculative execution are stored within a second cache set (e.g., cache set 1810b). During the speculative execution of the first instruction, the processor can be configured to validate a signal indicative of the speculative execution configured to block changes to the first cache set (e.g., cache set 1810a). When the signal is validated by the processor, the processor can be further configured to block the second cache set (e.g., cache set 1810b) from updating memory.

[0351] When the state of the cache set changes to the second state, the second cache set (rather than the first cache set) is used with the first instruction in response to determining that execution of the first instruction is to be performed with the main thread. The first cache set is used with the first instruction in response to determining that execution of the first instruction is not to be performed with the main thread.

[0352] In some embodiments, in the first state, during speculative execution of the first instruction, the processor accesses memory via the second cache set (e.g., cache set 1810b). And, during the speculative execution of the one or more instructions, access to contents of the second cache is limited to the speculative execution of the first instruction by the processor. The processor can be inhibited from changing the first cache set (e.g., cache set 1810a) during the speculative execution of the first instruction.

[0353] In some embodiments, contents of the first cache set (e.g., cache set 1810a) and / or the second cache set (e.g., cache set 1810b) can be accessible via a cache coherency protocol.

[0354] Figures 18 to 20 and 23 Methods 2200 and 2300 to use interchangeable cache sets for speculative and non-speculative execution by a processor, respectively, according to some embodiments of the present disclosure are shown. In particular, methods 2200 and 2300 can be performed by the computing device described in Figure 16 . Moreover, a similar method can be performed by the computing device described in Figure 17 as well as any of the computing devices disclosed herein; however, such a computing device would control the cache state, cache set state, or cache set register state via another parameter other than the effective bits of a block address. For example, in Figures 21 to 23 , the state of the cache set is controlled via a cache set indicator within a tag of a block of the cache set. And, for example, in Figure 21In this context, the state of the cache set is controlled via the state of the cache set register associated with the cache set. In this instance, the state is controlled via the cache set index stored in the cache set register. On the other hand, for cache sets accessed via… Figure 21 The disclosed embodiments control the state of the cache set via the valid bits of the block addresses within the cache set.

[0355] Method 2200 includes, at block 2202, a main thread and a speculative thread executed by a processor (e.g., processor 1001). Method 2200 includes, at block 2204, a first cache set (e.g., such as...) of a cache system coupled between the memory system and the processor. Figure 22 The cache set 1810a shown in the document provides the first plurality of blocks for the main thread (e.g., Figure 23 The blocks 2101a, 2101b, and 2101c depicted in the diagram. Each of the first plurality of blocks may contain cached data, a first valid bit, and a block address with an index and a tag. Method 2200 includes, at block 2206, a second plurality of blocks (e.g., blocks 2101d, 2101e, and 2101f) in a second cache set (e.g., cache set 1810b) coupled between the memory system and the processor, for speculative threads. Each of the second plurality of blocks may contain cached data, a second valid bit, and a block address with an index and a tag.

[0356] At box 2207, method 2200, for example, determines by the processor whether the speculation of the speculative thread has successfully continued, such that a first plurality of blocks become accessible to the speculative thread but blocked from the main thread, and a second plurality of blocks become accessible to the main thread but blocked from the speculative thread. Figure 21 As shown, if the speculative thread's speculation fails, the processor does not change the validity bits of the first and second plurality of blocks, retaining the same validity values ​​as before determining whether the speculative thread succeeded at box 2207. Therefore, the state of the cache set does not change from the first state to the second state.

[0357] At block 2208, the method 200 continues with the processor (alone or in conjunction with the cache controller) changing each first valid bit from indicating valid to indicating invalid when the speculation of the speculative thread succeeds, such that the first plurality of blocks become accessible for the speculative thread and blocked for the main thread. Further, at block 2210, the method 200 continues with the processor (alone or in conjunction with the cache controller) changing each second valid bit from indicating invalid to indicating valid when the speculation of the speculative thread succeeds, such that the second plurality of blocks become accessible for the main thread and blocked for the speculative thread. Thus, the state of the cache set does not change from the first state to the second state.

[0358] In some embodiments, during the speculative execution of the first instruction by the speculative thread, the effects of the speculative execution are stored within the second cache set. In such embodiments, during the speculative execution of the first instruction, the processor can assert a signal indicating that the speculative execution can block changes to the first cache. Further, when the signal is asserted by the processor, the processor can block the second cache from updating the memory. This occurs when the cache sets are in the first state.

[0359] Further, in such embodiments, in response to determining that the execution of the first instruction is to be performed with the main thread, the second cache set (and not the first cache set) is used with the first instruction. In response to determining that the execution of the first instruction is not to be performed with the main thread, the first cache is used with the first instruction. This occurs when the cache sets are in the second state.

[0360] In some embodiments, during the speculative execution of the first instruction, the processor accesses the memory via the second cache. Also, during the speculative execution of the one or more instructions, the accesses to the contents in the second cache are limited to the speculative execution of the first instruction by the processor. In such embodiments, during the speculative execution of the first instruction, the processor is prohibited from changing the first cache.

[0361] In some embodiments, the contents of the first cache can be accessed via a cache coherency protocol.

[0362] In Figure 21 In some embodiments, the method 2300 includes the operations at blocks 2202, 2204, 2206, 2207, 2208, and 2210 of the method 2200.

[0363] The method 2300 includes, at block 2302, asserting, by a first physical-to-logical-set-map (PLSM) register (e.g., shown in FIG. 2B), a first set of bits to indicate that the first cache set is to be used for the speculative thread and the second cache set is to be used for the main thread. The first set of bits can be asserted in response to determining that the execution of the first instruction is to be performed with the speculative thread. Figure 21The first valid bit can indicate validity of cached data for the block in the first plurality of blocks. Further, the method 2300 includes receiving, by a second PLSM register (e.g., PLSM register 2108b), a second valid bit for a block in a second plurality of blocks at block 2304. The second valid bit can indicate validity of cached data for the block in the second plurality of blocks.

[0364] At block 2306, the method 2300 includes determining, by a first logic unit (e.g., logic unit 2104a) for the first cache set, whether the block in the first plurality of blocks is a hit or a miss. At block 2307, the method 2300 continues with outputting, by the first logic unit, a first hit or miss result in accordance with the determination. Further, at block 2308, the method 2300 includes determining, by a second logic unit (e.g., logic unit 2104b) for the second cache set, whether the block in the second plurality of blocks is a hit or a miss. At block 2309, the method 2300 continues with outputting, by the second logic unit, a second hit or miss result in accordance with the determination. ​ At block 2310, the method 2300 continues with outputting, by a first multiplexer (e.g., multiplexer 2110a) in accordance with the first valid bit received by the first PLSM register, the first hit or miss result or the second hit or miss result to the processor. In some embodiments, the first multiplexer outputs the first hit or miss result when the first valid bit received by the first PLSM register indicates valid, and the first multiplexer outputs the second hit or miss result when the first valid bit received by the first PLSM register indicates invalid.

[0365] ​ At block 2312, the second hit or miss result or the first hit or miss result is outputted, by a second multiplexer (e.g., multiplexer 2110b) in accordance with the second valid bit received by the second PLSM register, to the processor. In some embodiments, the second multiplexer outputs the second hit or miss result when the second valid bit received by the second PLSM register indicates valid. Also, the second multiplexer outputs the first hit or miss result when the second valid bit received by the second PLSM register indicates invalid.

[0366] At block 2312, the second hit or miss result or the first hit or miss result is outputted, by a second multiplexer (e.g., multiplexer 2110b) in accordance with the second valid bit received by the second PLSM register, to the processor. In some embodiments, the second multiplexer outputs the second hit or miss result when the second valid bit received by the second PLSM register indicates valid. Also, the second multiplexer outputs the first hit or miss result when the second valid bit received by the second PLSM register indicates invalid.

[0367] ​Some embodiments can include a central processing unit having processing circuitry configured to execute a main thread and a speculative thread. The central processing unit can also include or be connected to a first cache set of a cache system configured to be coupled between a main memory and the processing circuitry, the first cache set having a first plurality of blocks for the main thread. Each block of the first plurality of blocks can include cached data, a first valid bit, and a block address including an index and a tag. The processing circuitry, alone or in conjunction with a cache controller, can be configured to change each first valid bit from indicating valid to indicating invalid when a speculation of the speculative thread succeeds, such that the first plurality of blocks become accessible for the speculative thread and blocked for the main thread. The central processing unit can also include or be connected to a second cache set of the cache system configured to be coupled between the main memory and the processing circuitry, the second cache set including a second plurality of blocks for the speculative thread. Each block of the second plurality of blocks can include cached data, a second valid bit, and a block address having an index and a tag. The processing circuitry, alone or in conjunction with the cache controller, can be configured to change each second valid bit from indicating invalid to indicating valid when the speculation of the speculative thread succeeds, such that the second plurality of blocks become accessible for the main thread and blocked for the speculative thread. Also, a block of the first plurality of blocks corresponds to a respective block of the second plurality of blocks by having the same block address as the respective block of the second plurality of blocks.

[0368] The technology disclosed herein can be applied at least to computer systems where the processor is separate from the memory and the processor communicates with the memory and storage devices via a communication bus and / or computer network. Additionally, the technology disclosed herein can be applied to computer systems where processing capability is integrated within the memory / storage devices. For example, processing circuitry including execution units and / or registers of a typical processor can be implemented within an integrated circuit and / or integrated circuit package of a memory medium to perform processing within the memory device. Thus, the processors as discussed above and illustrated in the figures (e.g., see processors 201, 401, 601, and 1001) are not necessarily central processing units in a von Neumann architecture. The processors can be units integrated within the memory to overcome the von Neumann bottleneck that limits computing performance due to the latency in moving data between a central processing unit separately configured from the memory according to a von Neumann architecture.

[0369] The description of the present disclosure and the accompanying drawings are illustrative and are not to be understood as restrictive. Numerous specific details are described to provide a thorough understanding. However, in certain instances, well-known or conventional details are not described in order to avoid obscuring the description. References to one or an embodiment in the present disclosure are not necessarily references to the same embodiment; and, such references mean at least one.

[0370] In the foregoing specification, the disclosure has been described with reference to specific exemplary embodiments thereof. It will, of course, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The Specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A cache system comprising: a first cache; a second cache; a connection to a command bus, the command bus coupled between the cache system and a processor; a connection to an address bus, the address bus coupled between the cache system and the processor; a connection to a data bus, the data bus coupled between the cache system and the processor; a connection to an execution type signal line from the processor, the execution type signal line identifying an execution type; a configurable data bit; a logic circuit coupled to the processor to control the first cache and the second cache based on the configurable data bit; wherein the cache system is configured to be coupled between the processor and a memory system; wherein when the configurable data bit is in a first state, the logic circuit is configured to: implement commands received from the command bus for accessing the memory system via the first cache when the execution type is a first type, wherein the first type is configured to indicate non-speculative execution of instructions by the processor; and implement commands received from the command bus for accessing the memory system via the second cache when the execution type is a second type, wherein the second type is configured to indicate speculative execution of instructions by the processor; and wherein when the configurable data bit is in a second state, the logic circuit is configured to: implement commands received from the command bus for accessing the memory system via the second cache when the execution type is the first type; and implement commands received from the command bus for accessing the memory system via the first cache when the execution type is the second type.

2. The cache system of claim 1, further comprising: a connection to a speculation status signal line from the processor, the speculation status signal line identifying a status of speculative execution of instructions by the processor; wherein the connection to the speculation status signal line is configured to receive the status of speculative execution, and wherein the status of speculative execution indicates whether results of speculative execution are to be accepted or rejected.

3. The cache system of claim 2, wherein when the execution type changes from the second type to the first type, the logic circuit is configured to: toggle the configurable data bit if the status of speculative execution indicates results of speculative execution are to be accepted; and maintain the configurable data bit without change if the status of speculative execution indicates results of speculative execution are to be rejected.

4. The cache system of claim 1, wherein when the execution type changes from the second type to the first type, the logic circuit is configured to toggle the configurable data bit.

5. The cache system of claim 1, further comprising: a connection to a second command bus, the second command bus coupled between the cache system and the memory system; ​ ​ a connection to a second address bus, the second address bus coupled between the cache system and the memory system; a connection to a second data bus, the second data bus coupled between the cache system and the memory system; wherein when the configurable data bit is in a first state, the logic circuit is configured to: provide commands for accessing the memory system via the first cache to the second command bus when the type of execution is a first type; and provide commands for accessing the memory system via the second cache to the second command bus when the type of execution is a second type; and wherein when the configurable data bit is in a second state, the logic circuit is configured to: provide commands for accessing the memory system via the second cache to the second command bus when the type of execution is the first type; and provide commands for accessing the memory system via the first cache to the second command bus when the type of execution is the second type.

6. The cache system of claim 1, wherein the connection to the command bus is configured to receive a read command or a write command from the processor for accessing the memory system; wherein the connection to the address bus is configured to receive a memory address from the processor for accessing the memory system for the read command or the write command; wherein the connection to the data bus is configured to: communicate data to the processor for the processor to read the data for the read command; receive data from the processor for writing in the memory system for the write command; and wherein memory access requests from the processor and memory usage by the processor are controlled through the command bus, the address bus, and the data bus.

7. The cache system of claim 1, wherein the connection to the type of execution signal line is configured to receive an identification of the type of execution from the processor.

8. The cache system of claim 1, wherein the logic circuit is configured to: select the first cache for memory access requests from the processor when the configurable data bit is in the first state and the connection to the type of execution signal line receives an indication of the first type; select the second cache for memory access requests from the processor when the configurable data bit is in the first state and the connection to the type of execution signal line receives an indication of the second type; select the second cache for memory access requests from the processor when the configurable data bit is in the second state and the connection to the type of execution signal line receives an indication of the first type; and ​ ​ selecting the first cache for memory access requests from the processor when the configurable data bit is in the second state and the connection to the execution type signal line receives an indication of the second type.

9. A cache system comprising: a first cache; a second cache; a connection to a command bus configured to receive a read command or a write command from a processor connected to the cache system for reading from or writing to a memory system; a connection to an address bus configured to receive a memory address from the processor for accessing the memory system for the read command or the write command; a connection to a data bus configured to: communicate data to the processor for the processor to read the data for the read command; and receive data from the processor to write in the memory system for the write command; an execution type signal line configured to receive an identification of an execution type from the processor, wherein the execution type is a first type of execution or a second type of execution, wherein the first type of execution is a speculative execution of an instruction by the processor, and wherein the second type of execution is a non-speculative execution of an instruction by the processor; a configurable data bit; and a logic circuit configured to: select the first cache for use by the processor when the configurable data bit is in a first state and the execution type signal line receives an indication of the first type of execution; select the second cache for use by the processor when the configurable data bit is in the first state and the execution type signal line receives an indication of the second type of execution; select the second cache for use by the processor when the configurable data bit is in a second state and the execution type signal line receives an indication of the first type of execution; and select the first cache for use by the processor when the configurable data bit is in the second state and the execution type signal line receives an indication of the second type of execution.

10. The cache system of claim 9, further comprising a connection to a speculation state signal line configured to receive a speculation state from the processor, wherein the speculation state is an acceptance or a rejection of a condition with a nested instruction, the nested instruction initially executed by a speculative execution of the processor and subsequently executed by a normal execution of the processor when the speculation state is the acceptance of the condition.

11. The cache system of claim 10, wherein the logic circuit is configured to toggle the configurable data bit from the first state to the second state when the speculation state received by the speculation state signal line is the acceptance of the condition.

12. The cache system of claim 10, wherein the logic circuit is configured to maintain the state of the configurable data bit when the speculation state received by the speculation state signal line is the rejection of the condition. ​ ​ ​ 13. The cache system of claim 9, further comprising: a connection to a second command bus configured to communicate read or write commands to the memory system, wherein the read or write commands are received by the cache system from the processor; a connection to a second address bus configured to communicate memory addresses to the memory system, wherein the memory addresses are received by the cache system from the processor; and a connection to a second data bus configured to: communicate data to the memory system for writing in the memory system; and receive data from the memory system for communication to the processor for reading by the processor.

14. The cache system of claim 13, wherein when the configurable data bit is in a first state, the logic circuit is configured to: and when the execution type is a first type, providing commands for accessing the memory system via the first cache to the second command bus; when the type of execution is a second type, provide commands for accessing the memory system via the second cache to the second command bus; and wherein when the configurable data bit is in a second state, the logic circuit is configured to: when the type of execution is the first type, provide commands for accessing the memory system via the second cache to the second command bus; and when the type of execution is the second type, provide commands for accessing the memory system via the first cache to the second command bus.

15. A computing system comprising: a processor; a memory system; and a cache system coupled between the processor and the memory system, the cache system comprising: a first cache; a second cache; a connection to a command bus, the command bus coupled between the cache system and the processor; a connection to an address bus, the address bus coupled between the cache system and the processor; a connection to a data bus, the data bus coupled between the cache system and the processor; a connection from a type of execution signal line from the processor, the type of execution signal line identifying a type of execution; a configurable data bit; a logic circuit coupled to the processor to control the first cache and the second cache based on the configurable data bit; wherein when the configurable data bit is in a first state, the logic circuit is configured to: when the type of execution is a first type, implement commands received from the command bus for accessing the memory system via the first cache, wherein the first type is configured to indicate speculative execution of instructions by the processor; and when the type of execution is a second type, implement commands received from the command bus for accessing the memory system via the second cache, wherein the second type is configured to indicate non-speculative execution of instructions by the processor; and wherein when the configurable data bit is in a second state, the logic circuit is configured to: ​ implementing commands received from the command bus for accessing the memory system via the second cache when the type of execution is the first type; and implementing commands received from the command bus for accessing the memory system via the first cache when the type of execution is the second type.

16. The computing system of claim 15, further comprising: a connection to a speculation status signal line from the processor, the speculation status signal line identifying a status of speculative execution of instructions by the processor; wherein the connection to the speculation status signal line is configured to receive the status of speculative execution, and wherein the status of speculative execution indicates whether results of speculative execution are to be accepted or rejected.

17. The computing system of claim 16, wherein when the type of execution changes from the first type to the second type, the logic circuit is configured to: if the status of speculative execution indicates that results of speculative execution are to be accepted, then toggle the configurable data bit; and if the status of speculative execution indicates that results of speculative execution are to be rejected, then maintain the configurable data bit without change.

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