Block and omission fidelity estimation

Abstract

Methods, systems, and apparatuses for estimating quantum processor performance. In one aspect, a method includes defining a benchmarking circuit configured to operate on a qubit array, where the benchmarking circuit includes one or more cycles of quantum gates, each cycle including a respective layer of randomly sampled single-qubit gates and a layer of multiple instances of the same multi-qubit gate; dividing the defined benchmarking circuit into two or more sub-circuits, including defining one or more boundaries between qubits in the qubit array, removing instances of the multi-qubit gate that cross the defined one or more boundaries to create the two or more sub-circuits; performing a benchmarking process using the divided benchmarking circuit to estimate a respective circuit fidelity of each of the sub-circuits; and multiplying the estimated circuit fidelities of each of the sub-circuits to obtain an estimate of a quantum processor fidelity.

Description

Background Technology

[0001] This manual relates to quantum computing.

[0002] Quantum computing uses quantum mechanical phenomena, such as superposition and entanglement, to perform computations. A quantum circuit is an example model used in quantum computing, where computation is a series of quantum logic gates that are reversible transformations of a quantum mechanical simulation of an n-bit register. Summary of the Invention

[0003] This manual describes techniques for estimating the fidelity of quantum computers.

[0004] Generally, an innovative aspect of the subject matter described in this specification can be implemented as a method for estimating the performance of a quantum processor, the method comprising: defining a benchmarking quantum circuit configured to operate on a qubit array, wherein the benchmarking quantum circuit includes one or more quantum gate cycles, each quantum gate cycle including a corresponding layer of randomly sampled single-qubit gates and a layer of multiple instances of the same multi-qubit gates; dividing the defined benchmarking quantum circuit into two or more sub-circuits, including: defining one or more boundaries between qubits in the qubit array; removing instances of multi-qubit gates that cross the one or more defined boundaries to create two or more sub-circuits, each sub-circuit being a circuit that does not cross any of the one or more defined boundaries; performing a benchmarking process using the divided benchmarking quantum circuit to estimate the corresponding circuit fidelity of each of the two or more sub-circuits; and multiplying the estimated circuit fidelities of each of the two or more sub-circuits to obtain an estimate of the fidelity of the defined benchmarking quantum circuit.

[0005] Other implementations of this aspect include corresponding classical and quantum computer systems and apparatuses, and computer programs recorded on one or more computer storage devices, each configured to perform actions of the method. A system of one or more computers can be configured to perform specific operations or actions by installing software, firmware, hardware, or combinations thereof on the system, which, in operation, cause the system to perform actions. One or more computer programs can be configured to perform specific operations or actions by including instructions that, when executed by a data processing apparatus, cause the apparatus to perform actions.

[0006] Each of the foregoing and other implementations may optionally include one or more of the following features, individually or in combination. In some implementations, defining a benchmark quantum circuit includes: randomly sampling a plurality of single-qubit quantum gates from a predetermined set of single-qubit quantum gates, wherein each randomly sampled single-qubit quantum gate corresponds to a corresponding qubit in a qubit array and corresponds to a corresponding period of one or more periods; assigning the randomly sampled plurality of single-qubit quantum gates to corresponding layers of the randomly sampled single-qubit gates in the defined benchmark quantum circuit; and assigning instances of multi-qubit gates to layers of multiple instances of the same multi-qubit gate.

[0007] In some implementations, each layer of multiple instances of a multi-qubit quantum gate includes multiple copies of a two-qubit gate, wherein each copy of the two-qubit gate operates on the corresponding nearest-neighbor pair of qubits in the qubit array.

[0008] In some implementations, multiple copies of a two-qubit gate operate on all adjacent qubit pairs in the qubit array.

[0009] In some implementations, two or more sub-circuits include disjoint sub-circuits that operate on disjoint subsets of qubits in the qubit array, respectively.

[0010] In some implementations, using partitioned benchmark quantum circuits to perform a benchmarking process to determine the corresponding circuit fidelity of each of two or more sub-circuits includes: implementing the partitioned benchmark quantum circuits using quantum computing hardware to obtain experimental benchmark data; classically simulating an idealized implementation of the partitioned benchmark quantum circuits, including performing separate simulations of the idealized implementation of each of the two or more sub-circuits to obtain corresponding sets of classical benchmark data, each set representing the output distribution of the idealized implementation of the corresponding sub-circuit; and for each sub-circuit, comparing the classical benchmark data of the sub-circuit with a corresponding portion of the obtained experimental data to determine the estimated fidelity of the sub-circuit.

[0011] In some implementations, using quantum computing hardware to implement partitioned benchmark quantum circuits to obtain experimental benchmark data includes: initializing each qubit in the qubit array to an initial state; applying the partitioned benchmark quantum circuits to the initialized qubits; and measuring each qubit in the qubit array to obtain measurement data for each qubit.

[0012] In some implementations, the method further includes applying a Hadamard gate to each qubit after initializing each qubit in the qubit array to an initial state and before applying the partitioned benchmark quantum circuit.

[0013] In some implementations, applying the partitioned benchmark quantum circuitry to the initialized qubits involves performing a single experiment in which each of two or more of the sub-circuits is implemented approximately simultaneously.

[0014] In some implementations, the method further includes defining a plurality of benchmark quantum circuits configured to operate on the qubit array, wherein the defined plurality of benchmark quantum circuits include quantum circuits having different circuit depths from a predetermined range of circuit depths; and estimating the fidelity of each defined benchmark quantum circuit.

[0015] In some implementations, the method further includes determining one or more adjustments to the quantum hardware control parameters based on the obtained estimate of the fidelity of the defined benchmark quantum circuit; and implementing the determined one or more adjustments to perform quantum computing using the quantum computing hardware.

[0016] Generally, another innovative aspect of the subject matter described in this specification can be implemented as a method for estimating the performance of a quantum processor, the method comprising: defining a benchmark quantum circuit configured to operate on a qubit array, wherein the benchmark quantum circuit includes one or more quantum gate cycles, each quantum gate cycle including a corresponding layer of randomly sampled single-qubit gates and a layer of multiple instances of the same multi-qubit gates; modifying the defined benchmark quantum circuit, including: defining one or more boundaries between qubits in the qubit array, removing an appropriate subset of instances of multi-qubit gates that cross the one or more defined boundaries; and performing a benchmarking process using the modified benchmark quantum circuit to estimate the fidelity of the defined benchmark quantum circuit.

[0017] Other implementations of this aspect include corresponding classical and quantum computer systems and apparatuses, and computer programs recorded on one or more computer storage devices, each configured to perform actions of these methods. A system of one or more computers can be configured to perform specific operations or actions by installing software, firmware, hardware, or combinations thereof on the system, which, in operation, cause the system to perform actions. One or more computer programs can be configured to perform specific operations or actions by including instructions that, when executed by a data processing apparatus, cause the apparatus to perform actions.

[0018] Each of the foregoing and other implementations may optionally include one or more of the following features, either individually or in combination. In some implementations, removing an appropriate subset of instances of multi-qubit gates that cross one or more defined boundaries includes removing an appropriate subset of instances of multi-qubit quantum gates that cross one or more boundaries in a predetermined number of quantum gate cycles.

[0019] In some implementations, defining a benchmark quantum circuit includes: randomly sampling a plurality of single-qubit quantum gates from a predetermined set of single-qubit quantum gates, wherein each randomly sampled single-qubit quantum gate corresponds to a corresponding qubit in a qubit array and corresponds to a corresponding period of one or more periods; assigning the randomly sampled plurality of single-qubit quantum gates to corresponding layers of the randomly sampled single-qubit gates in the defined benchmark quantum circuit; and assigning instances of multi-qubit gates to layers of multiple instances of the same multi-qubit gate.

[0020] In some implementations, each layer of multiple instances of a multi-qubit quantum gate includes multiple copies of a two-qubit gate, wherein each copy of the two-qubit gate performs pairwise operations on the corresponding nearest-neighbor qubit in the qubit array.

[0021] In some implementations, multiple copies of a two-qubit gate operate on all adjacent qubit pairs in the qubit array.

[0022] In some implementations, using a modified benchmark quantum circuit to perform a benchmarking process to estimate the fidelity of the defined benchmark quantum circuit includes: implementing the modified benchmark quantum circuit using quantum computing hardware to obtain experimental benchmark data; and classically simulating an idealized implementation of the modified benchmark quantum circuit, including performing... – The Feynman algorithm is used to obtain classical benchmark data; the classical benchmark data is compared with experimental data to determine the fidelity of the estimated benchmark quantum circuit.

[0023] In some implementations, using quantum computing hardware to implement a modified benchmark quantum circuit to obtain experimental benchmark data includes: initializing each qubit in the qubit array to an initial state; applying the modified benchmark quantum circuit to the initialized qubits; and measuring each qubit in the qubit array to obtain measurement data for each qubit.

[0024] In some implementations, the method further includes applying a Hadamard gate to each qubit after initializing each qubit in the qubit array to an initial state and before applying a modified benchmark quantum circuit.

[0025] In some implementations, the method further includes defining a plurality of benchmark quantum circuits configured to operate on the qubit array, wherein the defined plurality of benchmark quantum circuits include quantum circuits having different circuit depths from a predetermined range of circuit depths; and estimating the fidelity of each defined benchmark quantum circuit.

[0026] In some implementations, the method further includes determining one or more adjustments to the quantum hardware control parameters based on the obtained estimate of the fidelity of the defined benchmark quantum circuit; and implementing the determined one or more adjustments to perform quantum computing using the quantum computing hardware.

[0027] The subjects described in this specification can be implemented in a particular manner to achieve one or more of the following advantages.

[0028] Systems implementing the techniques described herein can determine accurate estimates of system fidelity at a manageable classical computational cost. Specifically, the techniques described herein offer an exponential reduction in computational cost. Therefore, systems implementing the techniques described herein can rapidly obtain daily-based estimates of the performance of large-scale systems, including those too large to be simulated using classical algorithms.

[0029] Furthermore, compared to conventional techniques, the currently described technique determines a more accurate estimate of the performance of large-scale systems because it uses circuit instances similar to other instances that cannot be simulated to estimate fidelity. The currently described technique is also scalable and can be extended to any number of qubits while maintaining the analysis time as linear (or in some cases constant) as possible with the number of qubits.

[0030] The techniques described can be applied to improve quantum computing hardware and quantum control—key features of high-fidelity quantum computing. For example, adjustments to the control model that can improve the accuracy of quantum operations performed by the quantum computing hardware can be determined based on the fidelity of estimates of the quantum states generated by the quantum computing hardware.

[0031] Details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the following description. Further features, aspects, and advantages of this subject matter will become clearer from the specification and drawings. Attached Figure Description

[0032] Figure 1 An example system for benchmarking the performance of quantum computing hardware is described.

[0033] Figure 2This is a flowchart of a first example process for estimating the performance of a quantum processor.

[0034] Figure 3 This is a flowchart of a second example process for estimating the performance of a quantum processor.

[0035] Figure 4 An example illustration of a quantum circuit for benchmark testing is shown. Detailed Implementation

[0036] Overview

[0037] Quantum circuits are models used in quantum computing, where quantum logic gates are applied in a specific sequence to the registers of qubits to encode quantum information. Theoretically, any quantum algorithm can be implemented with high precision by applying the correctly chosen sequence of quantum logic gates. However, in practice, quantum logic gates are prone to error—instead of implementing the unitary quantum operations that represent ideal quantum logic gates, they implement the corresponding noisy quantum operations.

[0038] The fidelity of quantum operations is between noisy quantum operations ε and ideal unitary quantum operations. A measure of how close ε is to ρ. For a given quantum state ρ, ε is similar to ρ. The quantum logic gate fidelity between them can be given by the following formula:

[0039]

[0040] Estimating the fidelity of quantum logic gates is an important process for tuning or correcting the quantum hardware that physically implements quantum logic gates, and consequently, for performing successful quantum computing.

[0041] Traditional benchmarking techniques (such as cross-entropy benchmarking (XEB) or statistical methods) can be used to characterize how far a quantum state generated by a quantum machine deviates from the desired state of an ideal quantum operation, thus characterizing the amount of error. Benchmarking techniques typically involve executing a random quantum circuit on a quantum processor to determine the probability of the bit string representing the measurement result, simulating the execution of the random quantum circuit using classical algorithms to obtain the corresponding ideal probability of the bit string representing the measurement result, and estimating fidelity using probabilities based on equations from different methods.

[0042] The cost of implementing classical algorithms to simulate the execution of random quantum circuits grows exponentially, becoming extremely expensive with increasing the number of qubits or circuit depth. Traditional benchmarking techniques overcome this problem by estimating the system fidelity of quantum circuits with increasing numbers of qubits, provided classical simulation is affordable. System fidelity can also be estimated for circuits with the same number of qubits and increased depth. The obtained fidelity can then be extrapolated to the number of qubits and circuit depth in ways that are impossible to simulate at an affordable cost.

[0043] Therefore, traditional benchmarking techniques rely on extrapolation and cannot always provide accurate estimates of fidelity. Furthermore, as the complexity of quantum computing grows exponentially, experiments are venturing into previously unexplored realms of complexity. In physics and engineering, when exploring new areas for the first time—such as those with increasing complexity, number of qubits, and circuit depth—the ability to rely on the most accurate possible metrics (e.g., fidelity) is crucial.

[0044] This manual describes techniques for simplifying the estimation of the fidelity of a complete experiment using classical simulations. These techniques can provide accurate estimates of system fidelity at a manageable classical computational cost.

[0045] One technique—referred to in this paper as “patchXEB”—involves spatially dividing a quantum circuit into two isolated blocks by removing slices of two-qubit gates. The remaining blocks can be easily simulated. For example, for a 50-qubit circuit, we can remove slices of two-qubit gates approximately along the middle. The remaining two isolated blocks are circuits with 25 qubits each, which are easy to simulate.

[0046] Another technique—referred to in this paper as “elided XEB”—builds upon block XEB and reintroduces some of the removed two-qubit gates to more closely simulate the entire experiment while still maintaining simulation feasibility. The resulting circuit can be used with existing algorithms (e.g., -Feynman algorithm (also known as The Feynman hybrid algorithm is used for simulation. The cost of these algorithms is exponentially related to the number of two-qubit gates that span the lines of the circuit in which the two-qubit gates have been removed.

[0047] Example hardware

[0048] Figure 1An example system for benchmarking the performance of quantum computing hardware is depicted. This example system 100 is an example of a system implemented as a classical and quantum computer program on one or more classical and quantum computers at one or more locations, wherein the systems, components, and techniques described below can be implemented.

[0049] System 100 includes a classical processor 102 that communicates data with quantum computing hardware 104. For convenience, the classical processor 102 and the quantum computing hardware 104 are shown as separate entities; however, in some implementations, the classical processor 102 may be included in the quantum computing hardware 104. For example, the quantum computing hardware 104 may include one or more components for performing classical computation operations.

[0050] Quantum computing hardware 104 includes components for performing quantum computing using quantum circuits. For example, quantum computing hardware 104 includes a quantum system 120 and a control device 122. Quantum system 120 includes one or more multi-level quantum subsystems, such as qubits, for performing algorithmic operations or quantum computing. The specific implementation of the multi-level quantum subsystems included in quantum computing hardware 104 and how these multi-level quantum subsystems interact with each other depends on several factors, including the type of quantum computing the quantum computing hardware is performing. For example, the multi-level quantum subsystems may include qubits implemented via atomic, molecular, or solid-state quantum systems. In other examples, qubits may include, but are not limited to, superconducting qubits or semiconductor qubits.

[0051] Multilevel quantum systems can be frequency-tunable. For example, each qubit can have an associated operating frequency, which can be adjusted, for instance, by applying voltage pulses via one or more drivelines coupled to the qubit, or by using one or more control devices 122. Example operating frequencies include qubit idling frequencies, qubit interaction frequencies, and qubit readout frequencies. Different frequencies correspond to different operations that the qubit can perform. For example, setting the operating frequency to the corresponding idling frequency can place the qubit in a state in which it does not interact strongly with other qubits, and in which state the qubit can be used to perform single-qubit gates. As another example, where qubits interact with each other via couplers at a fixed coupling, the qubits can be configured to interact with each other by setting their respective operating frequencies to some gate-dependent frequencies detuned from their common interaction frequency. In other cases, such as when qubits interact via tunable couplers, the qubits can be configured to enable interaction between qubits by setting the parameters of their respective couplers, and then interact with each other by setting the respective operating frequencies of the qubits to some gate-dependent frequencies detuned from their common interaction frequency. Such interactions can be performed in order to execute a many-qubit gate.

[0052] The control device 122 may also include a measurement device, such as a readout resonator. The measurement results (measurement data) obtained via the measurement device may be provided to a classical processor included in the quantum computing hardware 104 or to a classical processor 102 for processing and analysis.

[0053] The classical processor 102 receives input data 106 representing the quantum hardware to be benchmarked. For example, the input data 106 may include data representing the quantum logic gates or quantum circuits that the quantum computing hardware 104 is configured to implement.

[0054] The classical processor 102 processes the received input data 106 to generate output data 108 representing benchmark results (e.g., properties of the implementation of quantum logic gates or quantum circuits). For example, the output data 108 may include data representing the fidelity of an estimate of the quantum states output during the implementation of quantum logic gates or quantum circuits in the quantum computing hardware 104.

[0055] The classical processor 102 includes multiple components for processing received input data. For example, the classical processor 102 may include a random quantum circuit generator 110, a classical simulator 112, and a data processing module 114.

[0056] The random quantum circuit generator 110 can be configured to define random quantum circuits based on the quantum computing hardware 104 and the received input data 106. A random quantum circuit is a quantum circuit that includes one or more quantum gates randomly sampled from a predetermined set of quantum gates. The type of random quantum circuit defined by the random quantum circuit generator 110 depends on the benchmark experiment being performed by the system 100.

[0057] For example, the random quantum circuit generator 110 can define multiple random quantum circuits, wherein each random quantum circuit includes one or more corresponding randomly sampled single-qubit gates. For example, the random quantum circuit generator 110 can be configured to generate a set of single-qubit gates from a predefined set (e.g., including...). A single qubit gate is randomly sampled from a set of T quantum gates, where This represents a rotation of π / 2 around the X-axis. Let T denote a rotation of π / 2 around the y-axis, and let T denote a non-Clifford diagonal matrix {0, e}. iπ / 4 In a single-qubit benchmark experiment, the single-qubit gates included in the random quantum circuit defined by the random quantum circuit generator 110 can have approximately equal error rates. For example, the error rate of each single-qubit gate in the set of single-qubit gates sampled by the random quantum circuit generator 110 has an error rate within a predetermined range.

[0058] The random quantum circuit generator 110 can also define multiple random quantum circuits, each of which includes one or more corresponding randomly sampled single-qubit gates and the same multi-qubit quantum gates. Similarly, in multi-qubit benchmark experiments, the single-qubit gates included in the random quantum circuits defined by the random quantum circuit generator 110 can have approximately equal error rates.

[0059] The random quantum circuits defined by the random quantum circuit generator 110 can have different depths. The random quantum circuit generator 110 can define circuits of different depths by applying multiple gate clock cycles. That is, the random quantum circuit generator 110 can define a random quantum circuit of depth d as the same sequence of gates equal to d cycles. In some implementations, the random quantum circuit generator 110 can define gate sequences, for example, including multiple randomly sampled single-qubit gates and subsequent multiple multi-qubit gates, and use the defined gate sequences to define multiple random quantum circuits, where each defined random quantum circuit corresponds to a defined gate sequence of a corresponding number of cycles. For example, the random quantum circuit generator can define 500 random quantum circuits corresponding to gate sequences of 1-500 cycles.

[0060] Quantum circuit 130 is an example of a random quantum circuit generated by random quantum circuit generator 110. Example quantum circuit 130 illustrates a benchmark quantum circuit configured to operate on two qubits q1, q2. Example quantum circuit 130 comprises four cycles, each cycle including two randomly sampled single-qubit gates R1, R2 that operate on qubits q1, q2 respectively, and a copy of a two-qubit quantum gate, for example, a CZ gate in this example.

[0061] The classical processor 102 is configured to partition or modify the random quantum circuits defined by the random quantum circuit generator 110. For example, the classical processor 102 can be configured to execute the following reference. Figure 2 and Figure 3 The operations described in example procedures 200 and 300.

[0062] The classical processor 102 is configured to transmit data 116 representing partitioned or modified random quantum circuits to the quantum computing hardware 104. The quantum computing hardware 104 is configured to implement partitioned or modified random quantum circuits using a quantum system 120 and a control device 122.

[0063] The quantum computing hardware 104 can provide output data representing the results of the circuit implementation, such as experimental benchmark data 124, and send this data to the classical processor 102.

[0064] The classical processor 102 is also configured to provide data 116 representing a partitioned or modified benchmark quantum circuit to the circuit simulator 112. The circuit simulator 112 is configured to perform classical calculations to simulate the implementation of the benchmark quantum circuit defined by the data 116, for example, to calculate the output probability of an ideal implementation of the constructed benchmark circuit. See below for further details. Figure 2 and Figure 3 The circuit simulator 112 can be configured to perform individual simulations to implement sub-circuits in a partitioned benchmark quantum circuit, and can be configured to perform... – The Feynman algorithm or hybrid quantum simulation algorithm is used to simulate the implementation of modified benchmark quantum circuits.

[0065] The circuit simulator 112 can provide output data representing the results of circuit simulation, such as classical benchmark data 126, to the data processing module 114 included in the classical processor 102.

[0066] The data processing module 114 is configured to process experimental benchmark data 124 received from quantum computing hardware 104 and classical benchmark data 126 received from circuit simulator 112.

[0067] Processing experimental and classical benchmark data can include applying a cross-entropy benchmarking technique, in which cross-entropy is used as a measure of the correspondence between experimental benchmark data and classical benchmark data representing the output distribution of an ideal circuit. For example, data processing module 114 can be configured to determine the cross-entropy (or average cross-entropy) of experimental benchmark data 124 (or a corresponding portion thereof) and the cross-entropy (or average cross-entropy) of classical benchmark data 126. The (average) cross-entropy difference can be used as an estimate of the fidelity of the simulated circuit—this property applies to both incoherent and coherent errors, the difference being that fluctuations around the mean are greater in the case of coherent errors than in the case of incoherent errors.

[0068] See below for reference. Figure 2 and Figure 3 In more detail, the data processing module can be configured to determine the cross-entropy (or average cross-entropy) of the relevant portions of experimental benchmark data 124 and classical benchmark data 126 corresponding to the classical simulation of the implementation of the sub-circuit of the partitioned benchmark quantum circuit. The average cross-entropy difference can be used as an estimate of the sub-circuit fidelity. The data processing module 114 can multiply the determined estimates of the sub-circuit fidelity to obtain an estimate of the corresponding benchmark quantum circuit defined by the random quantum circuit generator 110.

[0069] By estimating the circuit fidelity as a function of circuit depth, the data processing module 114 can further determine a measure of the error per cycle by fitting the fidelity as a function of circuit depth to an exponential form.

[0070] In some implementations, the data processing module 114 can be configured to process or analyze the estimated fidelity value to determine properties of the quantum computing hardware 104 (e.g., its performance) or to calibrate, verify, or benchmark the quantum computing hardware 104. Furthermore, the data processing module 114 can also generate output data representing one or more adjustments that can be used to tweak and improve the quantum computing hardware 104. For example, the data processing module 114 can use the estimated fidelity value to determine how to control the tweaks to the quantum computing hardware when implementing a particular quantum circuit or a particular type of quantum circuit, for example, determining modifications to the programming of the control device 122 to achieve a higher fidelity quantum gate. A parameterized control model can be used to determine the modifications, where the parameterized control model correlates the parameters of the quantum gate (e.g., phase, qubit rotation angle, etc.) with the physical parameters of the system used to implement / control the quantum gate (e.g., voltage, pulse shape, frequency, etc.). An outer loop can then be executed to find the optimal experimental control to improve the performance of the quantum computing hardware 104. For example, this method can be iterated until a certain threshold condition is met. Threshold conditions can, for example, optimize the control model to within a threshold and / or a number of threshold iterations.

[0071] Programming the hardware

[0072] Figure 2 This is a flowchart of a first example process 200 for estimating the performance of a quantum processor. For convenience, process 200 will be described as being executed by a system of one or more classical and quantum computing devices located at one or more locations. For example, a system appropriately programmed according to this specification... Figure 1 System 100 can execute process 200.

[0073] The system defines a benchmark quantum circuit configured to operate on an array of n qubits (step 202). As described above, the qubit array can include a large number of qubits, such as 50 or more. The defined benchmark quantum circuit includes one or more quantum gate cycles, wherein each cycle includes a corresponding layer of randomly sampled single-qubit gates and layers of multiple instances of the same multi-qubit gates.

[0074] To define a benchmark quantum circuit, the system randomly samples multiple single-qubit quantum gates from a predetermined set of single-qubit quantum gates. For example, the system can sample gates from a set including... A single-qubit quantum gate is randomly sampled from the set of T quantum gates. Each randomly sampled single-qubit quantum gate corresponds to a corresponding period and a corresponding qubit in the qubit array. For example, in some implementations, the corresponding randomly sampled single-qubit quantum gate is assigned to each qubit in the qubit array in each period; that is, the total number of randomly sampled single-qubit quantum gates can be equal to the number of qubits n in the array multiplied by the number of periods (circuit depth) d.

[0075] The system assigns multiple randomly sampled single-qubit gates to the corresponding layers of the randomly sampled single-qubit gates. In some implementations, the system may implement one or more rules for assigning the randomly sampled single-qubit gates to layers. For example, the system may implement a rule that, according to this rule, any single-qubit gate assigned to qubit q in the array for the current layer should be different from the single-qubit gate assigned to qubit q in the previous layer.

[0076] The system also assigns instances of multi-qubit quantum gates to layers of multiple instances of the same multi-qubit gate. For example, each layer of multiple instances of a multi-qubit quantum gate may include multiple copies of a two-qubit gate, where each copy of the two-qubit gate operates on the corresponding nearest-neighbor qubit pair in the qubit array. In some implementations, multiple copies of the two-qubit gate operate on all adjacent qubit pairs in the qubit array, as follows: Figure 4 shown.

[0077] The system divides the defined benchmark quantum circuit into two or more sub-circuits or "blocks" (step 204). The system divides the defined benchmark quantum circuit into two or more blocks by defining one or more boundaries in the qubit array and removing all instances of the multi-qubit quantum gates along one or more boundaries in each layer of multiple instances of the multi-qubit gates. That is, in each cycle, the same (multiple) boundaries are defined in the qubit array, and all multi-qubit quantum gates located on or across the boundaries are removed. Figure 4 Example boundaries are shown, and the removal of instances of two-qubit quantum gates is illustrated.

[0078] One or more boundaries can be selected based on the computational power of the classical processor implementing the aforementioned classical algorithm to simulate the execution of random quantum circuits. The number of qubits that can be efficiently simulated by a classical processor can be used to determine the block size for dividing the qubit array into blocks. For example, if a classical processor can efficiently simulate the execution of a random quantum circuit operating on 25 qubits, the system can divide a defined benchmark quantum circuit configured to operate on a 50-qubit array into two 25-qubit blocks. As another example, if a classical processor can efficiently simulate the execution of a random quantum circuit operating on 25 qubits, the system can divide a defined benchmark quantum circuit configured to operate on a 100-qubit array into four 25-qubit blocks.

[0079] After the system divides the defined benchmark circuit into two or more blocks, the defined benchmark quantum circuit comprises two or more sub-circuits that operate on corresponding subsets of qubits in the qubit array. Each sub-circuit comprises one or more quantum gate cycles, wherein each cycle comprises a corresponding layer of randomly sampled single-qubit gates operating on a subset of qubits and corresponding layers of multiple instances of multi-qubit gates.

[0080] The system uses a partitioned benchmark quantum circuit to perform a benchmarking process to determine the circuit fidelity of each of two or more sub-circuits (step 206). Performing the benchmarking process includes implementing the partitioned benchmark circuit to obtain experimental benchmark data. Implementing the partitioned benchmark circuit may include starting in an initial state. Each qubit in the qubit array is initialized, a partitioned benchmark circuit is applied to the initialized qubits in the qubit array, and each qubit in the qubit array is measured to obtain measurement data for each qubit. In some implementations, after initializing the qubits in the qubit array to their initial state and before applying the partitioned benchmark circuit, the system may also apply a Hadamard gate to each qubit. The partitioned benchmark circuit can be applied to the qubits initialized in the same experiment; that is, the sub-circuits (corresponding to separate subsystems of the qubits) can be approximately simultaneous in the same experiment (e.g., ...).

[0081] For example, it can operate within the limitations of quantum computing hardware that performs the experimental implementation. This makes it possible to capture the effects of measurement crosstalk, such as between gates and blocks, in the implementation.

[0082] The benchmarking process also includes classically simulating an ideal implementation of the partitioned benchmark circuit. Classically simulating the partitioned benchmark circuit involves simulating individual sub-circuits of the partitioned benchmark circuit. That is, the system performs two or more simulations, each corresponding to a specific sub-circuit. Each classical simulation produces classical benchmark data representing the output distribution of the ideal implementation of the sub-circuit.

[0083] The system can then compare classical benchmark data representing the output distribution of an ideal implementation of each sub-circuit with corresponding portions of experimental benchmark data (e.g., experimental benchmark data obtained from the qubits operating on each sub-circuit) to determine an estimate of the circuit fidelity for each of two or more sub-circuits. For example, the system can apply cross-entropy benchmarking techniques to estimate the fidelity of the sub-circuit implementation.

[0084] The system multiplies the determined circuit fidelity of each of two or more block fidelities to obtain an estimate of the fidelity of the defined benchmark circuit (208).

[0085] The main difference between the fidelity obtained in step 208 and the fidelity obtained using conventional techniques, compared to the complete benchmarking process (e.g., conventional XEB), lies in the absence of entanglement between two or more blocks. However, for sufficiently large systems (such as those with 50 or more qubits), the multi-qubit gates removed in step 204 (and the corresponding lack of entanglement) represent a small fraction of the entire benchmark quantum circuit defined in step 202. Therefore, the fidelity of the complete benchmark circuit can be accurately estimated as the product of the fidelities of the two subsystems.

[0086] In some implementations, example process 200 can be repeated for multiple benchmark quantum circuits of the same circuit depth and multiple benchmark circuits of different depths. For example, the system can repeat example process 200 for multiple circuits of different depths as part of a normal benchmarking process to estimate the fidelity as a function of circuit depth, and determine a measure of the error per cycle by fitting the fidelity as a function of circuit depth to an exponential function.

[0087] In some implementations, the system may use one or more estimated fidelities to determine one or more adjustments to the quantum computing hardware, such as adjustments to the control parameters of the control model used by the quantum computing hardware to implement quantum operations. The system can then implement the determined adjustments when performing future computations to improve the operation and / or performance of the quantum computing hardware.

[0088] Figure 3It is a flowchart of a second example process 300 for estimating the performance of a quantum processor. For convenience, process 300 will be described as being performed by a system of one or more classical and quantum computing devices located at one or more locations. For example, a system 100 suitably programmed in accordance with this specification can perform process 300. Figure 1 The system defines a benchmark quantum circuit configured to operate on an array of n qubits (step 302). The defined benchmark quantum circuit can take the same form as that described in step 202 of

[0089] The system modifies the defined benchmark quantum circuit (step 304). The system modifies the defined benchmark quantum circuit by defining one or more boundaries in the qubit array and removing a suitable subset of instances of multi-qubit quantum gates along one or more boundaries in one or more layers of multiple instances of multi-qubit gates. For example, the system can define one or more boundaries in the qubit array and, in a predetermined number of cycles (e.g., in the first x < d cycles), remove a fraction of the instances of multi-qubit quantum gates along one or more boundaries. Figure 2 An example boundary is shown, and the removal of a fraction of the instances of two-qubit quantum gates is shown.

[0090] The system uses the modified benchmark quantum circuit to perform a benchmarking process to obtain an estimate of the fidelity of the defined benchmark circuit (step 306). Figure 4 Performing the benchmarking process includes implementing the modified benchmark circuit to obtain experimental benchmark data, as described in step 206 of

[0091] Performing the benchmarking process also includes classically simulating the modified benchmark circuit to obtain classical benchmark data. However, unlike steps 206 and 208 of

[0092] the modified benchmark quantum circuit generated in step 304 does not include multiple disjoint blocks by construction. Thus, the modified benchmark quantum circuit cannot be classically simulated separately, and the individual fidelities cannot be multiplied. Instead, to simulate the modified benchmark circuit, the system applies Figure 2 the -Feynman algorithm or a quantum simulation hybrid algorithm to perform the classical simulation.

[0093] A traditional method of simulating a quantum circuit is a full state vector simulator or Figure 2 -Feynman algorithm or a quantum simulation hybrid algorithm to perform the classical simulation.

[0094] A traditional method of simulating a quantum circuit is a full state vector simulator or The algorithm stores the entire quantum state (i.e., a complex vector) in memory, and quantum gates (complex or unitary matrices) are applied sequentially to the state vector. For n qubits, the main cost of this algorithm is 2^n. n That is, the size of the state vector in memory. In the Feynman algorithm, the system divides the lattice into multiple (e.g., two) blocks and applies Schmidt decomposition to the multi-qubit gates on the boundaries. If the Schmidt rank of each gate is r and the number of gates on the boundaries is g, then there exists r g Path. The system simulates all r g Calculate the number of paths and sum the results. Total runtime is calculated as follows: r g Proportional, where n1 and n2 are the number of qubits in the first and second blocks, respectively. Each block consists of... Algorithms are used for simulation. Path simulations are independent of each other and can be parallelized for use on supercomputers or data centers.

[0095] It operates in the center.

[0096] Note that in example procedure 200 (“Block XEB”), all multi-qubit gates are removed across the boundary, therefore g = 0, and the simulation cost is In example process 300 (“XEB omitted”), some of the multi-qubit gates are removed across the boundary. For example, in the benchmark quantum circuit defined in step 302, there might be g = 35 gates crossing the boundary, and in step 304, 20 gates can be removed to define a modified benchmark quantum circuit with g = 15 gates crossing the boundary. For example, the gates crossing the boundary could be control-Z quantum gates with a Schmidt rank r = 2. Therefore, the cost of simulating the omitted circuit is... The cost of the initial circuit is

[0097] The system can then compare classical benchmark data with experimental benchmark data to estimate the fidelity of the benchmark quantum circuit. For example, the system can apply cross-entropy benchmarking techniques to estimate the fidelity of the benchmark quantum circuit.

[0098] As per the above reference Figure 2 In some implementations, example process 300 can be repeated for multiple benchmark quantum circuits of the same circuit depth and for multiple benchmark circuits of different depths. For example, the system can repeat example process 300 for multiple circuits of different depths as part of a normal benchmarking process to estimate the fidelity as a function of circuit depth, and determine a measure of the error per cycle by fitting the fidelity as a function of circuit depth to an exponential function.

[0099] In some implementations, the system may use one or more estimated fidelities to determine one or more adjustments to the quantum computing hardware, such as adjustments to the control parameters of the control model used by the quantum computing hardware to implement quantum operations. The system can then implement the determined adjustments when performing future computations to improve the operation and / or performance of the quantum computing hardware.

[0100] Compared to block XEB, omitting XEB provides a closer description of the complete system performance under a full XEB circuit – in addition to capturing issues such as control and readout crosstalk, omitting XEB allows entanglement to form between two weakly connected subsystems. It essentially covers all possible processes that occur in a full XEB measurement, and therefore can be used to predict system performance at a significantly reduced computational cost (although still higher than that of block XEB).

[0101] Figure 4 This is an example illustration of partitioning or modifying a benchmark quantum circuit. As described above with reference to steps 202 and 302, the system-defined benchmark quantum circuit includes one or more quantum gate cycles, wherein each cycle includes a corresponding layer of randomly sampled single-qubit gates and layers of multiple instances of the same multi-qubit gates. Figure 4 Example layer 400 illustrates multiple instances of a two-qubit gate. In example layer 400, circles represent qubits in a qubit array used to benchmark quantum circuit operations. Solid lines between qubits represent instances of two-qubit gates. In example layer 400, the two-qubit gate operates on each adjacent pair of qubits.

[0102] As described above with reference to steps 204 and 304, the system divides or modifies the defined benchmark quantum circuit into two or more blocks by defining one or more boundaries in the qubit array. Example layer 400 illustrates a defined boundary 406. Boundary 406 is located at the center of the qubit array; however, as described above with reference to... Figure 2 The system can define multiple boundaries, and the positions of the defined boundaries can vary.

[0103] As described above with reference to steps 204 and 304, the system can remove all or a small portion of an instance of a multi-qubit gate along one or more boundaries in one or more layers of multiple instances of a multi-qubit gate. Example layer 410 illustrates a candidate two-qubit gate that can be removed, such as two-qubit gate 408. Example layer 420 illustrates two sub-circuits generated according to example process 200, wherein all two-qubit gates on or across boundary 406 have been removed. Figure 4As shown, the two resulting sub-circuits are disjoint and can therefore be classically simulated separately. Example layer 430 illustrates a benchmark quantum circuit obtained after a small portion of the two-qubit gate on or across boundary 406 has been removed. Figure 4 As shown, the blocks generated in step 304 are not disjoint and therefore cannot be classically simulated alone.

[0104] The digital and / or quantum themes and implementations of digital functional operations and quantum operations described in this specification may be implemented in digital electronic circuits, suitable quantum circuits, or more generally in quantum computing systems, in physically implemented digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them. The term "quantum computing system" may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

[0105] The implementation of the digital and / or quantum themes described in this specification can be implemented as one or more digital and / or quantum computer programs (i.e., one or more modules of digital and / or quantum computer program instructions encoded on a tangible, non-transitory storage medium) for execution by a data processing device or for controlling the operation of a data processing device. The digital and / or quantum computer storage medium can be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory device, one or more qubits, or a combination thereof. Alternatively or additionally, program instructions can be encoded on artificially generated propagation signals (e.g., machine-generated electrical, optical, or electromagnetic signals) capable of encoding digital and / or quantum information, generating such propagation signals to encode the digital and / or quantum information for transmission to a suitable receiver device for execution by the data processing device.

[0106] The terms quantum information and quantum data refer to information or data carried, stored, or contained in quantum systems, the smallest non-trivial system being a qubit, i.e., a system that defines a unit of quantum information. It should be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the appropriate context. Such quantum systems can include, for example, multi-level systems with two or more levels. For example, such systems can include atomic, electron, photon, ionic, or superconducting qubits. In many implementations, the fundamental computational state is identified by the ground state and the first excited state; however, it should be understood that other settings where the computational state is identified by a higher-level excited state are possible.

[0107] The term "data processing device" refers to digital and / or quantum data processing hardware and encompasses all types of devices, apparatuses, and machines for processing digital and / or quantum data, including, for example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, multiple digital and quantum processors or computers, and combinations thereof. The device may also be or include special-purpose logic circuitry, such as FPGAs (Field-Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), or quantum simulators—quantum data processing devices designed to simulate or generate information about a particular quantum system. Specifically, a quantum simulator is a special-purpose quantum computer that lacks the capability to perform general-purpose quantum computing. In addition to hardware, the device may optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or combinations thereof.

[0108] Digital computer programs (also referred to or described as programs, software, software applications, modules, software modules, scripts, or code) can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages) and can be deployed in any form (including as standalone programs or as modules, components, subroutines, or other units suitable for digital computing environments). Quantum computer programs (also referred to or described as programs, software, software applications, modules, software modules, scripts, or code) can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages) and translated into a suitable quantum programming language, or can be written in a quantum programming language (e.g., QCL or Quipper).

[0109] Digital and / or quantum computer programs may, but do not need to, correspond to files in a file system. Programs may be stored in sections of files that store other programs or data, such as in markup language documents, in a single file dedicated to the program in question, or in one or more scripts within multiple coordinating files (e.g., files storing one or more modules, subroutines, or code sections). Digital and / or quantum computer programs can be deployed to execute on a single digital or quantum computer, or on multiple digital and / or quantum computers located in one location or distributed across multiple locations and interconnected via digital and / or quantum data communication networks. A quantum data communication network is understood as a network that can use quantum systems (e.g., qubits) to transmit quantum data. Generally, digital data communication networks cannot transmit quantum data, but quantum data communication networks can transmit both quantum data and digital data.

[0110] The processes and logical flows described in this specification can be executed by one or more programmable digital and / or quantum computers, which, as needed, operate in conjunction with one or more digital and / or quantum processors to execute one or more digital and / or quantum computer programs to perform functions by manipulating input digital and quantum data and generating outputs. The processes and logical flows can also be executed by dedicated logic circuitry (e.g., FPGA or ASIC) or a quantum simulator, or by a combination of dedicated logic circuitry or a quantum simulator with one or more programmable digital and / or quantum computers, and the apparatus can also be implemented as a combination of dedicated logic circuitry (e.g., FPGA or ASIC) or a quantum simulator, or a combination of dedicated logic circuitry or a quantum simulator with one or more programmable digital and / or quantum computers.

[0111] For a system of one or more digital and / or quantum computers to be "configured to" perform a specific operation or action, this means that the system has software, firmware, hardware, or a combination thereof installed on it that, when operated, causes the system to perform the operation or action. For one or more digital and / or quantum computer programs to be configured to perform a specific operation or action, this means that one or more programs include instructions that, when executed by a digital and / or quantum data processing device, cause the device to perform an operation or action. A quantum computer can receive instructions from a digital computer that, when executed by a quantum computing device, cause the device to perform an operation or action.

[0112] Digital and / or quantum computers suitable for executing digital and / or quantum computer programs can be based on general-purpose or special-purpose digital and / or quantum processors or both, or on any other kind of central digital and / or quantum processing unit. Generally, the central digital and / or quantum processing unit receives instructions and digital and / or quantum data from read-only memory, random access memory, or a quantum system (e.g., photons) suitable for transmitting quantum data, or a combination thereof.

[0113] The basic components of a digital and / or quantum computer are a central processing unit (CPU) for executing or running instructions and one or more memory devices for storing instructions and digital and / or quantum data. The CPU and memory may be supplemented or incorporated into dedicated logic circuitry or a quantum simulator. Generally, a digital and / or quantum computer will also include one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, optical disks, or quantum systems suitable for storing quantum information) for storing digital and / or quantum data, or operatively coupled to one or more mass storage devices to receive digital and / or quantum data from, or to transmit digital and / or quantum data, or both. However, a digital and / or quantum computer does not need to have such devices.

[0114] Digital and / or quantum computer-readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memories, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; disks such as internal hard disks or removable disks; magneto-optical disks; CD-ROM and DVD-ROM disks; and quantum systems such as trapped atoms or electrons. It is understood that quantum memory is a device capable of storing quantum data for long periods with high fidelity and efficiency, such as a light-matter interface in which light is used for transmission and matter is used for storage and preservation of quantum characteristics (such as superposition or quantum coherence) of the quantum data.

[0115] Control of the various systems or portions thereof described in this specification may be implemented in a digital and / or quantum computer program product comprising instructions stored on one or more non-transitory machine-readable storage media and executable on one or more digital and / or quantum processing devices. Each system or portion thereof described in this specification may be implemented as comprising an apparatus, method, or system for storing one or more digital and / or quantum processing devices and memories for performing the operations described in this specification.

[0116] Although this specification includes details of various specific implementations, these details should not be construed as limiting the scope of claims, but rather as descriptions of features specific to particular implementations. Certain features described in this specification within the context of separate implementations may also be implemented in combination within a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination within multiple implementations. Furthermore, although features are described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combinations may, in some cases, be removed from the combinations, and the claimed combinations may be for sub-combinations or variations thereof.

[0117] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific order shown or sequentially, nor as requiring the execution of all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system modules and components in the above implementations should not be construed as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0118] Specific implementations of the subject matter have been described. Other implementations are within the scope of this disclosure. For example, the actions stated in this application can be performed in a different order and still achieve the desired result. As an example, the processes depicted in the figures do not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A method for estimating quantum processor performance, the method comprising: defining a benchmark quantum circuit configured to operate on an array of qubits, wherein the benchmark quantum circuit comprises one or more cycles of quantum gates, each cycle of quantum gates comprising a respective layer of randomly sampled single-qubit gates and a layer of multiple instances of the same multi-qubit gate; partitioning the defined benchmark quantum circuit into two or more sub-circuits, including: defining one or more boundaries between qubits in the array of qubits, removing instances of the multi-qubit gate that cross the defined one or more boundaries to create two or more sub-circuits, each sub-circuit being a circuit that does not cross any of the defined one or more boundaries; executing a benchmarking process using the partitioned benchmark quantum circuit to estimate a respective circuit fidelity of each of the two or more sub-circuits; and multiplying the estimated circuit fidelities of each of the two or more sub-circuits to obtain an estimate of the fidelity of the defined benchmark quantum circuit, wherein the two or more sub-circuits comprise disjoint sub-circuits that respectively operate on disjoint subsets of qubits in the array of qubits.

2. The method of claim 1, wherein, defining the benchmark quantum circuit comprises: randomly sampling a plurality of single-qubit quantum gates from a predetermined set of single-qubit quantum gates, wherein each randomly sampled single-qubit quantum gate corresponds to a respective qubit in the array of qubits and to a respective cycle of the one or more cycles; assigning the randomly sampled plurality of single-qubit quantum gates to respective layers of randomly sampled single-qubit gates in the defined benchmark quantum circuit; and assigning instances of the multi-qubit gate to layers of multiple instances of the same multi-qubit gate.

3. The method of any one of claims 1 and 2, wherein, each layer of multiple instances of the multi-qubit gate comprises multiple copies of a two-qubit gate, wherein each copy of the two-qubit gate operates on a respective nearest-neighbor pair of qubits in the array of qubits.

4. The method of claim 3, wherein, the multiple copies of the two-qubit gate operate on all pairs of adjacent qubits in the array of qubits.

5. The method of claim 1, wherein, executing the benchmarking process using the partitioned benchmark quantum circuit to determine a respective circuit fidelity of each of the two or more sub-circuits comprises: implementing the partitioned benchmark quantum circuit using quantum computing hardware to obtain experimental benchmark data; classically simulating an ideal implementation of the partitioned benchmark quantum circuit, including performing separate simulations of the ideal implementation for each of the two or more sub-circuits to obtain a respective set of classical benchmark data, each set representing an output distribution of the ideal implementation of the respective sub-circuit; for each sub-circuit, comparing the classical benchmark data for the sub-circuit to a respective portion of the obtained experimental data to determine an estimated fidelity of the sub-circuit.

6. The method of claim 1, wherein, implementing the partitioned benchmark quantum circuit using quantum computing hardware to obtain experimental benchmark data comprises: initializing each qubit in the array of qubits in an initial state; applying the partitioned benchmark quantum circuit to the initialized qubits; and measuring each qubit in the array of qubits to obtain measurement data for each qubit.

7. The method of claim 6, further comprising: applying a Hadamard gate to each qubit after initializing each qubit in the array of qubits in an initial state and before applying the partitioned benchmark quantum circuit.

8. The method of claim 6, wherein, applying the partitioned benchmark quantum circuit to the initialized qubits includes performing a single-shot experiment in which each of the two or more sub-circuits is implemented simultaneously.

9. The method of claim 1, further comprising: defining a plurality of benchmark quantum circuits configured to operate on an array of qubits, wherein the defined plurality of benchmark quantum circuits includes quantum circuits having different circuit depths from a predetermined range of circuit depths; estimating a fidelity of each defined benchmark quantum circuit.

10. The method of claim 1, further comprising: determining one or more adjustments to quantum hardware control parameters based on the obtained estimates of fidelity of the defined benchmark quantum circuits; and implementing the determined one or more adjustments to perform a quantum computation using quantum computing hardware.

11. An apparatus for estimating quantum processor performance, comprising one or more classical and / or quantum storage devices storing instructions that are operable, when executed by one or more computers, to cause the one or more computing devices to perform operations comprising the method of claim 1.

12. A method for estimating quantum processor performance, the method comprising: defining a benchmark quantum circuit configured to operate on an array of qubits, wherein the benchmark quantum circuit includes one or more cycles of quantum gates, each cycle of quantum gates including a respective layer of randomly sampled single-qubit gates and a layer of multiple instances of the same multi-qubit gate; modifying the defined benchmark quantum circuit, including: defining one or more boundaries between qubits in the array of qubits, removing an appropriate subset of instances of the multi-qubit gate that cross the defined one or more boundaries such that one or more instances of the multi-qubit gate that cross the defined one or more boundaries remain; and performing a benchmarking process using the modified benchmark quantum circuit to estimate a fidelity of the defined benchmark quantum circuit.

13. The method of claim 12, wherein, removing an appropriate subset of instances of the multi-qubit gate that cross the defined one or more boundaries includes removing an appropriate subset of instances of the multi-qubit gate that cross the one or more boundaries in a predetermined number of cycles of quantum gates.

14. The method of claim 12, wherein, defining the benchmark quantum circuit includes: randomly sampling a plurality of single-qubit quantum gates from a predetermined set of single-qubit quantum gates, wherein each randomly sampled single-qubit quantum gate corresponds to a respective qubit in the array of qubits and to a respective cycle in the one or more cycles; assigning the randomly sampled plurality of single-qubit quantum gates to respective layers of randomly sampled single-qubit gates in the defined benchmark quantum circuit; and assigning an instance of the multi-qubit gate to a layer of a plurality of instances of the same multi-qubit gate.

15. The method of any one of claims 12 and 14, wherein, Each layer of the plurality of instances of the multi-qubit gate comprises a plurality of copies of a two-qubit gate, wherein each copy of the two-qubit gate operates on a respective nearest-neighbor pair of qubits in the array of qubits.

16. The method of claim 15, wherein, The plurality of copies of the two-qubit gate operate on all pairs of adjacent qubits in the array of qubits.

17. The method of claim 12, wherein, The method further comprises: implementing the modified benchmark quantum circuit using quantum computing hardware to obtain experimental benchmark data; classically simulating an ideal implementation of the modified benchmark quantum circuit, including executing a Schrödinger-Feynman algorithm to obtain classical benchmark data; comparing the classical benchmark data to the experimental data to determine an estimated fidelity of the defined benchmark quantum circuit.

18. The method of claim 12, wherein, Implementing the modified benchmark quantum circuit using quantum computing hardware to obtain experimental benchmark data comprises: initializing each qubit in the array of qubits in an initial state; applying the modified benchmark quantum circuit to the initialized qubits; and measuring each qubit in the array of qubits to obtain measurement data for each qubit.

19. The method of claim 18, further comprising: Applying a Hadamard gate to each qubit after initializing each qubit in the array of qubits in an initial state and before applying the modified benchmark quantum circuit.

20. The method of claim 12, further comprising: defining a plurality of benchmark quantum circuits configured to operate on the array of qubits, wherein the defined plurality of benchmark quantum circuits includes quantum circuits having different circuit depths from a predetermined range of circuit depths; estimating a fidelity of each defined benchmark quantum circuit.

21. The method of claim 12, further comprising: determining one or more adjustments to quantum hardware control parameters based on the obtained estimates of fidelity of the defined benchmark quantum circuits; and implementing the determined one or more adjustments to perform a quantum computation using quantum computing hardware.

22. An apparatus for estimating quantum processor performance, comprising one or more classical and / or quantum storage devices storing instructions that are operable, when executed by one or more computers, to cause the one or more computing devices to perform operations comprising the method of claim 12.

Images