CMOS-MEMS fully integrated thermopile chip based on CMOS process and manufacturing method

Abstract

The present invention provides a CMOS-MEMS fully integrated thermopile chip based on CMOS technology and a manufacturing method thereof, comprising a substrate, a micro-electromechanical system and a dedicated integrated circuit system, wherein the micro-electromechanical system and the integrated circuit system are separately arranged on the substrate, and an isolation layer is arranged on the substrate; the dedicated integrated circuit system comprises a MOS tube, the micro-electromechanical system comprises a thermopile and a heat sink area formed by a plurality of groups of thermocouples connected in series, a cavity is opened at the back of the substrate where the micro-electromechanical system is located, and the isolation layer separates the thermocouple and the heat sink area from the cavity; the thermocouple is electrically connected to the dedicated integrated circuit system, the heat sink area is grounded or suspended, and the inner wall of the heat sink area constitutes a cold end boundary and extends to the top of the cavity, so that the inner wall of the heat sink area is the cold end of the thermopile, the distance between the cold end and the hot end of the thermopile is fixed, and the consistency of the product is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of thermopile chip structure design, and in particular to a CMOS-MEMS fully integrated thermopile chip based on a CMOS process and a manufacturing method thereof. Background Art

[0002] Thermopile sensors are widely used in the field of infrared temperature measurement, such as ear thermometers, forehead thermometers, infrared temperature measuring guns, microwave ovens and other products. The principle of thermopile sensors is mainly based on the Seebeck effect, that is, when one end of different materials are connected together and there is a temperature difference between the two ends of the materials, an electromotive force will be generated. By collecting voltage parameters, the temperature difference between the cold end and the hot end of the material can be obtained, thereby realizing remote temperature measurement.

[0003] With the development of MEMS technology, there are two main types of technologies for realizing thermopile chips. One is the beam-membrane combination structure. The advantage of this solution is that the hot end has a strong heat collection ability and the sensor has a high sensitivity. The other is the closed membrane structure. The sensitivity of this solution is slightly lower, but it is compatible with CMOS technology.

[0004] The existing Chinese patent with announcement number CN214121427U discloses a thermopile sensor system with integrated CMOS circuit, including a substrate, the substrate including a first area and a second area; a CMOS circuit located in the first area; a thermopile sensor located in the second area, including a plurality of thermopile structures and a first type of metal connection, wherein the first type of metal connection connects the plurality of thermopile structures in series with the CMOS circuit. The thermopile sensor also includes: a cavity located in the substrate, the plurality of thermopile structures located above the cavity; and a release hole located between the plurality of thermopile structures, wherein each of the thermopile structures includes a plurality of first cantilever beams, at least one thermocouple on each of the first cantilever beams, and an infrared absorption film.

[0005] The inventors believe that in the prior art, the back cavity etching of the thermopile chip has certain process deviations during processing. The angle of the back cavity etching will directly affect the distance between the cold end and the hot end of the sealing membrane, which will lead to large differences in the thermal voltage output of different devices, resulting in poor product consistency. Summary of the invention

[0006] In view of the defects in the prior art, the object of the present invention is to provide a CMOS-MEMS fully integrated thermopile chip structure and a manufacturing method based on CMOS technology.

[0007] A CMOS-MEMS fully integrated thermopile chip based on CMOS process provided by the present invention comprises a substrate, a micro-electromechanical system and a special integrated circuit system, wherein the micro-electromechanical system and the special integrated circuit system are arranged separately on the substrate, and an isolation layer is arranged on the substrate; the special integrated circuit system comprises a MOS tube, and the MOS tube comprises an NMOS tube and a PMOS tube, and the NMOS tube and the PMOS tube are separated by an isolation layer; the micro-electromechanical system comprises a thermopile and a heat sink area, a cavity is opened at the back of the substrate where the micro-electromechanical system is located, and the isolation layer separates the thermocouple and the heat sink area from the cavity; the thermopile is formed by a plurality of groups of thermocouples connected in series, the thermopile extends from the edge of the substrate to the middle of the substrate, the thermopile is electrically connected to the special integrated circuit system, the heat sink area is grounded or suspended, and the inner wall of the heat sink area forms a cold end boundary.

[0008] Preferably, the thermocouple includes P-type polycrystal and N-type polycrystal, and the P-type polycrystal and N-type polycrystal are connected in series.

[0009] Preferably, the heat sink area includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer, the second metal layer, and the third metal layer are sequentially arranged at intervals or sequentially connected from bottom to top.

[0010] Preferably, the gaps between the first metal layer, the second metal layer and the third metal layer are filled with a dielectric isolation layer, and a passivation layer is arranged on top of the dielectric isolation layer.

[0011] Preferably, the heat sink area is a rectangular frame structure, and the inner wall of the heat sink area extends to the top of the cavity.

[0012] According to a manufacturing method of a CMOS-MEMS fully integrated thermopile chip based on a CMOS process provided by the present invention, the manufacturing method comprises the following steps: S1, preparing the substrate for standby; S2, making an isolation layer on the substrate; S3, making an NMOS tube and a PMOS tube on the substrate, and the NMOS tube and the PMOS tube are isolated by the isolation layer; S4, in-situ growing a gate oxide layer on the NMOS tube and the PMOS tube by a thermal oxidation process; S5, depositing a polycrystalline layer on the gate oxide layer and the substrate respectively, and the polycrystalline layer located on the other side of the substrate includes a P-type polycrystalline and an N-type polycrystalline; S6, making the first through-hole layer, then depositing the first metal layer, and connecting the P-type polycrystalline and the N-type polycrystalline in series through the first through-hole layer and the first metal layer; S7, sequentially making the second through-hole layer, depositing the second metal layer, making the third through-hole layer, and depositing the third metal layer to form a heat sink area; S8, depositing a passivation layer on the dielectric isolation layer; S9, etching the back side of the substrate to form a cavity, and the cavity etching stops at the isolation layer.

[0013] Preferably, for the production of the isolation layer in step S2, a shallow groove is etched on the substrate, a dielectric layer is deposited, and then the isolation layer is planarized by a CMP process to achieve production.

[0014] Preferably, an NMOS tube and a PMOS tube are manufactured for step S3; the formation process of the NMOS tube is as follows: boron is injected into the substrate to form a Pwell, and then phosphorus is injected into the Pwell to form the drain and source of the NMOS tube; the formation process of the PMOS tube is as follows: Nwell is first formed on the substrate, and then phosphorus and arsenic are injected into the Nwell to form the drain and source of the PMOS tube.

[0015] Preferably, for step 5, step S6 and step S7, after the polycrystalline layer is completed, a dielectric is deposited, then a first metal layer is deposited, then a dielectric is deposited, and then a second metal layer is deposited, and so on.

[0016] Preferably, for step S6 and step S7, the first metal layer, the second metal layer and the third metal layer located on the same side as the NMOS transistor and the PMOS transistor are used for routing, forming capacitor devices or forming resistor devices.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The present invention forms a rectangular heat sink area through the cooperation of the first metal layer, the second metal layer and the third metal layer, and the inner wall of the heat sink area extends to the top of the cavity, so that the inner wall of the heat sink area is the cold end of the thermopile, which helps to fix the distance between the cold end and the hot end of the thermopile, thereby helping to improve the consistency of the product;

[0019] 2. The present invention helps to improve the integration of chips and reduce costs by arranging the micro-electromechanical system and the application-specific integrated circuit system together;

[0020] 3. The present invention isolates the heat sink area and the cavity through an isolation layer. On the one hand, the isolation layer can serve as a stop layer for etching the cavity, which helps to improve the convenience of the etching operation. On the other hand, the isolation layer supports the heat sink area and the thermopile, which helps to improve the stability of the chip structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0022] Figure 1 It is a schematic diagram of the cross-sectional structure of the fully integrated thermopile chip from the front view of the present invention;

[0023] Figure 2 It is a schematic diagram of the cross-sectional structure of a fully integrated thermopile chip from a top view according to the present invention;

[0024] Figure 3 It is a schematic diagram mainly showing the positions of the cavities and heat sink areas on the fully integrated thermopile chip of the present invention;

[0025] Figure 4 The temperature rise spectrum of the thermopile film when the deep trench etching process capability is 90±5° is mainly reflected in the present invention.

[0026] As shown in the figure:

[0027] DETAILED DESCRIPTION

[0028] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0029] like Figure 1 and Figure 2 As shown, a CMOS-MEMS fully integrated thermopile chip based on CMOS process provided by the present invention includes a substrate 100, an isolation layer 101, a micro-electromechanical system 11 and a special integrated circuit system 12, wherein the isolation layer 101 is located on the substrate 100, the micro-electromechanical system 11 and the special integrated circuit system 12 are separated and arranged on the substrate 100, and the special integrated circuit system 12 is distributed and arranged around the micro-electromechanical system 11. The substrate 100 is a P-type silicon substrate 100.

[0030] The patented integrated circuit system includes a MOS tube 102, which includes an NMOS tube and a PMOS tube, and the NMOS tube and the PMOS tube are separated by an isolation layer 101. The NMOS tube is formed by injecting boron on the substrate 100 to form a Pwell, and then phosphorus is injected into the Pwell to form the drain and source of the NMOS tube; the PMOS tube is first formed on the substrate 100 to form an Nwell, and then phosphorus and arsenic are injected into the Nwell to form the drain and source of the PMOS tube. A gate oxide layer 103 is grown above the NMOS tube and the PMOS tube on the substrate 100, thereby forming the gates of the NMOS tube and the PMOS tube respectively, and a polycrystalline layer 104 is deposited on any gate oxide layer 103.

[0031] like Figure 1As shown, the micro-electromechanical system 11 includes a thermopile and a heat sink area. The thermopile is formed by a plurality of thermocouples connected in series. The thermocouples are deposited on the substrate 100, and the thermocouples extend from the edge of the substrate 100 to the middle of the substrate 100. The micro-electromechanical system 11 area is composed of a polycrystalline layer 104, which includes a P-type polycrystalline 114 and an N-type polycrystalline 115. The thermocouples are formed by the P-type polycrystalline 114 and the N-type polycrystalline 115 connected in series. A first through-hole layer 105 is formed above the P-type polycrystal 114 and the N-type polycrystal 115, and the lower end of any first through-hole layer 105 is connected to the corresponding P-type polycrystal 114 or N-type polycrystal 115. A first metal layer 106 is also deposited above the polycrystal layer 104. One or more first metal layers 106 are deposited in the middle and edge positions of the micro-electromechanical system 11 area on the substrate 100. The first metal layer 106 located in the middle of the micro-electromechanical system 11 area on the substrate 100 cooperates with the first through-hole layer 105 to connect the adjacent P-type polycrystal 114 and N-type polycrystal 115 in series to form a thermocouple, and finally form two interfaces, IP (positive end) and IN (negative end), which are connected to the dedicated integrated circuit system 12 for voltage collection.

[0032] The ASIC system 12 includes an ADC module, a bandgap reference voltage module, an oscillator digital circuit interface, and an OTP calibration module. The two interfaces IP (positive end) and IN (negative end) are connected to the ADC module.

[0033] like Figure 1 and Figure 2 As shown, a second metal layer 108 and a third metal layer 110 are deposited from bottom to top on the first metal layer 106 in the micro-electromechanical system 11 region on the substrate 100, a second through-hole layer 107 is connected between the first metal layer 106 and the second metal layer 108, and a third through-hole layer 109 is connected between the second metal layer 108 and the third metal layer 110. The heat sink area is formed by the first metal layer 106, the second metal layer 108, the third metal layer 110, the second through-hole layer 107 and the third through-hole layer 109. In the overall circuit, the heat sink area can be connected to the analog ground or left floating.

[0034] The first via layer 105, the first metal layer 106, the second via layer 107, the second metal layer 108, the third via layer 109 and the third metal layer 110 are formed in three groups above the NMOS transistor 102 and the PMOS transistor 102 of the ASIC system 12 on the substrate 100. The first metal layer 106, the second metal layer 108 and the third metal layer 110 located in the ASIC system area are used for routing, forming capacitor devices or forming resistor devices.

[0035] The areas of the micro-electromechanical system 11 and the ASIC system 12 located above the substrate 100 are filled with SiO2 to form a dielectric isolation layer 112. A passivation layer 111 is provided on top of the dielectric isolation layer 112 to protect the micro-electromechanical system 11 and the ASIC system 12.

[0036] like Figure 1 and Figure 3 As shown, a cavity 113 is provided on the back of the substrate 100 where the micro-electromechanical system 11 is located, and an isolation layer 101 separates the thermocouple and the heat sink area from the cavity 113. The isolation layer 101 supports the devices above the substrate 100. The heat sink area is a rectangular frame structure, and the inner wall of the heat sink area extends to the top of the cavity 113. The inner side of the heat sink area is the cold end boundary. Because metal has very good thermal conductivity, the temperature gradient between the cold end boundary of the heat sink area and the silicon substrate 100 is very small, and it can be considered as the cold end of the chip.

[0037] When a cavity 113 is formed on the back of the substrate 100, the ideal situation is to form a completely vertical sidewall of the cavity 113. However, in the actual process, the etching angle cannot form a 90° completely vertical morphology. Secondly, due to process fluctuations, it may form an inverted trapezoidal or regular trapezoidal morphology. If there is no heat sink area, the distance from the hot end (center) to the cold end of the thermopile chip will deviate from the design value, resulting in differences in the sensitivity of the thermopile sensor, which in turn affects the consistency of the product.

[0038] When there is a heat sink area, it is only necessary to reasonably design the width of the heat sink area to ensure that the distance between the hot end and the cold end remains constant without being affected by the back cavity etching process. At the same time, the design of the heat sink area brings a larger process tolerance to the back cavity etching process, reducing the process difficulty and cost.

[0039] The following is a calculation process for designing the width w of the heat sink area for this application:

[0040] 1) Assume that the thickness of the silicon wafer is h,

[0041] 2) The process error of deep trench etching is 90±α°,

[0042] 3) d = h * tan α;

[0043] 4) w ≥ h * tanα. In order to ensure the sensitivity of the thermopile and better heat sink effect, the redundant design is that the width of the heat sink area can be extended as far as possible to the outer edge.

[0044] like Figure 4As shown in the figure, it is the temperature rise spectrum of the thermopile film when the deep groove etching process capability is 90±5°. The temperature rise simulation is based on the thermopile film 900μm*900μm and the thickness of the silicon substrate 100 is 400μm. It can be seen from the figure that when the back cavity etches an inverted trapezoidal morphology, the film size is about 935μm*935μm, at which time the temperature rise is the largest, and the maximum temperature difference between the center and the edge is 261mK. When the back cavity etches a positive trapezoidal morphology, the film size is about 865μm*865μm, at which time the temperature rise is the smallest, and the maximum temperature difference between the center and the edge is 224mK. When designing the heat sink area, the cold end boundary is fixed, and the effective film area of ​​the thermopile is always 900μm*900μm. Within the process specifications, no matter what morphology is etched, the maximum temperature difference between the center and the edge can basically be maintained at 243mK. When the heat sink area is not designed, the resulting temperature rise error reaches ±7.8%, so the present invention can significantly improve the consistency of the product.

[0045] A method for manufacturing a CMOS-MEMS fully integrated thermopile chip based on a CMOS process provided by the present invention includes the above-mentioned CMOS-MEMS fully integrated thermopile chip structure based on a CMOS process, and the manufacturing method includes the following steps:

[0046] S1, prepare a P-type silicon substrate 100 for standby use;

[0047] S2. Manufacturing an isolation layer 101 on the substrate 100. Etching a shallow groove on the substrate 100, depositing a dielectric layer, and then planarizing the isolation layer 101 through a CMP process.

[0048] S3. NMOS and PMOS are fabricated in the ASIC 12 region of the substrate 100, and the NMOS and PMOS are isolated by the isolation layer 101. Formation process of the NMOS: Boron is injected into the substrate 100 to form Pwell, and then phosphorus is injected into Pwell to form the drain and source of the NMOS. Formation process of the PMOS: Nwell is first formed on the substrate 100, and then phosphorus and arsenic are injected into Nwell to form the drain and source of the PMOS.

[0049] S4, forming a gate oxide layer 103 by in-situ growth on the NMOS tube and the PMOS tube through a thermal oxidation process;

[0050] S5, depositing a polycrystalline layer 104 on the gate oxide layer 103 and the substrate 100 respectively, wherein the polycrystalline layer 104 on the other side of the substrate 100 includes a P-type polycrystalline 114 and an N-type polycrystalline 115. After the polycrystalline layer 104 is completed, a dielectric is deposited.

[0051] S6. The first via layer 105 is manufactured by the 1P3M process, and the first metal layer 106 is deposited. The P-type polycrystalline 114 and the N-type polycrystalline 115 are connected in series through the first via layer 105 and the first metal layer 106, and then a dielectric is deposited.

[0052] S7, using the 1P3M process, sequentially fabricating the second via layer 107, depositing the second metal layer 108, depositing a dielectric, fabricating the third via layer 109, and depositing the third metal layer 110 to form a heat sink area.

[0053] S8, depositing a passivation layer 111 on the dielectric isolation layer 112;

[0054] S9 , etching the back side of the other side of the substrate 100 to form a cavity 113 , and the etching of the cavity 113 stops at the isolation layer 101 .

[0055] How it works

[0056] During the manufacturing process, the substrate 100 is first prepared for standby use; an isolation layer 101 is then manufactured on the substrate 100; an NMOS tube and a PMOS tube are then manufactured on the substrate 100, and the NMOS tube and the PMOS tube are isolated by the isolation layer 101; a gate oxide layer 103 is then in-situ grown on the NMOS tube and the PMOS tube by a thermal oxidation process; a polycrystalline layer 104 is then deposited on the gate oxide layer 103 and the substrate 100, respectively, and the polycrystalline layer 104 located on the other side of the substrate 100 includes a P-type polycrystalline 114 and an N-type polycrystalline 115; and The first through-hole layer 105 is then manufactured, and the first metal layer 106 is deposited, and the P-type polycrystalline 114 and the N-type polycrystalline 115 are connected in series through the first through-hole layer 105 and the first metal layer 106; then the second through-hole layer 107 is manufactured in sequence, the second metal layer 108 is deposited, the third through-hole layer 109 is manufactured, and the third metal layer 110 is deposited to form a heat sink area; then the passivation layer 111 is deposited on the dielectric isolation layer 112; finally, the back side of the substrate 100 is etched to form a cavity 113, and the etching of the cavity 113 stops at the isolation layer 101.

[0057] In the description of the present application, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0058] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A CMOS-MEMS fully integrated thermopile chip based on CMOS technology, characterized in that: Comprising a substrate (100), a micro-electromechanical system (11) and a dedicated integrated circuit system (12), wherein the micro-electromechanical system (11) and the dedicated integrated circuit system (12) are arranged separately on the substrate (100), and an isolation layer (101) is arranged on the substrate (100); The dedicated integrated circuit system (12) comprises a MOS tube (102), the MOS tube (102) comprises an NMOS tube and a PMOS tube, and the NMOS tube and the PMOS tube are separated by an isolation layer (101); The micro-electromechanical system (11) comprises a thermopile and a heat sink area, a cavity (113) is provided at the back of a substrate (100) on which the micro-electromechanical system (11) is located, and the isolation layer (101) separates the thermocouple and the heat sink area from the cavity (113); The thermopile is formed by a plurality of groups of thermocouples connected in series, the thermopile extends from an edge of a substrate (100) to a middle of the substrate (100), the thermopile is electrically connected to a dedicated integrated circuit system (12), the heat sink area is grounded or suspended, and the inner wall of the heat sink area forms a cold end boundary.

2. The CMOS-MEMS fully integrated thermopile chip based on CMOS process as claimed in claim 1, wherein the thermocouple comprises a P-type polycrystal (114) and an N-type polycrystal (115), and the P-type polycrystal (114) and the N-type polycrystal (115) are connected in series.

3. The CMOS-MEMS fully integrated thermopile chip based on CMOS technology according to claim 1, characterized in that: The heat sink area comprises a first metal layer (106), a second metal layer (108), and a third metal layer (110). The first metal layer (106), the second metal layer (108), and the third metal layer (110) are sequentially arranged at intervals or sequentially connected from bottom to top.

4. The CMOS-MEMS fully integrated thermopile chip based on CMOS technology as claimed in claim 3, characterized in that: The gaps between the first metal layer (106), the second metal layer (108) and the third metal layer (110) are filled with a dielectric isolation layer (112), and a passivation layer (111) is arranged on the top of the dielectric isolation layer (112).

5. The CMOS-MEMS fully integrated thermopile chip based on CMOS technology according to claim 1, characterized in that: The heat sink area is a rectangular frame structure, and the inner wall of the heat sink area extends to the top of the cavity (113).

6. A method for manufacturing a CMOS-MEMS fully integrated thermopile chip based on CMOS technology, characterized in that: The manufacturing method comprises the following steps: S1, prepare a substrate (100) for standby use; S2, manufacturing an isolation layer (101) on the substrate (100); S3, manufacturing an NMOS tube and a PMOS tube on the substrate (100), and the NMOS tube and the PMOS tube are isolated by an isolation layer (101); S4, in-situ growth of a gate oxide layer (103) is performed on the NMOS tube and the PMOS tube by a thermal oxidation process; S5, depositing a polycrystalline layer (104) on the gate oxide layer (103) and the substrate (100) respectively, wherein the polycrystalline layer (104) located on the substrate (100) includes a P-type polycrystalline (114) and an N-type polycrystalline (115); S6, manufacturing a first through-hole layer (105), depositing a first metal layer (106), and connecting the P-type polycrystalline (114) and the N-type polycrystalline (115) in series via the first through-hole layer (105) and the first metal layer (106); S7, sequentially manufacturing a second through hole layer (107), depositing a second metal layer (108), manufacturing a third through hole layer (109), and depositing a third metal layer (110) to form a heat sink area; S8, the gaps between the first metal layer (106), the second metal layer (108) and the third metal layer (110) are filled with a dielectric isolation layer (112), the material of the dielectric isolation layer (112) is SiO2, and a passivation layer (111) is deposited on the dielectric isolation layer (112); S9, etching to form a cavity (113) on the back side of the substrate (100), wherein the etching of the cavity (113) stops at the isolation layer (101).

7. The method for manufacturing a CMOS-MEMS fully integrated thermopile chip based on CMOS technology according to claim 6, characterized in that: In step S2, for the production of the isolation layer (101), a shallow groove is etched on the substrate (100), a dielectric layer is deposited, and then planarization is performed through a CMP process to achieve the production of the isolation layer (101).

8. The method for manufacturing a CMOS-MEMS fully integrated thermopile chip based on CMOS technology according to claim 6, characterized in that: According to step S3, an NMOS tube and a PMOS tube are manufactured; The formation process of the NMOS tube is as follows: boron is implanted on the substrate (100) to form a Pwell, and then phosphorus is implanted in the Pwell to form the drain and source of the NMOS tube; The formation process of the PMOS tube is as follows: firstly, a Nwell is formed on the substrate (100), and then phosphorus and arsenic are implanted into the Nwell to form the drain and source of the PMOS tube.

9. The method for manufacturing a CMOS-MEMS fully integrated thermopile chip based on CMOS technology according to claim 6, characterized in that: With respect to step S5, step S6, and step S7, after the polycrystalline layer (104) is completed, a dielectric is deposited, then a first metal layer (106) is deposited, then a dielectric is deposited, and then a second metal layer (108) is deposited, and so on.

10. The method for manufacturing a CMOS-MEMS fully integrated thermopile chip based on CMOS technology according to claim 6, characterized in that: For step S6 and step S7, the first metal layer (106), the second metal layer (108) and the third metal layer (110) located on the same side as the NMOS tube and the PMOS tube are used for routing, forming capacitor devices or forming resistor devices.

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