A register selection optimization method to improve instruction-level parallelism

Abstract

The present invention discloses a register selection optimization method for improving instruction-level parallelism, and the steps include: 1) describing the mapping relationship between instructions and instruction subsets; 2) analyzing the registers used in other instructions related to the instruction where the candidate is located, if there are unassigned registers in addition to these registers, jump to step 4); otherwise, execute the next step; 3) find the instruction subset that contains both the allocation candidate and its candidate register, and calculate the number of instruction subsets and the number of instructions containing the candidate register in units of a single candidate register; 4) select the register with the least impact on the dependency for each register allocation candidate. The present invention fully considers the logical parallel relationship between instructions, and can cause additional data dependencies between instructions within as few instruction subsets and as few instruction ranges as possible, so as to improve the freedom of instruction scheduling and obtain target code with higher instruction-level parallelism.

Description

Technical Field

[0001] The present invention relates to the technical field of code optimization compilation, and in particular to a register selection optimization technology when assigning physical registers to the life cycle of symbolic variables in a very long instruction word architecture processor. Background Art

[0002] In a compiler, mapping symbolic variables in the code to physical registers is one of the core tasks of compilation. The corresponding process is usually called register allocation, where the subprocess of mapping the life cycle of symbolic variables to specific physical registers is called register assignment. The optimal use of register resources is closely related to the running performance of the compiled target code. Among the existing register allocation methods, the global register allocation method based on the graph coloring idea is based on a detailed characterization of the variable life cycle and is a method with better register allocation effect.

[0003] Traditional register allocation methods only focus on the allocation of register resources to ensure that as much data as possible is stored in registers, which can easily lead to additional data dependencies between instructions due to the use of registers, which is not conducive to obtaining better instruction scheduling results. The improved method mainly considers register allocation in combination with basic block instruction scheduling, such as placing instruction scheduling before register allocation, or performing instruction scheduling before and after register allocation.

[0004] It should be pointed out that parallel technologies such as Very Long Instruction Word (VLIW) have been widely valued and increasingly applied and developed in modern high-performance microprocessors, especially high-performance digital signal processors (DSPs). In such processors, the number of registers is often large, and the number of functional units that execute instructions is also large. Existing register allocation methods can easily lead to additional data dependencies between instructions due to the use of registers, which is not conducive to improving the instruction-level parallelism of the compiled code. Summary of the invention

[0005] The technical problem to be solved by the present invention is: in view of the shortcomings of the existing register allocation method, a register selection method is provided for register allocation candidates (i.e., variable life cycle) to reduce the data dependency between instructions (also known as instruction dependency) caused by unrelated register allocation candidates being mapped to the same physical register, so that the subsequent instruction scheduling process has more room for optimization.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0007] 1) At the beginning of the register allocation process, the logical parallel execution relationship between instructions in the basic block determined by the symbolic variable name contained in the process (or function) is considered to obtain a corresponding instruction priority (also called logical priority) information;

[0008] 2) Based on the information, the instruction sequence of each basic block is divided into a number of subsets that can be executed in parallel logically to form an instruction subset sequence;

[0009] 3) When assigning registers for variable lifetimes (i.e., making register selections), a register is appropriately selected for the variable lifetime based on these instruction subset sequences and the dynamics of register allocation.

[0010] A register selection optimization method for improving instruction level parallelism, comprising:

[0011] Step S1: improving the register allocation process, after replacing the variable name at the corresponding position in the function with the variable life cycle name for the first time, returning to the starting position of the register allocation process and re-performing the register allocation process;

[0012] Step S2: adding a processing link, which is used to obtain the dependency relationship between instructions in each basic block of the function, and divide the instructions in each basic block into multiple subsets according to the transmission order of the dependency relationship, and this link is used as the first link in the register allocation processing process;

[0013] Step S3: at the beginning of the register assignment process, before selecting a register for a specific variable lifecycle (also referred to as a register assignment candidate, or simply a candidate), construct a mapping relationship between instructions and the instruction subset to which they belong;

[0014] Step S4: Analyze the registers used in other instructions related to the candidate instruction. If there are unassigned registers besides these registers, jump to step S6; otherwise, execute step S5;

[0015] Step S5: Find the instruction subsets that contain both the allocation candidate and its candidate register, and calculate the number of instruction subsets and the number of instructions containing the candidate register in units of a single candidate register;

[0016] Step S6: For each register allocation candidate, select the register that has the least impact on the dependency.

[0017] In the above process, the data structure of the instruction includes:

[0018] 1) List of instruction subsets in each basic block: For the instruction sequence in each basic block, they are divided into multiple instruction subsets according to the dependencies between them; these instruction subsets in the basic block together constitute the instruction subset list instnGroupList;

[0019] 2) Mapping relationship between instructions and instruction subsets: Each instruction is in an instruction subset, and they form a mapping relationship pair; all such mapping relationship pairs form a set mI_igroup;

[0020] 3) Mapping relationship between instructions and w sets: An instruction may access multiple ws, which form a corresponding set. This instruction and the corresponding w set form a mapping pair. All such mapping pairs form a set, called mI_sA.

[0021] 4) The mapping relationship between w and the physical register it obtains: Each w and the register mapping pair assigned to it constitute a set, called mW_PR.

[0022] In the above step S3, for each instruction ix of each basic block, find the maximum value idnMax among the idns corresponding to the instructions on which ix depends, and set the idn of ix equal to idnMax+1; then, put the instructions with the same idn value into the corresponding set igroup, igroup is the instruction subset corresponding to the instruction; finally, add the mapping pair of ix and igroup to the mI_igroup set.

[0023] In the above step S4, when analyzing the registers used in other instructions related to the instruction where the candidate is located, the following steps are taken:

[0024] Step S401: Find the registers that have not been used by the adjacent candidates (i.e., the lifecycles have an intersection) of W, and form a candidate register set SA; if SA is empty, there is no candidate register for w to use, and the assignment process ends; otherwise, execute the next step;

[0025] Step S402: Obtain a mapping relationship mI_sA between an instruction and its related register allocation candidates;

[0026] Step S403: According to the content of the mapping relationship mI_sA, analyze which registers have been used in the instruction subset where all instructions using W are located, and put these registers into SX;

[0027] Step S404: Calculate C=SA-SX. If C is not empty, select a register from C as the register to be assigned according to certain rules, such as the largest, smallest or random number; otherwise, execute step S5.

[0028] In the above step S402, in the process of obtaining the mapping relationship between the instruction and the register allocation candidate involved, for each candidate w, each instruction that sets a value for w and each instruction that uses w is traversed respectively, and w is added to the set SA corresponding to these instructions for storing register candidates, and the mapping relationship mI_sA between the instruction and the candidate set is obtained.

[0029] In the above step S5, when calculating the number of instruction subsets and the number of instructions containing candidate registers in units of single candidate registers, for the candidate register set SA, the following heuristics 1 and 2 are used to further process SA. If SA is empty after processing, SA is restored to its state before processing; if the number of registers in SA is 1, the register is selected and assigned to W; if the number of registers remaining in SA is greater than 1, one of the registers is selected and assigned to w according to a certain rule, such as the largest, smallest or random number;

[0030] In the above process, the heuristic method 1 is to select registers from SA that have an impact on as few instruction subsets as possible. The method is to analyze the number ng of instruction subsets that contain both W and this reg for each register reg in SA, and then, only keep the register corresponding to the minimum ng value in SA, and remove all other registers from SA;

[0031] In the above process, the second heuristic is to select registers from SA that affect as few instructions as possible. The method is to analyze, for each register reg in SA, the number ni of instructions that use this reg in the instruction subset that contains both W and this reg, and then, only retain the register corresponding to the minimum ni value in SA, and remove all other registers from SA.

[0032] Compared with the prior art, the advantages of the present invention are:

[0033] Compared with the existing register assignment method, the method of the present invention takes into account the logical parallel relationship between instructions. When selecting registers, first try to avoid all registers in the candidate register set that have been obtained by other instructions that can be executed in parallel with the instructions containing the candidates at the symbol variable level. If the remaining candidate registers are empty sets, then try to avoid those registers involving more instruction subsets and more instructions. In this way, the registers finally selected can cause additional data dependencies between instructions within as few instruction subsets and as few instructions as possible, which is conducive to improving the freedom of instruction scheduling and obtaining target code with higher instruction-level parallelism. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 : is the overall process diagram of the present invention performing register assignment processing on all candidates.

[0035] Figure 2 : is a diagram of an assignment processing method for selecting a register for a register allocation candidate according to the present invention. DETAILED DESCRIPTION

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] The register selection optimization method for improving instruction-level parallelism of the present invention is an improvement on the shortcomings of existing register allocation methods that only focus on the allocation of register resources themselves and do not consider the data correlation between instructions. Register allocation is combined with basic block instruction scheduling to improve the freedom of instruction scheduling and obtain target code with higher instruction-level parallelism.

[0038] In object-oriented language software, data and related functional modules are encapsulated in classes. The implementation content involved in the method of the present invention can be encapsulated into a register assigner class, with the required data as data members of this class and the required sub-methods as member functions of this class.

[0039] Because the method of the present invention is an optimization method for the register selection problem, it is assumed that the method is implemented on the following main basic information: register resource information of the processor architecture, a list or set composed of various candidates, a conflict graph and an adjacency list describing the conflict relationship between the candidates, information related to the constants (def) and uses (use) involved in w, a stack stk composed of w that needs to be assigned physical registers in sequence, and dependencies between basic blocks and instructions within the basic blocks.

[0040] In the following description, only the contents directly related to the present invention are involved.

[0041] See also Figure 1 and Figure 2 The register selection optimization method for improving instruction level parallelism of the present invention comprises:

[0042] 1) Describe the mapping relationship between instructions and instruction subsets;

[0043] 2) Analyze the registers used in other instructions related to the candidate instruction. If there are unassigned registers besides these registers, jump to step 4); otherwise, execute the next step;

[0044] 3) Find the instruction subsets that contain both the allocation candidate and its candidate register, and calculate the number of instruction subsets and the number of instructions containing the candidate register respectively based on a single candidate register;

[0045] 4) For each register allocation candidate, select the register that has the least impact on the dependency.

[0046] In a specific application example, in the above step 1), for each instruction ix of each basic block, find the maximum value idnMax of the idns corresponding to the instructions that ix depends on, and set the idn of ix equal to idnMax+1. Then, put the instructions with the same idn value into the corresponding set igroup, igroup being the instruction subset corresponding to the instruction. Finally, add the mapping pair of ix and igroup to the mI_igroup set.

[0047] In a specific application example, in the above step 2), when analyzing the registers used in other instructions related to the instruction where the candidate is located, the following steps are taken:

[0048] a) Find the registers that have not been used by the adjacent candidates of W (i.e., those with overlapping life cycles), and form a candidate register set SA. If SA is empty, there is no candidate register for w to use, and the assignment process ends; otherwise, proceed to the next step;

[0049] b) Obtain the mapping relationship mI_sA between the instruction and the register allocation candidate involved;

[0050] c) According to the content of the mapping relationship mI_sA, analyze which registers have been used in the instruction subset where all instructions using W are located, and put these registers into SX;

[0051] d) Calculate C=SA-SX. If C is not empty, select a register from C as the register to be assigned according to certain rules, such as the largest, smallest or random number; otherwise, execute step 3).

[0052] In a specific application example, in the above step 3), when calculating the number of instruction subsets and the number of instructions containing candidate registers in units of single candidate registers, for the candidate register set SA, the following heuristics 1 and 2 are used to further process SA. If SA is empty after processing, SA is restored to its state before processing; if the number of registers in SA is 1, the register is selected and assigned to W; if the number of registers remaining in SA is greater than 1, one of the registers is selected and assigned to w according to certain rules, such as the largest, smallest or random number;

[0053] In the above process, the heuristic method 1 is to select registers from SA that have an impact on as few instruction subsets as possible. The method is to analyze the number ng of instruction subsets that contain both W and this reg for each register reg in SA, and then, only keep the register corresponding to the minimum ng value in SA, and remove all other registers from SA;

[0054] In the above process, the second heuristic is to select registers from SA that affect as few instructions as possible. The method is to analyze, for each register reg in SA, the number ni of instructions that use this reg in the instruction subset that contains both W and this reg, and then, only retain the register corresponding to the minimum ni value in SA, and remove all other registers from SA.

[0055] In conjunction with a specific application example, the implementation steps of the present invention are described in a graph coloring global register allocation framework.

[0056] As a basis for implementing the method, it is assumed that a conflict graph and a corresponding adjacency list describing the conflict relationship between candidates have been established in advance, and a stack stk for storing candidates to be assigned registers in sequence has been established. The steps of the method of the present invention are as follows:

[0057] 1) According to the dependencies between instructions in the basic block, construct the instruction subsets of the instructions related to all candidates;

[0058] 2) Take each candidate W from the top of stk in turn and select a register to assign to it until stk is empty. For each register assignment candidate W taken out, process it once with the following steps;

[0059] 3) Find the registers that have not been used by the adjacent candidates of W (i.e., those whose life cycles overlap), and form a candidate register set SA;

[0060] 4) Define a set SX to store register numbers, analyze which registers have been used in the instruction subset where all instructions using W are located, and put these registers into SX. Construct a difference set SB = SA-SX. If SB is an empty set, go to the next step; otherwise, according to certain rules, such as the largest, smallest or random number, select one of the registers as the register to be assigned, and then go to step 2) to process the next candidate;

[0061] 5) For each register reg in SA, analyze the number of instruction subsets ng that contain both W and this reg. Then, only keep those registers corresponding to the smallest ng value in SA;

[0062] 6) For each register reg in SA, analyze the number of instructions ni that use this reg in the instruction subset that contains both W and this reg. Then, only keep those registers corresponding to the smallest ni value in SA;

[0063] 7) According to certain rules, such as the largest, smallest or random number, select a register in SA as the register assigned to W, and then go to step 2) to process the next candidate.

[0064] The special data structures that need to be constructed by the method of the present invention are:

[0065] 1) List of instruction subsets in each basic block: For the instruction sequence in each basic block, they are divided into multiple instruction subsets according to the dependencies between them. These instruction subsets in the basic block together constitute the instruction subset list instnGroupList;

[0066] 2) Mapping relationship between instructions and instruction subsets: Each instruction is in an instruction subset, and they form a mapping relationship pair. All such mapping relationship pairs form a set mI_igroup;

[0067] 3) Mapping relationship between instructions and w sets: An instruction may access multiple ws, which form a corresponding set. This instruction and the corresponding w set form a mapping pair. All such mapping pairs form a set, called mI_sA;

[0068] 4) The mapping relationship between w and the physical register it obtains: Each w and the register mapping pair assigned to it constitute a set, called mW_PR.

[0069] In a specific application example, when establishing a mapping relationship between instructions and instruction subsets, the present invention may further adopt the following steps for each basic block bb:

[0070] 1) Create a mapping set ix_idn that stores the instruction ix to its dependency level number idn. Traverse each instruction in bb in turn and initialize the idn of each ix to 0;

[0071] 2) Traverse each instruction in bb in turn until all instructions are processed and then go to the next step. In this step, for each instruction ix, find the maximum value idnMax among the idns corresponding to the dependent instructions based on the instructions that ix depends on. Then set idn of ix = idnMax+1, and put the mapping pair composed of ix and idn into the set ix_idn;

[0072] 3) Count the number of different idn values, let it be k. Set the number of list elements in instnGroupList to k;

[0073] 4) Traverse each instruction ix in bb in turn, and perform the following processing: read the value idn corresponding to ix from ix_idn, then put ix into the set igroup corresponding to the idnth element of instnGroupList, and add the mapping pair of ix and igroup to the mI_igroup set;

[0074] In a specific application example, when mapping the instruction and the register allocation candidate involved, the present invention can further adopt the following steps for each register candidate w:

[0075] 1) For each fixed value instruction and use instruction that uses w, create an empty set sA for storing candidates, and add the mapping pairs consisting of these instructions and their sA to mI_sA;

[0076] 2) Traverse each instruction ix that sets the value of w (this can be achieved by scanning the instruction information recorded in all defs of w), and add w to sA corresponding to ix;

[0077] 3) Traverse each instruction ix that uses w (this can be achieved by scanning the instruction information recorded in all uses of w), and add w to sA corresponding to ix.

[0078] In a specific application example, when register selection is performed based on the logical parallel relationship between instructions, the following steps may be further adopted:

[0079] Take a register allocation candidate w from the top of stk and select a register for w as follows:

[0080] 1) Create an empty set usedRegs for storing registers. Traverse the adjacency list of w, read the registers that have been obtained in each adjacent node of w and add them to usedRegs. For the hardware assignable register set GR, use the formula "SA = GR-usedRegs" to calculate the complement set SA of usedRegs. If SA is empty, there is no candidate register for w to use, and the assignment process ends. Otherwise, execute the next step;

[0081] 2) Create an empty set SDep. Traverse all instruction subsets to which all fixed-value instructions and usage instructions of w belong, scan each instruction Ix in these instruction subsets, and perform processing: obtain the candidate set Sx corresponding to Ix through mI_sA. For those candidates in Sx that have been assigned registers, add the registers they use to the set SDep;

[0082] 3) Calculate C = SA - SDep. If C is not empty, set it to SN and go to step 6). Otherwise, go to the next step;

[0083] 4) Create an empty set SM. For each register r in SA, count the number of instruction subsets that involve both r and w, and get an instruction subset number n for each r (different r may correspond to the same n value). Take the minimum value nMin of these n, and put the r corresponding to nMin into SM;

[0084] 5) Create an empty set SN. For each register r in the SM, count the number of instructions involving r in the instruction subset that involves both r and w, and get an instruction number n for each r (different r may correspond to the same n value). Take the minimum value nMin of these n, and put the r corresponding to nMin into SN;

[0085] 6) According to certain rules, such as the largest, smallest or random number, select a register from C as the register PR to be assigned from SN. Add the mapping relationship between w and PR to the mapping mW_PR.

[0086] In a specific application example, when analyzing the registers already used in the candidate-related instruction subset, the present invention implements step 2) in the previous section as follows:

[0087] Traverse all the fixed value instructions and use instructions of w, and for each instruction instn, perform the following steps:

[0088] 1) According to the information recorded in mI_igroup, find the instruction subset igroup corresponding to instn;

[0089] 2) Traverse each instruction Ix in igroup and process Ix as follows:

[0090] a) If Ix is instn itself, switch Ix to the next instruction in igroup and execute this step again;

[0091] b) Obtain the candidate set sw involved in Ix from mI_sA;

[0092] c) Traverse each candidate wx in sw, and handle each wx in the following two cases: If it is not in the mW_PR mapping set as a key value, switch to the next wx and re-execute this step. If it is a key value in the mW_PR mapping set, read the register rx corresponding to wx from mW_PR. If rx is a member of the candidate register set SA, add rx to the set SDep.

[0093] In a specific application example, the present invention may further adopt the following steps when analyzing the number of instruction subsets and the number of instructions involved in a register:

[0094] 1) Create an empty set regs, create a mapping set reg_igroupNum of registers to the number of instruction subsets they are in, and create a mapping set reg_iNum of registers to the number of instructions they are in. In reg_igroupNum and reg_iNum, for each register r in SA, initialize its mapping value to 0;

[0095] 2) Traverse all the fixed value instructions and use instructions of w, and for each fixed value instruction or use instruction instn, perform the following steps;

[0096] 3) According to the information recorded in mI_igroup, find the instruction subset igroup corresponding to instn;

[0097] 4) Create an empty set foundRegs, traverse each instruction Ix in igroup, and process Ix as follows:

[0098] a) If Ix is instn itself, switch Ix to the next instruction in igroup and execute this step again;

[0099] b) Obtain the register allocation candidate set sw involved in Ix from mI_sA;

[0100] c) Traverse each candidate wx in sw, and perform the following steps for wx: If wx is not in the mW_PR mapping set as a key value, switch to the next wx; read the register rx corresponding to wx from mW_PR, if rx is not a member of SA, switch to the next wx; if rx is not in regs yet, add rx to the set regs and foundRegs. Otherwise, increase the mapping value of rx in reg_iNum by 1, and, if rx is not in foundRegs yet, increase the mapping value of rx in reg_igroupNum by 1 and add rx to foundRegs;

[0101] 5) According to the data in reg_igroupNum and reg_iNum, analyze the registers involved in the minimum instruction subset and the register r of the minimum instruction, and put these r into SM and SN respectively.

[0102] In a specific application example, when analyzing the registers involved in the minimum instruction subset and the registers of the minimum instructions, the present invention specifically implements step 5) in the previous section as follows:

[0103] 1) Create a mapping relationship set ng_regs between the number of instruction subsets and the corresponding register sets, and create a mapping relationship set ni_regs between the number of instruction subsets and the corresponding register sets;

[0104] 2) Initialize both ng_regs and ni_regs to empty sets;

[0105] 3) Let: ngMin = the number of all instruction subsets, niMin = the number of all instructions;

[0106] 4) Traverse each key r and its corresponding value x in reg_igroupNum obtained above, add r to the set corresponding to the key value x in ng_regs, if x is less than ngMin, set ngMin = x;

[0107] 5) Traverse each key r and its corresponding value x in reg_iNum obtained above, add r to the set corresponding to the key value x in ni_regs, if x is less than niMin, set niMin = x;

[0108] 6) Let SM be the set corresponding to ngMin in ng_regs, and SN be the set corresponding to niMin in ni_regs.

[0109] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A register selection optimization method for improving instruction level parallelism, characterized in that: The relevant instruction data structures include: 1) List of instruction subsets in each basic block: For the instruction sequence in each basic block, they are divided into multiple instruction subsets according to the dependencies between them; these instruction subsets in the basic block together constitute the instruction subset list instnGroupList; 2) Mapping relationship between instructions and instruction subsets: Each instruction is in an instruction subset, and they form a mapping relationship pair; all such mapping relationship pairs form a set mI_igroup; 3) Mapping relationship between instructions and w sets: An instruction may access multiple ws, which form a corresponding set. This instruction and the corresponding w set form a mapping pair. All such mapping pairs form a set, called mI_sA. 4) The mapping relationship between w and the physical register it obtains: Each w and the register mapping pair assigned to it constitute a set, called mW_PR; The specific implementation process includes: Step S1: improving the register allocation process, after replacing the variable name at the corresponding position in the function with the variable life cycle name for the first time, returning to the starting position of the register allocation process and re-performing the register allocation process; Step S2: adding a processing link, which is used to obtain the dependency relationship between instructions in each basic block of the function, and divide the instructions in each basic block into multiple subsets according to the transmission order of the dependency relationship, and this link is used as the first link in the register allocation processing process; Step S3: at the beginning of the register assignment process, before selecting a register for a specific variable lifecycle (also referred to as a register assignment candidate, or simply a candidate), construct a mapping relationship between instructions and the instruction subset to which they belong; Step S4: Analyze the registers used in other instructions related to the candidate instruction. If there are unassigned registers besides these registers, jump to step S6; otherwise, execute step S5; Step S5: Find the instruction subsets that contain both the allocation candidate and its candidate register, and calculate the number of instruction subsets and the number of instructions containing the candidate register in units of a single candidate register; Step S6: Selecting the register with the least impact on the dependency for each register allocation candidate; In the above step S3, when obtaining the mapping relationship between instructions and instruction subsets, the following steps are taken: For each instruction ix of each basic block, find the maximum value idnMax among the idns corresponding to the instructions that ix depends on, and set the idn of ix equal to idnMax+1; then, put the instructions with the same idn value into the corresponding set igroup, igroup is the instruction subset corresponding to the instruction; finally, add the mapping pair of ix and igroup to the mI_igroup set; In the above step S4, when analyzing the registers used in other instructions related to the instruction where the candidate is located, the following steps are taken: Step S401: Find the registers that have not been used by the adjacent candidates (i.e., the lifecycles have an intersection) of W, and form a candidate register set SA; if SA is empty, there is no candidate register for w to use, and the assignment process ends; otherwise, execute the next step; Step S402: Obtain a mapping relationship mI_sA between an instruction and its related register allocation candidates; Step S403: According to the content of the mapping relationship mI_sA, analyze which registers have been used in the instruction subset where all instructions using W are located, and put these registers into SX; Step S404: Calculate C=SA-SX; if C is not empty, select a register from C as the register to be assigned according to a certain rule, such as the largest, smallest or random number; otherwise, execute step S5; In the above step S402, when obtaining the mapping relationship between the instruction and the register allocation candidate involved, the following steps are taken: For each candidate w, traverse each instruction that sets a value for w and each instruction that uses w, and add w to the set SA for storing register candidates corresponding to these instructions; obtain the mapping relationship mI_sA between the instruction and the candidate set; In the above step S5, when calculating the number of instruction subsets and the number of instructions including the candidate register in units of a single candidate register, the following steps are taken: For the candidate register set SA, use the following heuristics 1 and 2 to further process SA. If SA is empty after processing, restore SA to its state before processing; if the number of registers in SA is 1, select the register to assign to W; if the number of registers remaining in SA is greater than 1, select one of the registers to assign to w according to certain rules, such as the largest, smallest or random number; In the above process, the heuristic method 1 is to select registers that affect as few instruction subsets as possible from SA, by analyzing the number ng of instruction subsets that contain both W and reg for each register reg in SA, and then, only the register corresponding to the minimum ng value is retained in SA, and all other registers are removed from SA; In the above process, the second heuristic is to select registers from SA that affect as few instructions as possible. The method is to analyze, for each register reg in SA, the number ni of instructions that use this reg in the instruction subset that contains both W and this reg, and then, only retain the register corresponding to the minimum ni value in SA, and remove all other registers from SA.

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