3D NAND memory device and method of manufacturing the same

Abstract

The application provides a 3D NAND memory device and a manufacturing method thereof. A plurality of storage areas are separated by a pseudo storage area. A stack layer is etched to form a plurality of gate line isolation gaps and a pseudo channel hole in the pseudo storage area. An insulating layer is formed in the pseudo channel hole, and the insulating layer is etched to obtain a connecting hole penetrating through the insulating layer to a substrate. A metal is filled in the connecting hole to form a contact plug in the pseudo channel hole. Finally, an electrical connection is formed from one side surface of the 3D NAND memory device to the opposite side surface through a plurality of contact plugs. As can be seen, the application can form sufficient contact plugs in the 3D NAND memory device by forming the contact plugs in the pseudo channel hole, and can avoid reducing the area of the storage area in the memory device, thereby improving the performance of the memory device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices and their manufacturing, and particularly to a 3D NAND memory device and its manufacturing method. Background Technology

[0002] NAND flash memory devices are non-volatile memory products with low power consumption, light weight, and high performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limits. To further increase storage capacity and reduce the cost per bit, 3D NAND flash memory devices have been proposed.

[0003] However, current 3D NAND storage devices have insufficient storage performance and cannot meet the needs of high-performance storage. Summary of the Invention

[0004] The purpose of this application is to provide a 3D NAND memory device and a method for manufacturing the same, which can form sufficient contact plugs in the memory device wafer of the 3D NAND memory device to improve the performance of the memory device.

[0005] This application provides a method for manufacturing a 3D NAND memory device, including:

[0006] A substrate is provided on which a stack of sacrificial layers and dielectric layers are formed alternately;

[0007] The stacked layer is etched to form a plurality of gate isolation gaps and a plurality of pseudo-channel vias in the stacked layer, the gate isolation gaps and the pseudo-channel vias penetrating the stacked layer to the substrate, the plurality of gate isolation gaps and the plurality of pseudo-channel vias being formed in a pseudo memory region, the pseudo memory region dividing the stacked layer into a plurality of memory regions;

[0008] The dummy channel hole is filled with insulating material to form a first insulating layer in the dummy channel hole;

[0009] The first insulating layer is etched to form a connection hole, the connection hole penetrating the first insulating layer to the substrate;

[0010] The connection hole is then filled with metal.

[0011] Optionally, it also includes:

[0012] Etching is performed from the substrate to form a contact hole penetrating the substrate; the contact hole exposes the metal filling the connection hole;

[0013] The contact hole is then filled with metal.

[0014] Optionally, before performing metal filling of the contact hole, the method further includes:

[0015] Deposited insulating materials;

[0016] Remove the insulating material at the bottom of the contact hole, while retaining the insulating material on the sidewalls of the contact hole;

[0017] The contact holes are wet-cleaned.

[0018] Optionally, it also includes:

[0019] Insulating material is filled into the gaps in the grid lines.

[0020] Optionally, the grid isolation gap is located near the storage area and further includes:

[0021] Etching is performed from the substrate to form an isolation via penetrating the substrate; the isolation via is adjacent to the storage region and exposes the insulating material of the gate isolation gap;

[0022] The insulating material is filled into the isolation vias to form a deep trench isolation layer.

[0023] Optionally, a channel hole is formed in the stacked layer of the storage region, the channel hole penetrates the stacked layer to the substrate, and a storage functional layer and a channel layer are sequentially formed in the channel hole;

[0024] Before filling the grid wire isolation gaps with insulating material, the method further includes:

[0025] The sacrificial layer is removed by using the grid lines to isolate the gaps, thus forming an opening;

[0026] A gate layer is formed in the opening.

[0027] Optionally, after filling the connection hole with metal, the process further includes:

[0028] A bonding layer is formed on the stacked layers, the bonding layer comprising a metal bonding layer;

[0029] The metal bonding layer is electrically connected to the metal inside the connection hole.

[0030] This application provides a 3D NAND storage device, including:

[0031] A substrate on which a stack of sacrificial layers and dielectric layers are alternately stacked;

[0032] The stacked layer has a plurality of gate isolation gaps and a plurality of pseudo-channel vias formed therein, the gate isolation gaps and the plurality of pseudo-channel vias penetrating the stacked layer to the substrate; the plurality of gate isolation gaps and the plurality of pseudo-channel vias are formed in a pseudo memory region, the pseudo memory region dividing the stacked layer into a plurality of memory regions;

[0033] A first insulating layer and a connection hole are formed in the pseudo-channel hole; the connection hole penetrates the first insulating layer to the substrate.

[0034] The connection hole is filled with metal.

[0035] Optionally, it also includes:

[0036] Contact holes extending through the substrate to expose the metal within the connection hole and isolation vias extending through the substrate;

[0037] The contact hole is filled with metal, and a deep trench isolation layer is formed in the isolation through hole.

[0038] Optionally, it also includes:

[0039] A bonding layer is formed on the stacked layer, and the bonding layer includes a metal bonding layer;

[0040] The metal bonding layer is electrically connected to the metal inside the connection hole.

[0041] The 3D NAND memory device and its manufacturing method provided in this application separate multiple memory regions through pseudo-memory regions. A stacked layer is etched to form multiple gate isolation gaps and pseudo-channel vias in the pseudo-memory regions. A first insulating layer is formed in the pseudo-channel vias, and the first insulating layer is etched to obtain a connection hole penetrating the first insulating layer to the substrate. Metal is filled into the connection hole to form contact plugs in the pseudo-channel vias. Finally, multiple contact plugs form an electrical connection from one surface of the 3D NAND memory device to the opposite surface. Therefore, by forming contact plugs in the pseudo-channel vias, this application can form sufficient contact plugs in the 3D NAND memory device and avoid reducing the area occupied by the memory regions, thereby improving the performance of the memory device. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A schematic diagram of a 3D NAND memory device is shown.

[0044] Figure 2 A flowchart illustrating a method for manufacturing a 3D NAND memory device according to an embodiment of this application is shown;

[0045] Figures 3-7 This paper shows a schematic diagram of the structure of a 3D NAND memory device according to an embodiment of this application;

[0046] Figure 8 This paper shows a top view of a 3D NAND memory device according to an embodiment of this application;

[0047] Figures 9-13 A schematic diagram of the structure of another 3D NAND memory device according to an embodiment of this application is shown. Detailed Implementation

[0048] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0049] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0050] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0051] refer to Figure 1 As shown, multiple storage regions 100 in a 3D NAND memory device are isolated and distinguished only by a gate isolation structure 210 and a small pseudo-storage region 200. This can increase the proportion of storage regions in the 3D NAND memory device and improve storage performance. However, in this type of 3D NAND memory device, there is no spare area to form sufficient contact plugs, which prevents electrical signals from being transmitted from one side of the 3D NAND memory device to the opposite side, ultimately leading to a decrease in memory device performance.

[0052] Based on this, embodiments of this application provide a 3D NAND memory device and its manufacturing method. Multiple memory regions are separated by pseudo-memory regions. A stacked layer is etched to form multiple gate isolation gaps and pseudo-channel vias in the pseudo-memory regions. A first insulating layer is formed in the pseudo-channel vias, and the first insulating layer is etched to obtain a connection hole penetrating the first insulating layer to the substrate. Metal is filled into the connection hole to form contact plugs in the pseudo-channel vias. Finally, multiple contact plugs form an electrical connection from one surface of the 3D NAND memory device to the opposite surface. Therefore, by forming contact plugs in the pseudo-channel vias, sufficient contact plugs can be formed in the 3D NAND memory device, and the area occupied by the memory regions can be avoided, thus improving the performance of the memory device.

[0053] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0054] refer to Figure 2 The image shows a method for manufacturing a 3D NAND memory device according to an embodiment of this application. This method may include:

[0055] S201, a substrate 100 is provided, on which a stacked layer 110 of alternating sacrificial layers 111 and dielectric layers 112 is formed, reference. Figure 3 As shown.

[0056] In the embodiments of this application, the substrate 100 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In other embodiments, the semiconductor substrate may also include substrates of other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as a Si / SiGe substrate, or other epitaxial structures, such as SGOI (Silicon On Germanium). In this embodiment, the substrate 100 is a silicon substrate.

[0057] In embodiments of this application, a stacked layer 110 may be formed on the substrate 100, as shown in the reference. Figure 3 As shown. Stacked layer 110 is used to form a string of memory cells perpendicular to the substrate direction. The string of memory cells has a storage function. The number of stacked layers 130 is determined by the number of memory cell layers in the formed 3D NAND memory device. The more stacked layers 130 there are, the more memory cells are contained in the formed string of memory cells, and the higher the integration of the device.

[0058] The stacked layer 110 may include a sacrificial layer 111 and a dielectric layer 112. The sacrificial layer 111 occupies the site for the subsequent formation of the gate layer, and the dielectric layer 112 isolates the sacrificial layer 111. After the sacrificial layer 111 is replaced by the gate layer, the dielectric layer 112 isolates the gate layer to prevent gate layer contact. The dielectric layer 112 may be, for example, a silicon oxide layer, and the sacrificial layer 111 may be, for example, a silicon nitride layer.

[0059] The stacked layer 110 can be formed by a single deck, for example by alternating layers of sacrificial layer 111 and dielectric layer 112, or by sequentially stacking multiple sub-decks, for example by first alternately stacking portions of sacrificial layer 111 and dielectric layer 112 to form a sub-deck. In a specific embodiment, chemical vapor deposition, atomic layer deposition, or other suitable deposition methods can be used to sequentially and alternately deposit sacrificial layer 111 and dielectric layer 112 to form the stacked layer 110.

[0060] S202, etch the stacked layer 110 to form a plurality of gate isolation gaps 120 and a plurality of pseudo-channel vias 130 in the stacked layer 110. The gate isolation gaps 120 and the pseudo-channel vias 130 penetrate the stacked layer 110 to the substrate 100. The plurality of gate isolation gaps 120 and the plurality of pseudo-channel vias 130 are formed in a pseudo memory region 1000, which divides the stacked layer 110 into a plurality of memory regions 2000. Reference Figure 4 As shown.

[0061] In embodiments of this application, after forming a stacked layer 110 on the substrate 100, the stacked layer 110 can be etched to form a plurality of gate isolation gaps 120 and a plurality of dummy channel vias 130. The region where the plurality of gate isolation gaps 120 and the plurality of dummy channel vias 130 are located is a dummy memory region 1000. The dummy memory region 1000 divides the stacked layer 110 into a plurality of memory regions 2000, and the stacked layer 110 of the memory regions is used to form memory cells.

[0062] In the embodiments of this application, the stacked layer 110 can be etched using etching techniques, such as reactive ion etching, until the surface of the substrate 100 is reached, thereby forming a gate isolation gap 120 and a pseudo-channel via 130 penetrating the stacked layer 110 to the substrate 100. (Refer to...) Figure 4 As shown, the formation processes of the grid isolation gap 120 and the pseudo-channel hole 130 can be carried out simultaneously to save process steps and reduce manufacturing costs.

[0063] In embodiments of this application, the gate isolation gap 120 is located near the storage region 2000 and is used to isolate memory cells subsequently formed in different storage regions. The dummy channel via 130 is located away from the storage region 2000 and is used to subsequently form connection vias to increase the number of contact plugs in the 3D NAND memory device, thereby improving device performance. The dummy channel via 130 is formed between the gate isolation gaps 120.

[0064] S203, fill the dummy channel hole 130 with insulating material to form a first insulating layer 140 in the dummy channel hole 130, reference. Figure 5 As shown.

[0065] In embodiments of this application, after etching the stacked layer 110 to form a plurality of dummy channel holes 130, insulating material can be filled into the dummy channel holes 130, that is, insulating material is deposited in the dummy channel holes 130 to form a first insulating layer 140 in the dummy channel holes 130, as shown in the reference. Figure 5 As shown. The first insulating layer 140 can be a single-layer structure, such as silicon nitride, silicon oxide, silicon oxynitride, etc., or it can be a multilayer structure, such as a stack of silicon nitride, silicon oxide, silicon oxynitride, etc. The deposition method of the first insulating layer 140 can be chemical vapor deposition (CVD). In this embodiment, the first insulating layer 140 is a silicon oxide layer.

[0066] In practical applications, the pseudo-channel hole 130 will subsequently form a contact plug. Therefore, when etching the stacked layer 110 to form the pseudo-channel hole 130, the size of the pseudo-channel hole 130 can be larger than the size of the pseudo-channel hole in the current storage device, so that there is enough space in the pseudo-channel hole 130 to form a contact plug.

[0067] In the embodiments of this application, when depositing insulating material in the pseudo-channel via 130, insulating material can also be filled in the gate line isolation gap 120 to form a second insulating layer 141 located in the gate line isolation gap 120. The second insulating layer 141 located in the gate line isolation gap 120 is used to isolate the memory cells subsequently formed in different memory regions. Such a process can reduce the device manufacturing cost.

[0068] S204, Etch the first insulating layer 140 to form a connection hole 150, the connection hole 150 penetrating the first insulating layer 140 to the substrate 100, Reference Figure 6 As shown.

[0069] In embodiments of this application, after depositing and forming a first insulating layer 140 in a plurality of dummy channel vias 130, the insulating layer in the dummy channel vias 130 can be etched to form a connection via 150 in the dummy channel vias 130. The connection via 150 penetrates the first insulating layer 140 to the substrate 100. The connection via 150 is used for subsequent formation of contact plugs to realize electrical connection between the first surface and the second surface of the memory device. The first surface and the second surface are two opposite surfaces of the memory device. (Refer to...) Figure 6 As shown.

[0070] S205, perform metal filling of the connecting hole 150, refer to Figure 7 As shown.

[0071] In the embodiments of this application, after etching the first insulating layer 140 in the dummy channel hole 130 to obtain the connection hole 150, the connection hole 150 can be filled. (Refer to...) Figure 7 As shown. Since the connection hole 150 is for forming a contact plug to achieve electrical connection between the first and second surfaces of the storage device, the metal layer 160 in the connection hole 150 is a conductive material, such as copper, tungsten, or other metal materials. In this embodiment, the material of the metal layer 160 is tungsten.

[0072] refer to Figure 8 The diagram shown is a top view of a 3D NAND memory device provided in an embodiment of this application. Figure 7 The schematic diagram of the 3D NAND memory device shown is from... Figure 8 It is obtained by truncating along the AA direction.

[0073] from Figure 8As can be seen, the gate isolation gap 120 isolates the pseudo memory region 1000 and the memory region 2000. Multiple pseudo-channel holes 130 are provided within the pseudo memory region, and each pseudo-channel hole 130 forms a connection hole 150. The connection hole 150 is filled with metal to form a contact plug. The shape of the channel holes and connection holes is not specifically limited in this embodiment and can be set according to actual conditions. The number of connection holes 150 and the distance between them can be set according to actual conditions. The connection holes 150 can be arranged in an array. Therefore, the method provided in this embodiment separates multiple memory regions through pseudo memory regions, etches the stacked layer to form multiple gate isolation gaps and pseudo-channel holes in the pseudo memory region, forms a first insulating layer in the pseudo-channel holes, etches the first insulating layer to obtain a connection hole penetrating the first insulating layer to the substrate, fills the connection hole with metal to form a contact plug in the pseudo-channel hole, and finally forms an electrical connection from one surface of the 3D NAND memory device to the opposite surface through multiple contact plugs. Therefore, this application can form sufficient contact plugs in 3D NAND memory devices by forming contact plugs in pseudo-channel holes, and can avoid reducing the area occupied by the storage area in the memory device, thereby improving the performance of the memory device.

[0074] Furthermore, during the formation of the connection hole, only the insulating layer filling the pseudo-channel hole needs to be etched, without the need to etch the stacked layer, thus reducing the process difficulty.

[0075] In the embodiments of this application, a connection hole 150 is formed in the pseudo-channel hole 130 of the stacked layer 110, and after the connection hole 150 is filled with metal, a bonding layer can be formed on the stacked layer 110. The material of the bonding layer can be a dielectric material. A metal bonding layer is formed in the bonding layer, and the metal bonding layer is electrically connected to the metal in the connection hole 150 for subsequent electrical connection when bonding with other wafers or devices.

[0076] In the embodiments of this application, a connection hole 150 is formed in the pseudo-channel hole 130, and metal is filled in the connection hole 150 to form a metal layer 160. Then, the substrate 100 can be etched to obtain a contact hole 170 that penetrates the substrate 100, and metal is filled in the contact hole 170 to form an electrical connection between the metal in the contact hole 170 and the metal layer 160 in the connection hole 150.

[0077] Specifically, substrate 100 has opposing first and second surfaces. A stacked layer 110 is formed on the first surface of substrate 100, followed by the formation of a connection hole 150. Etching is performed from the second surface of substrate 100 to form a contact hole 170 penetrating substrate 100. The contact hole 170 exposes a metal layer 160 filled within the connection hole 150 of the dummy channel via 130. (Refer to...) Figure 9 As shown.

[0078] After the contact hole 170 is formed, an insulating material 180 can be deposited, thus covering the bottom and sidewalls of the contact hole 170 with the insulating material 180. (See reference...) Figure 10 As shown. The insulating material 180 can be formed into a single-layer structure, such as silicon nitride, silicon oxide, silicon oxynitride, etc., or it can be formed into a multilayer structure, such as a stack of silicon nitride, silicon oxide, silicon oxynitride, etc. In this embodiment, the insulating material can be silicon oxide. The insulating material can be deposited by chemical vapor deposition (CVD). The insulating material 180 is used for insulation and isolation between the metal filler material subsequently formed in the contact hole 170 and the substrate 100, thereby improving the reliability and performance of the device.

[0079] In embodiments of this application, after depositing the insulating material, an etching process can be used to remove the insulating material at the bottom of the contact hole 170 to expose the metal layer 160 filling the connection hole 150 of the dummy channel hole 130, while retaining the insulating material 180 on the sidewalls of the contact hole 170. (Refer to...) Figure 11 As shown. Specifically, the insulating material at the bottom of contact hole 170 can be removed using a dry etching process. The dry etching process can utilize chlorine gas or a fluorine-containing gas, such as carbon tetrafluoride (CF4).

[0080] After removing the insulating material at the bottom of the contact hole 170 using an etching process, the contact hole 170 can be cleaned using a wet cleaning process to remove any residue left after etching. Following wet cleaning, metal is filled into the contact hole 170 to form a contact 190 for subsequent electrical lead-out. The insulating material 180 on the sidewalls of the contact hole 170 surrounds the contact 190 and serves to isolate the contact 190 from the substrate 100. (Refer to...) Figure 12 As shown. A conductive material, such as copper or tungsten, is filled into the contact hole 170. In this embodiment, the conductive material is tungsten.

[0081] In embodiments of this application, the gate line isolation gap 120 is located near the storage region 2000. After the gate line isolation gap is filled with insulating material, the insulating material is used to isolate the memory cells subsequently formed in different storage regions. That is, no connection via 150 is formed in the gate line isolation gap 120. In order to isolate the substrates 100 of different storage regions, the substrate 100 can be etched to form an isolation via 200 penetrating the substrate 100. The isolation via 200 is located near the storage region 2000 and exposes the second insulating layer 141 located within the gate line isolation gap 120. Figure 9 As shown.

[0082] The isolation via 200 can be etched simultaneously with the contact hole 170, or they can be etched separately. This application does not specifically limit the order in which the isolation via 200 and the contact hole 170 are etched.

[0083] In embodiments of this application, after etching to obtain isolation vias 200 penetrating the substrate 100, insulating material can be deposited and filled in the isolation vias 200 to form a deep trench isolation layer 210. The deep trench isolation layer 210 is used to isolate different storage regions of the substrate 100. (Refer to...) Figure 10 As shown.

[0084] In practical applications, the isolation via 200 can be etched simultaneously with the contact hole 170. Afterwards, insulating material can be deposited and filled in both the isolation via 200 and the contact hole 170, saving process steps and reducing process costs.

[0085] refer to Figure 13 As shown, a pseudo memory region 1000 is used to isolate multiple memory regions 2000. A channel hole 220 is formed in the stacked layer 110 of the multiple memory regions 2000. The channel hole 220 penetrates the stacked layer 110 to the substrate 100. A memory functional layer 221 and a channel layer 222 are formed sequentially in the channel hole 220.

[0086] Specifically, after forming a stacked layer 110 on the substrate 100, the stacked layer 110 can be etched to form a channel hole 220, which is used to form a memory cell string in the future.

[0087] The method for forming the via 220 can be as follows: a hard mask layer is formed on the surface of the stacked layer 110, such as a silicon oxide or silicon nitride layer; then a photoresist layer is spin-coated onto the surface of the hard mask layer, and a patterned photoresist layer is formed through exposure, development, and other steps. The pattern of the photoresist can be determined by a mask used to form the via in the 3D NAND memory manufacturing process; the pattern is transferred to the hard mask layer; then the stacked layer 110 is etched using the hard mask layer as a shield to form the via 220 penetrating through the stacked layer 110, which can extend into the substrate 100. After forming the via 220, the hard mask layer and the photoresist layer can be removed. In a specific implementation, the via 220 can extend from the stacked layer 110 into the substrate 100.

[0088] Subsequently, a storage functional layer 221 and a channel layer 222 are sequentially formed in the channel via 220. The storage functional layer 221 may include a barrier layer, a charge storage layer, and a tunneling layer stacked sequentially. In a specific embodiment, the barrier layer, charge storage layer, and tunneling layer may be an ONO stack, which is a stack of oxide, nitride, and oxide. The channel layer 222 may be a polysilicon layer.

[0089] In embodiments of this application, a storage functional layer 221 can be formed by sequentially stacking a barrier layer, a charge storage layer, and a tunneling layer in the channel via 220. Then, a channel layer 222 is formed on the sidewall of the storage functional layer 221. An insulating material filling layer, such as a silicon oxide layer, can be formed between the channel layers 222. In a specific embodiment, a conductive layer can be formed above the memory cell string. This conductive layer forms the upper selector device of the memory cell string and also forms interconnect structures to further form bit lines. Then, a dielectric layer can be formed above the stacked layer 110. This dielectric layer protects the formed storage functional layer and conductive layer. The dielectric layer can be, for example, silicon oxide or silicon nitride. In a specific embodiment, a dielectric layer material can be deposited above the stacked layer 110, followed by a planarization process to form a dielectric layer of uniform thickness above the stacked layer. For example, chemical mechanical polishing can be used to planarize the dielectric layer.

[0090] In embodiments of this application, a channel hole 220 may be formed before the gate isolation gap 120 is formed, and a storage function layer and a channel layer may be formed within the channel hole 220.

[0091] In the embodiments of this application, before filling the gate line isolation gap 120 with insulating material to form the second insulating layer 141 located in the gate line isolation gap, the gate line isolation gap 120 can be used to etch and remove the sacrificial layer 111 in the stacked layer 110 to form an opening so that the gate layer can be formed in the opening subsequently. Specifically, the gate layer is formed in the opening through the gate line isolation gap 120, and the material of the gate layer is a metal material.

[0092] The manufacturing method of the embodiments of this application has been described in detail above. Furthermore, the embodiments of this application also provide a 3D NAND memory device formed by the above method. (See reference...) Figure 13 As shown, the storage device includes:

[0093] A substrate on which a stack of sacrificial layers and dielectric layers are alternately stacked;

[0094] The stacked layer has a plurality of gate isolation gaps and a plurality of pseudo-channel vias formed therein, the gate isolation gaps and the plurality of pseudo-channel vias penetrating the stacked layer to the substrate; the plurality of gate isolation gaps and the plurality of pseudo-channel vias are formed in a pseudo memory region, the pseudo memory region dividing the stacked layer into a plurality of memory regions;

[0095] A first insulating layer and a connection hole are formed in the pseudo-channel hole; the connection hole penetrates the first insulating layer to the substrate.

[0096] The connection hole is filled with metal.

[0097] Optionally, it also includes:

[0098] Contact holes extending through the substrate to expose the metal within the connection hole and isolation vias extending through the substrate;

[0099] The contact hole is filled with metal, and a deep trench isolation layer is formed in the isolation through hole.

[0100] Optionally, it also includes:

[0101] A bonding layer is formed on the stacked layer, and the bonding layer includes a metal bonding layer;

[0102] The metal bonding layer is electrically connected to the metal inside the connection hole.

[0103] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for manufacturing a 3D NAND memory device, characterized in that, include: A substrate is provided on which a stack of sacrificial layers and dielectric layers are formed alternately; The stacked layer is etched to form a plurality of gate isolation gaps and a plurality of pseudo-channel vias in the stacked layer, the gate isolation gaps and the pseudo-channel vias penetrating the stacked layer to the substrate, the plurality of gate isolation gaps and the plurality of pseudo-channel vias being formed in a pseudo memory region, the pseudo memory region dividing the stacked layer into a plurality of memory regions; The dummy channel hole is filled with insulating material to form a first insulating layer in the dummy channel hole; The first insulating layer is etched to form a connection hole, the connection hole penetrating the first insulating layer to the substrate; Metal filling is performed on the connection hole to form a contact plug in the pseudo-channel hole; An electrical connection is formed through the contact plug.

2. The manufacturing method according to claim 1, characterized in that, Also includes: Etching is performed from the substrate to form contact holes that penetrate the substrate; The contact hole exposes the metal filling the connection hole; The contact hole is then filled with metal.

3. The manufacturing method according to claim 2, characterized in that, Before performing the metal filling of the contact hole, the following steps are also included: Deposited insulating materials; Remove the insulating material at the bottom of the contact hole, while retaining the insulating material on the sidewalls of the contact hole; The contact holes are wet-cleaned.

4. The manufacturing method according to claim 1, characterized in that, Also includes: Insulating material is filled into the gaps in the grid lines.

5. The manufacturing method according to claim 4, characterized in that, The grid isolation gap is located near the storage area and also includes: Etching is performed from the substrate to form an isolation via penetrating the substrate; the isolation via is adjacent to the storage region and exposes the insulating material of the gate isolation gap; The insulating material is filled into the isolation vias to form a deep trench isolation layer.

6. The manufacturing method according to claim 1, characterized in that, A channel hole is formed in the stacked layer of the storage region, the channel hole penetrates the stacked layer to the substrate, and a storage functional layer and a channel layer are formed sequentially in the channel hole; Before filling the grid wire isolation gaps with insulating material, the method further includes: The sacrificial layer is removed by using the grid lines to isolate the gaps, thus forming an opening; A gate layer is formed in the opening.

7. The method according to claim 1, characterized in that, After filling the connection hole with metal, the process further includes: A bonding layer is formed on the stacked layers, the bonding layer comprising a metal bonding layer; The metal bonding layer is electrically connected to the metal inside the connection hole.

8. A 3D NAND storage device, characterized in that, include: A substrate on which a stacked layer of alternating gate layers and dielectric layers is formed; The stacked layer has a plurality of gate isolation gaps and a plurality of pseudo-channel vias formed therein, the gate isolation gaps and the plurality of pseudo-channel vias penetrating the stacked layer to the substrate; the plurality of gate isolation gaps and the plurality of pseudo-channel vias are formed in a pseudo memory region, the pseudo memory region dividing the stacked layer into a plurality of memory regions; A first insulating layer and a connection hole are formed in the pseudo-channel hole; the connection hole penetrates the first insulating layer to the substrate. The connection hole is filled with metal, and the pseudo-channel hole contains a contact plug. The contact plug is used to form an electrical connection.

9. The device according to claim 8, characterized in that, Also includes: Contact holes extending through the substrate to expose the metal within the connection hole and isolation vias extending through the substrate; The contact hole is filled with metal, and a deep trench isolation layer is formed in the isolation through hole.

10. The device according to claim 8, characterized in that, Also includes: A bonding layer is formed on the stacked layer, and the bonding layer includes a metal bonding layer; The metal bonding layer is electrically connected to the metal inside the connection hole.

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